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RDMA/cxgb4: Add module_params to enable DB FC & Coalescing on T5
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
3cbdb928 45int db_fc_threshold = 1000;
422eea0a 46module_param(db_fc_threshold, int, 0644);
3cbdb928
VP		 47MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51int db_coalescing_threshold;
52module_param(db_coalescing_threshold, int, 0644);
53MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
422eea0a 56
2f5b48c3
SW		 57static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
58{
59 unsigned long flag;
60 spin_lock_irqsave(&qhp->lock, flag);
61 qhp->attr.state = state;
62 spin_unlock_irqrestore(&qhp->lock, flag);
63}
64
c6d7b267
SW		 65static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
66{
67 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
68}
69
70static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
71{
72 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
73 pci_unmap_addr(sq, mapping));
74}
75
76static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
77{
78 if (t4_sq_onchip(sq))
79 dealloc_oc_sq(rdev, sq);
80 else
81 dealloc_host_sq(rdev, sq);
82}
83
84static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
85{
f079af7a 86 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
c6d7b267
SW		 87 return -ENOSYS;
88 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
89 if (!sq->dma_addr)
90 return -ENOMEM;
91 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
92 rdev->lldi.vr->ocq.start;
93 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
94 rdev->lldi.vr->ocq.start);
95 sq->flags |= T4_SQ_ONCHIP;
96 return 0;
97}
98
99static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100{
101 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
102 &(sq->dma_addr), GFP_KERNEL);
103 if (!sq->queue)
104 return -ENOMEM;
105 sq->phys_addr = virt_to_phys(sq->queue);
106 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
107 return 0;
108}
109
cfdda9d7
SW		 110static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
111 struct c4iw_dev_ucontext *uctx)
112{
113 /*
114 * uP clears EQ contexts when the connection exits rdma mode,
115 * so no need to post a RESET WR for these EQs.
116 */
117 dma_free_coherent(&(rdev->lldi.pdev->dev),
118 wq->rq.memsize, wq->rq.queue,
f38926aa 119 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 120 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 121 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
122 kfree(wq->rq.sw_rq);
123 kfree(wq->sq.sw_sq);
124 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
125 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
126 return 0;
127}
128
129static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
130 struct t4_cq *rcq, struct t4_cq *scq,
131 struct c4iw_dev_ucontext *uctx)
132{
133 int user = (uctx != &rdev->uctx);
134 struct fw_ri_res_wr *res_wr;
135 struct fw_ri_res *res;
136 int wr_len;
137 struct c4iw_wr_wait wr_wait;
138 struct sk_buff *skb;
139 int ret;
140 int eqsize;
141
142 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
143 if (!wq->sq.qid)
144 return -ENOMEM;
145
146 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
c079c287
EG		 147 if (!wq->rq.qid) {
148 ret = -ENOMEM;
149 goto free_sq_qid;
150 }
cfdda9d7
SW		 151
152 if (!user) {
153 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
154 GFP_KERNEL);
c079c287
EG		 155 if (!wq->sq.sw_sq) {
156 ret = -ENOMEM;
157 goto free_rq_qid;
158 }
cfdda9d7
SW		 159
160 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
161 GFP_KERNEL);
c079c287
EG		 162 if (!wq->rq.sw_rq) {
163 ret = -ENOMEM;
164 goto free_sw_sq;
165 }
cfdda9d7
SW		 166 }
167
168 /*
169 * RQT must be a power of 2.
170 */
171 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
172 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
c079c287
EG		 173 if (!wq->rq.rqt_hwaddr) {
174 ret = -ENOMEM;
175 goto free_sw_rq;
176 }
cfdda9d7 177
c6d7b267 178 if (user) {
c079c287
EG		 179 ret = alloc_oc_sq(rdev, &wq->sq);
180 if (ret)
181 goto free_hwaddr;
182
183 ret = alloc_host_sq(rdev, &wq->sq);
184 if (ret)
185 goto free_sq;
c6d7b267 186 } else
c079c287
EG		 187 ret = alloc_host_sq(rdev, &wq->sq);
188 if (ret)
189 goto free_hwaddr;
cfdda9d7 190 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 191 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 192
193 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
194 wq->rq.memsize, &(wq->rq.dma_addr),
195 GFP_KERNEL);
196 if (!wq->rq.queue)
c079c287 197 goto free_sq;
cfdda9d7
SW		 198 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
199 __func__, wq->sq.queue,
200 (unsigned long long)virt_to_phys(wq->sq.queue),
201 wq->rq.queue,
202 (unsigned long long)virt_to_phys(wq->rq.queue));
203 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 204 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 205
206 wq->db = rdev->lldi.db_reg;
207 wq->gts = rdev->lldi.gts_reg;
208 if (user) {
209 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
210 (wq->sq.qid << rdev->qpshift);
211 wq->sq.udb &= PAGE_MASK;
212 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
213 (wq->rq.qid << rdev->qpshift);
214 wq->rq.udb &= PAGE_MASK;
215 }
216 wq->rdev = rdev;
217 wq->rq.msn = 1;
218
219 /* build fw_ri_res_wr */
220 wr_len = sizeof *res_wr + 2 * sizeof *res;
221
d3c814e8 222 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 223 if (!skb) {
224 ret = -ENOMEM;
c079c287 225 goto free_dma;
cfdda9d7
SW		 226 }
227 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
228
229 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
230 memset(res_wr, 0, wr_len);
231 res_wr->op_nres = cpu_to_be32(
232 FW_WR_OP(FW_RI_RES_WR) |
233 V_FW_RI_RES_WR_NRES(2) |
234 FW_WR_COMPL(1));
235 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 236 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 237 res = res_wr->res;
238 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
239 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
240
241 /*
242 * eqsize is the number of 64B entries plus the status page size.
243 */
244 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
245
246 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
247 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
248 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
249 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 250 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 251 V_FW_RI_RES_WR_IQID(scq->cqid));
252 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
253 V_FW_RI_RES_WR_DCAEN(0) |
254 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 255 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 256 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 257 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
258 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
259 V_FW_RI_RES_WR_EQSIZE(eqsize));
260 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
261 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
262 res++;
263 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
264 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
265
266 /*
267 * eqsize is the number of 64B entries plus the status page size.
268 */
269 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
270 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
271 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
272 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
273 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
274 V_FW_RI_RES_WR_IQID(rcq->cqid));
275 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
276 V_FW_RI_RES_WR_DCAEN(0) |
277 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 278 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 279 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 280 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
281 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
282 V_FW_RI_RES_WR_EQSIZE(eqsize));
283 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
284 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
285
286 c4iw_init_wr_wait(&wr_wait);
287
288 ret = c4iw_ofld_send(rdev, skb);
289 if (ret)
c079c287 290 goto free_dma;
aadc4df3 291 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7 292 if (ret)
c079c287 293 goto free_dma;
cfdda9d7
SW		 294
295 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
296 __func__, wq->sq.qid, wq->rq.qid, wq->db,
297 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
298
299 return 0;
c079c287 300free_dma:
cfdda9d7
SW		 301 dma_free_coherent(&(rdev->lldi.pdev->dev),
302 wq->rq.memsize, wq->rq.queue,
f38926aa 303 dma_unmap_addr(&wq->rq, mapping));
c079c287 304free_sq:
c6d7b267 305 dealloc_sq(rdev, &wq->sq);
c079c287 306free_hwaddr:
cfdda9d7 307 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
c079c287 308free_sw_rq:
cfdda9d7 309 kfree(wq->rq.sw_rq);
c079c287 310free_sw_sq:
cfdda9d7 311 kfree(wq->sq.sw_sq);
c079c287 312free_rq_qid:
cfdda9d7 313 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
c079c287 314free_sq_qid:
cfdda9d7 315 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
c079c287 316 return ret;
cfdda9d7
SW		 317}
318
d37ac31d
SW		 319static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
320 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 321{
d37ac31d
SW		 322 u8 *dstp, *srcp;
323 u32 plen = 0;
cfdda9d7 324 int i;
d37ac31d
SW		 325 int rem, len;
326
327 dstp = (u8 *)immdp->data;
328 for (i = 0; i < wr->num_sge; i++) {
329 if ((plen + wr->sg_list[i].length) > max)
330 return -EMSGSIZE;
331 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
332 plen += wr->sg_list[i].length;
333 rem = wr->sg_list[i].length;
334 while (rem) {
335 if (dstp == (u8 *)&sq->queue[sq->size])
336 dstp = (u8 *)sq->queue;
337 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
338 len = rem;
339 else
340 len = (u8 *)&sq->queue[sq->size] - dstp;
341 memcpy(dstp, srcp, len);
342 dstp += len;
343 srcp += len;
344 rem -= len;
345 }
346 }
13fecb83
SW		 347 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
348 if (len)
349 memset(dstp, 0, len);
d37ac31d
SW		 350 immdp->op = FW_RI_DATA_IMMD;
351 immdp->r1 = 0;
352 immdp->r2 = 0;
353 immdp->immdlen = cpu_to_be32(plen);
354 *plenp = plen;
355 return 0;
356}
357
358static int build_isgl(__be64 *queue_start, __be64 *queue_end,
359 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
360 int num_sge, u32 *plenp)
361
362{
363 int i;
364 u32 plen = 0;
365 __be64 *flitp = (__be64 *)isglp->sge;
366
367 for (i = 0; i < num_sge; i++) {
368 if ((plen + sg_list[i].length) < plen)
369 return -EMSGSIZE;
370 plen += sg_list[i].length;
371 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
372 sg_list[i].length);
373 if (++flitp == queue_end)
374 flitp = queue_start;
375 *flitp = cpu_to_be64(sg_list[i].addr);
376 if (++flitp == queue_end)
377 flitp = queue_start;
378 }
13fecb83 379 *flitp = (__force __be64)0;
d37ac31d
SW		 380 isglp->op = FW_RI_DATA_ISGL;
381 isglp->r1 = 0;
382 isglp->nsge = cpu_to_be16(num_sge);
383 isglp->r2 = 0;
384 if (plenp)
385 *plenp = plen;
386 return 0;
387}
388
389static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
390 struct ib_send_wr *wr, u8 *len16)
391{
cfdda9d7
SW		 392 u32 plen;
393 int size;
d37ac31d 394 int ret;
cfdda9d7
SW		 395
396 if (wr->num_sge > T4_MAX_SEND_SGE)
397 return -EINVAL;
398 switch (wr->opcode) {
399 case IB_WR_SEND:
400 if (wr->send_flags & IB_SEND_SOLICITED)
401 wqe->send.sendop_pkd = cpu_to_be32(
402 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
403 else
404 wqe->send.sendop_pkd = cpu_to_be32(
405 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
406 wqe->send.stag_inv = 0;
407 break;
408 case IB_WR_SEND_WITH_INV:
409 if (wr->send_flags & IB_SEND_SOLICITED)
410 wqe->send.sendop_pkd = cpu_to_be32(
411 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
412 else
413 wqe->send.sendop_pkd = cpu_to_be32(
414 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
415 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
416 break;
417
418 default:
419 return -EINVAL;
420 }
d37ac31d 421
cfdda9d7
SW		 422 plen = 0;
423 if (wr->num_sge) {
424 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 425 ret = build_immd(sq, wqe->send.u.immd_src, wr,
426 T4_MAX_SEND_INLINE, &plen);
427 if (ret)
428 return ret;
cfdda9d7
SW		 429 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
430 plen;
431 } else {
d37ac31d
SW		 432 ret = build_isgl((__be64 *)sq->queue,
433 (__be64 *)&sq->queue[sq->size],
434 wqe->send.u.isgl_src,
435 wr->sg_list, wr->num_sge, &plen);
436 if (ret)
437 return ret;
cfdda9d7
SW		 438 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
439 wr->num_sge * sizeof(struct fw_ri_sge);
440 }
441 } else {
442 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
443 wqe->send.u.immd_src[0].r1 = 0;
444 wqe->send.u.immd_src[0].r2 = 0;
445 wqe->send.u.immd_src[0].immdlen = 0;
446 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 447 plen = 0;
cfdda9d7
SW		 448 }
449 *len16 = DIV_ROUND_UP(size, 16);
450 wqe->send.plen = cpu_to_be32(plen);
451 return 0;
452}
453
d37ac31d
SW		 454static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
455 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 456{
cfdda9d7
SW		 457 u32 plen;
458 int size;
d37ac31d 459 int ret;
cfdda9d7 460
d37ac31d 461 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 462 return -EINVAL;
463 wqe->write.r2 = 0;
464 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
465 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 466 if (wr->num_sge) {
467 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 468 ret = build_immd(sq, wqe->write.u.immd_src, wr,
469 T4_MAX_WRITE_INLINE, &plen);
470 if (ret)
471 return ret;
cfdda9d7
SW		 472 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
473 plen;
474 } else {
d37ac31d
SW		 475 ret = build_isgl((__be64 *)sq->queue,
476 (__be64 *)&sq->queue[sq->size],
477 wqe->write.u.isgl_src,
478 wr->sg_list, wr->num_sge, &plen);
479 if (ret)
480 return ret;
cfdda9d7
SW		 481 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
482 wr->num_sge * sizeof(struct fw_ri_sge);
483 }
484 } else {
485 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
486 wqe->write.u.immd_src[0].r1 = 0;
487 wqe->write.u.immd_src[0].r2 = 0;
488 wqe->write.u.immd_src[0].immdlen = 0;
489 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 490 plen = 0;
cfdda9d7
SW		 491 }
492 *len16 = DIV_ROUND_UP(size, 16);
493 wqe->write.plen = cpu_to_be32(plen);
494 return 0;
495}
496
497static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
498{
499 if (wr->num_sge > 1)
500 return -EINVAL;
501 if (wr->num_sge) {
502 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
503 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
504 >> 32));
505 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
506 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
507 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
508 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
509 >> 32));
510 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
511 } else {
512 wqe->read.stag_src = cpu_to_be32(2);
513 wqe->read.to_src_hi = 0;
514 wqe->read.to_src_lo = 0;
515 wqe->read.stag_sink = cpu_to_be32(2);
516 wqe->read.plen = 0;
517 wqe->read.to_sink_hi = 0;
518 wqe->read.to_sink_lo = 0;
519 }
520 wqe->read.r2 = 0;
521 wqe->read.r5 = 0;
522 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
523 return 0;
524}
525
526static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
527 struct ib_recv_wr *wr, u8 *len16)
528{
d37ac31d 529 int ret;
cfdda9d7 530
d37ac31d
SW		 531 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
532 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
533 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
534 if (ret)
535 return ret;
cfdda9d7
SW		 536 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
537 wr->num_sge * sizeof(struct fw_ri_sge), 16);
538 return 0;
539}
540
40dbf6ee
SW		 541static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
542 struct ib_send_wr *wr, u8 *len16)
cfdda9d7
SW		 543{
544
545 struct fw_ri_immd *imdp;
546 __be64 *p;
547 int i;
548 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 549 int rem;
cfdda9d7
SW		 550
551 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
552 return -EINVAL;
553
554 wqe->fr.qpbinde_to_dcacpu = 0;
555 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
556 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
557 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
558 wqe->fr.len_hi = 0;
559 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
560 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
561 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
562 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
563 0xffffffff);
40dbf6ee
SW		 564 WARN_ON(pbllen > T4_MAX_FR_IMMD);
565 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
566 imdp->op = FW_RI_DATA_IMMD;
567 imdp->r1 = 0;
568 imdp->r2 = 0;
569 imdp->immdlen = cpu_to_be32(pbllen);
570 p = (__be64 *)(imdp + 1);
571 rem = pbllen;
572 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
573 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
574 rem -= sizeof *p;
575 if (++p == (__be64 *)&sq->queue[sq->size])
576 p = (__be64 *)sq->queue;
577 }
578 BUG_ON(rem < 0);
579 while (rem) {
580 *p = 0;
581 rem -= sizeof *p;
582 if (++p == (__be64 *)&sq->queue[sq->size])
583 p = (__be64 *)sq->queue;
cfdda9d7 584 }
40dbf6ee 585 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
cfdda9d7
SW		 586 return 0;
587}
588
589static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
590 u8 *len16)
591{
592 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
593 wqe->inv.r2 = 0;
594 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
595 return 0;
596}
597
598void c4iw_qp_add_ref(struct ib_qp *qp)
599{
600 PDBG("%s ib_qp %p\n", __func__, qp);
601 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
602}
603
604void c4iw_qp_rem_ref(struct ib_qp *qp)
605{
606 PDBG("%s ib_qp %p\n", __func__, qp);
607 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
608 wake_up(&(to_c4iw_qp(qp)->wait));
609}
610
611int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
612 struct ib_send_wr **bad_wr)
613{
614 int err = 0;
615 u8 len16 = 0;
616 enum fw_wr_opcodes fw_opcode = 0;
617 enum fw_ri_wr_flags fw_flags;
618 struct c4iw_qp *qhp;
619 union t4_wr *wqe;
620 u32 num_wrs;
621 struct t4_swsqe *swsqe;
622 unsigned long flag;
623 u16 idx = 0;
624
625 qhp = to_c4iw_qp(ibqp);
626 spin_lock_irqsave(&qhp->lock, flag);
627 if (t4_wq_in_error(&qhp->wq)) {
628 spin_unlock_irqrestore(&qhp->lock, flag);
629 return -EINVAL;
630 }
631 num_wrs = t4_sq_avail(&qhp->wq);
632 if (num_wrs == 0) {
633 spin_unlock_irqrestore(&qhp->lock, flag);
634 return -ENOMEM;
635 }
636 while (wr) {
637 if (num_wrs == 0) {
638 err = -ENOMEM;
639 *bad_wr = wr;
640 break;
641 }
d37ac31d
SW		 642 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
643 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
644
cfdda9d7
SW		 645 fw_flags = 0;
646 if (wr->send_flags & IB_SEND_SOLICITED)
647 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
648 if (wr->send_flags & IB_SEND_SIGNALED)
649 fw_flags |= FW_RI_COMPLETION_FLAG;
650 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
651 switch (wr->opcode) {
652 case IB_WR_SEND_WITH_INV:
653 case IB_WR_SEND:
654 if (wr->send_flags & IB_SEND_FENCE)
655 fw_flags |= FW_RI_READ_FENCE_FLAG;
656 fw_opcode = FW_RI_SEND_WR;
657 if (wr->opcode == IB_WR_SEND)
658 swsqe->opcode = FW_RI_SEND;
659 else
660 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 661 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 662 break;
663 case IB_WR_RDMA_WRITE:
664 fw_opcode = FW_RI_RDMA_WRITE_WR;
665 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 666 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 667 break;
668 case IB_WR_RDMA_READ:
2f1fb507 669 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 670 fw_opcode = FW_RI_RDMA_READ_WR;
671 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 672 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 673 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 674 else
675 fw_flags = 0;
cfdda9d7
SW		 676 err = build_rdma_read(wqe, wr, &len16);
677 if (err)
678 break;
679 swsqe->read_len = wr->sg_list[0].length;
680 if (!qhp->wq.sq.oldest_read)
681 qhp->wq.sq.oldest_read = swsqe;
682 break;
683 case IB_WR_FAST_REG_MR:
684 fw_opcode = FW_RI_FR_NSMR_WR;
685 swsqe->opcode = FW_RI_FAST_REGISTER;
40dbf6ee 686 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 687 break;
688 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 689 if (wr->send_flags & IB_SEND_FENCE)
690 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 691 fw_opcode = FW_RI_INV_LSTAG_WR;
692 swsqe->opcode = FW_RI_LOCAL_INV;
693 err = build_inv_stag(wqe, wr, &len16);
694 break;
695 default:
696 PDBG("%s post of type=%d TBD!\n", __func__,
697 wr->opcode);
698 err = -EINVAL;
699 }
700 if (err) {
701 *bad_wr = wr;
702 break;
703 }
704 swsqe->idx = qhp->wq.sq.pidx;
705 swsqe->complete = 0;
706 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
707 swsqe->wr_id = wr->wr_id;
708
709 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
710
711 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
712 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
713 swsqe->opcode, swsqe->read_len);
714 wr = wr->next;
715 num_wrs--;
d37ac31d
SW		 716 t4_sq_produce(&qhp->wq, len16);
717 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 718 }
719 if (t4_wq_db_enabled(&qhp->wq))
720 t4_ring_sq_db(&qhp->wq, idx);
721 spin_unlock_irqrestore(&qhp->lock, flag);
722 return err;
723}
724
725int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
726 struct ib_recv_wr **bad_wr)
727{
728 int err = 0;
729 struct c4iw_qp *qhp;
730 union t4_recv_wr *wqe;
731 u32 num_wrs;
732 u8 len16 = 0;
733 unsigned long flag;
734 u16 idx = 0;
735
736 qhp = to_c4iw_qp(ibqp);
737 spin_lock_irqsave(&qhp->lock, flag);
738 if (t4_wq_in_error(&qhp->wq)) {
739 spin_unlock_irqrestore(&qhp->lock, flag);
740 return -EINVAL;
741 }
742 num_wrs = t4_rq_avail(&qhp->wq);
743 if (num_wrs == 0) {
744 spin_unlock_irqrestore(&qhp->lock, flag);
745 return -ENOMEM;
746 }
747 while (wr) {
748 if (wr->num_sge > T4_MAX_RECV_SGE) {
749 err = -EINVAL;
750 *bad_wr = wr;
751 break;
752 }
d37ac31d
SW		 753 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
754 qhp->wq.rq.wq_pidx *
755 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 756 if (num_wrs)
757 err = build_rdma_recv(qhp, wqe, wr, &len16);
758 else
759 err = -ENOMEM;
760 if (err) {
761 *bad_wr = wr;
762 break;
763 }
764
765 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
766
767 wqe->recv.opcode = FW_RI_RECV_WR;
768 wqe->recv.r1 = 0;
769 wqe->recv.wrid = qhp->wq.rq.pidx;
770 wqe->recv.r2[0] = 0;
771 wqe->recv.r2[1] = 0;
772 wqe->recv.r2[2] = 0;
773 wqe->recv.len16 = len16;
cfdda9d7
SW		 774 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
775 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 776 t4_rq_produce(&qhp->wq, len16);
777 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 778 wr = wr->next;
779 num_wrs--;
cfdda9d7
SW		 780 }
781 if (t4_wq_db_enabled(&qhp->wq))
782 t4_ring_rq_db(&qhp->wq, idx);
783 spin_unlock_irqrestore(&qhp->lock, flag);
784 return err;
785}
786
787int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
788{
789 return -ENOSYS;
790}
791
792static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
793 u8 *ecode)
794{
795 int status;
796 int tagged;
797 int opcode;
798 int rqtype;
799 int send_inv;
800
801 if (!err_cqe) {
802 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
803 *ecode = 0;
804 return;
805 }
806
807 status = CQE_STATUS(err_cqe);
808 opcode = CQE_OPCODE(err_cqe);
809 rqtype = RQ_TYPE(err_cqe);
810 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
811 (opcode == FW_RI_SEND_WITH_SE_INV);
812 tagged = (opcode == FW_RI_RDMA_WRITE) ||
813 (rqtype && (opcode == FW_RI_READ_RESP));
814
815 switch (status) {
816 case T4_ERR_STAG:
817 if (send_inv) {
818 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
819 *ecode = RDMAP_CANT_INV_STAG;
820 } else {
821 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
822 *ecode = RDMAP_INV_STAG;
823 }
824 break;
825 case T4_ERR_PDID:
826 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
827 if ((opcode == FW_RI_SEND_WITH_INV) ||
828 (opcode == FW_RI_SEND_WITH_SE_INV))
829 *ecode = RDMAP_CANT_INV_STAG;
830 else
831 *ecode = RDMAP_STAG_NOT_ASSOC;
832 break;
833 case T4_ERR_QPID:
834 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
835 *ecode = RDMAP_STAG_NOT_ASSOC;
836 break;
837 case T4_ERR_ACCESS:
838 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
839 *ecode = RDMAP_ACC_VIOL;
840 break;
841 case T4_ERR_WRAP:
842 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
843 *ecode = RDMAP_TO_WRAP;
844 break;
845 case T4_ERR_BOUND:
846 if (tagged) {
847 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
848 *ecode = DDPT_BASE_BOUNDS;
849 } else {
850 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
851 *ecode = RDMAP_BASE_BOUNDS;
852 }
853 break;
854 case T4_ERR_INVALIDATE_SHARED_MR:
855 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
856 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
857 *ecode = RDMAP_CANT_INV_STAG;
858 break;
859 case T4_ERR_ECC:
860 case T4_ERR_ECC_PSTAG:
861 case T4_ERR_INTERNAL_ERR:
862 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
863 *ecode = 0;
864 break;
865 case T4_ERR_OUT_OF_RQE:
866 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
867 *ecode = DDPU_INV_MSN_NOBUF;
868 break;
869 case T4_ERR_PBL_ADDR_BOUND:
870 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
871 *ecode = DDPT_BASE_BOUNDS;
872 break;
873 case T4_ERR_CRC:
874 *layer_type = LAYER_MPA|DDP_LLP;
875 *ecode = MPA_CRC_ERR;
876 break;
877 case T4_ERR_MARKER:
878 *layer_type = LAYER_MPA|DDP_LLP;
879 *ecode = MPA_MARKER_ERR;
880 break;
881 case T4_ERR_PDU_LEN_ERR:
882 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
883 *ecode = DDPU_MSG_TOOBIG;
884 break;
885 case T4_ERR_DDP_VERSION:
886 if (tagged) {
887 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
888 *ecode = DDPT_INV_VERS;
889 } else {
890 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
891 *ecode = DDPU_INV_VERS;
892 }
893 break;
894 case T4_ERR_RDMA_VERSION:
895 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
896 *ecode = RDMAP_INV_VERS;
897 break;
898 case T4_ERR_OPCODE:
899 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
900 *ecode = RDMAP_INV_OPCODE;
901 break;
902 case T4_ERR_DDP_QUEUE_NUM:
903 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
904 *ecode = DDPU_INV_QN;
905 break;
906 case T4_ERR_MSN:
907 case T4_ERR_MSN_GAP:
908 case T4_ERR_MSN_RANGE:
909 case T4_ERR_IRD_OVERFLOW:
910 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
911 *ecode = DDPU_INV_MSN_RANGE;
912 break;
913 case T4_ERR_TBIT:
914 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
915 *ecode = 0;
916 break;
917 case T4_ERR_MO:
918 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
919 *ecode = DDPU_INV_MO;
920 break;
921 default:
922 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
923 *ecode = 0;
924 break;
925 }
926}
927
be4c9bad
RD		 928static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
929 gfp_t gfp)
cfdda9d7
SW		 930{
931 struct fw_ri_wr *wqe;
932 struct sk_buff *skb;
933 struct terminate_message *term;
934
935 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
936 qhp->ep->hwtid);
937
be4c9bad 938 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 939 if (!skb)
be4c9bad 940 return;
cfdda9d7
SW		 941 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
942
943 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
944 memset(wqe, 0, sizeof *wqe);
945 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
946 wqe->flowid_len16 = cpu_to_be32(
947 FW_WR_FLOWID(qhp->ep->hwtid) |
948 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
949
950 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
951 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
952 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 953 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
954 term->layer_etype = qhp->attr.layer_etype;
955 term->ecode = qhp->attr.ecode;
956 } else
957 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 958 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 959}
960
961/*
962 * Assumes qhp lock is held.
963 */
964static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 965 struct c4iw_cq *schp)
cfdda9d7
SW		 966{
967 int count;
968 int flushed;
2f5b48c3 969 unsigned long flag;
cfdda9d7
SW		 970
971 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 972
732bee7a 973 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 974 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7
SW		 975 spin_lock(&qhp->lock);
976 c4iw_flush_hw_cq(&rchp->cq);
977 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
978 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
979 spin_unlock(&qhp->lock);
2f5b48c3 980 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 981 if (flushed) {
982 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 983 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 984 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
985 }
cfdda9d7 986
732bee7a 987 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 988 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7
SW		 989 spin_lock(&qhp->lock);
990 c4iw_flush_hw_cq(&schp->cq);
991 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
992 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
993 spin_unlock(&qhp->lock);
2f5b48c3 994 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 995 if (flushed) {
996 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 997 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 998 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
999 }
cfdda9d7
SW		 1000}
1001
2f5b48c3 1002static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 1003{
1004 struct c4iw_cq *rchp, *schp;
581bbe2c 1005 unsigned long flag;
cfdda9d7
SW		 1006
1007 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
1008 schp = get_chp(qhp->rhp, qhp->attr.scq);
1009
1010 if (qhp->ibqp.uobject) {
1011 t4_set_wq_in_error(&qhp->wq);
1012 t4_set_cq_in_error(&rchp->cq);
581bbe2c 1013 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 1014 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 1015 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 1016 if (schp != rchp) {
cfdda9d7 1017 t4_set_cq_in_error(&schp->cq);
581bbe2c 1018 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 1019 (*schp->ibcq.comp_handler)(&schp->ibcq,
1020 schp->ibcq.cq_context);
581bbe2c 1021 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 1022 }
cfdda9d7
SW		 1023 return;
1024 }
2f5b48c3 1025 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1026}
1027
73d6fcad
SW		 1028static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1029 struct c4iw_ep *ep)
cfdda9d7
SW		 1030{
1031 struct fw_ri_wr *wqe;
1032 int ret;
cfdda9d7
SW		 1033 struct sk_buff *skb;
1034
1035 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1036 ep->hwtid);
cfdda9d7 1037
d3c814e8 1038 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1039 if (!skb)
1040 return -ENOMEM;
73d6fcad 1041 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1042
1043 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1044 memset(wqe, 0, sizeof *wqe);
1045 wqe->op_compl = cpu_to_be32(
1046 FW_WR_OP(FW_RI_INIT_WR) |
1047 FW_WR_COMPL(1));
1048 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1049 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1050 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1051 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1052
1053 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1054 ret = c4iw_ofld_send(&rhp->rdev, skb);
1055 if (ret)
1056 goto out;
1057
2f5b48c3 1058 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1059 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1060out:
1061 PDBG("%s ret %d\n", __func__, ret);
1062 return ret;
1063}
1064
1065static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1066{
d2fe99e8 1067 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1068 memset(&init->u, 0, sizeof init->u);
1069 switch (p2p_type) {
1070 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1071 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1072 init->u.write.stag_sink = cpu_to_be32(1);
1073 init->u.write.to_sink = cpu_to_be64(1);
1074 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1075 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1076 sizeof(struct fw_ri_immd),
1077 16);
1078 break;
1079 case FW_RI_INIT_P2PTYPE_READ_REQ:
1080 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1081 init->u.read.stag_src = cpu_to_be32(1);
1082 init->u.read.to_src_lo = cpu_to_be32(1);
1083 init->u.read.stag_sink = cpu_to_be32(1);
1084 init->u.read.to_sink_lo = cpu_to_be32(1);
1085 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1086 break;
1087 }
1088}
1089
1090static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1091{
1092 struct fw_ri_wr *wqe;
1093 int ret;
cfdda9d7
SW		 1094 struct sk_buff *skb;
1095
1096 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1097 qhp->ep->hwtid);
1098
d3c814e8 1099 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1100 if (!skb)
1101 return -ENOMEM;
1102 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1103
1104 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1105 memset(wqe, 0, sizeof *wqe);
1106 wqe->op_compl = cpu_to_be32(
1107 FW_WR_OP(FW_RI_INIT_WR) |
1108 FW_WR_COMPL(1));
1109 wqe->flowid_len16 = cpu_to_be32(
1110 FW_WR_FLOWID(qhp->ep->hwtid) |
1111 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1112
2f5b48c3 1113 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1114
1115 wqe->u.init.type = FW_RI_TYPE_INIT;
1116 wqe->u.init.mpareqbit_p2ptype =
1117 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1118 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1119 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1120 if (qhp->attr.mpa_attr.recv_marker_enabled)
1121 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1122 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1123 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1124 if (qhp->attr.mpa_attr.crc_enabled)
1125 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1126
1127 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1128 FW_RI_QP_RDMA_WRITE_ENABLE |
1129 FW_RI_QP_BIND_ENABLE;
1130 if (!qhp->ibqp.uobject)
1131 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1132 FW_RI_QP_STAG0_ENABLE;
1133 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1134 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1135 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1136 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1137 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1138 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1139 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1140 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1141 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1142 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1143 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1144 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1145 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1146 rhp->rdev.lldi.vr->rq.start);
1147 if (qhp->attr.mpa_attr.initiator)
1148 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1149
cfdda9d7
SW		 1150 ret = c4iw_ofld_send(&rhp->rdev, skb);
1151 if (ret)
1152 goto out;
1153
2f5b48c3
SW		 1154 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1155 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1156out:
1157 PDBG("%s ret %d\n", __func__, ret);
1158 return ret;
1159}
1160
2c974781
VP		 1161/*
1162 * Called by the library when the qp has user dbs disabled due to
1163 * a DB_FULL condition. This function will single-thread all user
1164 * DB rings to avoid overflowing the hw db-fifo.
1165 */
1166static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1167{
1168 int delay = db_delay_usecs;
1169
1170 mutex_lock(&qhp->rhp->db_mutex);
1171 do {
422eea0a
VP		 1172
1173 /*
1174 * The interrupt threshold is dbfifo_int_thresh << 6. So
1175 * make sure we don't cross that and generate an interrupt.
1176 */
1177 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1178 (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
e5619c12 1179 writel(QID(qid) | PIDX(inc), qhp->wq.db);
2c974781
VP		 1180 break;
1181 }
1182 set_current_state(TASK_UNINTERRUPTIBLE);
1183 schedule_timeout(usecs_to_jiffies(delay));
422eea0a 1184 delay = min(delay << 1, 2000);
2c974781
VP		 1185 } while (1);
1186 mutex_unlock(&qhp->rhp->db_mutex);
1187 return 0;
1188}
1189
cfdda9d7
SW		 1190int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1191 enum c4iw_qp_attr_mask mask,
1192 struct c4iw_qp_attributes *attrs,
1193 int internal)
1194{
1195 int ret = 0;
1196 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1197 int disconnect = 0;
1198 int terminate = 0;
1199 int abort = 0;
1200 int free = 0;
1201 struct c4iw_ep *ep = NULL;
1202
1203 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1204 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1205 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1206
2f5b48c3 1207 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1208
1209 /* Process attr changes if in IDLE */
1210 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1211 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1212 ret = -EIO;
1213 goto out;
1214 }
1215 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1216 newattr.enable_rdma_read = attrs->enable_rdma_read;
1217 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1218 newattr.enable_rdma_write = attrs->enable_rdma_write;
1219 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1220 newattr.enable_bind = attrs->enable_bind;
1221 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1222 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1223 ret = -EINVAL;
1224 goto out;
1225 }
1226 newattr.max_ord = attrs->max_ord;
1227 }
1228 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1229 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1230 ret = -EINVAL;
1231 goto out;
1232 }
1233 newattr.max_ird = attrs->max_ird;
1234 }
1235 qhp->attr = newattr;
1236 }
1237
2c974781
VP		 1238 if (mask & C4IW_QP_ATTR_SQ_DB) {
1239 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1240 goto out;
1241 }
1242 if (mask & C4IW_QP_ATTR_RQ_DB) {
1243 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1244 goto out;
1245 }
1246
cfdda9d7
SW		 1247 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1248 goto out;
1249 if (qhp->attr.state == attrs->next_state)
1250 goto out;
1251
1252 switch (qhp->attr.state) {
1253 case C4IW_QP_STATE_IDLE:
1254 switch (attrs->next_state) {
1255 case C4IW_QP_STATE_RTS:
1256 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1257 ret = -EINVAL;
1258 goto out;
1259 }
1260 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1261 ret = -EINVAL;
1262 goto out;
1263 }
1264 qhp->attr.mpa_attr = attrs->mpa_attr;
1265 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1266 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1267 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1268
1269 /*
1270 * Ref the endpoint here and deref when we
1271 * disassociate the endpoint from the QP. This
1272 * happens in CLOSING->IDLE transition or *->ERROR
1273 * transition.
1274 */
1275 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1276 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1277 if (ret)
1278 goto err;
1279 break;
1280 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1281 set_state(qhp, C4IW_QP_STATE_ERROR);
1282 flush_qp(qhp);
cfdda9d7
SW		 1283 break;
1284 default:
1285 ret = -EINVAL;
1286 goto out;
1287 }
1288 break;
1289 case C4IW_QP_STATE_RTS:
1290 switch (attrs->next_state) {
1291 case C4IW_QP_STATE_CLOSING:
1292 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
2f5b48c3 1293 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1294 ep = qhp->ep;
cfdda9d7
SW		 1295 if (!internal) {
1296 abort = 0;
1297 disconnect = 1;
2f5b48c3 1298 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1299 }
d32ae393
TT		 1300 if (qhp->ibqp.uobject)
1301 t4_set_wq_in_error(&qhp->wq);
73d6fcad 1302 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1303 if (ret)
cfdda9d7 1304 goto err;
cfdda9d7
SW		 1305 break;
1306 case C4IW_QP_STATE_TERMINATE:
2f5b48c3 1307 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1308 qhp->attr.layer_etype = attrs->layer_etype;
1309 qhp->attr.ecode = attrs->ecode;
cfdda9d7
SW		 1310 if (qhp->ibqp.uobject)
1311 t4_set_wq_in_error(&qhp->wq);
be4c9bad 1312 ep = qhp->ep;
0e42c1f4
SW		 1313 if (!internal)
1314 terminate = 1;
be4c9bad 1315 disconnect = 1;
2f5b48c3 1316 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1317 break;
1318 case C4IW_QP_STATE_ERROR:
2f5b48c3 1319 set_state(qhp, C4IW_QP_STATE_ERROR);
d32ae393
TT		 1320 if (qhp->ibqp.uobject)
1321 t4_set_wq_in_error(&qhp->wq);
cfdda9d7
SW		 1322 if (!internal) {
1323 abort = 1;
1324 disconnect = 1;
1325 ep = qhp->ep;
2f5b48c3 1326 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1327 }
1328 goto err;
1329 break;
1330 default:
1331 ret = -EINVAL;
1332 goto out;
1333 }
1334 break;
1335 case C4IW_QP_STATE_CLOSING:
1336 if (!internal) {
1337 ret = -EINVAL;
1338 goto out;
1339 }
1340 switch (attrs->next_state) {
1341 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1342 flush_qp(qhp);
1343 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1344 qhp->attr.llp_stream_handle = NULL;
1345 c4iw_put_ep(&qhp->ep->com);
1346 qhp->ep = NULL;
1347 wake_up(&qhp->wait);
1348 break;
1349 case C4IW_QP_STATE_ERROR:
1350 goto err;
1351 default:
1352 ret = -EINVAL;
1353 goto err;
1354 }
1355 break;
1356 case C4IW_QP_STATE_ERROR:
1357 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1358 ret = -EINVAL;
1359 goto out;
1360 }
1361 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1362 ret = -EINVAL;
1363 goto out;
1364 }
2f5b48c3 1365 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1366 break;
1367 case C4IW_QP_STATE_TERMINATE:
1368 if (!internal) {
1369 ret = -EINVAL;
1370 goto out;
1371 }
1372 goto err;
1373 break;
1374 default:
1375 printk(KERN_ERR "%s in a bad state %d\n",
1376 __func__, qhp->attr.state);
1377 ret = -EINVAL;
1378 goto err;
1379 break;
1380 }
1381 goto out;
1382err:
1383 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1384 qhp->wq.sq.qid);
1385
1386 /* disassociate the LLP connection */
1387 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1388 if (!ep)
1389 ep = qhp->ep;
cfdda9d7 1390 qhp->ep = NULL;
2f5b48c3 1391 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7 1392 free = 1;
91e9c071 1393 abort = 1;
cfdda9d7
SW		 1394 wake_up(&qhp->wait);
1395 BUG_ON(!ep);
2f5b48c3 1396 flush_qp(qhp);
cfdda9d7 1397out:
2f5b48c3 1398 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1399
1400 if (terminate)
be4c9bad 1401 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1402
1403 /*
1404 * If disconnect is 1, then we need to initiate a disconnect
1405 * on the EP. This can be a normal close (RTS->CLOSING) or
1406 * an abnormal close (RTS/CLOSING->ERROR).
1407 */
1408 if (disconnect) {
be4c9bad
RD		 1409 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1410 GFP_KERNEL);
cfdda9d7
SW		 1411 c4iw_put_ep(&ep->com);
1412 }
1413
1414 /*
1415 * If free is 1, then we've disassociated the EP from the QP
1416 * and we need to dereference the EP.
1417 */
1418 if (free)
1419 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1420 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1421 return ret;
1422}
1423
422eea0a
VP		 1424static int enable_qp_db(int id, void *p, void *data)
1425{
1426 struct c4iw_qp *qp = p;
1427
1428 t4_enable_wq_db(&qp->wq);
1429 return 0;
1430}
1431
cfdda9d7
SW		 1432int c4iw_destroy_qp(struct ib_qp *ib_qp)
1433{
1434 struct c4iw_dev *rhp;
1435 struct c4iw_qp *qhp;
1436 struct c4iw_qp_attributes attrs;
1437 struct c4iw_ucontext *ucontext;
1438
1439 qhp = to_c4iw_qp(ib_qp);
1440 rhp = qhp->rhp;
1441
1442 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1443 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1444 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1445 else
1446 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1447 wait_event(qhp->wait, !qhp->ep);
1448
422eea0a
VP		 1449 spin_lock_irq(&rhp->lock);
1450 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1451 rhp->qpcnt--;
1452 BUG_ON(rhp->qpcnt < 0);
1453 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1454 rhp->rdev.stats.db_state_transitions++;
1455 rhp->db_state = NORMAL;
1456 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1457 }
80ccdd60
VP		 1458 if (db_coalescing_threshold >= 0)
1459 if (rhp->qpcnt <= db_coalescing_threshold)
1460 cxgb4_enable_db_coalescing(rhp->rdev.lldi.ports[0]);
422eea0a 1461 spin_unlock_irq(&rhp->lock);
cfdda9d7
SW		 1462 atomic_dec(&qhp->refcnt);
1463 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1464
1465 ucontext = ib_qp->uobject ?
1466 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1467 destroy_qp(&rhp->rdev, &qhp->wq,
1468 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1469
1470 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1471 kfree(qhp);
1472 return 0;
1473}
1474
422eea0a
VP		 1475static int disable_qp_db(int id, void *p, void *data)
1476{
1477 struct c4iw_qp *qp = p;
1478
1479 t4_disable_wq_db(&qp->wq);
1480 return 0;
1481}
1482
cfdda9d7
SW		 1483struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1484 struct ib_udata *udata)
1485{
1486 struct c4iw_dev *rhp;
1487 struct c4iw_qp *qhp;
1488 struct c4iw_pd *php;
1489 struct c4iw_cq *schp;
1490 struct c4iw_cq *rchp;
1491 struct c4iw_create_qp_resp uresp;
1492 int sqsize, rqsize;
1493 struct c4iw_ucontext *ucontext;
1494 int ret;
c6d7b267 1495 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1496
1497 PDBG("%s ib_pd %p\n", __func__, pd);
1498
1499 if (attrs->qp_type != IB_QPT_RC)
1500 return ERR_PTR(-EINVAL);
1501
1502 php = to_c4iw_pd(pd);
1503 rhp = php->rhp;
1504 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1505 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1506 if (!schp || !rchp)
1507 return ERR_PTR(-EINVAL);
1508
1509 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1510 return ERR_PTR(-EINVAL);
1511
1512 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1513 if (rqsize > T4_MAX_RQ_SIZE)
1514 return ERR_PTR(-E2BIG);
1515
1516 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1517 if (sqsize > T4_MAX_SQ_SIZE)
1518 return ERR_PTR(-E2BIG);
1519
1520 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1521
1522
1523 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1524 if (!qhp)
1525 return ERR_PTR(-ENOMEM);
1526 qhp->wq.sq.size = sqsize;
1527 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1528 qhp->wq.rq.size = rqsize;
1529 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1530
1531 if (ucontext) {
1532 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1533 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1534 }
1535
1536 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1537 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1538
1539 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1540 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1541 if (ret)
1542 goto err1;
1543
1544 attrs->cap.max_recv_wr = rqsize - 1;
1545 attrs->cap.max_send_wr = sqsize - 1;
1546 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1547
1548 qhp->rhp = rhp;
1549 qhp->attr.pd = php->pdid;
1550 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1551 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1552 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1553 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1554 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1555 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1556 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1557 qhp->attr.state = C4IW_QP_STATE_IDLE;
1558 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1559 qhp->attr.enable_rdma_read = 1;
1560 qhp->attr.enable_rdma_write = 1;
1561 qhp->attr.enable_bind = 1;
1562 qhp->attr.max_ord = 1;
1563 qhp->attr.max_ird = 1;
1564 spin_lock_init(&qhp->lock);
2f5b48c3 1565 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1566 init_waitqueue_head(&qhp->wait);
1567 atomic_set(&qhp->refcnt, 1);
1568
2c974781
VP		 1569 spin_lock_irq(&rhp->lock);
1570 if (rhp->db_state != NORMAL)
1571 t4_disable_wq_db(&qhp->wq);
3cbdb928
VP		 1572 rhp->qpcnt++;
1573 if (rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
422eea0a
VP		 1574 rhp->rdev.stats.db_state_transitions++;
1575 rhp->db_state = FLOW_CONTROL;
1576 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1577 }
80ccdd60
VP		 1578 if (db_coalescing_threshold >= 0)
1579 if (rhp->qpcnt > db_coalescing_threshold)
1580 cxgb4_disable_db_coalescing(rhp->rdev.lldi.ports[0]);
2c974781
VP		 1581 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1582 spin_unlock_irq(&rhp->lock);
cfdda9d7
SW		 1583 if (ret)
1584 goto err2;
1585
cfdda9d7
SW		 1586 if (udata) {
1587 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1588 if (!mm1) {
1589 ret = -ENOMEM;
30a6a62f 1590 goto err3;
cfdda9d7
SW		 1591 }
1592 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1593 if (!mm2) {
1594 ret = -ENOMEM;
30a6a62f 1595 goto err4;
cfdda9d7
SW		 1596 }
1597 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1598 if (!mm3) {
1599 ret = -ENOMEM;
30a6a62f 1600 goto err5;
cfdda9d7
SW		 1601 }
1602 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1603 if (!mm4) {
1604 ret = -ENOMEM;
30a6a62f 1605 goto err6;
cfdda9d7 1606 }
c6d7b267
SW		 1607 if (t4_sq_onchip(&qhp->wq.sq)) {
1608 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1609 if (!mm5) {
1610 ret = -ENOMEM;
1611 goto err7;
1612 }
1613 uresp.flags = C4IW_QPF_ONCHIP;
1614 } else
1615 uresp.flags = 0;
cfdda9d7
SW		 1616 uresp.qid_mask = rhp->rdev.qpmask;
1617 uresp.sqid = qhp->wq.sq.qid;
1618 uresp.sq_size = qhp->wq.sq.size;
1619 uresp.sq_memsize = qhp->wq.sq.memsize;
1620 uresp.rqid = qhp->wq.rq.qid;
1621 uresp.rq_size = qhp->wq.rq.size;
1622 uresp.rq_memsize = qhp->wq.rq.memsize;
1623 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1624 if (mm5) {
1625 uresp.ma_sync_key = ucontext->key;
1626 ucontext->key += PAGE_SIZE;
1627 }
cfdda9d7
SW		 1628 uresp.sq_key = ucontext->key;
1629 ucontext->key += PAGE_SIZE;
1630 uresp.rq_key = ucontext->key;
1631 ucontext->key += PAGE_SIZE;
1632 uresp.sq_db_gts_key = ucontext->key;
1633 ucontext->key += PAGE_SIZE;
1634 uresp.rq_db_gts_key = ucontext->key;
1635 ucontext->key += PAGE_SIZE;
1636 spin_unlock(&ucontext->mmap_lock);
1637 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1638 if (ret)
c6d7b267 1639 goto err8;
cfdda9d7 1640 mm1->key = uresp.sq_key;
c6d7b267 1641 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1642 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1643 insert_mmap(ucontext, mm1);
1644 mm2->key = uresp.rq_key;
1645 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1646 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1647 insert_mmap(ucontext, mm2);
1648 mm3->key = uresp.sq_db_gts_key;
1649 mm3->addr = qhp->wq.sq.udb;
1650 mm3->len = PAGE_SIZE;
1651 insert_mmap(ucontext, mm3);
1652 mm4->key = uresp.rq_db_gts_key;
1653 mm4->addr = qhp->wq.rq.udb;
1654 mm4->len = PAGE_SIZE;
1655 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1656 if (mm5) {
1657 mm5->key = uresp.ma_sync_key;
1658 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1659 + A_PCIE_MA_SYNC) & PAGE_MASK;
1660 mm5->len = PAGE_SIZE;
1661 insert_mmap(ucontext, mm5);
1662 }
cfdda9d7
SW		 1663 }
1664 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1665 init_timer(&(qhp->timer));
1666 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1667 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1668 qhp->wq.sq.qid);
1669 return &qhp->ibqp;
c6d7b267
SW		 1670err8:
1671 kfree(mm5);
cfdda9d7 1672err7:
30a6a62f 1673 kfree(mm4);
cfdda9d7 1674err6:
30a6a62f 1675 kfree(mm3);
cfdda9d7 1676err5:
30a6a62f 1677 kfree(mm2);
cfdda9d7 1678err4:
30a6a62f 1679 kfree(mm1);
cfdda9d7
SW		 1680err3:
1681 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1682err2:
1683 destroy_qp(&rhp->rdev, &qhp->wq,
1684 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1685err1:
1686 kfree(qhp);
1687 return ERR_PTR(ret);
1688}
1689
1690int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1691 int attr_mask, struct ib_udata *udata)
1692{
1693 struct c4iw_dev *rhp;
1694 struct c4iw_qp *qhp;
1695 enum c4iw_qp_attr_mask mask = 0;
1696 struct c4iw_qp_attributes attrs;
1697
1698 PDBG("%s ib_qp %p\n", __func__, ibqp);
1699
1700 /* iwarp does not support the RTR state */
1701 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1702 attr_mask &= ~IB_QP_STATE;
1703
1704 /* Make sure we still have something left to do */
1705 if (!attr_mask)
1706 return 0;
1707
1708 memset(&attrs, 0, sizeof attrs);
1709 qhp = to_c4iw_qp(ibqp);
1710 rhp = qhp->rhp;
1711
1712 attrs.next_state = c4iw_convert_state(attr->qp_state);
1713 attrs.enable_rdma_read = (attr->qp_access_flags &
1714 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1715 attrs.enable_rdma_write = (attr->qp_access_flags &
1716 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1717 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1718
1719
1720 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1721 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1722 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1723 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1724 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1725
2c974781
VP		 1726 /*
1727 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1728 * ringing the queue db when we're in DB_FULL mode.
1729 */
1730 attrs.sq_db_inc = attr->sq_psn;
1731 attrs.rq_db_inc = attr->rq_psn;
1732 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1733 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1734
cfdda9d7
SW		 1735 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1736}
1737
1738struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1739{
1740 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1741 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1742}
67bbc055
VP		 1743
1744int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1745 int attr_mask, struct ib_qp_init_attr *init_attr)
1746{
1747 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1748
1749 memset(attr, 0, sizeof *attr);
1750 memset(init_attr, 0, sizeof *init_attr);
1751 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1752 return 0;
1753}
Linux 6.x block layer and io_uring tree(s)