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cxgb4/iw_cxgb4: Treat CPL_ERR_KEEPALV_NEG_ADVICE as negative advice
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
3cbdb928 45int db_fc_threshold = 1000;
422eea0a 46module_param(db_fc_threshold, int, 0644);
3cbdb928
VP		 47MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51int db_coalescing_threshold;
52module_param(db_coalescing_threshold, int, 0644);
53MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
422eea0a 56
42b6a949
VP		 57static int max_fr_immd = T4_MAX_FR_IMMD;
58module_param(max_fr_immd, int, 0644);
59MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
2f5b48c3
SW		 61static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
62{
63 unsigned long flag;
64 spin_lock_irqsave(&qhp->lock, flag);
65 qhp->attr.state = state;
66 spin_unlock_irqrestore(&qhp->lock, flag);
67}
68
c6d7b267
SW		 69static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
70{
71 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
72}
73
74static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
75{
76 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
77 pci_unmap_addr(sq, mapping));
78}
79
80static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 if (t4_sq_onchip(sq))
83 dealloc_oc_sq(rdev, sq);
84 else
85 dealloc_host_sq(rdev, sq);
86}
87
88static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
89{
f079af7a 90 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
c6d7b267
SW		 91 return -ENOSYS;
92 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
93 if (!sq->dma_addr)
94 return -ENOMEM;
95 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
96 rdev->lldi.vr->ocq.start;
97 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
98 rdev->lldi.vr->ocq.start);
99 sq->flags |= T4_SQ_ONCHIP;
100 return 0;
101}
102
103static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
104{
105 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
106 &(sq->dma_addr), GFP_KERNEL);
107 if (!sq->queue)
108 return -ENOMEM;
109 sq->phys_addr = virt_to_phys(sq->queue);
110 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
111 return 0;
112}
113
5b0c2759
TLSC		 114static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
115{
116 int ret = -ENOSYS;
117 if (user)
118 ret = alloc_oc_sq(rdev, sq);
119 if (ret)
120 ret = alloc_host_sq(rdev, sq);
121 return ret;
122}
123
cfdda9d7
SW		 124static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct c4iw_dev_ucontext *uctx)
126{
127 /*
128 * uP clears EQ contexts when the connection exits rdma mode,
129 * so no need to post a RESET WR for these EQs.
130 */
131 dma_free_coherent(&(rdev->lldi.pdev->dev),
132 wq->rq.memsize, wq->rq.queue,
f38926aa 133 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 134 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 135 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
136 kfree(wq->rq.sw_rq);
137 kfree(wq->sq.sw_sq);
138 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
139 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
140 return 0;
141}
142
143static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 struct t4_cq *rcq, struct t4_cq *scq,
145 struct c4iw_dev_ucontext *uctx)
146{
147 int user = (uctx != &rdev->uctx);
148 struct fw_ri_res_wr *res_wr;
149 struct fw_ri_res *res;
150 int wr_len;
151 struct c4iw_wr_wait wr_wait;
152 struct sk_buff *skb;
9919d5bd 153 int ret = 0;
cfdda9d7
SW		 154 int eqsize;
155
156 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
157 if (!wq->sq.qid)
158 return -ENOMEM;
159
160 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
c079c287
EG		 161 if (!wq->rq.qid) {
162 ret = -ENOMEM;
163 goto free_sq_qid;
164 }
cfdda9d7
SW		 165
166 if (!user) {
167 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
168 GFP_KERNEL);
c079c287
EG		 169 if (!wq->sq.sw_sq) {
170 ret = -ENOMEM;
171 goto free_rq_qid;
172 }
cfdda9d7
SW		 173
174 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
175 GFP_KERNEL);
c079c287
EG		 176 if (!wq->rq.sw_rq) {
177 ret = -ENOMEM;
178 goto free_sw_sq;
179 }
cfdda9d7
SW		 180 }
181
182 /*
183 * RQT must be a power of 2.
184 */
185 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
186 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
c079c287
EG		 187 if (!wq->rq.rqt_hwaddr) {
188 ret = -ENOMEM;
189 goto free_sw_rq;
190 }
cfdda9d7 191
5b0c2759
TLSC		 192 ret = alloc_sq(rdev, &wq->sq, user);
193 if (ret)
194 goto free_hwaddr;
cfdda9d7 195 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 196 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 197
198 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
199 wq->rq.memsize, &(wq->rq.dma_addr),
200 GFP_KERNEL);
55e57a78
WY		 201 if (!wq->rq.queue) {
202 ret = -ENOMEM;
c079c287 203 goto free_sq;
55e57a78 204 }
cfdda9d7
SW		 205 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
206 __func__, wq->sq.queue,
207 (unsigned long long)virt_to_phys(wq->sq.queue),
208 wq->rq.queue,
209 (unsigned long long)virt_to_phys(wq->rq.queue));
210 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 211 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 212
213 wq->db = rdev->lldi.db_reg;
214 wq->gts = rdev->lldi.gts_reg;
215 if (user) {
216 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
217 (wq->sq.qid << rdev->qpshift);
218 wq->sq.udb &= PAGE_MASK;
219 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
220 (wq->rq.qid << rdev->qpshift);
221 wq->rq.udb &= PAGE_MASK;
222 }
223 wq->rdev = rdev;
224 wq->rq.msn = 1;
225
226 /* build fw_ri_res_wr */
227 wr_len = sizeof *res_wr + 2 * sizeof *res;
228
d3c814e8 229 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 230 if (!skb) {
231 ret = -ENOMEM;
c079c287 232 goto free_dma;
cfdda9d7
SW		 233 }
234 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
235
236 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
237 memset(res_wr, 0, wr_len);
238 res_wr->op_nres = cpu_to_be32(
239 FW_WR_OP(FW_RI_RES_WR) |
240 V_FW_RI_RES_WR_NRES(2) |
241 FW_WR_COMPL(1));
242 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 243 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 244 res = res_wr->res;
245 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
246 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
247
248 /*
249 * eqsize is the number of 64B entries plus the status page size.
250 */
251 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
252
253 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
254 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
255 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
256 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 257 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 258 V_FW_RI_RES_WR_IQID(scq->cqid));
259 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
260 V_FW_RI_RES_WR_DCAEN(0) |
261 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 262 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 263 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 264 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
265 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
266 V_FW_RI_RES_WR_EQSIZE(eqsize));
267 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
268 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
269 res++;
270 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
271 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
272
273 /*
274 * eqsize is the number of 64B entries plus the status page size.
275 */
276 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
277 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
278 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
279 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
280 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
281 V_FW_RI_RES_WR_IQID(rcq->cqid));
282 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
283 V_FW_RI_RES_WR_DCAEN(0) |
284 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 285 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 286 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 287 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
288 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
289 V_FW_RI_RES_WR_EQSIZE(eqsize));
290 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
291 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
292
293 c4iw_init_wr_wait(&wr_wait);
294
295 ret = c4iw_ofld_send(rdev, skb);
296 if (ret)
c079c287 297 goto free_dma;
aadc4df3 298 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7 299 if (ret)
c079c287 300 goto free_dma;
cfdda9d7
SW		 301
302 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
303 __func__, wq->sq.qid, wq->rq.qid, wq->db,
304 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
305
306 return 0;
c079c287 307free_dma:
cfdda9d7
SW		 308 dma_free_coherent(&(rdev->lldi.pdev->dev),
309 wq->rq.memsize, wq->rq.queue,
f38926aa 310 dma_unmap_addr(&wq->rq, mapping));
c079c287 311free_sq:
c6d7b267 312 dealloc_sq(rdev, &wq->sq);
c079c287 313free_hwaddr:
cfdda9d7 314 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
c079c287 315free_sw_rq:
cfdda9d7 316 kfree(wq->rq.sw_rq);
c079c287 317free_sw_sq:
cfdda9d7 318 kfree(wq->sq.sw_sq);
c079c287 319free_rq_qid:
cfdda9d7 320 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
c079c287 321free_sq_qid:
cfdda9d7 322 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
c079c287 323 return ret;
cfdda9d7
SW		 324}
325
d37ac31d
SW		 326static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
327 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 328{
d37ac31d
SW		 329 u8 *dstp, *srcp;
330 u32 plen = 0;
cfdda9d7 331 int i;
d37ac31d
SW		 332 int rem, len;
333
334 dstp = (u8 *)immdp->data;
335 for (i = 0; i < wr->num_sge; i++) {
336 if ((plen + wr->sg_list[i].length) > max)
337 return -EMSGSIZE;
338 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
339 plen += wr->sg_list[i].length;
340 rem = wr->sg_list[i].length;
341 while (rem) {
342 if (dstp == (u8 *)&sq->queue[sq->size])
343 dstp = (u8 *)sq->queue;
344 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
345 len = rem;
346 else
347 len = (u8 *)&sq->queue[sq->size] - dstp;
348 memcpy(dstp, srcp, len);
349 dstp += len;
350 srcp += len;
351 rem -= len;
352 }
353 }
13fecb83
SW		 354 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
355 if (len)
356 memset(dstp, 0, len);
d37ac31d
SW		 357 immdp->op = FW_RI_DATA_IMMD;
358 immdp->r1 = 0;
359 immdp->r2 = 0;
360 immdp->immdlen = cpu_to_be32(plen);
361 *plenp = plen;
362 return 0;
363}
364
365static int build_isgl(__be64 *queue_start, __be64 *queue_end,
366 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
367 int num_sge, u32 *plenp)
368
369{
370 int i;
371 u32 plen = 0;
372 __be64 *flitp = (__be64 *)isglp->sge;
373
374 for (i = 0; i < num_sge; i++) {
375 if ((plen + sg_list[i].length) < plen)
376 return -EMSGSIZE;
377 plen += sg_list[i].length;
378 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
379 sg_list[i].length);
380 if (++flitp == queue_end)
381 flitp = queue_start;
382 *flitp = cpu_to_be64(sg_list[i].addr);
383 if (++flitp == queue_end)
384 flitp = queue_start;
385 }
13fecb83 386 *flitp = (__force __be64)0;
d37ac31d
SW		 387 isglp->op = FW_RI_DATA_ISGL;
388 isglp->r1 = 0;
389 isglp->nsge = cpu_to_be16(num_sge);
390 isglp->r2 = 0;
391 if (plenp)
392 *plenp = plen;
393 return 0;
394}
395
396static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
397 struct ib_send_wr *wr, u8 *len16)
398{
cfdda9d7
SW		 399 u32 plen;
400 int size;
d37ac31d 401 int ret;
cfdda9d7
SW		 402
403 if (wr->num_sge > T4_MAX_SEND_SGE)
404 return -EINVAL;
405 switch (wr->opcode) {
406 case IB_WR_SEND:
407 if (wr->send_flags & IB_SEND_SOLICITED)
408 wqe->send.sendop_pkd = cpu_to_be32(
409 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
410 else
411 wqe->send.sendop_pkd = cpu_to_be32(
412 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
413 wqe->send.stag_inv = 0;
414 break;
415 case IB_WR_SEND_WITH_INV:
416 if (wr->send_flags & IB_SEND_SOLICITED)
417 wqe->send.sendop_pkd = cpu_to_be32(
418 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
419 else
420 wqe->send.sendop_pkd = cpu_to_be32(
421 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
422 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
423 break;
424
425 default:
426 return -EINVAL;
427 }
d37ac31d 428
cfdda9d7
SW		 429 plen = 0;
430 if (wr->num_sge) {
431 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 432 ret = build_immd(sq, wqe->send.u.immd_src, wr,
433 T4_MAX_SEND_INLINE, &plen);
434 if (ret)
435 return ret;
cfdda9d7
SW		 436 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
437 plen;
438 } else {
d37ac31d
SW		 439 ret = build_isgl((__be64 *)sq->queue,
440 (__be64 *)&sq->queue[sq->size],
441 wqe->send.u.isgl_src,
442 wr->sg_list, wr->num_sge, &plen);
443 if (ret)
444 return ret;
cfdda9d7
SW		 445 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
446 wr->num_sge * sizeof(struct fw_ri_sge);
447 }
448 } else {
449 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
450 wqe->send.u.immd_src[0].r1 = 0;
451 wqe->send.u.immd_src[0].r2 = 0;
452 wqe->send.u.immd_src[0].immdlen = 0;
453 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 454 plen = 0;
cfdda9d7
SW		 455 }
456 *len16 = DIV_ROUND_UP(size, 16);
457 wqe->send.plen = cpu_to_be32(plen);
458 return 0;
459}
460
d37ac31d
SW		 461static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
462 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 463{
cfdda9d7
SW		 464 u32 plen;
465 int size;
d37ac31d 466 int ret;
cfdda9d7 467
d37ac31d 468 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 469 return -EINVAL;
470 wqe->write.r2 = 0;
471 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
472 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 473 if (wr->num_sge) {
474 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 475 ret = build_immd(sq, wqe->write.u.immd_src, wr,
476 T4_MAX_WRITE_INLINE, &plen);
477 if (ret)
478 return ret;
cfdda9d7
SW		 479 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
480 plen;
481 } else {
d37ac31d
SW		 482 ret = build_isgl((__be64 *)sq->queue,
483 (__be64 *)&sq->queue[sq->size],
484 wqe->write.u.isgl_src,
485 wr->sg_list, wr->num_sge, &plen);
486 if (ret)
487 return ret;
cfdda9d7
SW		 488 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
489 wr->num_sge * sizeof(struct fw_ri_sge);
490 }
491 } else {
492 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
493 wqe->write.u.immd_src[0].r1 = 0;
494 wqe->write.u.immd_src[0].r2 = 0;
495 wqe->write.u.immd_src[0].immdlen = 0;
496 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 497 plen = 0;
cfdda9d7
SW		 498 }
499 *len16 = DIV_ROUND_UP(size, 16);
500 wqe->write.plen = cpu_to_be32(plen);
501 return 0;
502}
503
504static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
505{
506 if (wr->num_sge > 1)
507 return -EINVAL;
508 if (wr->num_sge) {
509 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
510 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
511 >> 32));
512 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
513 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
514 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
515 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
516 >> 32));
517 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
518 } else {
519 wqe->read.stag_src = cpu_to_be32(2);
520 wqe->read.to_src_hi = 0;
521 wqe->read.to_src_lo = 0;
522 wqe->read.stag_sink = cpu_to_be32(2);
523 wqe->read.plen = 0;
524 wqe->read.to_sink_hi = 0;
525 wqe->read.to_sink_lo = 0;
526 }
527 wqe->read.r2 = 0;
528 wqe->read.r5 = 0;
529 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
530 return 0;
531}
532
533static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
534 struct ib_recv_wr *wr, u8 *len16)
535{
d37ac31d 536 int ret;
cfdda9d7 537
d37ac31d
SW		 538 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
539 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
540 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
541 if (ret)
542 return ret;
cfdda9d7
SW		 543 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
544 wr->num_sge * sizeof(struct fw_ri_sge), 16);
545 return 0;
546}
547
40dbf6ee 548static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
42b6a949 549 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
cfdda9d7
SW		 550{
551
552 struct fw_ri_immd *imdp;
553 __be64 *p;
554 int i;
555 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 556 int rem;
cfdda9d7
SW		 557
558 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
559 return -EINVAL;
560
561 wqe->fr.qpbinde_to_dcacpu = 0;
562 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
563 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
564 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
565 wqe->fr.len_hi = 0;
566 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
567 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
568 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
569 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
570 0xffffffff);
42b6a949
VP		 571
572 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
573 struct c4iw_fr_page_list *c4pl =
574 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
575 struct fw_ri_dsgl *sglp;
576
577 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
578 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
579 cpu_to_be64((u64)
580 wr->wr.fast_reg.page_list->page_list[i]);
581 }
582
583 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
584 sglp->op = FW_RI_DATA_DSGL;
585 sglp->r1 = 0;
586 sglp->nsge = cpu_to_be16(1);
587 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
588 sglp->len0 = cpu_to_be32(pbllen);
589
590 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
591 } else {
592 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
593 imdp->op = FW_RI_DATA_IMMD;
594 imdp->r1 = 0;
595 imdp->r2 = 0;
596 imdp->immdlen = cpu_to_be32(pbllen);
597 p = (__be64 *)(imdp + 1);
598 rem = pbllen;
599 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
600 *p = cpu_to_be64(
601 (u64)wr->wr.fast_reg.page_list->page_list[i]);
602 rem -= sizeof(*p);
603 if (++p == (__be64 *)&sq->queue[sq->size])
604 p = (__be64 *)sq->queue;
605 }
606 BUG_ON(rem < 0);
607 while (rem) {
608 *p = 0;
609 rem -= sizeof(*p);
610 if (++p == (__be64 *)&sq->queue[sq->size])
611 p = (__be64 *)sq->queue;
612 }
613 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
614 + pbllen, 16);
cfdda9d7
SW		 615 }
616 return 0;
617}
618
619static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
620 u8 *len16)
621{
622 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
623 wqe->inv.r2 = 0;
624 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
625 return 0;
626}
627
628void c4iw_qp_add_ref(struct ib_qp *qp)
629{
630 PDBG("%s ib_qp %p\n", __func__, qp);
631 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
632}
633
634void c4iw_qp_rem_ref(struct ib_qp *qp)
635{
636 PDBG("%s ib_qp %p\n", __func__, qp);
637 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
638 wake_up(&(to_c4iw_qp(qp)->wait));
639}
640
641int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
642 struct ib_send_wr **bad_wr)
643{
644 int err = 0;
645 u8 len16 = 0;
646 enum fw_wr_opcodes fw_opcode = 0;
647 enum fw_ri_wr_flags fw_flags;
648 struct c4iw_qp *qhp;
649 union t4_wr *wqe;
650 u32 num_wrs;
651 struct t4_swsqe *swsqe;
652 unsigned long flag;
653 u16 idx = 0;
654
655 qhp = to_c4iw_qp(ibqp);
656 spin_lock_irqsave(&qhp->lock, flag);
657 if (t4_wq_in_error(&qhp->wq)) {
658 spin_unlock_irqrestore(&qhp->lock, flag);
659 return -EINVAL;
660 }
661 num_wrs = t4_sq_avail(&qhp->wq);
662 if (num_wrs == 0) {
663 spin_unlock_irqrestore(&qhp->lock, flag);
664 return -ENOMEM;
665 }
666 while (wr) {
667 if (num_wrs == 0) {
668 err = -ENOMEM;
669 *bad_wr = wr;
670 break;
671 }
d37ac31d
SW		 672 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
673 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
674
cfdda9d7
SW		 675 fw_flags = 0;
676 if (wr->send_flags & IB_SEND_SOLICITED)
677 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
678 if (wr->send_flags & IB_SEND_SIGNALED)
679 fw_flags |= FW_RI_COMPLETION_FLAG;
680 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
681 switch (wr->opcode) {
682 case IB_WR_SEND_WITH_INV:
683 case IB_WR_SEND:
684 if (wr->send_flags & IB_SEND_FENCE)
685 fw_flags |= FW_RI_READ_FENCE_FLAG;
686 fw_opcode = FW_RI_SEND_WR;
687 if (wr->opcode == IB_WR_SEND)
688 swsqe->opcode = FW_RI_SEND;
689 else
690 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 691 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 692 break;
693 case IB_WR_RDMA_WRITE:
694 fw_opcode = FW_RI_RDMA_WRITE_WR;
695 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 696 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 697 break;
698 case IB_WR_RDMA_READ:
2f1fb507 699 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 700 fw_opcode = FW_RI_RDMA_READ_WR;
701 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 702 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 703 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 704 else
705 fw_flags = 0;
cfdda9d7
SW		 706 err = build_rdma_read(wqe, wr, &len16);
707 if (err)
708 break;
709 swsqe->read_len = wr->sg_list[0].length;
710 if (!qhp->wq.sq.oldest_read)
711 qhp->wq.sq.oldest_read = swsqe;
712 break;
713 case IB_WR_FAST_REG_MR:
714 fw_opcode = FW_RI_FR_NSMR_WR;
715 swsqe->opcode = FW_RI_FAST_REGISTER;
42b6a949
VP		 716 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
717 is_t5(
718 qhp->rhp->rdev.lldi.adapter_type) ?
719 1 : 0);
cfdda9d7
SW		 720 break;
721 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 722 if (wr->send_flags & IB_SEND_FENCE)
723 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 724 fw_opcode = FW_RI_INV_LSTAG_WR;
725 swsqe->opcode = FW_RI_LOCAL_INV;
726 err = build_inv_stag(wqe, wr, &len16);
727 break;
728 default:
729 PDBG("%s post of type=%d TBD!\n", __func__,
730 wr->opcode);
731 err = -EINVAL;
732 }
733 if (err) {
734 *bad_wr = wr;
735 break;
736 }
737 swsqe->idx = qhp->wq.sq.pidx;
738 swsqe->complete = 0;
739 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
1cf24dce 740 swsqe->flushed = 0;
cfdda9d7
SW		 741 swsqe->wr_id = wr->wr_id;
742
743 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
744
745 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
746 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
747 swsqe->opcode, swsqe->read_len);
748 wr = wr->next;
749 num_wrs--;
d37ac31d
SW		 750 t4_sq_produce(&qhp->wq, len16);
751 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 752 }
753 if (t4_wq_db_enabled(&qhp->wq))
754 t4_ring_sq_db(&qhp->wq, idx);
755 spin_unlock_irqrestore(&qhp->lock, flag);
756 return err;
757}
758
759int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
760 struct ib_recv_wr **bad_wr)
761{
762 int err = 0;
763 struct c4iw_qp *qhp;
764 union t4_recv_wr *wqe;
765 u32 num_wrs;
766 u8 len16 = 0;
767 unsigned long flag;
768 u16 idx = 0;
769
770 qhp = to_c4iw_qp(ibqp);
771 spin_lock_irqsave(&qhp->lock, flag);
772 if (t4_wq_in_error(&qhp->wq)) {
773 spin_unlock_irqrestore(&qhp->lock, flag);
774 return -EINVAL;
775 }
776 num_wrs = t4_rq_avail(&qhp->wq);
777 if (num_wrs == 0) {
778 spin_unlock_irqrestore(&qhp->lock, flag);
779 return -ENOMEM;
780 }
781 while (wr) {
782 if (wr->num_sge > T4_MAX_RECV_SGE) {
783 err = -EINVAL;
784 *bad_wr = wr;
785 break;
786 }
d37ac31d
SW		 787 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
788 qhp->wq.rq.wq_pidx *
789 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 790 if (num_wrs)
791 err = build_rdma_recv(qhp, wqe, wr, &len16);
792 else
793 err = -ENOMEM;
794 if (err) {
795 *bad_wr = wr;
796 break;
797 }
798
799 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
800
801 wqe->recv.opcode = FW_RI_RECV_WR;
802 wqe->recv.r1 = 0;
803 wqe->recv.wrid = qhp->wq.rq.pidx;
804 wqe->recv.r2[0] = 0;
805 wqe->recv.r2[1] = 0;
806 wqe->recv.r2[2] = 0;
807 wqe->recv.len16 = len16;
cfdda9d7
SW		 808 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
809 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 810 t4_rq_produce(&qhp->wq, len16);
811 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 812 wr = wr->next;
813 num_wrs--;
cfdda9d7
SW		 814 }
815 if (t4_wq_db_enabled(&qhp->wq))
816 t4_ring_rq_db(&qhp->wq, idx);
817 spin_unlock_irqrestore(&qhp->lock, flag);
818 return err;
819}
820
821int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
822{
823 return -ENOSYS;
824}
825
826static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
827 u8 *ecode)
828{
829 int status;
830 int tagged;
831 int opcode;
832 int rqtype;
833 int send_inv;
834
835 if (!err_cqe) {
836 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
837 *ecode = 0;
838 return;
839 }
840
841 status = CQE_STATUS(err_cqe);
842 opcode = CQE_OPCODE(err_cqe);
843 rqtype = RQ_TYPE(err_cqe);
844 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
845 (opcode == FW_RI_SEND_WITH_SE_INV);
846 tagged = (opcode == FW_RI_RDMA_WRITE) ||
847 (rqtype && (opcode == FW_RI_READ_RESP));
848
849 switch (status) {
850 case T4_ERR_STAG:
851 if (send_inv) {
852 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
853 *ecode = RDMAP_CANT_INV_STAG;
854 } else {
855 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
856 *ecode = RDMAP_INV_STAG;
857 }
858 break;
859 case T4_ERR_PDID:
860 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
861 if ((opcode == FW_RI_SEND_WITH_INV) ||
862 (opcode == FW_RI_SEND_WITH_SE_INV))
863 *ecode = RDMAP_CANT_INV_STAG;
864 else
865 *ecode = RDMAP_STAG_NOT_ASSOC;
866 break;
867 case T4_ERR_QPID:
868 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
869 *ecode = RDMAP_STAG_NOT_ASSOC;
870 break;
871 case T4_ERR_ACCESS:
872 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
873 *ecode = RDMAP_ACC_VIOL;
874 break;
875 case T4_ERR_WRAP:
876 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
877 *ecode = RDMAP_TO_WRAP;
878 break;
879 case T4_ERR_BOUND:
880 if (tagged) {
881 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
882 *ecode = DDPT_BASE_BOUNDS;
883 } else {
884 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
885 *ecode = RDMAP_BASE_BOUNDS;
886 }
887 break;
888 case T4_ERR_INVALIDATE_SHARED_MR:
889 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
890 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
891 *ecode = RDMAP_CANT_INV_STAG;
892 break;
893 case T4_ERR_ECC:
894 case T4_ERR_ECC_PSTAG:
895 case T4_ERR_INTERNAL_ERR:
896 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
897 *ecode = 0;
898 break;
899 case T4_ERR_OUT_OF_RQE:
900 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
901 *ecode = DDPU_INV_MSN_NOBUF;
902 break;
903 case T4_ERR_PBL_ADDR_BOUND:
904 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
905 *ecode = DDPT_BASE_BOUNDS;
906 break;
907 case T4_ERR_CRC:
908 *layer_type = LAYER_MPA|DDP_LLP;
909 *ecode = MPA_CRC_ERR;
910 break;
911 case T4_ERR_MARKER:
912 *layer_type = LAYER_MPA|DDP_LLP;
913 *ecode = MPA_MARKER_ERR;
914 break;
915 case T4_ERR_PDU_LEN_ERR:
916 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
917 *ecode = DDPU_MSG_TOOBIG;
918 break;
919 case T4_ERR_DDP_VERSION:
920 if (tagged) {
921 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
922 *ecode = DDPT_INV_VERS;
923 } else {
924 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
925 *ecode = DDPU_INV_VERS;
926 }
927 break;
928 case T4_ERR_RDMA_VERSION:
929 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
930 *ecode = RDMAP_INV_VERS;
931 break;
932 case T4_ERR_OPCODE:
933 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
934 *ecode = RDMAP_INV_OPCODE;
935 break;
936 case T4_ERR_DDP_QUEUE_NUM:
937 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
938 *ecode = DDPU_INV_QN;
939 break;
940 case T4_ERR_MSN:
941 case T4_ERR_MSN_GAP:
942 case T4_ERR_MSN_RANGE:
943 case T4_ERR_IRD_OVERFLOW:
944 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
945 *ecode = DDPU_INV_MSN_RANGE;
946 break;
947 case T4_ERR_TBIT:
948 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
949 *ecode = 0;
950 break;
951 case T4_ERR_MO:
952 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
953 *ecode = DDPU_INV_MO;
954 break;
955 default:
956 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
957 *ecode = 0;
958 break;
959 }
960}
961
be4c9bad
RD		 962static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
963 gfp_t gfp)
cfdda9d7
SW		 964{
965 struct fw_ri_wr *wqe;
966 struct sk_buff *skb;
967 struct terminate_message *term;
968
969 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
970 qhp->ep->hwtid);
971
be4c9bad 972 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 973 if (!skb)
be4c9bad 974 return;
cfdda9d7
SW		 975 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
976
977 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
978 memset(wqe, 0, sizeof *wqe);
979 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
980 wqe->flowid_len16 = cpu_to_be32(
981 FW_WR_FLOWID(qhp->ep->hwtid) |
982 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
983
984 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
985 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
986 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 987 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
988 term->layer_etype = qhp->attr.layer_etype;
989 term->ecode = qhp->attr.ecode;
990 } else
991 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 992 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 993}
994
995/*
996 * Assumes qhp lock is held.
997 */
998static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 999 struct c4iw_cq *schp)
cfdda9d7
SW		 1000{
1001 int count;
1002 int flushed;
2f5b48c3 1003 unsigned long flag;
cfdda9d7
SW		 1004
1005 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 1006
732bee7a 1007 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1008 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7 1009 spin_lock(&qhp->lock);
1cf24dce
SW		 1010
1011 if (qhp->wq.flushed) {
1012 spin_unlock(&qhp->lock);
1013 spin_unlock_irqrestore(&rchp->lock, flag);
1014 return;
1015 }
1016 qhp->wq.flushed = 1;
1017
1018 c4iw_flush_hw_cq(rchp);
cfdda9d7
SW		 1019 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1020 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1021 spin_unlock(&qhp->lock);
2f5b48c3 1022 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 1023 if (flushed) {
1024 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 1025 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 1026 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1027 }
cfdda9d7 1028
732bee7a 1029 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1030 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7 1031 spin_lock(&qhp->lock);
1cf24dce
SW		 1032 if (schp != rchp)
1033 c4iw_flush_hw_cq(schp);
1034 flushed = c4iw_flush_sq(qhp);
cfdda9d7 1035 spin_unlock(&qhp->lock);
2f5b48c3 1036 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 1037 if (flushed) {
1038 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 1039 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 1040 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1041 }
cfdda9d7
SW		 1042}
1043
2f5b48c3 1044static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 1045{
1046 struct c4iw_cq *rchp, *schp;
581bbe2c 1047 unsigned long flag;
cfdda9d7 1048
1cf24dce
SW		 1049 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1050 schp = to_c4iw_cq(qhp->ibqp.send_cq);
cfdda9d7 1051
1cf24dce 1052 t4_set_wq_in_error(&qhp->wq);
cfdda9d7 1053 if (qhp->ibqp.uobject) {
cfdda9d7 1054 t4_set_cq_in_error(&rchp->cq);
581bbe2c 1055 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 1056 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 1057 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 1058 if (schp != rchp) {
cfdda9d7 1059 t4_set_cq_in_error(&schp->cq);
581bbe2c 1060 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 1061 (*schp->ibcq.comp_handler)(&schp->ibcq,
1062 schp->ibcq.cq_context);
581bbe2c 1063 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 1064 }
cfdda9d7
SW		 1065 return;
1066 }
2f5b48c3 1067 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1068}
1069
73d6fcad
SW		 1070static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1071 struct c4iw_ep *ep)
cfdda9d7
SW		 1072{
1073 struct fw_ri_wr *wqe;
1074 int ret;
cfdda9d7
SW		 1075 struct sk_buff *skb;
1076
1077 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1078 ep->hwtid);
cfdda9d7 1079
d3c814e8 1080 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1081 if (!skb)
1082 return -ENOMEM;
73d6fcad 1083 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1084
1085 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1086 memset(wqe, 0, sizeof *wqe);
1087 wqe->op_compl = cpu_to_be32(
1088 FW_WR_OP(FW_RI_INIT_WR) |
1089 FW_WR_COMPL(1));
1090 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1091 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1092 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1093 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1094
1095 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1096 ret = c4iw_ofld_send(&rhp->rdev, skb);
1097 if (ret)
1098 goto out;
1099
2f5b48c3 1100 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1101 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1102out:
1103 PDBG("%s ret %d\n", __func__, ret);
1104 return ret;
1105}
1106
1107static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1108{
d2fe99e8 1109 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1110 memset(&init->u, 0, sizeof init->u);
1111 switch (p2p_type) {
1112 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1113 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1114 init->u.write.stag_sink = cpu_to_be32(1);
1115 init->u.write.to_sink = cpu_to_be64(1);
1116 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1117 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1118 sizeof(struct fw_ri_immd),
1119 16);
1120 break;
1121 case FW_RI_INIT_P2PTYPE_READ_REQ:
1122 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1123 init->u.read.stag_src = cpu_to_be32(1);
1124 init->u.read.to_src_lo = cpu_to_be32(1);
1125 init->u.read.stag_sink = cpu_to_be32(1);
1126 init->u.read.to_sink_lo = cpu_to_be32(1);
1127 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1128 break;
1129 }
1130}
1131
1132static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1133{
1134 struct fw_ri_wr *wqe;
1135 int ret;
cfdda9d7
SW		 1136 struct sk_buff *skb;
1137
1138 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1139 qhp->ep->hwtid);
1140
d3c814e8 1141 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1142 if (!skb)
1143 return -ENOMEM;
1144 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1145
1146 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1147 memset(wqe, 0, sizeof *wqe);
1148 wqe->op_compl = cpu_to_be32(
1149 FW_WR_OP(FW_RI_INIT_WR) |
1150 FW_WR_COMPL(1));
1151 wqe->flowid_len16 = cpu_to_be32(
1152 FW_WR_FLOWID(qhp->ep->hwtid) |
1153 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1154
2f5b48c3 1155 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1156
1157 wqe->u.init.type = FW_RI_TYPE_INIT;
1158 wqe->u.init.mpareqbit_p2ptype =
1159 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1160 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1161 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1162 if (qhp->attr.mpa_attr.recv_marker_enabled)
1163 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1164 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1165 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1166 if (qhp->attr.mpa_attr.crc_enabled)
1167 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1168
1169 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1170 FW_RI_QP_RDMA_WRITE_ENABLE |
1171 FW_RI_QP_BIND_ENABLE;
1172 if (!qhp->ibqp.uobject)
1173 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1174 FW_RI_QP_STAG0_ENABLE;
1175 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1176 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1177 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1178 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1179 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1180 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1181 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1182 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1183 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1184 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1185 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1186 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1187 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1188 rhp->rdev.lldi.vr->rq.start);
1189 if (qhp->attr.mpa_attr.initiator)
1190 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1191
cfdda9d7
SW		 1192 ret = c4iw_ofld_send(&rhp->rdev, skb);
1193 if (ret)
1194 goto out;
1195
2f5b48c3
SW		 1196 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1197 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1198out:
1199 PDBG("%s ret %d\n", __func__, ret);
1200 return ret;
1201}
1202
2c974781
VP		 1203/*
1204 * Called by the library when the qp has user dbs disabled due to
1205 * a DB_FULL condition. This function will single-thread all user
1206 * DB rings to avoid overflowing the hw db-fifo.
1207 */
1208static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1209{
1210 int delay = db_delay_usecs;
1211
1212 mutex_lock(&qhp->rhp->db_mutex);
1213 do {
422eea0a
VP		 1214
1215 /*
1216 * The interrupt threshold is dbfifo_int_thresh << 6. So
1217 * make sure we don't cross that and generate an interrupt.
1218 */
1219 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1220 (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
e5619c12 1221 writel(QID(qid) | PIDX(inc), qhp->wq.db);
2c974781
VP		 1222 break;
1223 }
1224 set_current_state(TASK_UNINTERRUPTIBLE);
1225 schedule_timeout(usecs_to_jiffies(delay));
422eea0a 1226 delay = min(delay << 1, 2000);
2c974781
VP		 1227 } while (1);
1228 mutex_unlock(&qhp->rhp->db_mutex);
1229 return 0;
1230}
1231
cfdda9d7
SW		 1232int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1233 enum c4iw_qp_attr_mask mask,
1234 struct c4iw_qp_attributes *attrs,
1235 int internal)
1236{
1237 int ret = 0;
1238 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1239 int disconnect = 0;
1240 int terminate = 0;
1241 int abort = 0;
1242 int free = 0;
1243 struct c4iw_ep *ep = NULL;
1244
1245 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1246 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1247 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1248
2f5b48c3 1249 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1250
1251 /* Process attr changes if in IDLE */
1252 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1253 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1254 ret = -EIO;
1255 goto out;
1256 }
1257 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1258 newattr.enable_rdma_read = attrs->enable_rdma_read;
1259 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1260 newattr.enable_rdma_write = attrs->enable_rdma_write;
1261 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1262 newattr.enable_bind = attrs->enable_bind;
1263 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1264 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1265 ret = -EINVAL;
1266 goto out;
1267 }
1268 newattr.max_ord = attrs->max_ord;
1269 }
1270 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1271 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1272 ret = -EINVAL;
1273 goto out;
1274 }
1275 newattr.max_ird = attrs->max_ird;
1276 }
1277 qhp->attr = newattr;
1278 }
1279
2c974781
VP		 1280 if (mask & C4IW_QP_ATTR_SQ_DB) {
1281 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1282 goto out;
1283 }
1284 if (mask & C4IW_QP_ATTR_RQ_DB) {
1285 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1286 goto out;
1287 }
1288
cfdda9d7
SW		 1289 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1290 goto out;
1291 if (qhp->attr.state == attrs->next_state)
1292 goto out;
1293
1294 switch (qhp->attr.state) {
1295 case C4IW_QP_STATE_IDLE:
1296 switch (attrs->next_state) {
1297 case C4IW_QP_STATE_RTS:
1298 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1299 ret = -EINVAL;
1300 goto out;
1301 }
1302 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1303 ret = -EINVAL;
1304 goto out;
1305 }
1306 qhp->attr.mpa_attr = attrs->mpa_attr;
1307 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1308 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1309 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1310
1311 /*
1312 * Ref the endpoint here and deref when we
1313 * disassociate the endpoint from the QP. This
1314 * happens in CLOSING->IDLE transition or *->ERROR
1315 * transition.
1316 */
1317 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1318 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1319 if (ret)
1320 goto err;
1321 break;
1322 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1323 set_state(qhp, C4IW_QP_STATE_ERROR);
1324 flush_qp(qhp);
cfdda9d7
SW		 1325 break;
1326 default:
1327 ret = -EINVAL;
1328 goto out;
1329 }
1330 break;
1331 case C4IW_QP_STATE_RTS:
1332 switch (attrs->next_state) {
1333 case C4IW_QP_STATE_CLOSING:
1334 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
2f5b48c3 1335 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1336 ep = qhp->ep;
cfdda9d7
SW		 1337 if (!internal) {
1338 abort = 0;
1339 disconnect = 1;
2f5b48c3 1340 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1341 }
1cf24dce 1342 t4_set_wq_in_error(&qhp->wq);
73d6fcad 1343 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1344 if (ret)
cfdda9d7 1345 goto err;
cfdda9d7
SW		 1346 break;
1347 case C4IW_QP_STATE_TERMINATE:
2f5b48c3 1348 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1349 qhp->attr.layer_etype = attrs->layer_etype;
1350 qhp->attr.ecode = attrs->ecode;
1cf24dce 1351 t4_set_wq_in_error(&qhp->wq);
be4c9bad 1352 ep = qhp->ep;
09992579 1353 disconnect = 1;
0e42c1f4
SW		 1354 if (!internal)
1355 terminate = 1;
09992579
SW		 1356 else {
1357 ret = rdma_fini(rhp, qhp, ep);
1358 if (ret)
1359 goto err;
1360 }
2f5b48c3 1361 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1362 break;
1363 case C4IW_QP_STATE_ERROR:
2f5b48c3 1364 set_state(qhp, C4IW_QP_STATE_ERROR);
1cf24dce 1365 t4_set_wq_in_error(&qhp->wq);
cfdda9d7
SW		 1366 if (!internal) {
1367 abort = 1;
1368 disconnect = 1;
1369 ep = qhp->ep;
2f5b48c3 1370 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1371 }
1372 goto err;
1373 break;
1374 default:
1375 ret = -EINVAL;
1376 goto out;
1377 }
1378 break;
1379 case C4IW_QP_STATE_CLOSING:
1380 if (!internal) {
1381 ret = -EINVAL;
1382 goto out;
1383 }
1384 switch (attrs->next_state) {
1385 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1386 flush_qp(qhp);
1387 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1388 qhp->attr.llp_stream_handle = NULL;
1389 c4iw_put_ep(&qhp->ep->com);
1390 qhp->ep = NULL;
1391 wake_up(&qhp->wait);
1392 break;
1393 case C4IW_QP_STATE_ERROR:
1394 goto err;
1395 default:
1396 ret = -EINVAL;
1397 goto err;
1398 }
1399 break;
1400 case C4IW_QP_STATE_ERROR:
1401 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1402 ret = -EINVAL;
1403 goto out;
1404 }
1405 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1406 ret = -EINVAL;
1407 goto out;
1408 }
2f5b48c3 1409 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1410 break;
1411 case C4IW_QP_STATE_TERMINATE:
1412 if (!internal) {
1413 ret = -EINVAL;
1414 goto out;
1415 }
1416 goto err;
1417 break;
1418 default:
1419 printk(KERN_ERR "%s in a bad state %d\n",
1420 __func__, qhp->attr.state);
1421 ret = -EINVAL;
1422 goto err;
1423 break;
1424 }
1425 goto out;
1426err:
1427 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1428 qhp->wq.sq.qid);
1429
1430 /* disassociate the LLP connection */
1431 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1432 if (!ep)
1433 ep = qhp->ep;
cfdda9d7 1434 qhp->ep = NULL;
2f5b48c3 1435 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7 1436 free = 1;
91e9c071 1437 abort = 1;
cfdda9d7
SW		 1438 wake_up(&qhp->wait);
1439 BUG_ON(!ep);
2f5b48c3 1440 flush_qp(qhp);
cfdda9d7 1441out:
2f5b48c3 1442 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1443
1444 if (terminate)
be4c9bad 1445 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1446
1447 /*
1448 * If disconnect is 1, then we need to initiate a disconnect
1449 * on the EP. This can be a normal close (RTS->CLOSING) or
1450 * an abnormal close (RTS/CLOSING->ERROR).
1451 */
1452 if (disconnect) {
be4c9bad
RD		 1453 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1454 GFP_KERNEL);
cfdda9d7
SW		 1455 c4iw_put_ep(&ep->com);
1456 }
1457
1458 /*
1459 * If free is 1, then we've disassociated the EP from the QP
1460 * and we need to dereference the EP.
1461 */
1462 if (free)
1463 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1464 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1465 return ret;
1466}
1467
422eea0a
VP		 1468static int enable_qp_db(int id, void *p, void *data)
1469{
1470 struct c4iw_qp *qp = p;
1471
1472 t4_enable_wq_db(&qp->wq);
1473 return 0;
1474}
1475
cfdda9d7
SW		 1476int c4iw_destroy_qp(struct ib_qp *ib_qp)
1477{
1478 struct c4iw_dev *rhp;
1479 struct c4iw_qp *qhp;
1480 struct c4iw_qp_attributes attrs;
1481 struct c4iw_ucontext *ucontext;
1482
1483 qhp = to_c4iw_qp(ib_qp);
1484 rhp = qhp->rhp;
1485
1486 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1487 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1488 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1489 else
1490 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1491 wait_event(qhp->wait, !qhp->ep);
1492
422eea0a
VP		 1493 spin_lock_irq(&rhp->lock);
1494 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1495 rhp->qpcnt--;
1496 BUG_ON(rhp->qpcnt < 0);
1497 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1498 rhp->rdev.stats.db_state_transitions++;
1499 rhp->db_state = NORMAL;
1500 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1501 }
80ccdd60
VP		 1502 if (db_coalescing_threshold >= 0)
1503 if (rhp->qpcnt <= db_coalescing_threshold)
1504 cxgb4_enable_db_coalescing(rhp->rdev.lldi.ports[0]);
422eea0a 1505 spin_unlock_irq(&rhp->lock);
cfdda9d7
SW		 1506 atomic_dec(&qhp->refcnt);
1507 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1508
1509 ucontext = ib_qp->uobject ?
1510 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1511 destroy_qp(&rhp->rdev, &qhp->wq,
1512 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1513
1514 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1515 kfree(qhp);
1516 return 0;
1517}
1518
422eea0a
VP		 1519static int disable_qp_db(int id, void *p, void *data)
1520{
1521 struct c4iw_qp *qp = p;
1522
1523 t4_disable_wq_db(&qp->wq);
1524 return 0;
1525}
1526
cfdda9d7
SW		 1527struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1528 struct ib_udata *udata)
1529{
1530 struct c4iw_dev *rhp;
1531 struct c4iw_qp *qhp;
1532 struct c4iw_pd *php;
1533 struct c4iw_cq *schp;
1534 struct c4iw_cq *rchp;
1535 struct c4iw_create_qp_resp uresp;
1536 int sqsize, rqsize;
1537 struct c4iw_ucontext *ucontext;
1538 int ret;
c6d7b267 1539 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1540
1541 PDBG("%s ib_pd %p\n", __func__, pd);
1542
1543 if (attrs->qp_type != IB_QPT_RC)
1544 return ERR_PTR(-EINVAL);
1545
1546 php = to_c4iw_pd(pd);
1547 rhp = php->rhp;
1548 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1549 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1550 if (!schp || !rchp)
1551 return ERR_PTR(-EINVAL);
1552
1553 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1554 return ERR_PTR(-EINVAL);
1555
1556 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1557 if (rqsize > T4_MAX_RQ_SIZE)
1558 return ERR_PTR(-E2BIG);
1559
1560 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1561 if (sqsize > T4_MAX_SQ_SIZE)
1562 return ERR_PTR(-E2BIG);
1563
1564 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1565
cfdda9d7
SW		 1566 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1567 if (!qhp)
1568 return ERR_PTR(-ENOMEM);
1569 qhp->wq.sq.size = sqsize;
1570 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1cf24dce 1571 qhp->wq.sq.flush_cidx = -1;
cfdda9d7
SW		 1572 qhp->wq.rq.size = rqsize;
1573 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1574
1575 if (ucontext) {
1576 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1577 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1578 }
1579
1580 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1581 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1582
1583 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1584 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1585 if (ret)
1586 goto err1;
1587
1588 attrs->cap.max_recv_wr = rqsize - 1;
1589 attrs->cap.max_send_wr = sqsize - 1;
1590 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1591
1592 qhp->rhp = rhp;
1593 qhp->attr.pd = php->pdid;
1594 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1595 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1596 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1597 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1598 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1599 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1600 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1601 qhp->attr.state = C4IW_QP_STATE_IDLE;
1602 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1603 qhp->attr.enable_rdma_read = 1;
1604 qhp->attr.enable_rdma_write = 1;
1605 qhp->attr.enable_bind = 1;
1606 qhp->attr.max_ord = 1;
1607 qhp->attr.max_ird = 1;
1608 spin_lock_init(&qhp->lock);
2f5b48c3 1609 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1610 init_waitqueue_head(&qhp->wait);
1611 atomic_set(&qhp->refcnt, 1);
1612
2c974781
VP		 1613 spin_lock_irq(&rhp->lock);
1614 if (rhp->db_state != NORMAL)
1615 t4_disable_wq_db(&qhp->wq);
3cbdb928
VP		 1616 rhp->qpcnt++;
1617 if (rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
422eea0a
VP		 1618 rhp->rdev.stats.db_state_transitions++;
1619 rhp->db_state = FLOW_CONTROL;
1620 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1621 }
80ccdd60
VP		 1622 if (db_coalescing_threshold >= 0)
1623 if (rhp->qpcnt > db_coalescing_threshold)
1624 cxgb4_disable_db_coalescing(rhp->rdev.lldi.ports[0]);
2c974781
VP		 1625 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1626 spin_unlock_irq(&rhp->lock);
cfdda9d7
SW		 1627 if (ret)
1628 goto err2;
1629
cfdda9d7
SW		 1630 if (udata) {
1631 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1632 if (!mm1) {
1633 ret = -ENOMEM;
30a6a62f 1634 goto err3;
cfdda9d7
SW		 1635 }
1636 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1637 if (!mm2) {
1638 ret = -ENOMEM;
30a6a62f 1639 goto err4;
cfdda9d7
SW		 1640 }
1641 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1642 if (!mm3) {
1643 ret = -ENOMEM;
30a6a62f 1644 goto err5;
cfdda9d7
SW		 1645 }
1646 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1647 if (!mm4) {
1648 ret = -ENOMEM;
30a6a62f 1649 goto err6;
cfdda9d7 1650 }
c6d7b267
SW		 1651 if (t4_sq_onchip(&qhp->wq.sq)) {
1652 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1653 if (!mm5) {
1654 ret = -ENOMEM;
1655 goto err7;
1656 }
1657 uresp.flags = C4IW_QPF_ONCHIP;
1658 } else
1659 uresp.flags = 0;
cfdda9d7
SW		 1660 uresp.qid_mask = rhp->rdev.qpmask;
1661 uresp.sqid = qhp->wq.sq.qid;
1662 uresp.sq_size = qhp->wq.sq.size;
1663 uresp.sq_memsize = qhp->wq.sq.memsize;
1664 uresp.rqid = qhp->wq.rq.qid;
1665 uresp.rq_size = qhp->wq.rq.size;
1666 uresp.rq_memsize = qhp->wq.rq.memsize;
1667 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1668 if (mm5) {
1669 uresp.ma_sync_key = ucontext->key;
1670 ucontext->key += PAGE_SIZE;
ae1fe07f
DC		 1671 } else {
1672 uresp.ma_sync_key = 0;
c6d7b267 1673 }
cfdda9d7
SW		 1674 uresp.sq_key = ucontext->key;
1675 ucontext->key += PAGE_SIZE;
1676 uresp.rq_key = ucontext->key;
1677 ucontext->key += PAGE_SIZE;
1678 uresp.sq_db_gts_key = ucontext->key;
1679 ucontext->key += PAGE_SIZE;
1680 uresp.rq_db_gts_key = ucontext->key;
1681 ucontext->key += PAGE_SIZE;
1682 spin_unlock(&ucontext->mmap_lock);
1683 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1684 if (ret)
c6d7b267 1685 goto err8;
cfdda9d7 1686 mm1->key = uresp.sq_key;
c6d7b267 1687 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1688 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1689 insert_mmap(ucontext, mm1);
1690 mm2->key = uresp.rq_key;
1691 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1692 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1693 insert_mmap(ucontext, mm2);
1694 mm3->key = uresp.sq_db_gts_key;
1695 mm3->addr = qhp->wq.sq.udb;
1696 mm3->len = PAGE_SIZE;
1697 insert_mmap(ucontext, mm3);
1698 mm4->key = uresp.rq_db_gts_key;
1699 mm4->addr = qhp->wq.rq.udb;
1700 mm4->len = PAGE_SIZE;
1701 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1702 if (mm5) {
1703 mm5->key = uresp.ma_sync_key;
1704 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1705 + A_PCIE_MA_SYNC) & PAGE_MASK;
1706 mm5->len = PAGE_SIZE;
1707 insert_mmap(ucontext, mm5);
1708 }
cfdda9d7
SW		 1709 }
1710 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1711 init_timer(&(qhp->timer));
1712 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1713 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1714 qhp->wq.sq.qid);
1715 return &qhp->ibqp;
c6d7b267
SW		 1716err8:
1717 kfree(mm5);
cfdda9d7 1718err7:
30a6a62f 1719 kfree(mm4);
cfdda9d7 1720err6:
30a6a62f 1721 kfree(mm3);
cfdda9d7 1722err5:
30a6a62f 1723 kfree(mm2);
cfdda9d7 1724err4:
30a6a62f 1725 kfree(mm1);
cfdda9d7
SW		 1726err3:
1727 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1728err2:
1729 destroy_qp(&rhp->rdev, &qhp->wq,
1730 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1731err1:
1732 kfree(qhp);
1733 return ERR_PTR(ret);
1734}
1735
1736int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1737 int attr_mask, struct ib_udata *udata)
1738{
1739 struct c4iw_dev *rhp;
1740 struct c4iw_qp *qhp;
1741 enum c4iw_qp_attr_mask mask = 0;
1742 struct c4iw_qp_attributes attrs;
1743
1744 PDBG("%s ib_qp %p\n", __func__, ibqp);
1745
1746 /* iwarp does not support the RTR state */
1747 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1748 attr_mask &= ~IB_QP_STATE;
1749
1750 /* Make sure we still have something left to do */
1751 if (!attr_mask)
1752 return 0;
1753
1754 memset(&attrs, 0, sizeof attrs);
1755 qhp = to_c4iw_qp(ibqp);
1756 rhp = qhp->rhp;
1757
1758 attrs.next_state = c4iw_convert_state(attr->qp_state);
1759 attrs.enable_rdma_read = (attr->qp_access_flags &
1760 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1761 attrs.enable_rdma_write = (attr->qp_access_flags &
1762 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1763 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1764
1765
1766 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1767 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1768 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1769 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1770 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1771
2c974781
VP		 1772 /*
1773 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1774 * ringing the queue db when we're in DB_FULL mode.
1775 */
1776 attrs.sq_db_inc = attr->sq_psn;
1777 attrs.rq_db_inc = attr->rq_psn;
1778 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1779 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1780
cfdda9d7
SW		 1781 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1782}
1783
1784struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1785{
1786 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1787 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1788}
67bbc055
VP		 1789
1790int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1791 int attr_mask, struct ib_qp_init_attr *init_attr)
1792{
1793 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1794
1795 memset(attr, 0, sizeof *attr);
1796 memset(init_attr, 0, sizeof *init_attr);
1797 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1798 return 0;
1799}
Linux 6.x block layer and io_uring tree(s)