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RDMA/cxgb4: Disable interrupts in c4iw_ev_dispatch()
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
2f5b48c3
SW		 45static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
46{
47 unsigned long flag;
48 spin_lock_irqsave(&qhp->lock, flag);
49 qhp->attr.state = state;
50 spin_unlock_irqrestore(&qhp->lock, flag);
51}
52
c6d7b267
SW		 53static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
54{
55 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
56}
57
58static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
59{
60 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
61 pci_unmap_addr(sq, mapping));
62}
63
64static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
65{
66 if (t4_sq_onchip(sq))
67 dealloc_oc_sq(rdev, sq);
68 else
69 dealloc_host_sq(rdev, sq);
70}
71
72static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
73{
74 if (!ocqp_support || !t4_ocqp_supported())
75 return -ENOSYS;
76 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
77 if (!sq->dma_addr)
78 return -ENOMEM;
79 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
80 rdev->lldi.vr->ocq.start;
81 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
82 rdev->lldi.vr->ocq.start);
83 sq->flags |= T4_SQ_ONCHIP;
84 return 0;
85}
86
87static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
88{
89 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
90 &(sq->dma_addr), GFP_KERNEL);
91 if (!sq->queue)
92 return -ENOMEM;
93 sq->phys_addr = virt_to_phys(sq->queue);
94 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
95 return 0;
96}
97
cfdda9d7
SW		 98static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
99 struct c4iw_dev_ucontext *uctx)
100{
101 /*
102 * uP clears EQ contexts when the connection exits rdma mode,
103 * so no need to post a RESET WR for these EQs.
104 */
105 dma_free_coherent(&(rdev->lldi.pdev->dev),
106 wq->rq.memsize, wq->rq.queue,
f38926aa 107 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 108 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 109 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
110 kfree(wq->rq.sw_rq);
111 kfree(wq->sq.sw_sq);
112 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
113 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
114 return 0;
115}
116
117static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
118 struct t4_cq *rcq, struct t4_cq *scq,
119 struct c4iw_dev_ucontext *uctx)
120{
121 int user = (uctx != &rdev->uctx);
122 struct fw_ri_res_wr *res_wr;
123 struct fw_ri_res *res;
124 int wr_len;
125 struct c4iw_wr_wait wr_wait;
126 struct sk_buff *skb;
127 int ret;
128 int eqsize;
129
130 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
131 if (!wq->sq.qid)
132 return -ENOMEM;
133
134 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
135 if (!wq->rq.qid)
136 goto err1;
137
138 if (!user) {
139 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
140 GFP_KERNEL);
141 if (!wq->sq.sw_sq)
142 goto err2;
143
144 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
145 GFP_KERNEL);
146 if (!wq->rq.sw_rq)
147 goto err3;
148 }
149
150 /*
151 * RQT must be a power of 2.
152 */
153 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
154 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
155 if (!wq->rq.rqt_hwaddr)
156 goto err4;
157
c6d7b267
SW		 158 if (user) {
159 if (alloc_oc_sq(rdev, &wq->sq) && alloc_host_sq(rdev, &wq->sq))
160 goto err5;
161 } else
162 if (alloc_host_sq(rdev, &wq->sq))
163 goto err5;
cfdda9d7 164 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 165 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 166
167 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
168 wq->rq.memsize, &(wq->rq.dma_addr),
169 GFP_KERNEL);
170 if (!wq->rq.queue)
171 goto err6;
172 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
173 __func__, wq->sq.queue,
174 (unsigned long long)virt_to_phys(wq->sq.queue),
175 wq->rq.queue,
176 (unsigned long long)virt_to_phys(wq->rq.queue));
177 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 178 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 179
180 wq->db = rdev->lldi.db_reg;
181 wq->gts = rdev->lldi.gts_reg;
182 if (user) {
183 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
184 (wq->sq.qid << rdev->qpshift);
185 wq->sq.udb &= PAGE_MASK;
186 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
187 (wq->rq.qid << rdev->qpshift);
188 wq->rq.udb &= PAGE_MASK;
189 }
190 wq->rdev = rdev;
191 wq->rq.msn = 1;
192
193 /* build fw_ri_res_wr */
194 wr_len = sizeof *res_wr + 2 * sizeof *res;
195
d3c814e8 196 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 197 if (!skb) {
198 ret = -ENOMEM;
199 goto err7;
200 }
201 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
202
203 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
204 memset(res_wr, 0, wr_len);
205 res_wr->op_nres = cpu_to_be32(
206 FW_WR_OP(FW_RI_RES_WR) |
207 V_FW_RI_RES_WR_NRES(2) |
208 FW_WR_COMPL(1));
209 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 210 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 211 res = res_wr->res;
212 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
213 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
214
215 /*
216 * eqsize is the number of 64B entries plus the status page size.
217 */
218 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
219
220 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
221 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
222 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
223 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 224 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 225 V_FW_RI_RES_WR_IQID(scq->cqid));
226 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
227 V_FW_RI_RES_WR_DCAEN(0) |
228 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 229 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 230 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 231 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
232 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
233 V_FW_RI_RES_WR_EQSIZE(eqsize));
234 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
235 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
236 res++;
237 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
238 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
239
240 /*
241 * eqsize is the number of 64B entries plus the status page size.
242 */
243 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
244 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
245 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
246 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
247 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
248 V_FW_RI_RES_WR_IQID(rcq->cqid));
249 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
250 V_FW_RI_RES_WR_DCAEN(0) |
251 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 252 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 253 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 254 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
255 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
256 V_FW_RI_RES_WR_EQSIZE(eqsize));
257 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
258 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
259
260 c4iw_init_wr_wait(&wr_wait);
261
262 ret = c4iw_ofld_send(rdev, skb);
263 if (ret)
264 goto err7;
aadc4df3 265 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7
SW		 266 if (ret)
267 goto err7;
268
269 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
270 __func__, wq->sq.qid, wq->rq.qid, wq->db,
271 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
272
273 return 0;
274err7:
275 dma_free_coherent(&(rdev->lldi.pdev->dev),
276 wq->rq.memsize, wq->rq.queue,
f38926aa 277 dma_unmap_addr(&wq->rq, mapping));
cfdda9d7 278err6:
c6d7b267 279 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 280err5:
281 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
282err4:
283 kfree(wq->rq.sw_rq);
284err3:
285 kfree(wq->sq.sw_sq);
286err2:
287 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
288err1:
289 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
290 return -ENOMEM;
291}
292
d37ac31d
SW		 293static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
294 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 295{
d37ac31d
SW		 296 u8 *dstp, *srcp;
297 u32 plen = 0;
cfdda9d7 298 int i;
d37ac31d
SW		 299 int rem, len;
300
301 dstp = (u8 *)immdp->data;
302 for (i = 0; i < wr->num_sge; i++) {
303 if ((plen + wr->sg_list[i].length) > max)
304 return -EMSGSIZE;
305 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
306 plen += wr->sg_list[i].length;
307 rem = wr->sg_list[i].length;
308 while (rem) {
309 if (dstp == (u8 *)&sq->queue[sq->size])
310 dstp = (u8 *)sq->queue;
311 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
312 len = rem;
313 else
314 len = (u8 *)&sq->queue[sq->size] - dstp;
315 memcpy(dstp, srcp, len);
316 dstp += len;
317 srcp += len;
318 rem -= len;
319 }
320 }
13fecb83
SW		 321 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
322 if (len)
323 memset(dstp, 0, len);
d37ac31d
SW		 324 immdp->op = FW_RI_DATA_IMMD;
325 immdp->r1 = 0;
326 immdp->r2 = 0;
327 immdp->immdlen = cpu_to_be32(plen);
328 *plenp = plen;
329 return 0;
330}
331
332static int build_isgl(__be64 *queue_start, __be64 *queue_end,
333 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
334 int num_sge, u32 *plenp)
335
336{
337 int i;
338 u32 plen = 0;
339 __be64 *flitp = (__be64 *)isglp->sge;
340
341 for (i = 0; i < num_sge; i++) {
342 if ((plen + sg_list[i].length) < plen)
343 return -EMSGSIZE;
344 plen += sg_list[i].length;
345 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
346 sg_list[i].length);
347 if (++flitp == queue_end)
348 flitp = queue_start;
349 *flitp = cpu_to_be64(sg_list[i].addr);
350 if (++flitp == queue_end)
351 flitp = queue_start;
352 }
13fecb83 353 *flitp = (__force __be64)0;
d37ac31d
SW		 354 isglp->op = FW_RI_DATA_ISGL;
355 isglp->r1 = 0;
356 isglp->nsge = cpu_to_be16(num_sge);
357 isglp->r2 = 0;
358 if (plenp)
359 *plenp = plen;
360 return 0;
361}
362
363static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
364 struct ib_send_wr *wr, u8 *len16)
365{
cfdda9d7
SW		 366 u32 plen;
367 int size;
d37ac31d 368 int ret;
cfdda9d7
SW		 369
370 if (wr->num_sge > T4_MAX_SEND_SGE)
371 return -EINVAL;
372 switch (wr->opcode) {
373 case IB_WR_SEND:
374 if (wr->send_flags & IB_SEND_SOLICITED)
375 wqe->send.sendop_pkd = cpu_to_be32(
376 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
377 else
378 wqe->send.sendop_pkd = cpu_to_be32(
379 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
380 wqe->send.stag_inv = 0;
381 break;
382 case IB_WR_SEND_WITH_INV:
383 if (wr->send_flags & IB_SEND_SOLICITED)
384 wqe->send.sendop_pkd = cpu_to_be32(
385 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
386 else
387 wqe->send.sendop_pkd = cpu_to_be32(
388 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
389 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
390 break;
391
392 default:
393 return -EINVAL;
394 }
d37ac31d 395
cfdda9d7
SW		 396 plen = 0;
397 if (wr->num_sge) {
398 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 399 ret = build_immd(sq, wqe->send.u.immd_src, wr,
400 T4_MAX_SEND_INLINE, &plen);
401 if (ret)
402 return ret;
cfdda9d7
SW		 403 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
404 plen;
405 } else {
d37ac31d
SW		 406 ret = build_isgl((__be64 *)sq->queue,
407 (__be64 *)&sq->queue[sq->size],
408 wqe->send.u.isgl_src,
409 wr->sg_list, wr->num_sge, &plen);
410 if (ret)
411 return ret;
cfdda9d7
SW		 412 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
413 wr->num_sge * sizeof(struct fw_ri_sge);
414 }
415 } else {
416 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
417 wqe->send.u.immd_src[0].r1 = 0;
418 wqe->send.u.immd_src[0].r2 = 0;
419 wqe->send.u.immd_src[0].immdlen = 0;
420 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 421 plen = 0;
cfdda9d7
SW		 422 }
423 *len16 = DIV_ROUND_UP(size, 16);
424 wqe->send.plen = cpu_to_be32(plen);
425 return 0;
426}
427
d37ac31d
SW		 428static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
429 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 430{
cfdda9d7
SW		 431 u32 plen;
432 int size;
d37ac31d 433 int ret;
cfdda9d7 434
d37ac31d 435 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 436 return -EINVAL;
437 wqe->write.r2 = 0;
438 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
439 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 440 if (wr->num_sge) {
441 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 442 ret = build_immd(sq, wqe->write.u.immd_src, wr,
443 T4_MAX_WRITE_INLINE, &plen);
444 if (ret)
445 return ret;
cfdda9d7
SW		 446 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
447 plen;
448 } else {
d37ac31d
SW		 449 ret = build_isgl((__be64 *)sq->queue,
450 (__be64 *)&sq->queue[sq->size],
451 wqe->write.u.isgl_src,
452 wr->sg_list, wr->num_sge, &plen);
453 if (ret)
454 return ret;
cfdda9d7
SW		 455 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
456 wr->num_sge * sizeof(struct fw_ri_sge);
457 }
458 } else {
459 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
460 wqe->write.u.immd_src[0].r1 = 0;
461 wqe->write.u.immd_src[0].r2 = 0;
462 wqe->write.u.immd_src[0].immdlen = 0;
463 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 464 plen = 0;
cfdda9d7
SW		 465 }
466 *len16 = DIV_ROUND_UP(size, 16);
467 wqe->write.plen = cpu_to_be32(plen);
468 return 0;
469}
470
471static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
472{
473 if (wr->num_sge > 1)
474 return -EINVAL;
475 if (wr->num_sge) {
476 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
477 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
478 >> 32));
479 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
480 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
481 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
482 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
483 >> 32));
484 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
485 } else {
486 wqe->read.stag_src = cpu_to_be32(2);
487 wqe->read.to_src_hi = 0;
488 wqe->read.to_src_lo = 0;
489 wqe->read.stag_sink = cpu_to_be32(2);
490 wqe->read.plen = 0;
491 wqe->read.to_sink_hi = 0;
492 wqe->read.to_sink_lo = 0;
493 }
494 wqe->read.r2 = 0;
495 wqe->read.r5 = 0;
496 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
497 return 0;
498}
499
500static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
501 struct ib_recv_wr *wr, u8 *len16)
502{
d37ac31d 503 int ret;
cfdda9d7 504
d37ac31d
SW		 505 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
506 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
507 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
508 if (ret)
509 return ret;
cfdda9d7
SW		 510 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
511 wr->num_sge * sizeof(struct fw_ri_sge), 16);
512 return 0;
513}
514
40dbf6ee
SW		 515static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
516 struct ib_send_wr *wr, u8 *len16)
cfdda9d7
SW		 517{
518
519 struct fw_ri_immd *imdp;
520 __be64 *p;
521 int i;
522 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 523 int rem;
cfdda9d7
SW		 524
525 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
526 return -EINVAL;
527
528 wqe->fr.qpbinde_to_dcacpu = 0;
529 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
530 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
531 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
532 wqe->fr.len_hi = 0;
533 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
534 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
535 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
536 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
537 0xffffffff);
40dbf6ee
SW		 538 WARN_ON(pbllen > T4_MAX_FR_IMMD);
539 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
540 imdp->op = FW_RI_DATA_IMMD;
541 imdp->r1 = 0;
542 imdp->r2 = 0;
543 imdp->immdlen = cpu_to_be32(pbllen);
544 p = (__be64 *)(imdp + 1);
545 rem = pbllen;
546 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
547 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
548 rem -= sizeof *p;
549 if (++p == (__be64 *)&sq->queue[sq->size])
550 p = (__be64 *)sq->queue;
551 }
552 BUG_ON(rem < 0);
553 while (rem) {
554 *p = 0;
555 rem -= sizeof *p;
556 if (++p == (__be64 *)&sq->queue[sq->size])
557 p = (__be64 *)sq->queue;
cfdda9d7 558 }
40dbf6ee 559 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
cfdda9d7
SW		 560 return 0;
561}
562
563static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
564 u8 *len16)
565{
566 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
567 wqe->inv.r2 = 0;
568 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
569 return 0;
570}
571
572void c4iw_qp_add_ref(struct ib_qp *qp)
573{
574 PDBG("%s ib_qp %p\n", __func__, qp);
575 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
576}
577
578void c4iw_qp_rem_ref(struct ib_qp *qp)
579{
580 PDBG("%s ib_qp %p\n", __func__, qp);
581 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
582 wake_up(&(to_c4iw_qp(qp)->wait));
583}
584
585int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
586 struct ib_send_wr **bad_wr)
587{
588 int err = 0;
589 u8 len16 = 0;
590 enum fw_wr_opcodes fw_opcode = 0;
591 enum fw_ri_wr_flags fw_flags;
592 struct c4iw_qp *qhp;
593 union t4_wr *wqe;
594 u32 num_wrs;
595 struct t4_swsqe *swsqe;
596 unsigned long flag;
597 u16 idx = 0;
598
599 qhp = to_c4iw_qp(ibqp);
600 spin_lock_irqsave(&qhp->lock, flag);
601 if (t4_wq_in_error(&qhp->wq)) {
602 spin_unlock_irqrestore(&qhp->lock, flag);
603 return -EINVAL;
604 }
605 num_wrs = t4_sq_avail(&qhp->wq);
606 if (num_wrs == 0) {
607 spin_unlock_irqrestore(&qhp->lock, flag);
608 return -ENOMEM;
609 }
610 while (wr) {
611 if (num_wrs == 0) {
612 err = -ENOMEM;
613 *bad_wr = wr;
614 break;
615 }
d37ac31d
SW		 616 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
617 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
618
cfdda9d7
SW		 619 fw_flags = 0;
620 if (wr->send_flags & IB_SEND_SOLICITED)
621 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
622 if (wr->send_flags & IB_SEND_SIGNALED)
623 fw_flags |= FW_RI_COMPLETION_FLAG;
624 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
625 switch (wr->opcode) {
626 case IB_WR_SEND_WITH_INV:
627 case IB_WR_SEND:
628 if (wr->send_flags & IB_SEND_FENCE)
629 fw_flags |= FW_RI_READ_FENCE_FLAG;
630 fw_opcode = FW_RI_SEND_WR;
631 if (wr->opcode == IB_WR_SEND)
632 swsqe->opcode = FW_RI_SEND;
633 else
634 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 635 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 636 break;
637 case IB_WR_RDMA_WRITE:
638 fw_opcode = FW_RI_RDMA_WRITE_WR;
639 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 640 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 641 break;
642 case IB_WR_RDMA_READ:
2f1fb507 643 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 644 fw_opcode = FW_RI_RDMA_READ_WR;
645 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 646 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 647 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 648 else
649 fw_flags = 0;
cfdda9d7
SW		 650 err = build_rdma_read(wqe, wr, &len16);
651 if (err)
652 break;
653 swsqe->read_len = wr->sg_list[0].length;
654 if (!qhp->wq.sq.oldest_read)
655 qhp->wq.sq.oldest_read = swsqe;
656 break;
657 case IB_WR_FAST_REG_MR:
658 fw_opcode = FW_RI_FR_NSMR_WR;
659 swsqe->opcode = FW_RI_FAST_REGISTER;
40dbf6ee 660 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 661 break;
662 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 663 if (wr->send_flags & IB_SEND_FENCE)
664 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 665 fw_opcode = FW_RI_INV_LSTAG_WR;
666 swsqe->opcode = FW_RI_LOCAL_INV;
667 err = build_inv_stag(wqe, wr, &len16);
668 break;
669 default:
670 PDBG("%s post of type=%d TBD!\n", __func__,
671 wr->opcode);
672 err = -EINVAL;
673 }
674 if (err) {
675 *bad_wr = wr;
676 break;
677 }
678 swsqe->idx = qhp->wq.sq.pidx;
679 swsqe->complete = 0;
680 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
681 swsqe->wr_id = wr->wr_id;
682
683 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
684
685 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
686 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
687 swsqe->opcode, swsqe->read_len);
688 wr = wr->next;
689 num_wrs--;
d37ac31d
SW		 690 t4_sq_produce(&qhp->wq, len16);
691 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 692 }
693 if (t4_wq_db_enabled(&qhp->wq))
694 t4_ring_sq_db(&qhp->wq, idx);
695 spin_unlock_irqrestore(&qhp->lock, flag);
696 return err;
697}
698
699int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
700 struct ib_recv_wr **bad_wr)
701{
702 int err = 0;
703 struct c4iw_qp *qhp;
704 union t4_recv_wr *wqe;
705 u32 num_wrs;
706 u8 len16 = 0;
707 unsigned long flag;
708 u16 idx = 0;
709
710 qhp = to_c4iw_qp(ibqp);
711 spin_lock_irqsave(&qhp->lock, flag);
712 if (t4_wq_in_error(&qhp->wq)) {
713 spin_unlock_irqrestore(&qhp->lock, flag);
714 return -EINVAL;
715 }
716 num_wrs = t4_rq_avail(&qhp->wq);
717 if (num_wrs == 0) {
718 spin_unlock_irqrestore(&qhp->lock, flag);
719 return -ENOMEM;
720 }
721 while (wr) {
722 if (wr->num_sge > T4_MAX_RECV_SGE) {
723 err = -EINVAL;
724 *bad_wr = wr;
725 break;
726 }
d37ac31d
SW		 727 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
728 qhp->wq.rq.wq_pidx *
729 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 730 if (num_wrs)
731 err = build_rdma_recv(qhp, wqe, wr, &len16);
732 else
733 err = -ENOMEM;
734 if (err) {
735 *bad_wr = wr;
736 break;
737 }
738
739 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
740
741 wqe->recv.opcode = FW_RI_RECV_WR;
742 wqe->recv.r1 = 0;
743 wqe->recv.wrid = qhp->wq.rq.pidx;
744 wqe->recv.r2[0] = 0;
745 wqe->recv.r2[1] = 0;
746 wqe->recv.r2[2] = 0;
747 wqe->recv.len16 = len16;
cfdda9d7
SW		 748 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
749 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 750 t4_rq_produce(&qhp->wq, len16);
751 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 752 wr = wr->next;
753 num_wrs--;
cfdda9d7
SW		 754 }
755 if (t4_wq_db_enabled(&qhp->wq))
756 t4_ring_rq_db(&qhp->wq, idx);
757 spin_unlock_irqrestore(&qhp->lock, flag);
758 return err;
759}
760
761int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
762{
763 return -ENOSYS;
764}
765
766static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
767 u8 *ecode)
768{
769 int status;
770 int tagged;
771 int opcode;
772 int rqtype;
773 int send_inv;
774
775 if (!err_cqe) {
776 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
777 *ecode = 0;
778 return;
779 }
780
781 status = CQE_STATUS(err_cqe);
782 opcode = CQE_OPCODE(err_cqe);
783 rqtype = RQ_TYPE(err_cqe);
784 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
785 (opcode == FW_RI_SEND_WITH_SE_INV);
786 tagged = (opcode == FW_RI_RDMA_WRITE) ||
787 (rqtype && (opcode == FW_RI_READ_RESP));
788
789 switch (status) {
790 case T4_ERR_STAG:
791 if (send_inv) {
792 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
793 *ecode = RDMAP_CANT_INV_STAG;
794 } else {
795 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
796 *ecode = RDMAP_INV_STAG;
797 }
798 break;
799 case T4_ERR_PDID:
800 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
801 if ((opcode == FW_RI_SEND_WITH_INV) ||
802 (opcode == FW_RI_SEND_WITH_SE_INV))
803 *ecode = RDMAP_CANT_INV_STAG;
804 else
805 *ecode = RDMAP_STAG_NOT_ASSOC;
806 break;
807 case T4_ERR_QPID:
808 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
809 *ecode = RDMAP_STAG_NOT_ASSOC;
810 break;
811 case T4_ERR_ACCESS:
812 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
813 *ecode = RDMAP_ACC_VIOL;
814 break;
815 case T4_ERR_WRAP:
816 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
817 *ecode = RDMAP_TO_WRAP;
818 break;
819 case T4_ERR_BOUND:
820 if (tagged) {
821 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
822 *ecode = DDPT_BASE_BOUNDS;
823 } else {
824 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
825 *ecode = RDMAP_BASE_BOUNDS;
826 }
827 break;
828 case T4_ERR_INVALIDATE_SHARED_MR:
829 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
830 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
831 *ecode = RDMAP_CANT_INV_STAG;
832 break;
833 case T4_ERR_ECC:
834 case T4_ERR_ECC_PSTAG:
835 case T4_ERR_INTERNAL_ERR:
836 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
837 *ecode = 0;
838 break;
839 case T4_ERR_OUT_OF_RQE:
840 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
841 *ecode = DDPU_INV_MSN_NOBUF;
842 break;
843 case T4_ERR_PBL_ADDR_BOUND:
844 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
845 *ecode = DDPT_BASE_BOUNDS;
846 break;
847 case T4_ERR_CRC:
848 *layer_type = LAYER_MPA|DDP_LLP;
849 *ecode = MPA_CRC_ERR;
850 break;
851 case T4_ERR_MARKER:
852 *layer_type = LAYER_MPA|DDP_LLP;
853 *ecode = MPA_MARKER_ERR;
854 break;
855 case T4_ERR_PDU_LEN_ERR:
856 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
857 *ecode = DDPU_MSG_TOOBIG;
858 break;
859 case T4_ERR_DDP_VERSION:
860 if (tagged) {
861 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
862 *ecode = DDPT_INV_VERS;
863 } else {
864 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
865 *ecode = DDPU_INV_VERS;
866 }
867 break;
868 case T4_ERR_RDMA_VERSION:
869 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
870 *ecode = RDMAP_INV_VERS;
871 break;
872 case T4_ERR_OPCODE:
873 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
874 *ecode = RDMAP_INV_OPCODE;
875 break;
876 case T4_ERR_DDP_QUEUE_NUM:
877 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
878 *ecode = DDPU_INV_QN;
879 break;
880 case T4_ERR_MSN:
881 case T4_ERR_MSN_GAP:
882 case T4_ERR_MSN_RANGE:
883 case T4_ERR_IRD_OVERFLOW:
884 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
885 *ecode = DDPU_INV_MSN_RANGE;
886 break;
887 case T4_ERR_TBIT:
888 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
889 *ecode = 0;
890 break;
891 case T4_ERR_MO:
892 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
893 *ecode = DDPU_INV_MO;
894 break;
895 default:
896 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
897 *ecode = 0;
898 break;
899 }
900}
901
be4c9bad
RD		 902static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
903 gfp_t gfp)
cfdda9d7
SW		 904{
905 struct fw_ri_wr *wqe;
906 struct sk_buff *skb;
907 struct terminate_message *term;
908
909 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
910 qhp->ep->hwtid);
911
be4c9bad 912 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 913 if (!skb)
be4c9bad 914 return;
cfdda9d7
SW		 915 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
916
917 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
918 memset(wqe, 0, sizeof *wqe);
919 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
920 wqe->flowid_len16 = cpu_to_be32(
921 FW_WR_FLOWID(qhp->ep->hwtid) |
922 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
923
924 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
925 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
926 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 927 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
928 term->layer_etype = qhp->attr.layer_etype;
929 term->ecode = qhp->attr.ecode;
930 } else
931 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 932 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 933}
934
935/*
936 * Assumes qhp lock is held.
937 */
938static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 939 struct c4iw_cq *schp)
cfdda9d7
SW		 940{
941 int count;
942 int flushed;
2f5b48c3 943 unsigned long flag;
cfdda9d7
SW		 944
945 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 946
732bee7a 947 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 948 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7
SW		 949 spin_lock(&qhp->lock);
950 c4iw_flush_hw_cq(&rchp->cq);
951 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
952 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
953 spin_unlock(&qhp->lock);
2f5b48c3 954 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 955 if (flushed) {
956 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 957 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 958 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
959 }
cfdda9d7 960
732bee7a 961 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 962 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7
SW		 963 spin_lock(&qhp->lock);
964 c4iw_flush_hw_cq(&schp->cq);
965 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
966 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
967 spin_unlock(&qhp->lock);
2f5b48c3 968 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 969 if (flushed) {
970 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 971 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 972 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
973 }
cfdda9d7
SW		 974}
975
2f5b48c3 976static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 977{
978 struct c4iw_cq *rchp, *schp;
581bbe2c 979 unsigned long flag;
cfdda9d7
SW		 980
981 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
982 schp = get_chp(qhp->rhp, qhp->attr.scq);
983
984 if (qhp->ibqp.uobject) {
985 t4_set_wq_in_error(&qhp->wq);
986 t4_set_cq_in_error(&rchp->cq);
581bbe2c 987 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 988 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 989 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 990 if (schp != rchp) {
cfdda9d7 991 t4_set_cq_in_error(&schp->cq);
581bbe2c 992 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 993 (*schp->ibcq.comp_handler)(&schp->ibcq,
994 schp->ibcq.cq_context);
581bbe2c 995 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 996 }
cfdda9d7
SW		 997 return;
998 }
2f5b48c3 999 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1000}
1001
73d6fcad
SW		 1002static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1003 struct c4iw_ep *ep)
cfdda9d7
SW		 1004{
1005 struct fw_ri_wr *wqe;
1006 int ret;
cfdda9d7
SW		 1007 struct sk_buff *skb;
1008
1009 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1010 ep->hwtid);
cfdda9d7 1011
d3c814e8 1012 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1013 if (!skb)
1014 return -ENOMEM;
73d6fcad 1015 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1016
1017 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1018 memset(wqe, 0, sizeof *wqe);
1019 wqe->op_compl = cpu_to_be32(
1020 FW_WR_OP(FW_RI_INIT_WR) |
1021 FW_WR_COMPL(1));
1022 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1023 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1024 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1025 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1026
1027 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1028 ret = c4iw_ofld_send(&rhp->rdev, skb);
1029 if (ret)
1030 goto out;
1031
2f5b48c3 1032 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1033 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1034out:
1035 PDBG("%s ret %d\n", __func__, ret);
1036 return ret;
1037}
1038
1039static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1040{
d2fe99e8 1041 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1042 memset(&init->u, 0, sizeof init->u);
1043 switch (p2p_type) {
1044 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1045 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1046 init->u.write.stag_sink = cpu_to_be32(1);
1047 init->u.write.to_sink = cpu_to_be64(1);
1048 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1049 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1050 sizeof(struct fw_ri_immd),
1051 16);
1052 break;
1053 case FW_RI_INIT_P2PTYPE_READ_REQ:
1054 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1055 init->u.read.stag_src = cpu_to_be32(1);
1056 init->u.read.to_src_lo = cpu_to_be32(1);
1057 init->u.read.stag_sink = cpu_to_be32(1);
1058 init->u.read.to_sink_lo = cpu_to_be32(1);
1059 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1060 break;
1061 }
1062}
1063
1064static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1065{
1066 struct fw_ri_wr *wqe;
1067 int ret;
cfdda9d7
SW		 1068 struct sk_buff *skb;
1069
1070 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1071 qhp->ep->hwtid);
1072
d3c814e8 1073 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1074 if (!skb)
1075 return -ENOMEM;
1076 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1077
1078 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1079 memset(wqe, 0, sizeof *wqe);
1080 wqe->op_compl = cpu_to_be32(
1081 FW_WR_OP(FW_RI_INIT_WR) |
1082 FW_WR_COMPL(1));
1083 wqe->flowid_len16 = cpu_to_be32(
1084 FW_WR_FLOWID(qhp->ep->hwtid) |
1085 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1086
2f5b48c3 1087 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1088
1089 wqe->u.init.type = FW_RI_TYPE_INIT;
1090 wqe->u.init.mpareqbit_p2ptype =
1091 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1092 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1093 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1094 if (qhp->attr.mpa_attr.recv_marker_enabled)
1095 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1096 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1097 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1098 if (qhp->attr.mpa_attr.crc_enabled)
1099 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1100
1101 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1102 FW_RI_QP_RDMA_WRITE_ENABLE |
1103 FW_RI_QP_BIND_ENABLE;
1104 if (!qhp->ibqp.uobject)
1105 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1106 FW_RI_QP_STAG0_ENABLE;
1107 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1108 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1109 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1110 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1111 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1112 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1113 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1114 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1115 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1116 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1117 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1118 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1119 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1120 rhp->rdev.lldi.vr->rq.start);
1121 if (qhp->attr.mpa_attr.initiator)
1122 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1123
cfdda9d7
SW		 1124 ret = c4iw_ofld_send(&rhp->rdev, skb);
1125 if (ret)
1126 goto out;
1127
2f5b48c3
SW		 1128 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1129 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1130out:
1131 PDBG("%s ret %d\n", __func__, ret);
1132 return ret;
1133}
1134
2c974781
VP		 1135/*
1136 * Called by the library when the qp has user dbs disabled due to
1137 * a DB_FULL condition. This function will single-thread all user
1138 * DB rings to avoid overflowing the hw db-fifo.
1139 */
1140static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1141{
1142 int delay = db_delay_usecs;
1143
1144 mutex_lock(&qhp->rhp->db_mutex);
1145 do {
1146 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) < 768) {
1147 writel(V_QID(qid) | V_PIDX(inc), qhp->wq.db);
1148 break;
1149 }
1150 set_current_state(TASK_UNINTERRUPTIBLE);
1151 schedule_timeout(usecs_to_jiffies(delay));
1152 delay = min(delay << 1, 200000);
1153 } while (1);
1154 mutex_unlock(&qhp->rhp->db_mutex);
1155 return 0;
1156}
1157
cfdda9d7
SW		 1158int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1159 enum c4iw_qp_attr_mask mask,
1160 struct c4iw_qp_attributes *attrs,
1161 int internal)
1162{
1163 int ret = 0;
1164 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1165 int disconnect = 0;
1166 int terminate = 0;
1167 int abort = 0;
1168 int free = 0;
1169 struct c4iw_ep *ep = NULL;
1170
1171 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1172 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1173 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1174
2f5b48c3 1175 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1176
1177 /* Process attr changes if in IDLE */
1178 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1179 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1180 ret = -EIO;
1181 goto out;
1182 }
1183 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1184 newattr.enable_rdma_read = attrs->enable_rdma_read;
1185 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1186 newattr.enable_rdma_write = attrs->enable_rdma_write;
1187 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1188 newattr.enable_bind = attrs->enable_bind;
1189 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1190 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1191 ret = -EINVAL;
1192 goto out;
1193 }
1194 newattr.max_ord = attrs->max_ord;
1195 }
1196 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1197 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1198 ret = -EINVAL;
1199 goto out;
1200 }
1201 newattr.max_ird = attrs->max_ird;
1202 }
1203 qhp->attr = newattr;
1204 }
1205
2c974781
VP		 1206 if (mask & C4IW_QP_ATTR_SQ_DB) {
1207 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1208 goto out;
1209 }
1210 if (mask & C4IW_QP_ATTR_RQ_DB) {
1211 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1212 goto out;
1213 }
1214
cfdda9d7
SW		 1215 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1216 goto out;
1217 if (qhp->attr.state == attrs->next_state)
1218 goto out;
1219
1220 switch (qhp->attr.state) {
1221 case C4IW_QP_STATE_IDLE:
1222 switch (attrs->next_state) {
1223 case C4IW_QP_STATE_RTS:
1224 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1225 ret = -EINVAL;
1226 goto out;
1227 }
1228 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1229 ret = -EINVAL;
1230 goto out;
1231 }
1232 qhp->attr.mpa_attr = attrs->mpa_attr;
1233 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1234 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1235 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1236
1237 /*
1238 * Ref the endpoint here and deref when we
1239 * disassociate the endpoint from the QP. This
1240 * happens in CLOSING->IDLE transition or *->ERROR
1241 * transition.
1242 */
1243 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1244 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1245 if (ret)
1246 goto err;
1247 break;
1248 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1249 set_state(qhp, C4IW_QP_STATE_ERROR);
1250 flush_qp(qhp);
cfdda9d7
SW		 1251 break;
1252 default:
1253 ret = -EINVAL;
1254 goto out;
1255 }
1256 break;
1257 case C4IW_QP_STATE_RTS:
1258 switch (attrs->next_state) {
1259 case C4IW_QP_STATE_CLOSING:
1260 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
2f5b48c3 1261 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1262 ep = qhp->ep;
cfdda9d7
SW		 1263 if (!internal) {
1264 abort = 0;
1265 disconnect = 1;
2f5b48c3 1266 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1267 }
d32ae393
TT		 1268 if (qhp->ibqp.uobject)
1269 t4_set_wq_in_error(&qhp->wq);
73d6fcad 1270 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1271 if (ret)
cfdda9d7 1272 goto err;
cfdda9d7
SW		 1273 break;
1274 case C4IW_QP_STATE_TERMINATE:
2f5b48c3 1275 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1276 qhp->attr.layer_etype = attrs->layer_etype;
1277 qhp->attr.ecode = attrs->ecode;
cfdda9d7
SW		 1278 if (qhp->ibqp.uobject)
1279 t4_set_wq_in_error(&qhp->wq);
be4c9bad 1280 ep = qhp->ep;
0e42c1f4
SW		 1281 if (!internal)
1282 terminate = 1;
be4c9bad 1283 disconnect = 1;
2f5b48c3 1284 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1285 break;
1286 case C4IW_QP_STATE_ERROR:
2f5b48c3 1287 set_state(qhp, C4IW_QP_STATE_ERROR);
d32ae393
TT		 1288 if (qhp->ibqp.uobject)
1289 t4_set_wq_in_error(&qhp->wq);
cfdda9d7
SW		 1290 if (!internal) {
1291 abort = 1;
1292 disconnect = 1;
1293 ep = qhp->ep;
2f5b48c3 1294 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1295 }
1296 goto err;
1297 break;
1298 default:
1299 ret = -EINVAL;
1300 goto out;
1301 }
1302 break;
1303 case C4IW_QP_STATE_CLOSING:
1304 if (!internal) {
1305 ret = -EINVAL;
1306 goto out;
1307 }
1308 switch (attrs->next_state) {
1309 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1310 flush_qp(qhp);
1311 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1312 qhp->attr.llp_stream_handle = NULL;
1313 c4iw_put_ep(&qhp->ep->com);
1314 qhp->ep = NULL;
1315 wake_up(&qhp->wait);
1316 break;
1317 case C4IW_QP_STATE_ERROR:
1318 goto err;
1319 default:
1320 ret = -EINVAL;
1321 goto err;
1322 }
1323 break;
1324 case C4IW_QP_STATE_ERROR:
1325 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1326 ret = -EINVAL;
1327 goto out;
1328 }
1329 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1330 ret = -EINVAL;
1331 goto out;
1332 }
2f5b48c3 1333 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1334 break;
1335 case C4IW_QP_STATE_TERMINATE:
1336 if (!internal) {
1337 ret = -EINVAL;
1338 goto out;
1339 }
1340 goto err;
1341 break;
1342 default:
1343 printk(KERN_ERR "%s in a bad state %d\n",
1344 __func__, qhp->attr.state);
1345 ret = -EINVAL;
1346 goto err;
1347 break;
1348 }
1349 goto out;
1350err:
1351 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1352 qhp->wq.sq.qid);
1353
1354 /* disassociate the LLP connection */
1355 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1356 if (!ep)
1357 ep = qhp->ep;
cfdda9d7 1358 qhp->ep = NULL;
2f5b48c3 1359 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1360 free = 1;
1361 wake_up(&qhp->wait);
1362 BUG_ON(!ep);
2f5b48c3 1363 flush_qp(qhp);
cfdda9d7 1364out:
2f5b48c3 1365 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1366
1367 if (terminate)
be4c9bad 1368 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1369
1370 /*
1371 * If disconnect is 1, then we need to initiate a disconnect
1372 * on the EP. This can be a normal close (RTS->CLOSING) or
1373 * an abnormal close (RTS/CLOSING->ERROR).
1374 */
1375 if (disconnect) {
be4c9bad
RD		 1376 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1377 GFP_KERNEL);
cfdda9d7
SW		 1378 c4iw_put_ep(&ep->com);
1379 }
1380
1381 /*
1382 * If free is 1, then we've disassociated the EP from the QP
1383 * and we need to dereference the EP.
1384 */
1385 if (free)
1386 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1387 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1388 return ret;
1389}
1390
1391int c4iw_destroy_qp(struct ib_qp *ib_qp)
1392{
1393 struct c4iw_dev *rhp;
1394 struct c4iw_qp *qhp;
1395 struct c4iw_qp_attributes attrs;
1396 struct c4iw_ucontext *ucontext;
1397
1398 qhp = to_c4iw_qp(ib_qp);
1399 rhp = qhp->rhp;
1400
1401 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1402 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1403 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1404 else
1405 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1406 wait_event(qhp->wait, !qhp->ep);
1407
1408 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1409 atomic_dec(&qhp->refcnt);
1410 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1411
1412 ucontext = ib_qp->uobject ?
1413 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1414 destroy_qp(&rhp->rdev, &qhp->wq,
1415 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1416
1417 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1418 kfree(qhp);
1419 return 0;
1420}
1421
1422struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1423 struct ib_udata *udata)
1424{
1425 struct c4iw_dev *rhp;
1426 struct c4iw_qp *qhp;
1427 struct c4iw_pd *php;
1428 struct c4iw_cq *schp;
1429 struct c4iw_cq *rchp;
1430 struct c4iw_create_qp_resp uresp;
1431 int sqsize, rqsize;
1432 struct c4iw_ucontext *ucontext;
1433 int ret;
c6d7b267 1434 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1435
1436 PDBG("%s ib_pd %p\n", __func__, pd);
1437
1438 if (attrs->qp_type != IB_QPT_RC)
1439 return ERR_PTR(-EINVAL);
1440
1441 php = to_c4iw_pd(pd);
1442 rhp = php->rhp;
1443 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1444 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1445 if (!schp || !rchp)
1446 return ERR_PTR(-EINVAL);
1447
1448 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1449 return ERR_PTR(-EINVAL);
1450
1451 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1452 if (rqsize > T4_MAX_RQ_SIZE)
1453 return ERR_PTR(-E2BIG);
1454
1455 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1456 if (sqsize > T4_MAX_SQ_SIZE)
1457 return ERR_PTR(-E2BIG);
1458
1459 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1460
1461
1462 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1463 if (!qhp)
1464 return ERR_PTR(-ENOMEM);
1465 qhp->wq.sq.size = sqsize;
1466 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1467 qhp->wq.rq.size = rqsize;
1468 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1469
1470 if (ucontext) {
1471 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1472 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1473 }
1474
1475 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1476 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1477
1478 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1479 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1480 if (ret)
1481 goto err1;
1482
1483 attrs->cap.max_recv_wr = rqsize - 1;
1484 attrs->cap.max_send_wr = sqsize - 1;
1485 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1486
1487 qhp->rhp = rhp;
1488 qhp->attr.pd = php->pdid;
1489 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1490 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1491 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1492 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1493 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1494 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1495 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1496 qhp->attr.state = C4IW_QP_STATE_IDLE;
1497 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1498 qhp->attr.enable_rdma_read = 1;
1499 qhp->attr.enable_rdma_write = 1;
1500 qhp->attr.enable_bind = 1;
1501 qhp->attr.max_ord = 1;
1502 qhp->attr.max_ird = 1;
1503 spin_lock_init(&qhp->lock);
2f5b48c3 1504 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1505 init_waitqueue_head(&qhp->wait);
1506 atomic_set(&qhp->refcnt, 1);
1507
2c974781
VP		 1508 spin_lock_irq(&rhp->lock);
1509 if (rhp->db_state != NORMAL)
1510 t4_disable_wq_db(&qhp->wq);
1511 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1512 spin_unlock_irq(&rhp->lock);
cfdda9d7
SW		 1513 if (ret)
1514 goto err2;
1515
cfdda9d7
SW		 1516 if (udata) {
1517 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1518 if (!mm1) {
1519 ret = -ENOMEM;
30a6a62f 1520 goto err3;
cfdda9d7
SW		 1521 }
1522 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1523 if (!mm2) {
1524 ret = -ENOMEM;
30a6a62f 1525 goto err4;
cfdda9d7
SW		 1526 }
1527 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1528 if (!mm3) {
1529 ret = -ENOMEM;
30a6a62f 1530 goto err5;
cfdda9d7
SW		 1531 }
1532 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1533 if (!mm4) {
1534 ret = -ENOMEM;
30a6a62f 1535 goto err6;
cfdda9d7 1536 }
c6d7b267
SW		 1537 if (t4_sq_onchip(&qhp->wq.sq)) {
1538 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1539 if (!mm5) {
1540 ret = -ENOMEM;
1541 goto err7;
1542 }
1543 uresp.flags = C4IW_QPF_ONCHIP;
1544 } else
1545 uresp.flags = 0;
cfdda9d7
SW		 1546 uresp.qid_mask = rhp->rdev.qpmask;
1547 uresp.sqid = qhp->wq.sq.qid;
1548 uresp.sq_size = qhp->wq.sq.size;
1549 uresp.sq_memsize = qhp->wq.sq.memsize;
1550 uresp.rqid = qhp->wq.rq.qid;
1551 uresp.rq_size = qhp->wq.rq.size;
1552 uresp.rq_memsize = qhp->wq.rq.memsize;
1553 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1554 if (mm5) {
1555 uresp.ma_sync_key = ucontext->key;
1556 ucontext->key += PAGE_SIZE;
1557 }
cfdda9d7
SW		 1558 uresp.sq_key = ucontext->key;
1559 ucontext->key += PAGE_SIZE;
1560 uresp.rq_key = ucontext->key;
1561 ucontext->key += PAGE_SIZE;
1562 uresp.sq_db_gts_key = ucontext->key;
1563 ucontext->key += PAGE_SIZE;
1564 uresp.rq_db_gts_key = ucontext->key;
1565 ucontext->key += PAGE_SIZE;
1566 spin_unlock(&ucontext->mmap_lock);
1567 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1568 if (ret)
c6d7b267 1569 goto err8;
cfdda9d7 1570 mm1->key = uresp.sq_key;
c6d7b267 1571 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1572 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1573 insert_mmap(ucontext, mm1);
1574 mm2->key = uresp.rq_key;
1575 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1576 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1577 insert_mmap(ucontext, mm2);
1578 mm3->key = uresp.sq_db_gts_key;
1579 mm3->addr = qhp->wq.sq.udb;
1580 mm3->len = PAGE_SIZE;
1581 insert_mmap(ucontext, mm3);
1582 mm4->key = uresp.rq_db_gts_key;
1583 mm4->addr = qhp->wq.rq.udb;
1584 mm4->len = PAGE_SIZE;
1585 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1586 if (mm5) {
1587 mm5->key = uresp.ma_sync_key;
1588 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1589 + A_PCIE_MA_SYNC) & PAGE_MASK;
1590 mm5->len = PAGE_SIZE;
1591 insert_mmap(ucontext, mm5);
1592 }
cfdda9d7
SW		 1593 }
1594 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1595 init_timer(&(qhp->timer));
1596 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1597 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1598 qhp->wq.sq.qid);
1599 return &qhp->ibqp;
c6d7b267
SW		 1600err8:
1601 kfree(mm5);
cfdda9d7 1602err7:
30a6a62f 1603 kfree(mm4);
cfdda9d7 1604err6:
30a6a62f 1605 kfree(mm3);
cfdda9d7 1606err5:
30a6a62f 1607 kfree(mm2);
cfdda9d7 1608err4:
30a6a62f 1609 kfree(mm1);
cfdda9d7
SW		 1610err3:
1611 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1612err2:
1613 destroy_qp(&rhp->rdev, &qhp->wq,
1614 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1615err1:
1616 kfree(qhp);
1617 return ERR_PTR(ret);
1618}
1619
1620int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1621 int attr_mask, struct ib_udata *udata)
1622{
1623 struct c4iw_dev *rhp;
1624 struct c4iw_qp *qhp;
1625 enum c4iw_qp_attr_mask mask = 0;
1626 struct c4iw_qp_attributes attrs;
1627
1628 PDBG("%s ib_qp %p\n", __func__, ibqp);
1629
1630 /* iwarp does not support the RTR state */
1631 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1632 attr_mask &= ~IB_QP_STATE;
1633
1634 /* Make sure we still have something left to do */
1635 if (!attr_mask)
1636 return 0;
1637
1638 memset(&attrs, 0, sizeof attrs);
1639 qhp = to_c4iw_qp(ibqp);
1640 rhp = qhp->rhp;
1641
1642 attrs.next_state = c4iw_convert_state(attr->qp_state);
1643 attrs.enable_rdma_read = (attr->qp_access_flags &
1644 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1645 attrs.enable_rdma_write = (attr->qp_access_flags &
1646 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1647 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1648
1649
1650 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1651 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1652 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1653 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1654 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1655
2c974781
VP		 1656 /*
1657 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1658 * ringing the queue db when we're in DB_FULL mode.
1659 */
1660 attrs.sq_db_inc = attr->sq_psn;
1661 attrs.rq_db_inc = attr->rq_psn;
1662 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1663 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1664
cfdda9d7
SW		 1665 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1666}
1667
1668struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1669{
1670 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1671 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1672}
Linux 6.x block layer and io_uring tree(s)