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iw_cxgb4: Detect Ing. Padding Boundary at run-time
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / qp.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e4dd23d7
PG		 32
33#include <linux/module.h>
34
cfdda9d7
SW		 35#include "iw_cxgb4.h"
36
2c974781
VP		 37static int db_delay_usecs = 1;
38module_param(db_delay_usecs, int, 0644);
39MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
a9c77198 41static int ocqp_support = 1;
c6d7b267 42module_param(ocqp_support, int, 0644);
a9c77198 43MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
c6d7b267 44
3cbdb928 45int db_fc_threshold = 1000;
422eea0a 46module_param(db_fc_threshold, int, 0644);
3cbdb928
VP		 47MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51int db_coalescing_threshold;
52module_param(db_coalescing_threshold, int, 0644);
53MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
422eea0a 56
42b6a949
VP		 57static int max_fr_immd = T4_MAX_FR_IMMD;
58module_param(max_fr_immd, int, 0644);
59MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
2f5b48c3
SW		 61static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
62{
63 unsigned long flag;
64 spin_lock_irqsave(&qhp->lock, flag);
65 qhp->attr.state = state;
66 spin_unlock_irqrestore(&qhp->lock, flag);
67}
68
c6d7b267
SW		 69static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
70{
71 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
72}
73
74static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
75{
76 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
77 pci_unmap_addr(sq, mapping));
78}
79
80static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
81{
82 if (t4_sq_onchip(sq))
83 dealloc_oc_sq(rdev, sq);
84 else
85 dealloc_host_sq(rdev, sq);
86}
87
88static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
89{
f079af7a 90 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
c6d7b267
SW		 91 return -ENOSYS;
92 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
93 if (!sq->dma_addr)
94 return -ENOMEM;
95 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
96 rdev->lldi.vr->ocq.start;
97 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
98 rdev->lldi.vr->ocq.start);
99 sq->flags |= T4_SQ_ONCHIP;
100 return 0;
101}
102
103static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
104{
105 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
106 &(sq->dma_addr), GFP_KERNEL);
107 if (!sq->queue)
108 return -ENOMEM;
109 sq->phys_addr = virt_to_phys(sq->queue);
110 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
111 return 0;
112}
113
5b0c2759
TLSC		 114static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
115{
116 int ret = -ENOSYS;
117 if (user)
118 ret = alloc_oc_sq(rdev, sq);
119 if (ret)
120 ret = alloc_host_sq(rdev, sq);
121 return ret;
122}
123
cfdda9d7
SW		 124static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct c4iw_dev_ucontext *uctx)
126{
127 /*
128 * uP clears EQ contexts when the connection exits rdma mode,
129 * so no need to post a RESET WR for these EQs.
130 */
131 dma_free_coherent(&(rdev->lldi.pdev->dev),
132 wq->rq.memsize, wq->rq.queue,
f38926aa 133 dma_unmap_addr(&wq->rq, mapping));
c6d7b267 134 dealloc_sq(rdev, &wq->sq);
cfdda9d7
SW		 135 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
136 kfree(wq->rq.sw_rq);
137 kfree(wq->sq.sw_sq);
138 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
139 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
140 return 0;
141}
142
143static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
144 struct t4_cq *rcq, struct t4_cq *scq,
145 struct c4iw_dev_ucontext *uctx)
146{
147 int user = (uctx != &rdev->uctx);
148 struct fw_ri_res_wr *res_wr;
149 struct fw_ri_res *res;
150 int wr_len;
151 struct c4iw_wr_wait wr_wait;
152 struct sk_buff *skb;
9919d5bd 153 int ret = 0;
cfdda9d7
SW		 154 int eqsize;
155
156 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
157 if (!wq->sq.qid)
158 return -ENOMEM;
159
160 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
c079c287
EG		 161 if (!wq->rq.qid) {
162 ret = -ENOMEM;
163 goto free_sq_qid;
164 }
cfdda9d7
SW		 165
166 if (!user) {
167 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
168 GFP_KERNEL);
c079c287
EG		 169 if (!wq->sq.sw_sq) {
170 ret = -ENOMEM;
171 goto free_rq_qid;
172 }
cfdda9d7
SW		 173
174 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
175 GFP_KERNEL);
c079c287
EG		 176 if (!wq->rq.sw_rq) {
177 ret = -ENOMEM;
178 goto free_sw_sq;
179 }
cfdda9d7
SW		 180 }
181
182 /*
183 * RQT must be a power of 2.
184 */
185 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
186 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
c079c287
EG		 187 if (!wq->rq.rqt_hwaddr) {
188 ret = -ENOMEM;
189 goto free_sw_rq;
190 }
cfdda9d7 191
5b0c2759
TLSC		 192 ret = alloc_sq(rdev, &wq->sq, user);
193 if (ret)
194 goto free_hwaddr;
cfdda9d7 195 memset(wq->sq.queue, 0, wq->sq.memsize);
f38926aa 196 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
cfdda9d7
SW		 197
198 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
199 wq->rq.memsize, &(wq->rq.dma_addr),
200 GFP_KERNEL);
55e57a78
WY		 201 if (!wq->rq.queue) {
202 ret = -ENOMEM;
c079c287 203 goto free_sq;
55e57a78 204 }
cfdda9d7
SW		 205 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
206 __func__, wq->sq.queue,
207 (unsigned long long)virt_to_phys(wq->sq.queue),
208 wq->rq.queue,
209 (unsigned long long)virt_to_phys(wq->rq.queue));
210 memset(wq->rq.queue, 0, wq->rq.memsize);
f38926aa 211 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
cfdda9d7
SW		 212
213 wq->db = rdev->lldi.db_reg;
214 wq->gts = rdev->lldi.gts_reg;
fa658a98
SW		 215 if (user || is_t5(rdev->lldi.adapter_type)) {
216 u32 off;
217
218 off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
219 if (user) {
220 wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
221 } else {
222 off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
223 wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
224 }
225 off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
226 if (user) {
227 wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
228 } else {
229 off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
230 wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
231 }
cfdda9d7
SW		 232 }
233 wq->rdev = rdev;
234 wq->rq.msn = 1;
235
236 /* build fw_ri_res_wr */
237 wr_len = sizeof *res_wr + 2 * sizeof *res;
238
d3c814e8 239 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 240 if (!skb) {
241 ret = -ENOMEM;
c079c287 242 goto free_dma;
cfdda9d7
SW		 243 }
244 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
245
246 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
247 memset(res_wr, 0, wr_len);
248 res_wr->op_nres = cpu_to_be32(
249 FW_WR_OP(FW_RI_RES_WR) |
250 V_FW_RI_RES_WR_NRES(2) |
251 FW_WR_COMPL(1));
252 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 253 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 254 res = res_wr->res;
255 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
256 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
257
258 /*
259 * eqsize is the number of 64B entries plus the status page size.
260 */
04e10e21
HS		 261 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
262 rdev->hw_queue.t4_eq_status_entries;
cfdda9d7
SW		 263
264 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
265 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
266 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
267 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
85d215b0 268 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
cfdda9d7
SW		 269 V_FW_RI_RES_WR_IQID(scq->cqid));
270 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
271 V_FW_RI_RES_WR_DCAEN(0) |
272 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 273 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 274 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 275 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
276 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
277 V_FW_RI_RES_WR_EQSIZE(eqsize));
278 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
279 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
280 res++;
281 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
282 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
283
284 /*
285 * eqsize is the number of 64B entries plus the status page size.
286 */
04e10e21
HS		 287 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
288 rdev->hw_queue.t4_eq_status_entries;
cfdda9d7
SW		 289 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
290 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
291 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
292 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
293 V_FW_RI_RES_WR_IQID(rcq->cqid));
294 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
295 V_FW_RI_RES_WR_DCAEN(0) |
296 V_FW_RI_RES_WR_DCACPU(0) |
d37ac31d 297 V_FW_RI_RES_WR_FBMIN(2) |
6a09a9d6 298 V_FW_RI_RES_WR_FBMAX(2) |
cfdda9d7
SW		 299 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
300 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
301 V_FW_RI_RES_WR_EQSIZE(eqsize));
302 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
303 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
304
305 c4iw_init_wr_wait(&wr_wait);
306
307 ret = c4iw_ofld_send(rdev, skb);
308 if (ret)
c079c287 309 goto free_dma;
aadc4df3 310 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
cfdda9d7 311 if (ret)
c079c287 312 goto free_dma;
cfdda9d7 313
fa658a98 314 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
cfdda9d7 315 __func__, wq->sq.qid, wq->rq.qid, wq->db,
fa658a98
SW		 316 (__force unsigned long) wq->sq.udb,
317 (__force unsigned long) wq->rq.udb);
cfdda9d7
SW		 318
319 return 0;
c079c287 320free_dma:
cfdda9d7
SW		 321 dma_free_coherent(&(rdev->lldi.pdev->dev),
322 wq->rq.memsize, wq->rq.queue,
f38926aa 323 dma_unmap_addr(&wq->rq, mapping));
c079c287 324free_sq:
c6d7b267 325 dealloc_sq(rdev, &wq->sq);
c079c287 326free_hwaddr:
cfdda9d7 327 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
c079c287 328free_sw_rq:
cfdda9d7 329 kfree(wq->rq.sw_rq);
c079c287 330free_sw_sq:
cfdda9d7 331 kfree(wq->sq.sw_sq);
c079c287 332free_rq_qid:
cfdda9d7 333 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
c079c287 334free_sq_qid:
cfdda9d7 335 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
c079c287 336 return ret;
cfdda9d7
SW		 337}
338
d37ac31d
SW		 339static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
340 struct ib_send_wr *wr, int max, u32 *plenp)
cfdda9d7 341{
d37ac31d
SW		 342 u8 *dstp, *srcp;
343 u32 plen = 0;
cfdda9d7 344 int i;
d37ac31d
SW		 345 int rem, len;
346
347 dstp = (u8 *)immdp->data;
348 for (i = 0; i < wr->num_sge; i++) {
349 if ((plen + wr->sg_list[i].length) > max)
350 return -EMSGSIZE;
351 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
352 plen += wr->sg_list[i].length;
353 rem = wr->sg_list[i].length;
354 while (rem) {
355 if (dstp == (u8 *)&sq->queue[sq->size])
356 dstp = (u8 *)sq->queue;
357 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
358 len = rem;
359 else
360 len = (u8 *)&sq->queue[sq->size] - dstp;
361 memcpy(dstp, srcp, len);
362 dstp += len;
363 srcp += len;
364 rem -= len;
365 }
366 }
13fecb83
SW		 367 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
368 if (len)
369 memset(dstp, 0, len);
d37ac31d
SW		 370 immdp->op = FW_RI_DATA_IMMD;
371 immdp->r1 = 0;
372 immdp->r2 = 0;
373 immdp->immdlen = cpu_to_be32(plen);
374 *plenp = plen;
375 return 0;
376}
377
378static int build_isgl(__be64 *queue_start, __be64 *queue_end,
379 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
380 int num_sge, u32 *plenp)
381
382{
383 int i;
384 u32 plen = 0;
385 __be64 *flitp = (__be64 *)isglp->sge;
386
387 for (i = 0; i < num_sge; i++) {
388 if ((plen + sg_list[i].length) < plen)
389 return -EMSGSIZE;
390 plen += sg_list[i].length;
391 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
392 sg_list[i].length);
393 if (++flitp == queue_end)
394 flitp = queue_start;
395 *flitp = cpu_to_be64(sg_list[i].addr);
396 if (++flitp == queue_end)
397 flitp = queue_start;
398 }
13fecb83 399 *flitp = (__force __be64)0;
d37ac31d
SW		 400 isglp->op = FW_RI_DATA_ISGL;
401 isglp->r1 = 0;
402 isglp->nsge = cpu_to_be16(num_sge);
403 isglp->r2 = 0;
404 if (plenp)
405 *plenp = plen;
406 return 0;
407}
408
409static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
410 struct ib_send_wr *wr, u8 *len16)
411{
cfdda9d7
SW		 412 u32 plen;
413 int size;
d37ac31d 414 int ret;
cfdda9d7
SW		 415
416 if (wr->num_sge > T4_MAX_SEND_SGE)
417 return -EINVAL;
418 switch (wr->opcode) {
419 case IB_WR_SEND:
420 if (wr->send_flags & IB_SEND_SOLICITED)
421 wqe->send.sendop_pkd = cpu_to_be32(
422 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
423 else
424 wqe->send.sendop_pkd = cpu_to_be32(
425 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
426 wqe->send.stag_inv = 0;
427 break;
428 case IB_WR_SEND_WITH_INV:
429 if (wr->send_flags & IB_SEND_SOLICITED)
430 wqe->send.sendop_pkd = cpu_to_be32(
431 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
432 else
433 wqe->send.sendop_pkd = cpu_to_be32(
434 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
435 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
436 break;
437
438 default:
439 return -EINVAL;
440 }
c3f98fa2
SW		 441 wqe->send.r3 = 0;
442 wqe->send.r4 = 0;
d37ac31d 443
cfdda9d7
SW		 444 plen = 0;
445 if (wr->num_sge) {
446 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 447 ret = build_immd(sq, wqe->send.u.immd_src, wr,
448 T4_MAX_SEND_INLINE, &plen);
449 if (ret)
450 return ret;
cfdda9d7
SW		 451 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
452 plen;
453 } else {
d37ac31d
SW		 454 ret = build_isgl((__be64 *)sq->queue,
455 (__be64 *)&sq->queue[sq->size],
456 wqe->send.u.isgl_src,
457 wr->sg_list, wr->num_sge, &plen);
458 if (ret)
459 return ret;
cfdda9d7
SW		 460 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
461 wr->num_sge * sizeof(struct fw_ri_sge);
462 }
463 } else {
464 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
465 wqe->send.u.immd_src[0].r1 = 0;
466 wqe->send.u.immd_src[0].r2 = 0;
467 wqe->send.u.immd_src[0].immdlen = 0;
468 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
d37ac31d 469 plen = 0;
cfdda9d7
SW		 470 }
471 *len16 = DIV_ROUND_UP(size, 16);
472 wqe->send.plen = cpu_to_be32(plen);
473 return 0;
474}
475
d37ac31d
SW		 476static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
477 struct ib_send_wr *wr, u8 *len16)
cfdda9d7 478{
cfdda9d7
SW		 479 u32 plen;
480 int size;
d37ac31d 481 int ret;
cfdda9d7 482
d37ac31d 483 if (wr->num_sge > T4_MAX_SEND_SGE)
cfdda9d7
SW		 484 return -EINVAL;
485 wqe->write.r2 = 0;
486 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
487 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
cfdda9d7
SW		 488 if (wr->num_sge) {
489 if (wr->send_flags & IB_SEND_INLINE) {
d37ac31d
SW		 490 ret = build_immd(sq, wqe->write.u.immd_src, wr,
491 T4_MAX_WRITE_INLINE, &plen);
492 if (ret)
493 return ret;
cfdda9d7
SW		 494 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
495 plen;
496 } else {
d37ac31d
SW		 497 ret = build_isgl((__be64 *)sq->queue,
498 (__be64 *)&sq->queue[sq->size],
499 wqe->write.u.isgl_src,
500 wr->sg_list, wr->num_sge, &plen);
501 if (ret)
502 return ret;
cfdda9d7
SW		 503 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
504 wr->num_sge * sizeof(struct fw_ri_sge);
505 }
506 } else {
507 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
508 wqe->write.u.immd_src[0].r1 = 0;
509 wqe->write.u.immd_src[0].r2 = 0;
510 wqe->write.u.immd_src[0].immdlen = 0;
511 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
d37ac31d 512 plen = 0;
cfdda9d7
SW		 513 }
514 *len16 = DIV_ROUND_UP(size, 16);
515 wqe->write.plen = cpu_to_be32(plen);
516 return 0;
517}
518
519static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
520{
521 if (wr->num_sge > 1)
522 return -EINVAL;
523 if (wr->num_sge) {
524 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
525 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
526 >> 32));
527 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
528 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
529 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
530 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
531 >> 32));
532 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
533 } else {
534 wqe->read.stag_src = cpu_to_be32(2);
535 wqe->read.to_src_hi = 0;
536 wqe->read.to_src_lo = 0;
537 wqe->read.stag_sink = cpu_to_be32(2);
538 wqe->read.plen = 0;
539 wqe->read.to_sink_hi = 0;
540 wqe->read.to_sink_lo = 0;
541 }
542 wqe->read.r2 = 0;
543 wqe->read.r5 = 0;
544 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
545 return 0;
546}
547
548static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
549 struct ib_recv_wr *wr, u8 *len16)
550{
d37ac31d 551 int ret;
cfdda9d7 552
d37ac31d
SW		 553 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
554 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
555 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
556 if (ret)
557 return ret;
cfdda9d7
SW		 558 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
559 wr->num_sge * sizeof(struct fw_ri_sge), 16);
560 return 0;
561}
562
40dbf6ee 563static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
42b6a949 564 struct ib_send_wr *wr, u8 *len16, u8 t5dev)
cfdda9d7
SW		 565{
566
567 struct fw_ri_immd *imdp;
568 __be64 *p;
569 int i;
570 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
40dbf6ee 571 int rem;
cfdda9d7 572
a03d9f94
SW		 573 if (wr->wr.fast_reg.page_list_len >
574 t4_max_fr_depth(use_dsgl))
cfdda9d7
SW		 575 return -EINVAL;
576
577 wqe->fr.qpbinde_to_dcacpu = 0;
578 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
579 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
580 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
581 wqe->fr.len_hi = 0;
582 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
583 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
584 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
585 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
586 0xffffffff);
42b6a949
VP		 587
588 if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
589 struct c4iw_fr_page_list *c4pl =
590 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
591 struct fw_ri_dsgl *sglp;
592
593 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
594 wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
595 cpu_to_be64((u64)
596 wr->wr.fast_reg.page_list->page_list[i]);
597 }
598
599 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
600 sglp->op = FW_RI_DATA_DSGL;
601 sglp->r1 = 0;
602 sglp->nsge = cpu_to_be16(1);
603 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
604 sglp->len0 = cpu_to_be32(pbllen);
605
606 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
607 } else {
608 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
609 imdp->op = FW_RI_DATA_IMMD;
610 imdp->r1 = 0;
611 imdp->r2 = 0;
612 imdp->immdlen = cpu_to_be32(pbllen);
613 p = (__be64 *)(imdp + 1);
614 rem = pbllen;
615 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
616 *p = cpu_to_be64(
617 (u64)wr->wr.fast_reg.page_list->page_list[i]);
618 rem -= sizeof(*p);
619 if (++p == (__be64 *)&sq->queue[sq->size])
620 p = (__be64 *)sq->queue;
621 }
622 BUG_ON(rem < 0);
623 while (rem) {
624 *p = 0;
625 rem -= sizeof(*p);
626 if (++p == (__be64 *)&sq->queue[sq->size])
627 p = (__be64 *)sq->queue;
628 }
629 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
630 + pbllen, 16);
cfdda9d7
SW		 631 }
632 return 0;
633}
634
635static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
636 u8 *len16)
637{
638 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
639 wqe->inv.r2 = 0;
640 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
641 return 0;
642}
643
644void c4iw_qp_add_ref(struct ib_qp *qp)
645{
646 PDBG("%s ib_qp %p\n", __func__, qp);
647 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
648}
649
650void c4iw_qp_rem_ref(struct ib_qp *qp)
651{
652 PDBG("%s ib_qp %p\n", __func__, qp);
653 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
654 wake_up(&(to_c4iw_qp(qp)->wait));
655}
656
05eb2389
SW		 657static void add_to_fc_list(struct list_head *head, struct list_head *entry)
658{
659 if (list_empty(entry))
660 list_add_tail(entry, head);
661}
662
663static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
664{
665 unsigned long flags;
666
667 spin_lock_irqsave(&qhp->rhp->lock, flags);
668 spin_lock(&qhp->lock);
fa658a98
SW		 669 if (qhp->rhp->db_state == NORMAL)
670 t4_ring_sq_db(&qhp->wq, inc,
671 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
672 else {
05eb2389
SW		 673 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
674 qhp->wq.sq.wq_pidx_inc += inc;
675 }
676 spin_unlock(&qhp->lock);
677 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
678 return 0;
679}
680
681static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
682{
683 unsigned long flags;
684
685 spin_lock_irqsave(&qhp->rhp->lock, flags);
686 spin_lock(&qhp->lock);
fa658a98
SW		 687 if (qhp->rhp->db_state == NORMAL)
688 t4_ring_rq_db(&qhp->wq, inc,
689 is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
690 else {
05eb2389
SW		 691 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
692 qhp->wq.rq.wq_pidx_inc += inc;
693 }
694 spin_unlock(&qhp->lock);
695 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
696 return 0;
697}
698
cfdda9d7
SW		 699int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
700 struct ib_send_wr **bad_wr)
701{
702 int err = 0;
703 u8 len16 = 0;
704 enum fw_wr_opcodes fw_opcode = 0;
705 enum fw_ri_wr_flags fw_flags;
706 struct c4iw_qp *qhp;
fa658a98 707 union t4_wr *wqe = NULL;
cfdda9d7
SW		 708 u32 num_wrs;
709 struct t4_swsqe *swsqe;
710 unsigned long flag;
711 u16 idx = 0;
712
713 qhp = to_c4iw_qp(ibqp);
714 spin_lock_irqsave(&qhp->lock, flag);
715 if (t4_wq_in_error(&qhp->wq)) {
716 spin_unlock_irqrestore(&qhp->lock, flag);
717 return -EINVAL;
718 }
719 num_wrs = t4_sq_avail(&qhp->wq);
720 if (num_wrs == 0) {
721 spin_unlock_irqrestore(&qhp->lock, flag);
722 return -ENOMEM;
723 }
724 while (wr) {
725 if (num_wrs == 0) {
726 err = -ENOMEM;
727 *bad_wr = wr;
728 break;
729 }
d37ac31d
SW		 730 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
731 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
732
cfdda9d7
SW		 733 fw_flags = 0;
734 if (wr->send_flags & IB_SEND_SOLICITED)
735 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
ba32de9d 736 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
cfdda9d7
SW		 737 fw_flags |= FW_RI_COMPLETION_FLAG;
738 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
739 switch (wr->opcode) {
740 case IB_WR_SEND_WITH_INV:
741 case IB_WR_SEND:
742 if (wr->send_flags & IB_SEND_FENCE)
743 fw_flags |= FW_RI_READ_FENCE_FLAG;
744 fw_opcode = FW_RI_SEND_WR;
745 if (wr->opcode == IB_WR_SEND)
746 swsqe->opcode = FW_RI_SEND;
747 else
748 swsqe->opcode = FW_RI_SEND_WITH_INV;
d37ac31d 749 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 750 break;
751 case IB_WR_RDMA_WRITE:
752 fw_opcode = FW_RI_RDMA_WRITE_WR;
753 swsqe->opcode = FW_RI_RDMA_WRITE;
d37ac31d 754 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
cfdda9d7
SW		 755 break;
756 case IB_WR_RDMA_READ:
2f1fb507 757 case IB_WR_RDMA_READ_WITH_INV:
cfdda9d7
SW		 758 fw_opcode = FW_RI_RDMA_READ_WR;
759 swsqe->opcode = FW_RI_READ_REQ;
2f1fb507 760 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
410ade4c 761 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
2f1fb507
SW		 762 else
763 fw_flags = 0;
cfdda9d7
SW		 764 err = build_rdma_read(wqe, wr, &len16);
765 if (err)
766 break;
767 swsqe->read_len = wr->sg_list[0].length;
768 if (!qhp->wq.sq.oldest_read)
769 qhp->wq.sq.oldest_read = swsqe;
770 break;
771 case IB_WR_FAST_REG_MR:
772 fw_opcode = FW_RI_FR_NSMR_WR;
773 swsqe->opcode = FW_RI_FAST_REGISTER;
42b6a949
VP		 774 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
775 is_t5(
776 qhp->rhp->rdev.lldi.adapter_type) ?
777 1 : 0);
cfdda9d7
SW		 778 break;
779 case IB_WR_LOCAL_INV:
4ab1eb9c
SW		 780 if (wr->send_flags & IB_SEND_FENCE)
781 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
cfdda9d7
SW		 782 fw_opcode = FW_RI_INV_LSTAG_WR;
783 swsqe->opcode = FW_RI_LOCAL_INV;
784 err = build_inv_stag(wqe, wr, &len16);
785 break;
786 default:
787 PDBG("%s post of type=%d TBD!\n", __func__,
788 wr->opcode);
789 err = -EINVAL;
790 }
791 if (err) {
792 *bad_wr = wr;
793 break;
794 }
795 swsqe->idx = qhp->wq.sq.pidx;
796 swsqe->complete = 0;
ba32de9d
SW		 797 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
798 qhp->sq_sig_all;
1cf24dce 799 swsqe->flushed = 0;
cfdda9d7
SW		 800 swsqe->wr_id = wr->wr_id;
801
802 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
803
804 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
805 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
806 swsqe->opcode, swsqe->read_len);
807 wr = wr->next;
808 num_wrs--;
d37ac31d
SW		 809 t4_sq_produce(&qhp->wq, len16);
810 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7 811 }
05eb2389 812 if (!qhp->rhp->rdev.status_page->db_off) {
fa658a98
SW		 813 t4_ring_sq_db(&qhp->wq, idx,
814 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
05eb2389
SW		 815 spin_unlock_irqrestore(&qhp->lock, flag);
816 } else {
817 spin_unlock_irqrestore(&qhp->lock, flag);
818 ring_kernel_sq_db(qhp, idx);
819 }
cfdda9d7
SW		 820 return err;
821}
822
823int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
824 struct ib_recv_wr **bad_wr)
825{
826 int err = 0;
827 struct c4iw_qp *qhp;
fa658a98 828 union t4_recv_wr *wqe = NULL;
cfdda9d7
SW		 829 u32 num_wrs;
830 u8 len16 = 0;
831 unsigned long flag;
832 u16 idx = 0;
833
834 qhp = to_c4iw_qp(ibqp);
835 spin_lock_irqsave(&qhp->lock, flag);
836 if (t4_wq_in_error(&qhp->wq)) {
837 spin_unlock_irqrestore(&qhp->lock, flag);
838 return -EINVAL;
839 }
840 num_wrs = t4_rq_avail(&qhp->wq);
841 if (num_wrs == 0) {
842 spin_unlock_irqrestore(&qhp->lock, flag);
843 return -ENOMEM;
844 }
845 while (wr) {
846 if (wr->num_sge > T4_MAX_RECV_SGE) {
847 err = -EINVAL;
848 *bad_wr = wr;
849 break;
850 }
d37ac31d
SW		 851 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
852 qhp->wq.rq.wq_pidx *
853 T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 854 if (num_wrs)
855 err = build_rdma_recv(qhp, wqe, wr, &len16);
856 else
857 err = -ENOMEM;
858 if (err) {
859 *bad_wr = wr;
860 break;
861 }
862
863 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
864
865 wqe->recv.opcode = FW_RI_RECV_WR;
866 wqe->recv.r1 = 0;
867 wqe->recv.wrid = qhp->wq.rq.pidx;
868 wqe->recv.r2[0] = 0;
869 wqe->recv.r2[1] = 0;
870 wqe->recv.r2[2] = 0;
871 wqe->recv.len16 = len16;
cfdda9d7
SW		 872 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
873 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
d37ac31d
SW		 874 t4_rq_produce(&qhp->wq, len16);
875 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
cfdda9d7
SW		 876 wr = wr->next;
877 num_wrs--;
cfdda9d7 878 }
05eb2389 879 if (!qhp->rhp->rdev.status_page->db_off) {
fa658a98
SW		 880 t4_ring_rq_db(&qhp->wq, idx,
881 is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
05eb2389
SW		 882 spin_unlock_irqrestore(&qhp->lock, flag);
883 } else {
884 spin_unlock_irqrestore(&qhp->lock, flag);
885 ring_kernel_rq_db(qhp, idx);
886 }
cfdda9d7
SW		 887 return err;
888}
889
890int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
891{
892 return -ENOSYS;
893}
894
895static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
896 u8 *ecode)
897{
898 int status;
899 int tagged;
900 int opcode;
901 int rqtype;
902 int send_inv;
903
904 if (!err_cqe) {
905 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
906 *ecode = 0;
907 return;
908 }
909
910 status = CQE_STATUS(err_cqe);
911 opcode = CQE_OPCODE(err_cqe);
912 rqtype = RQ_TYPE(err_cqe);
913 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
914 (opcode == FW_RI_SEND_WITH_SE_INV);
915 tagged = (opcode == FW_RI_RDMA_WRITE) ||
916 (rqtype && (opcode == FW_RI_READ_RESP));
917
918 switch (status) {
919 case T4_ERR_STAG:
920 if (send_inv) {
921 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
922 *ecode = RDMAP_CANT_INV_STAG;
923 } else {
924 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
925 *ecode = RDMAP_INV_STAG;
926 }
927 break;
928 case T4_ERR_PDID:
929 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
930 if ((opcode == FW_RI_SEND_WITH_INV) ||
931 (opcode == FW_RI_SEND_WITH_SE_INV))
932 *ecode = RDMAP_CANT_INV_STAG;
933 else
934 *ecode = RDMAP_STAG_NOT_ASSOC;
935 break;
936 case T4_ERR_QPID:
937 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
938 *ecode = RDMAP_STAG_NOT_ASSOC;
939 break;
940 case T4_ERR_ACCESS:
941 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
942 *ecode = RDMAP_ACC_VIOL;
943 break;
944 case T4_ERR_WRAP:
945 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
946 *ecode = RDMAP_TO_WRAP;
947 break;
948 case T4_ERR_BOUND:
949 if (tagged) {
950 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
951 *ecode = DDPT_BASE_BOUNDS;
952 } else {
953 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
954 *ecode = RDMAP_BASE_BOUNDS;
955 }
956 break;
957 case T4_ERR_INVALIDATE_SHARED_MR:
958 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
959 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
960 *ecode = RDMAP_CANT_INV_STAG;
961 break;
962 case T4_ERR_ECC:
963 case T4_ERR_ECC_PSTAG:
964 case T4_ERR_INTERNAL_ERR:
965 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
966 *ecode = 0;
967 break;
968 case T4_ERR_OUT_OF_RQE:
969 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
970 *ecode = DDPU_INV_MSN_NOBUF;
971 break;
972 case T4_ERR_PBL_ADDR_BOUND:
973 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
974 *ecode = DDPT_BASE_BOUNDS;
975 break;
976 case T4_ERR_CRC:
977 *layer_type = LAYER_MPA|DDP_LLP;
978 *ecode = MPA_CRC_ERR;
979 break;
980 case T4_ERR_MARKER:
981 *layer_type = LAYER_MPA|DDP_LLP;
982 *ecode = MPA_MARKER_ERR;
983 break;
984 case T4_ERR_PDU_LEN_ERR:
985 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
986 *ecode = DDPU_MSG_TOOBIG;
987 break;
988 case T4_ERR_DDP_VERSION:
989 if (tagged) {
990 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
991 *ecode = DDPT_INV_VERS;
992 } else {
993 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
994 *ecode = DDPU_INV_VERS;
995 }
996 break;
997 case T4_ERR_RDMA_VERSION:
998 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
999 *ecode = RDMAP_INV_VERS;
1000 break;
1001 case T4_ERR_OPCODE:
1002 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1003 *ecode = RDMAP_INV_OPCODE;
1004 break;
1005 case T4_ERR_DDP_QUEUE_NUM:
1006 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1007 *ecode = DDPU_INV_QN;
1008 break;
1009 case T4_ERR_MSN:
1010 case T4_ERR_MSN_GAP:
1011 case T4_ERR_MSN_RANGE:
1012 case T4_ERR_IRD_OVERFLOW:
1013 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1014 *ecode = DDPU_INV_MSN_RANGE;
1015 break;
1016 case T4_ERR_TBIT:
1017 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1018 *ecode = 0;
1019 break;
1020 case T4_ERR_MO:
1021 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1022 *ecode = DDPU_INV_MO;
1023 break;
1024 default:
1025 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1026 *ecode = 0;
1027 break;
1028 }
1029}
1030
be4c9bad
RD		 1031static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1032 gfp_t gfp)
cfdda9d7
SW		 1033{
1034 struct fw_ri_wr *wqe;
1035 struct sk_buff *skb;
1036 struct terminate_message *term;
1037
1038 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1039 qhp->ep->hwtid);
1040
be4c9bad 1041 skb = alloc_skb(sizeof *wqe, gfp);
cfdda9d7 1042 if (!skb)
be4c9bad 1043 return;
cfdda9d7
SW		 1044 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1045
1046 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1047 memset(wqe, 0, sizeof *wqe);
1048 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1049 wqe->flowid_len16 = cpu_to_be32(
1050 FW_WR_FLOWID(qhp->ep->hwtid) |
1051 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1052
1053 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1054 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1055 term = (struct terminate_message *)wqe->u.terminate.termmsg;
d2fe99e8
KS		 1056 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1057 term->layer_etype = qhp->attr.layer_etype;
1058 term->ecode = qhp->attr.ecode;
1059 } else
1060 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
be4c9bad 1061 c4iw_ofld_send(&qhp->rhp->rdev, skb);
cfdda9d7
SW		 1062}
1063
1064/*
1065 * Assumes qhp lock is held.
1066 */
1067static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
2f5b48c3 1068 struct c4iw_cq *schp)
cfdda9d7
SW		 1069{
1070 int count;
1071 int flushed;
2f5b48c3 1072 unsigned long flag;
cfdda9d7
SW		 1073
1074 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
cfdda9d7 1075
732bee7a 1076 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1077 spin_lock_irqsave(&rchp->lock, flag);
cfdda9d7 1078 spin_lock(&qhp->lock);
1cf24dce
SW		 1079
1080 if (qhp->wq.flushed) {
1081 spin_unlock(&qhp->lock);
1082 spin_unlock_irqrestore(&rchp->lock, flag);
1083 return;
1084 }
1085 qhp->wq.flushed = 1;
1086
1087 c4iw_flush_hw_cq(rchp);
cfdda9d7
SW		 1088 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1089 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1090 spin_unlock(&qhp->lock);
2f5b48c3 1091 spin_unlock_irqrestore(&rchp->lock, flag);
581bbe2c
KS		 1092 if (flushed) {
1093 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
cfdda9d7 1094 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c
KS		 1095 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1096 }
cfdda9d7 1097
732bee7a 1098 /* locking hierarchy: cq lock first, then qp lock. */
2f5b48c3 1099 spin_lock_irqsave(&schp->lock, flag);
cfdda9d7 1100 spin_lock(&qhp->lock);
1cf24dce
SW		 1101 if (schp != rchp)
1102 c4iw_flush_hw_cq(schp);
1103 flushed = c4iw_flush_sq(qhp);
cfdda9d7 1104 spin_unlock(&qhp->lock);
2f5b48c3 1105 spin_unlock_irqrestore(&schp->lock, flag);
581bbe2c
KS		 1106 if (flushed) {
1107 spin_lock_irqsave(&schp->comp_handler_lock, flag);
cfdda9d7 1108 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
581bbe2c
KS		 1109 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1110 }
cfdda9d7
SW		 1111}
1112
2f5b48c3 1113static void flush_qp(struct c4iw_qp *qhp)
cfdda9d7
SW		 1114{
1115 struct c4iw_cq *rchp, *schp;
581bbe2c 1116 unsigned long flag;
cfdda9d7 1117
1cf24dce
SW		 1118 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1119 schp = to_c4iw_cq(qhp->ibqp.send_cq);
cfdda9d7 1120
1cf24dce 1121 t4_set_wq_in_error(&qhp->wq);
cfdda9d7 1122 if (qhp->ibqp.uobject) {
cfdda9d7 1123 t4_set_cq_in_error(&rchp->cq);
581bbe2c 1124 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
01e7da6b 1125 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
581bbe2c 1126 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
01e7da6b 1127 if (schp != rchp) {
cfdda9d7 1128 t4_set_cq_in_error(&schp->cq);
581bbe2c 1129 spin_lock_irqsave(&schp->comp_handler_lock, flag);
01e7da6b
KS		 1130 (*schp->ibcq.comp_handler)(&schp->ibcq,
1131 schp->ibcq.cq_context);
581bbe2c 1132 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
01e7da6b 1133 }
cfdda9d7
SW		 1134 return;
1135 }
2f5b48c3 1136 __flush_qp(qhp, rchp, schp);
cfdda9d7
SW		 1137}
1138
73d6fcad
SW		 1139static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1140 struct c4iw_ep *ep)
cfdda9d7
SW		 1141{
1142 struct fw_ri_wr *wqe;
1143 int ret;
cfdda9d7
SW		 1144 struct sk_buff *skb;
1145
1146 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
73d6fcad 1147 ep->hwtid);
cfdda9d7 1148
d3c814e8 1149 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1150 if (!skb)
1151 return -ENOMEM;
73d6fcad 1152 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
cfdda9d7
SW		 1153
1154 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1155 memset(wqe, 0, sizeof *wqe);
1156 wqe->op_compl = cpu_to_be32(
1157 FW_WR_OP(FW_RI_INIT_WR) |
1158 FW_WR_COMPL(1));
1159 wqe->flowid_len16 = cpu_to_be32(
73d6fcad 1160 FW_WR_FLOWID(ep->hwtid) |
cfdda9d7 1161 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
2f5b48c3 1162 wqe->cookie = (unsigned long) &ep->com.wr_wait;
cfdda9d7
SW		 1163
1164 wqe->u.fini.type = FW_RI_TYPE_FINI;
cfdda9d7
SW		 1165 ret = c4iw_ofld_send(&rhp->rdev, skb);
1166 if (ret)
1167 goto out;
1168
2f5b48c3 1169 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
aadc4df3 1170 qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1171out:
1172 PDBG("%s ret %d\n", __func__, ret);
1173 return ret;
1174}
1175
1176static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1177{
d2fe99e8 1178 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
cfdda9d7
SW		 1179 memset(&init->u, 0, sizeof init->u);
1180 switch (p2p_type) {
1181 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1182 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1183 init->u.write.stag_sink = cpu_to_be32(1);
1184 init->u.write.to_sink = cpu_to_be64(1);
1185 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1186 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1187 sizeof(struct fw_ri_immd),
1188 16);
1189 break;
1190 case FW_RI_INIT_P2PTYPE_READ_REQ:
1191 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1192 init->u.read.stag_src = cpu_to_be32(1);
1193 init->u.read.to_src_lo = cpu_to_be32(1);
1194 init->u.read.stag_sink = cpu_to_be32(1);
1195 init->u.read.to_sink_lo = cpu_to_be32(1);
1196 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1197 break;
1198 }
1199}
1200
1201static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1202{
1203 struct fw_ri_wr *wqe;
1204 int ret;
cfdda9d7
SW		 1205 struct sk_buff *skb;
1206
1207 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1208 qhp->ep->hwtid);
1209
d3c814e8 1210 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
cfdda9d7
SW		 1211 if (!skb)
1212 return -ENOMEM;
1213 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1214
1215 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1216 memset(wqe, 0, sizeof *wqe);
1217 wqe->op_compl = cpu_to_be32(
1218 FW_WR_OP(FW_RI_INIT_WR) |
1219 FW_WR_COMPL(1));
1220 wqe->flowid_len16 = cpu_to_be32(
1221 FW_WR_FLOWID(qhp->ep->hwtid) |
1222 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1223
2f5b48c3 1224 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
cfdda9d7
SW		 1225
1226 wqe->u.init.type = FW_RI_TYPE_INIT;
1227 wqe->u.init.mpareqbit_p2ptype =
1228 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1229 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1230 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1231 if (qhp->attr.mpa_attr.recv_marker_enabled)
1232 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1233 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1234 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1235 if (qhp->attr.mpa_attr.crc_enabled)
1236 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1237
1238 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1239 FW_RI_QP_RDMA_WRITE_ENABLE |
1240 FW_RI_QP_BIND_ENABLE;
1241 if (!qhp->ibqp.uobject)
1242 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1243 FW_RI_QP_STAG0_ENABLE;
1244 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1245 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1246 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1247 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1248 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1249 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1250 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1251 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1252 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1253 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1254 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1255 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1256 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1257 rhp->rdev.lldi.vr->rq.start);
1258 if (qhp->attr.mpa_attr.initiator)
1259 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1260
cfdda9d7
SW		 1261 ret = c4iw_ofld_send(&rhp->rdev, skb);
1262 if (ret)
1263 goto out;
1264
2f5b48c3
SW		 1265 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1266 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
cfdda9d7
SW		 1267out:
1268 PDBG("%s ret %d\n", __func__, ret);
1269 return ret;
1270}
1271
1272int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1273 enum c4iw_qp_attr_mask mask,
1274 struct c4iw_qp_attributes *attrs,
1275 int internal)
1276{
1277 int ret = 0;
1278 struct c4iw_qp_attributes newattr = qhp->attr;
cfdda9d7
SW		 1279 int disconnect = 0;
1280 int terminate = 0;
1281 int abort = 0;
1282 int free = 0;
1283 struct c4iw_ep *ep = NULL;
1284
1285 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1286 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1287 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1288
2f5b48c3 1289 mutex_lock(&qhp->mutex);
cfdda9d7
SW		 1290
1291 /* Process attr changes if in IDLE */
1292 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1293 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1294 ret = -EIO;
1295 goto out;
1296 }
1297 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1298 newattr.enable_rdma_read = attrs->enable_rdma_read;
1299 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1300 newattr.enable_rdma_write = attrs->enable_rdma_write;
1301 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1302 newattr.enable_bind = attrs->enable_bind;
1303 if (mask & C4IW_QP_ATTR_MAX_ORD) {
be4c9bad 1304 if (attrs->max_ord > c4iw_max_read_depth) {
cfdda9d7
SW		 1305 ret = -EINVAL;
1306 goto out;
1307 }
1308 newattr.max_ord = attrs->max_ord;
1309 }
1310 if (mask & C4IW_QP_ATTR_MAX_IRD) {
be4c9bad 1311 if (attrs->max_ird > c4iw_max_read_depth) {
cfdda9d7
SW		 1312 ret = -EINVAL;
1313 goto out;
1314 }
1315 newattr.max_ird = attrs->max_ird;
1316 }
1317 qhp->attr = newattr;
1318 }
1319
2c974781 1320 if (mask & C4IW_QP_ATTR_SQ_DB) {
05eb2389 1321 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
2c974781
VP		 1322 goto out;
1323 }
1324 if (mask & C4IW_QP_ATTR_RQ_DB) {
05eb2389 1325 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
2c974781
VP		 1326 goto out;
1327 }
1328
cfdda9d7
SW		 1329 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1330 goto out;
1331 if (qhp->attr.state == attrs->next_state)
1332 goto out;
1333
1334 switch (qhp->attr.state) {
1335 case C4IW_QP_STATE_IDLE:
1336 switch (attrs->next_state) {
1337 case C4IW_QP_STATE_RTS:
1338 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1339 ret = -EINVAL;
1340 goto out;
1341 }
1342 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1343 ret = -EINVAL;
1344 goto out;
1345 }
1346 qhp->attr.mpa_attr = attrs->mpa_attr;
1347 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1348 qhp->ep = qhp->attr.llp_stream_handle;
2f5b48c3 1349 set_state(qhp, C4IW_QP_STATE_RTS);
cfdda9d7
SW		 1350
1351 /*
1352 * Ref the endpoint here and deref when we
1353 * disassociate the endpoint from the QP. This
1354 * happens in CLOSING->IDLE transition or *->ERROR
1355 * transition.
1356 */
1357 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1358 ret = rdma_init(rhp, qhp);
cfdda9d7
SW		 1359 if (ret)
1360 goto err;
1361 break;
1362 case C4IW_QP_STATE_ERROR:
2f5b48c3
SW		 1363 set_state(qhp, C4IW_QP_STATE_ERROR);
1364 flush_qp(qhp);
cfdda9d7
SW		 1365 break;
1366 default:
1367 ret = -EINVAL;
1368 goto out;
1369 }
1370 break;
1371 case C4IW_QP_STATE_RTS:
1372 switch (attrs->next_state) {
1373 case C4IW_QP_STATE_CLOSING:
1374 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
b4e2901c 1375 t4_set_wq_in_error(&qhp->wq);
2f5b48c3 1376 set_state(qhp, C4IW_QP_STATE_CLOSING);
73d6fcad 1377 ep = qhp->ep;
cfdda9d7
SW		 1378 if (!internal) {
1379 abort = 0;
1380 disconnect = 1;
2f5b48c3 1381 c4iw_get_ep(&qhp->ep->com);
cfdda9d7 1382 }
73d6fcad 1383 ret = rdma_fini(rhp, qhp, ep);
8da7e7a5 1384 if (ret)
cfdda9d7 1385 goto err;
cfdda9d7
SW		 1386 break;
1387 case C4IW_QP_STATE_TERMINATE:
b4e2901c 1388 t4_set_wq_in_error(&qhp->wq);
2f5b48c3 1389 set_state(qhp, C4IW_QP_STATE_TERMINATE);
d2fe99e8
KS		 1390 qhp->attr.layer_etype = attrs->layer_etype;
1391 qhp->attr.ecode = attrs->ecode;
be4c9bad 1392 ep = qhp->ep;
cc18b939
SW		 1393 if (!internal) {
1394 c4iw_get_ep(&qhp->ep->com);
0e42c1f4 1395 terminate = 1;
cc18b939
SW		 1396 disconnect = 1;
1397 } else {
1398 terminate = qhp->attr.send_term;
09992579
SW		 1399 ret = rdma_fini(rhp, qhp, ep);
1400 if (ret)
1401 goto err;
1402 }
cfdda9d7
SW		 1403 break;
1404 case C4IW_QP_STATE_ERROR:
1cf24dce 1405 t4_set_wq_in_error(&qhp->wq);
b4e2901c 1406 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7
SW		 1407 if (!internal) {
1408 abort = 1;
1409 disconnect = 1;
1410 ep = qhp->ep;
2f5b48c3 1411 c4iw_get_ep(&qhp->ep->com);
cfdda9d7
SW		 1412 }
1413 goto err;
1414 break;
1415 default:
1416 ret = -EINVAL;
1417 goto out;
1418 }
1419 break;
1420 case C4IW_QP_STATE_CLOSING:
1421 if (!internal) {
1422 ret = -EINVAL;
1423 goto out;
1424 }
1425 switch (attrs->next_state) {
1426 case C4IW_QP_STATE_IDLE:
2f5b48c3
SW		 1427 flush_qp(qhp);
1428 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1429 qhp->attr.llp_stream_handle = NULL;
1430 c4iw_put_ep(&qhp->ep->com);
1431 qhp->ep = NULL;
1432 wake_up(&qhp->wait);
1433 break;
1434 case C4IW_QP_STATE_ERROR:
1435 goto err;
1436 default:
1437 ret = -EINVAL;
1438 goto err;
1439 }
1440 break;
1441 case C4IW_QP_STATE_ERROR:
1442 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1443 ret = -EINVAL;
1444 goto out;
1445 }
1446 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1447 ret = -EINVAL;
1448 goto out;
1449 }
2f5b48c3 1450 set_state(qhp, C4IW_QP_STATE_IDLE);
cfdda9d7
SW		 1451 break;
1452 case C4IW_QP_STATE_TERMINATE:
1453 if (!internal) {
1454 ret = -EINVAL;
1455 goto out;
1456 }
1457 goto err;
1458 break;
1459 default:
1460 printk(KERN_ERR "%s in a bad state %d\n",
1461 __func__, qhp->attr.state);
1462 ret = -EINVAL;
1463 goto err;
1464 break;
1465 }
1466 goto out;
1467err:
1468 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1469 qhp->wq.sq.qid);
1470
1471 /* disassociate the LLP connection */
1472 qhp->attr.llp_stream_handle = NULL;
af93fb5d
SW		 1473 if (!ep)
1474 ep = qhp->ep;
cfdda9d7 1475 qhp->ep = NULL;
2f5b48c3 1476 set_state(qhp, C4IW_QP_STATE_ERROR);
cfdda9d7 1477 free = 1;
91e9c071 1478 abort = 1;
cfdda9d7
SW		 1479 wake_up(&qhp->wait);
1480 BUG_ON(!ep);
2f5b48c3 1481 flush_qp(qhp);
cfdda9d7 1482out:
2f5b48c3 1483 mutex_unlock(&qhp->mutex);
cfdda9d7
SW		 1484
1485 if (terminate)
be4c9bad 1486 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
cfdda9d7
SW		 1487
1488 /*
1489 * If disconnect is 1, then we need to initiate a disconnect
1490 * on the EP. This can be a normal close (RTS->CLOSING) or
1491 * an abnormal close (RTS/CLOSING->ERROR).
1492 */
1493 if (disconnect) {
be4c9bad
RD		 1494 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1495 GFP_KERNEL);
cfdda9d7
SW		 1496 c4iw_put_ep(&ep->com);
1497 }
1498
1499 /*
1500 * If free is 1, then we've disassociated the EP from the QP
1501 * and we need to dereference the EP.
1502 */
1503 if (free)
1504 c4iw_put_ep(&ep->com);
cfdda9d7
SW		 1505 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1506 return ret;
1507}
1508
1509int c4iw_destroy_qp(struct ib_qp *ib_qp)
1510{
1511 struct c4iw_dev *rhp;
1512 struct c4iw_qp *qhp;
1513 struct c4iw_qp_attributes attrs;
1514 struct c4iw_ucontext *ucontext;
1515
1516 qhp = to_c4iw_qp(ib_qp);
1517 rhp = qhp->rhp;
1518
1519 attrs.next_state = C4IW_QP_STATE_ERROR;
d2fe99e8
KS		 1520 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1521 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1522 else
1523 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
cfdda9d7
SW		 1524 wait_event(qhp->wait, !qhp->ep);
1525
05eb2389 1526 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
cfdda9d7
SW		 1527 atomic_dec(&qhp->refcnt);
1528 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1529
05eb2389
SW		 1530 spin_lock_irq(&rhp->lock);
1531 if (!list_empty(&qhp->db_fc_entry))
1532 list_del_init(&qhp->db_fc_entry);
1533 spin_unlock_irq(&rhp->lock);
1534
cfdda9d7
SW		 1535 ucontext = ib_qp->uobject ?
1536 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1537 destroy_qp(&rhp->rdev, &qhp->wq,
1538 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1539
1540 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1541 kfree(qhp);
1542 return 0;
1543}
1544
1545struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1546 struct ib_udata *udata)
1547{
1548 struct c4iw_dev *rhp;
1549 struct c4iw_qp *qhp;
1550 struct c4iw_pd *php;
1551 struct c4iw_cq *schp;
1552 struct c4iw_cq *rchp;
1553 struct c4iw_create_qp_resp uresp;
ff1706f4 1554 unsigned int sqsize, rqsize;
cfdda9d7
SW		 1555 struct c4iw_ucontext *ucontext;
1556 int ret;
c6d7b267 1557 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
cfdda9d7
SW		 1558
1559 PDBG("%s ib_pd %p\n", __func__, pd);
1560
1561 if (attrs->qp_type != IB_QPT_RC)
1562 return ERR_PTR(-EINVAL);
1563
1564 php = to_c4iw_pd(pd);
1565 rhp = php->rhp;
1566 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1567 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1568 if (!schp || !rchp)
1569 return ERR_PTR(-EINVAL);
1570
1571 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1572 return ERR_PTR(-EINVAL);
1573
1574 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
04e10e21 1575 if (rqsize > rhp->rdev.hw_queue.t4_max_rq_size)
cfdda9d7
SW		 1576 return ERR_PTR(-E2BIG);
1577
1578 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
04e10e21 1579 if (sqsize > rhp->rdev.hw_queue.t4_max_sq_size)
cfdda9d7
SW		 1580 return ERR_PTR(-E2BIG);
1581
1582 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1583
cfdda9d7
SW		 1584 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1585 if (!qhp)
1586 return ERR_PTR(-ENOMEM);
1587 qhp->wq.sq.size = sqsize;
1588 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1cf24dce 1589 qhp->wq.sq.flush_cidx = -1;
cfdda9d7
SW		 1590 qhp->wq.rq.size = rqsize;
1591 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1592
1593 if (ucontext) {
1594 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1595 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1596 }
1597
1598 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1599 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1600
1601 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1602 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1603 if (ret)
1604 goto err1;
1605
1606 attrs->cap.max_recv_wr = rqsize - 1;
1607 attrs->cap.max_send_wr = sqsize - 1;
1608 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1609
1610 qhp->rhp = rhp;
1611 qhp->attr.pd = php->pdid;
1612 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1613 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1614 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1615 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1616 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1617 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1618 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1619 qhp->attr.state = C4IW_QP_STATE_IDLE;
1620 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1621 qhp->attr.enable_rdma_read = 1;
1622 qhp->attr.enable_rdma_write = 1;
1623 qhp->attr.enable_bind = 1;
1624 qhp->attr.max_ord = 1;
1625 qhp->attr.max_ird = 1;
ba32de9d 1626 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
cfdda9d7 1627 spin_lock_init(&qhp->lock);
2f5b48c3 1628 mutex_init(&qhp->mutex);
cfdda9d7
SW		 1629 init_waitqueue_head(&qhp->wait);
1630 atomic_set(&qhp->refcnt, 1);
1631
05eb2389 1632 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
cfdda9d7
SW		 1633 if (ret)
1634 goto err2;
1635
cfdda9d7
SW		 1636 if (udata) {
1637 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1638 if (!mm1) {
1639 ret = -ENOMEM;
30a6a62f 1640 goto err3;
cfdda9d7
SW		 1641 }
1642 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1643 if (!mm2) {
1644 ret = -ENOMEM;
30a6a62f 1645 goto err4;
cfdda9d7
SW		 1646 }
1647 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1648 if (!mm3) {
1649 ret = -ENOMEM;
30a6a62f 1650 goto err5;
cfdda9d7
SW		 1651 }
1652 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1653 if (!mm4) {
1654 ret = -ENOMEM;
30a6a62f 1655 goto err6;
cfdda9d7 1656 }
c6d7b267
SW		 1657 if (t4_sq_onchip(&qhp->wq.sq)) {
1658 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1659 if (!mm5) {
1660 ret = -ENOMEM;
1661 goto err7;
1662 }
1663 uresp.flags = C4IW_QPF_ONCHIP;
1664 } else
1665 uresp.flags = 0;
cfdda9d7
SW		 1666 uresp.qid_mask = rhp->rdev.qpmask;
1667 uresp.sqid = qhp->wq.sq.qid;
1668 uresp.sq_size = qhp->wq.sq.size;
1669 uresp.sq_memsize = qhp->wq.sq.memsize;
1670 uresp.rqid = qhp->wq.rq.qid;
1671 uresp.rq_size = qhp->wq.rq.size;
1672 uresp.rq_memsize = qhp->wq.rq.memsize;
1673 spin_lock(&ucontext->mmap_lock);
c6d7b267
SW		 1674 if (mm5) {
1675 uresp.ma_sync_key = ucontext->key;
1676 ucontext->key += PAGE_SIZE;
ae1fe07f
DC		 1677 } else {
1678 uresp.ma_sync_key = 0;
c6d7b267 1679 }
cfdda9d7
SW		 1680 uresp.sq_key = ucontext->key;
1681 ucontext->key += PAGE_SIZE;
1682 uresp.rq_key = ucontext->key;
1683 ucontext->key += PAGE_SIZE;
1684 uresp.sq_db_gts_key = ucontext->key;
1685 ucontext->key += PAGE_SIZE;
1686 uresp.rq_db_gts_key = ucontext->key;
1687 ucontext->key += PAGE_SIZE;
1688 spin_unlock(&ucontext->mmap_lock);
1689 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1690 if (ret)
c6d7b267 1691 goto err8;
cfdda9d7 1692 mm1->key = uresp.sq_key;
c6d7b267 1693 mm1->addr = qhp->wq.sq.phys_addr;
cfdda9d7
SW		 1694 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1695 insert_mmap(ucontext, mm1);
1696 mm2->key = uresp.rq_key;
1697 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1698 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1699 insert_mmap(ucontext, mm2);
1700 mm3->key = uresp.sq_db_gts_key;
fa658a98 1701 mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
cfdda9d7
SW		 1702 mm3->len = PAGE_SIZE;
1703 insert_mmap(ucontext, mm3);
1704 mm4->key = uresp.rq_db_gts_key;
fa658a98 1705 mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
cfdda9d7
SW		 1706 mm4->len = PAGE_SIZE;
1707 insert_mmap(ucontext, mm4);
c6d7b267
SW		 1708 if (mm5) {
1709 mm5->key = uresp.ma_sync_key;
1710 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1711 + A_PCIE_MA_SYNC) & PAGE_MASK;
1712 mm5->len = PAGE_SIZE;
1713 insert_mmap(ucontext, mm5);
1714 }
cfdda9d7
SW		 1715 }
1716 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1717 init_timer(&(qhp->timer));
05eb2389 1718 INIT_LIST_HEAD(&qhp->db_fc_entry);
cfdda9d7
SW		 1719 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1720 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1721 qhp->wq.sq.qid);
1722 return &qhp->ibqp;
c6d7b267
SW		 1723err8:
1724 kfree(mm5);
cfdda9d7 1725err7:
30a6a62f 1726 kfree(mm4);
cfdda9d7 1727err6:
30a6a62f 1728 kfree(mm3);
cfdda9d7 1729err5:
30a6a62f 1730 kfree(mm2);
cfdda9d7 1731err4:
30a6a62f 1732 kfree(mm1);
cfdda9d7
SW		 1733err3:
1734 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1735err2:
1736 destroy_qp(&rhp->rdev, &qhp->wq,
1737 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1738err1:
1739 kfree(qhp);
1740 return ERR_PTR(ret);
1741}
1742
1743int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1744 int attr_mask, struct ib_udata *udata)
1745{
1746 struct c4iw_dev *rhp;
1747 struct c4iw_qp *qhp;
1748 enum c4iw_qp_attr_mask mask = 0;
1749 struct c4iw_qp_attributes attrs;
1750
1751 PDBG("%s ib_qp %p\n", __func__, ibqp);
1752
1753 /* iwarp does not support the RTR state */
1754 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1755 attr_mask &= ~IB_QP_STATE;
1756
1757 /* Make sure we still have something left to do */
1758 if (!attr_mask)
1759 return 0;
1760
1761 memset(&attrs, 0, sizeof attrs);
1762 qhp = to_c4iw_qp(ibqp);
1763 rhp = qhp->rhp;
1764
1765 attrs.next_state = c4iw_convert_state(attr->qp_state);
1766 attrs.enable_rdma_read = (attr->qp_access_flags &
1767 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1768 attrs.enable_rdma_write = (attr->qp_access_flags &
1769 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1770 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1771
1772
1773 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1774 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1775 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1776 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1777 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1778
2c974781
VP		 1779 /*
1780 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1781 * ringing the queue db when we're in DB_FULL mode.
c2f9da92 1782 * Only allow this on T4 devices.
2c974781
VP		 1783 */
1784 attrs.sq_db_inc = attr->sq_psn;
1785 attrs.rq_db_inc = attr->rq_psn;
1786 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1787 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
c2f9da92
SW		 1788 if (is_t5(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1789 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1790 return -EINVAL;
2c974781 1791
cfdda9d7
SW		 1792 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1793}
1794
1795struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1796{
1797 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1798 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1799}
67bbc055
VP		 1800
1801int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1802 int attr_mask, struct ib_qp_init_attr *init_attr)
1803{
1804 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1805
1806 memset(attr, 0, sizeof *attr);
1807 memset(init_attr, 0, sizeof *init_attr);
1808 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1809 return 0;
1810}
Linux 6.x block layer and io_uring tree(s)