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RDMA/cxgb4: Fix QP flush logic
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / cq.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "iw_cxgb4.h"
34
35static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
36 struct c4iw_dev_ucontext *uctx)
37{
38 struct fw_ri_res_wr *res_wr;
39 struct fw_ri_res *res;
40 int wr_len;
41 struct c4iw_wr_wait wr_wait;
42 struct sk_buff *skb;
43 int ret;
44
45 wr_len = sizeof *res_wr + sizeof *res;
d3c814e8 46 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 47 if (!skb)
48 return -ENOMEM;
49 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
50
51 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
52 memset(res_wr, 0, wr_len);
53 res_wr->op_nres = cpu_to_be32(
54 FW_WR_OP(FW_RI_RES_WR) |
55 V_FW_RI_RES_WR_NRES(1) |
56 FW_WR_COMPL(1));
57 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 58 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 59 res = res_wr->res;
60 res->u.cq.restype = FW_RI_RES_TYPE_CQ;
61 res->u.cq.op = FW_RI_RES_OP_RESET;
62 res->u.cq.iqid = cpu_to_be32(cq->cqid);
63
64 c4iw_init_wr_wait(&wr_wait);
65 ret = c4iw_ofld_send(rdev, skb);
66 if (!ret) {
aadc4df3 67 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
cfdda9d7
SW		 68 }
69
70 kfree(cq->sw_queue);
71 dma_free_coherent(&(rdev->lldi.pdev->dev),
72 cq->memsize, cq->queue,
f38926aa 73 dma_unmap_addr(cq, mapping));
cfdda9d7
SW		 74 c4iw_put_cqid(rdev, cq->cqid, uctx);
75 return ret;
76}
77
78static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
79 struct c4iw_dev_ucontext *uctx)
80{
81 struct fw_ri_res_wr *res_wr;
82 struct fw_ri_res *res;
83 int wr_len;
84 int user = (uctx != &rdev->uctx);
85 struct c4iw_wr_wait wr_wait;
86 int ret;
87 struct sk_buff *skb;
88
89 cq->cqid = c4iw_get_cqid(rdev, uctx);
90 if (!cq->cqid) {
91 ret = -ENOMEM;
92 goto err1;
93 }
94
95 if (!user) {
96 cq->sw_queue = kzalloc(cq->memsize, GFP_KERNEL);
97 if (!cq->sw_queue) {
98 ret = -ENOMEM;
99 goto err2;
100 }
101 }
102 cq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev, cq->memsize,
103 &cq->dma_addr, GFP_KERNEL);
104 if (!cq->queue) {
105 ret = -ENOMEM;
106 goto err3;
107 }
f38926aa 108 dma_unmap_addr_set(cq, mapping, cq->dma_addr);
cfdda9d7
SW		 109 memset(cq->queue, 0, cq->memsize);
110
111 /* build fw_ri_res_wr */
112 wr_len = sizeof *res_wr + sizeof *res;
113
d3c814e8 114 skb = alloc_skb(wr_len, GFP_KERNEL);
cfdda9d7
SW		 115 if (!skb) {
116 ret = -ENOMEM;
117 goto err4;
118 }
119 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
120
121 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
122 memset(res_wr, 0, wr_len);
123 res_wr->op_nres = cpu_to_be32(
124 FW_WR_OP(FW_RI_RES_WR) |
125 V_FW_RI_RES_WR_NRES(1) |
126 FW_WR_COMPL(1));
127 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
c8e081a1 128 res_wr->cookie = (unsigned long) &wr_wait;
cfdda9d7
SW		 129 res = res_wr->res;
130 res->u.cq.restype = FW_RI_RES_TYPE_CQ;
131 res->u.cq.op = FW_RI_RES_OP_WRITE;
132 res->u.cq.iqid = cpu_to_be32(cq->cqid);
133 res->u.cq.iqandst_to_iqandstindex = cpu_to_be32(
134 V_FW_RI_RES_WR_IQANUS(0) |
135 V_FW_RI_RES_WR_IQANUD(1) |
136 F_FW_RI_RES_WR_IQANDST |
137 V_FW_RI_RES_WR_IQANDSTINDEX(*rdev->lldi.rxq_ids));
138 res->u.cq.iqdroprss_to_iqesize = cpu_to_be16(
139 F_FW_RI_RES_WR_IQDROPRSS |
140 V_FW_RI_RES_WR_IQPCIECH(2) |
141 V_FW_RI_RES_WR_IQINTCNTTHRESH(0) |
142 F_FW_RI_RES_WR_IQO |
143 V_FW_RI_RES_WR_IQESIZE(1));
144 res->u.cq.iqsize = cpu_to_be16(cq->size);
145 res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr);
146
147 c4iw_init_wr_wait(&wr_wait);
148
149 ret = c4iw_ofld_send(rdev, skb);
150 if (ret)
151 goto err4;
152 PDBG("%s wait_event wr_wait %p\n", __func__, &wr_wait);
aadc4df3 153 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
cfdda9d7
SW		 154 if (ret)
155 goto err4;
156
157 cq->gen = 1;
158 cq->gts = rdev->lldi.gts_reg;
159 cq->rdev = rdev;
160 if (user) {
161 cq->ugts = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
162 (cq->cqid << rdev->cqshift);
163 cq->ugts &= PAGE_MASK;
164 }
165 return 0;
166err4:
167 dma_free_coherent(&rdev->lldi.pdev->dev, cq->memsize, cq->queue,
f38926aa 168 dma_unmap_addr(cq, mapping));
cfdda9d7
SW		 169err3:
170 kfree(cq->sw_queue);
171err2:
172 c4iw_put_cqid(rdev, cq->cqid, uctx);
173err1:
174 return ret;
175}
176
177static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq)
178{
179 struct t4_cqe cqe;
180
181 PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
182 wq, cq, cq->sw_cidx, cq->sw_pidx);
183 memset(&cqe, 0, sizeof(cqe));
184 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
185 V_CQE_OPCODE(FW_RI_SEND) |
186 V_CQE_TYPE(0) |
187 V_CQE_SWCQE(1) |
e14d62c0 188 V_CQE_QPID(wq->sq.qid));
cfdda9d7
SW		 189 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
190 cq->sw_queue[cq->sw_pidx] = cqe;
191 t4_swcq_produce(cq);
192}
193
194int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
195{
196 int flushed = 0;
197 int in_use = wq->rq.in_use - count;
198
199 BUG_ON(in_use < 0);
200 PDBG("%s wq %p cq %p rq.in_use %u skip count %u\n", __func__,
201 wq, cq, wq->rq.in_use, count);
202 while (in_use--) {
203 insert_recv_cqe(wq, cq);
204 flushed++;
205 }
206 return flushed;
207}
208
209static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
210 struct t4_swsqe *swcqe)
211{
212 struct t4_cqe cqe;
213
214 PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
215 wq, cq, cq->sw_cidx, cq->sw_pidx);
216 memset(&cqe, 0, sizeof(cqe));
217 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
218 V_CQE_OPCODE(swcqe->opcode) |
219 V_CQE_TYPE(1) |
220 V_CQE_SWCQE(1) |
221 V_CQE_QPID(wq->sq.qid));
222 CQE_WRID_SQ_IDX(&cqe) = swcqe->idx;
223 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
224 cq->sw_queue[cq->sw_pidx] = cqe;
225 t4_swcq_produce(cq);
226}
227
1cf24dce
SW		 228static void advance_oldest_read(struct t4_wq *wq);
229
230int c4iw_flush_sq(struct c4iw_qp *qhp)
cfdda9d7
SW		 231{
232 int flushed = 0;
1cf24dce
SW		 233 struct t4_wq *wq = &qhp->wq;
234 struct c4iw_cq *chp = to_c4iw_cq(qhp->ibqp.send_cq);
235 struct t4_cq *cq = &chp->cq;
236 int idx;
237 struct t4_swsqe *swsqe;
238 int error = (qhp->attr.state != C4IW_QP_STATE_CLOSING &&
239 qhp->attr.state != C4IW_QP_STATE_IDLE);
240
241 if (wq->sq.flush_cidx == -1)
242 wq->sq.flush_cidx = wq->sq.cidx;
243 idx = wq->sq.flush_cidx;
244 BUG_ON(idx >= wq->sq.size);
245 while (idx != wq->sq.pidx) {
246 if (error) {
247 swsqe = &wq->sq.sw_sq[idx];
248 BUG_ON(swsqe->flushed);
249 swsqe->flushed = 1;
250 insert_sq_cqe(wq, cq, swsqe);
251 if (wq->sq.oldest_read == swsqe) {
252 BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
253 advance_oldest_read(wq);
254 }
255 flushed++;
256 } else {
257 t4_sq_consume(wq);
258 }
259 if (++idx == wq->sq.size)
260 idx = 0;
cfdda9d7 261 }
1cf24dce
SW		 262 wq->sq.flush_cidx += flushed;
263 if (wq->sq.flush_cidx >= wq->sq.size)
264 wq->sq.flush_cidx -= wq->sq.size;
cfdda9d7
SW		 265 return flushed;
266}
267
1cf24dce
SW		 268static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
269{
270 struct t4_swsqe *swsqe;
271 int cidx;
272
273 if (wq->sq.flush_cidx == -1)
274 wq->sq.flush_cidx = wq->sq.cidx;
275 cidx = wq->sq.flush_cidx;
276 BUG_ON(cidx > wq->sq.size);
277
278 while (cidx != wq->sq.pidx) {
279 swsqe = &wq->sq.sw_sq[cidx];
280 if (!swsqe->signaled) {
281 if (++cidx == wq->sq.size)
282 cidx = 0;
283 } else if (swsqe->complete) {
284
285 BUG_ON(swsqe->flushed);
286
287 /*
288 * Insert this completed cqe into the swcq.
289 */
290 PDBG("%s moving cqe into swcq sq idx %u cq idx %u\n",
291 __func__, cidx, cq->sw_pidx);
292 swsqe->cqe.header |= htonl(V_CQE_SWCQE(1));
293 cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
294 t4_swcq_produce(cq);
295 swsqe->flushed = 1;
296 if (++cidx == wq->sq.size)
297 cidx = 0;
298 wq->sq.flush_cidx = cidx;
299 } else
300 break;
301 }
302}
303
304static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe,
305 struct t4_cqe *read_cqe)
306{
307 read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx;
308 read_cqe->len = htonl(wq->sq.oldest_read->read_len);
309 read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(hw_cqe)) |
310 V_CQE_SWCQE(SW_CQE(hw_cqe)) |
311 V_CQE_OPCODE(FW_RI_READ_REQ) |
312 V_CQE_TYPE(1));
313 read_cqe->bits_type_ts = hw_cqe->bits_type_ts;
314}
315
316static void advance_oldest_read(struct t4_wq *wq)
317{
318
319 u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1;
320
321 if (rptr == wq->sq.size)
322 rptr = 0;
323 while (rptr != wq->sq.pidx) {
324 wq->sq.oldest_read = &wq->sq.sw_sq[rptr];
325
326 if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ)
327 return;
328 if (++rptr == wq->sq.size)
329 rptr = 0;
330 }
331 wq->sq.oldest_read = NULL;
332}
333
cfdda9d7
SW		 334/*
335 * Move all CQEs from the HWCQ into the SWCQ.
1cf24dce
SW		 336 * Deal with out-of-order and/or completions that complete
337 * prior unsignalled WRs.
cfdda9d7 338 */
1cf24dce 339void c4iw_flush_hw_cq(struct c4iw_cq *chp)
cfdda9d7 340{
1cf24dce
SW		 341 struct t4_cqe *hw_cqe, *swcqe, read_cqe;
342 struct c4iw_qp *qhp;
343 struct t4_swsqe *swsqe;
cfdda9d7
SW		 344 int ret;
345
1cf24dce
SW		 346 PDBG("%s cqid 0x%x\n", __func__, chp->cq.cqid);
347 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
348
349 /*
350 * This logic is similar to poll_cq(), but not quite the same
351 * unfortunately. Need to move pertinent HW CQEs to the SW CQ but
352 * also do any translation magic that poll_cq() normally does.
353 */
cfdda9d7 354 while (!ret) {
1cf24dce
SW		 355 qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe));
356
357 /*
358 * drop CQEs with no associated QP
359 */
360 if (qhp == NULL)
361 goto next_cqe;
362
363 if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE)
364 goto next_cqe;
365
366 if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
367
368 /*
369 * drop peer2peer RTR reads.
370 */
371 if (CQE_WRID_STAG(hw_cqe) == 1)
372 goto next_cqe;
373
374 /*
375 * Eat completions for unsignaled read WRs.
376 */
377 if (!qhp->wq.sq.oldest_read->signaled) {
378 advance_oldest_read(&qhp->wq);
379 goto next_cqe;
380 }
381
382 /*
383 * Don't write to the HWCQ, create a new read req CQE
384 * in local memory and move it into the swcq.
385 */
386 create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe);
387 hw_cqe = &read_cqe;
388 advance_oldest_read(&qhp->wq);
389 }
390
391 /* if its a SQ completion, then do the magic to move all the
392 * unsignaled and now in-order completions into the swcq.
393 */
394 if (SQ_TYPE(hw_cqe)) {
395 swsqe = &qhp->wq.sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
396 swsqe->cqe = *hw_cqe;
397 swsqe->complete = 1;
398 flush_completed_wrs(&qhp->wq, &chp->cq);
399 } else {
400 swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx];
401 *swcqe = *hw_cqe;
402 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
403 t4_swcq_produce(&chp->cq);
404 }
405next_cqe:
406 t4_hwcq_consume(&chp->cq);
407 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
cfdda9d7
SW		 408 }
409}
410
411static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
412{
413 if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
414 return 0;
415
416 if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe))
417 return 0;
418
419 if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe))
420 return 0;
421
422 if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq))
423 return 0;
424 return 1;
425}
426
cfdda9d7
SW		 427void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
428{
429 struct t4_cqe *cqe;
430 u32 ptr;
431
432 *count = 0;
433 PDBG("%s count zero %d\n", __func__, *count);
434 ptr = cq->sw_cidx;
435 while (ptr != cq->sw_pidx) {
436 cqe = &cq->sw_queue[ptr];
437 if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) &&
c34c97ad 438 (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq))
cfdda9d7
SW		 439 (*count)++;
440 if (++ptr == cq->size)
441 ptr = 0;
442 }
443 PDBG("%s cq %p count %d\n", __func__, cq, *count);
444}
445
cfdda9d7
SW		 446/*
447 * poll_cq
448 *
449 * Caller must:
450 * check the validity of the first CQE,
451 * supply the wq assicated with the qpid.
452 *
453 * credit: cq credit to return to sge.
454 * cqe_flushed: 1 iff the CQE is flushed.
455 * cqe: copy of the polled CQE.
456 *
457 * return value:
458 * 0 CQE returned ok.
459 * -EAGAIN CQE skipped, try again.
460 * -EOVERFLOW CQ overflow detected.
461 */
462static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
463 u8 *cqe_flushed, u64 *cookie, u32 *credit)
464{
465 int ret = 0;
466 struct t4_cqe *hw_cqe, read_cqe;
467
468 *cqe_flushed = 0;
469 *credit = 0;
470 ret = t4_next_cqe(cq, &hw_cqe);
471 if (ret)
472 return ret;
473
474 PDBG("%s CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x"
475 " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
476 __func__, CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
477 CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
478 CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
479 CQE_WRID_LOW(hw_cqe));
480
481 /*
482 * skip cqe's not affiliated with a QP.
483 */
484 if (wq == NULL) {
485 ret = -EAGAIN;
486 goto skip_cqe;
487 }
488
1cf24dce
SW		 489 /*
490 * skip hw cqe's if the wq is flushed.
491 */
492 if (wq->flushed && !SW_CQE(hw_cqe)) {
493 ret = -EAGAIN;
494 goto skip_cqe;
495 }
496
497 /*
498 * skip TERMINATE cqes...
499 */
500 if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) {
501 ret = -EAGAIN;
502 goto skip_cqe;
503 }
504
cfdda9d7
SW		 505 /*
506 * Gotta tweak READ completions:
507 * 1) the cqe doesn't contain the sq_wptr from the wr.
508 * 2) opcode not reflected from the wr.
509 * 3) read_len not reflected from the wr.
510 * 4) cq_type is RQ_TYPE not SQ_TYPE.
511 */
512 if (RQ_TYPE(hw_cqe) && (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP)) {
513
514 /*
515 * If this is an unsolicited read response, then the read
516 * was generated by the kernel driver as part of peer-2-peer
517 * connection setup. So ignore the completion.
518 */
1cf24dce 519 if (CQE_WRID_STAG(hw_cqe) == 1) {
cfdda9d7
SW		 520 if (CQE_STATUS(hw_cqe))
521 t4_set_wq_in_error(wq);
522 ret = -EAGAIN;
523 goto skip_cqe;
524 }
525
1cf24dce
SW		 526 /*
527 * Eat completions for unsignaled read WRs.
528 */
529 if (!wq->sq.oldest_read->signaled) {
530 advance_oldest_read(wq);
531 ret = -EAGAIN;
532 goto skip_cqe;
533 }
534
cfdda9d7
SW		 535 /*
536 * Don't write to the HWCQ, so create a new read req CQE
537 * in local memory.
538 */
539 create_read_req_cqe(wq, hw_cqe, &read_cqe);
540 hw_cqe = &read_cqe;
541 advance_oldest_read(wq);
542 }
543
544 if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) {
1cf24dce 545 *cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH);
cfdda9d7 546 t4_set_wq_in_error(wq);
6ff0e343
SW		 547 }
548
cfdda9d7
SW		 549 /*
550 * RECV completion.
551 */
552 if (RQ_TYPE(hw_cqe)) {
553
554 /*
555 * HW only validates 4 bits of MSN. So we must validate that
556 * the MSN in the SEND is the next expected MSN. If its not,
557 * then we complete this with T4_ERR_MSN and mark the wq in
558 * error.
559 */
560
561 if (t4_rq_empty(wq)) {
562 t4_set_wq_in_error(wq);
563 ret = -EAGAIN;
564 goto skip_cqe;
565 }
566 if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) {
567 t4_set_wq_in_error(wq);
568 hw_cqe->header |= htonl(V_CQE_STATUS(T4_ERR_MSN));
569 goto proc_cqe;
570 }
571 goto proc_cqe;
572 }
573
574 /*
575 * If we get here its a send completion.
576 *
577 * Handle out of order completion. These get stuffed
578 * in the SW SQ. Then the SW SQ is walked to move any
579 * now in-order completions into the SW CQ. This handles
580 * 2 cases:
581 * 1) reaping unsignaled WRs when the first subsequent
582 * signaled WR is completed.
583 * 2) out of order read completions.
584 */
585 if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
586 struct t4_swsqe *swsqe;
587
588 PDBG("%s out of order completion going in sw_sq at idx %u\n",
589 __func__, CQE_WRID_SQ_IDX(hw_cqe));
590 swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
591 swsqe->cqe = *hw_cqe;
592 swsqe->complete = 1;
593 ret = -EAGAIN;
594 goto flush_wq;
595 }
596
597proc_cqe:
598 *cqe = *hw_cqe;
599
600 /*
601 * Reap the associated WR(s) that are freed up with this
602 * completion.
603 */
604 if (SQ_TYPE(hw_cqe)) {
1cf24dce
SW		 605 int idx = CQE_WRID_SQ_IDX(hw_cqe);
606 BUG_ON(idx > wq->sq.size);
607
608 /*
609 * Account for any unsignaled completions completed by
610 * this signaled completion. In this case, cidx points
611 * to the first unsignaled one, and idx points to the
612 * signaled one. So adjust in_use based on this delta.
613 * if this is not completing any unsigned wrs, then the
614 * delta will be 0.
615 */
616 wq->sq.in_use -= idx - wq->sq.cidx;
617 BUG_ON(wq->sq.in_use < 0 && wq->sq.in_use < wq->sq.size);
618
619 wq->sq.cidx = (uint16_t)idx;
cfdda9d7
SW		 620 PDBG("%s completing sq idx %u\n", __func__, wq->sq.cidx);
621 *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
622 t4_sq_consume(wq);
623 } else {
624 PDBG("%s completing rq idx %u\n", __func__, wq->rq.cidx);
625 *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
626 BUG_ON(t4_rq_empty(wq));
627 t4_rq_consume(wq);
1cf24dce 628 goto skip_cqe;
cfdda9d7
SW		 629 }
630
631flush_wq:
632 /*
633 * Flush any completed cqes that are now in-order.
634 */
635 flush_completed_wrs(wq, cq);
636
637skip_cqe:
638 if (SW_CQE(hw_cqe)) {
639 PDBG("%s cq %p cqid 0x%x skip sw cqe cidx %u\n",
640 __func__, cq, cq->cqid, cq->sw_cidx);
641 t4_swcq_consume(cq);
642 } else {
643 PDBG("%s cq %p cqid 0x%x skip hw cqe cidx %u\n",
644 __func__, cq, cq->cqid, cq->cidx);
645 t4_hwcq_consume(cq);
646 }
647 return ret;
648}
649
650/*
651 * Get one cq entry from c4iw and map it to openib.
652 *
653 * Returns:
654 * 0 cqe returned
655 * -ENODATA EMPTY;
656 * -EAGAIN caller must try again
657 * any other -errno fatal error
658 */
659static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
660{
661 struct c4iw_qp *qhp = NULL;
662 struct t4_cqe cqe = {0, 0}, *rd_cqe;
663 struct t4_wq *wq;
664 u32 credit = 0;
665 u8 cqe_flushed;
666 u64 cookie = 0;
667 int ret;
668
669 ret = t4_next_cqe(&chp->cq, &rd_cqe);
670
671 if (ret)
672 return ret;
673
674 qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe));
675 if (!qhp)
676 wq = NULL;
677 else {
678 spin_lock(&qhp->lock);
679 wq = &(qhp->wq);
680 }
681 ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit);
682 if (ret)
683 goto out;
684
685 wc->wr_id = cookie;
686 wc->qp = &qhp->ibqp;
687 wc->vendor_err = CQE_STATUS(&cqe);
688 wc->wc_flags = 0;
689
690 PDBG("%s qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x "
691 "lo 0x%x cookie 0x%llx\n", __func__, CQE_QPID(&cqe),
692 CQE_TYPE(&cqe), CQE_OPCODE(&cqe), CQE_STATUS(&cqe), CQE_LEN(&cqe),
693 CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe), (unsigned long long)cookie);
694
695 if (CQE_TYPE(&cqe) == 0) {
696 if (!CQE_STATUS(&cqe))
697 wc->byte_len = CQE_LEN(&cqe);
698 else
699 wc->byte_len = 0;
700 wc->opcode = IB_WC_RECV;
701 if (CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_INV ||
702 CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_SE_INV) {
703 wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe);
704 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
705 }
706 } else {
707 switch (CQE_OPCODE(&cqe)) {
708 case FW_RI_RDMA_WRITE:
709 wc->opcode = IB_WC_RDMA_WRITE;
710 break;
711 case FW_RI_READ_REQ:
712 wc->opcode = IB_WC_RDMA_READ;
713 wc->byte_len = CQE_LEN(&cqe);
714 break;
715 case FW_RI_SEND_WITH_INV:
716 case FW_RI_SEND_WITH_SE_INV:
717 wc->opcode = IB_WC_SEND;
718 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
719 break;
720 case FW_RI_SEND:
721 case FW_RI_SEND_WITH_SE:
722 wc->opcode = IB_WC_SEND;
723 break;
724 case FW_RI_BIND_MW:
725 wc->opcode = IB_WC_BIND_MW;
726 break;
727
728 case FW_RI_LOCAL_INV:
729 wc->opcode = IB_WC_LOCAL_INV;
730 break;
731 case FW_RI_FAST_REGISTER:
732 wc->opcode = IB_WC_FAST_REG_MR;
733 break;
734 default:
735 printk(KERN_ERR MOD "Unexpected opcode %d "
736 "in the CQE received for QPID=0x%0x\n",
737 CQE_OPCODE(&cqe), CQE_QPID(&cqe));
738 ret = -EINVAL;
739 goto out;
740 }
741 }
742
743 if (cqe_flushed)
744 wc->status = IB_WC_WR_FLUSH_ERR;
745 else {
746
747 switch (CQE_STATUS(&cqe)) {
748 case T4_ERR_SUCCESS:
749 wc->status = IB_WC_SUCCESS;
750 break;
751 case T4_ERR_STAG:
752 wc->status = IB_WC_LOC_ACCESS_ERR;
753 break;
754 case T4_ERR_PDID:
755 wc->status = IB_WC_LOC_PROT_ERR;
756 break;
757 case T4_ERR_QPID:
758 case T4_ERR_ACCESS:
759 wc->status = IB_WC_LOC_ACCESS_ERR;
760 break;
761 case T4_ERR_WRAP:
762 wc->status = IB_WC_GENERAL_ERR;
763 break;
764 case T4_ERR_BOUND:
765 wc->status = IB_WC_LOC_LEN_ERR;
766 break;
767 case T4_ERR_INVALIDATE_SHARED_MR:
768 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
769 wc->status = IB_WC_MW_BIND_ERR;
770 break;
771 case T4_ERR_CRC:
772 case T4_ERR_MARKER:
773 case T4_ERR_PDU_LEN_ERR:
774 case T4_ERR_OUT_OF_RQE:
775 case T4_ERR_DDP_VERSION:
776 case T4_ERR_RDMA_VERSION:
777 case T4_ERR_DDP_QUEUE_NUM:
778 case T4_ERR_MSN:
779 case T4_ERR_TBIT:
780 case T4_ERR_MO:
781 case T4_ERR_MSN_RANGE:
782 case T4_ERR_IRD_OVERFLOW:
783 case T4_ERR_OPCODE:
6ff0e343 784 case T4_ERR_INTERNAL_ERR:
cfdda9d7
SW		 785 wc->status = IB_WC_FATAL_ERR;
786 break;
787 case T4_ERR_SWFLUSH:
788 wc->status = IB_WC_WR_FLUSH_ERR;
789 break;
790 default:
791 printk(KERN_ERR MOD
792 "Unexpected cqe_status 0x%x for QPID=0x%0x\n",
793 CQE_STATUS(&cqe), CQE_QPID(&cqe));
794 ret = -EINVAL;
795 }
796 }
797out:
798 if (wq)
799 spin_unlock(&qhp->lock);
800 return ret;
801}
802
803int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
804{
805 struct c4iw_cq *chp;
806 unsigned long flags;
807 int npolled;
808 int err = 0;
809
810 chp = to_c4iw_cq(ibcq);
811
812 spin_lock_irqsave(&chp->lock, flags);
813 for (npolled = 0; npolled < num_entries; ++npolled) {
814 do {
815 err = c4iw_poll_cq_one(chp, wc + npolled);
816 } while (err == -EAGAIN);
817 if (err)
818 break;
819 }
820 spin_unlock_irqrestore(&chp->lock, flags);
821 return !err || err == -ENODATA ? npolled : err;
822}
823
824int c4iw_destroy_cq(struct ib_cq *ib_cq)
825{
826 struct c4iw_cq *chp;
827 struct c4iw_ucontext *ucontext;
828
829 PDBG("%s ib_cq %p\n", __func__, ib_cq);
830 chp = to_c4iw_cq(ib_cq);
831
832 remove_handle(chp->rhp, &chp->rhp->cqidr, chp->cq.cqid);
833 atomic_dec(&chp->refcnt);
834 wait_event(chp->wait, !atomic_read(&chp->refcnt));
835
836 ucontext = ib_cq->uobject ? to_c4iw_ucontext(ib_cq->uobject->context)
837 : NULL;
838 destroy_cq(&chp->rhp->rdev, &chp->cq,
839 ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx);
840 kfree(chp);
841 return 0;
842}
843
844struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
845 int vector, struct ib_ucontext *ib_context,
846 struct ib_udata *udata)
847{
848 struct c4iw_dev *rhp;
849 struct c4iw_cq *chp;
850 struct c4iw_create_cq_resp uresp;
851 struct c4iw_ucontext *ucontext = NULL;
852 int ret;
1973e8b8 853 size_t memsize, hwentries;
cfdda9d7
SW		 854 struct c4iw_mm_entry *mm, *mm2;
855
856 PDBG("%s ib_dev %p entries %d\n", __func__, ibdev, entries);
857
858 rhp = to_c4iw_dev(ibdev);
859
860 chp = kzalloc(sizeof(*chp), GFP_KERNEL);
861 if (!chp)
862 return ERR_PTR(-ENOMEM);
863
864 if (ib_context)
865 ucontext = to_c4iw_ucontext(ib_context);
866
867 /* account for the status page. */
868 entries++;
869
895cf5f3
SW		 870 /* IQ needs one extra entry to differentiate full vs empty. */
871 entries++;
872
cfdda9d7
SW		 873 /*
874 * entries must be multiple of 16 for HW.
875 */
876 entries = roundup(entries, 16);
1973e8b8
SW		 877
878 /*
879 * Make actual HW queue 2x to avoid cdix_inc overflows.
880 */
881 hwentries = entries * 2;
882
883 /*
884 * Make HW queue at least 64 entries so GTS updates aren't too
885 * frequent.
886 */
887 if (hwentries < 64)
888 hwentries = 64;
889
890 memsize = hwentries * sizeof *chp->cq.queue;
cfdda9d7
SW		 891
892 /*
893 * memsize must be a multiple of the page size if its a user cq.
894 */
1973e8b8 895 if (ucontext) {
cfdda9d7 896 memsize = roundup(memsize, PAGE_SIZE);
1973e8b8 897 hwentries = memsize / sizeof *chp->cq.queue;
2ff7d09a
SW		 898 while (hwentries > T4_MAX_IQ_SIZE) {
899 memsize -= PAGE_SIZE;
900 hwentries = memsize / sizeof *chp->cq.queue;
901 }
1973e8b8
SW		 902 }
903 chp->cq.size = hwentries;
cfdda9d7
SW		 904 chp->cq.memsize = memsize;
905
906 ret = create_cq(&rhp->rdev, &chp->cq,
907 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
908 if (ret)
909 goto err1;
910
911 chp->rhp = rhp;
912 chp->cq.size--; /* status page */
1973e8b8 913 chp->ibcq.cqe = entries - 2;
cfdda9d7 914 spin_lock_init(&chp->lock);
581bbe2c 915 spin_lock_init(&chp->comp_handler_lock);
cfdda9d7
SW		 916 atomic_set(&chp->refcnt, 1);
917 init_waitqueue_head(&chp->wait);
918 ret = insert_handle(rhp, &rhp->cqidr, chp, chp->cq.cqid);
919 if (ret)
920 goto err2;
921
922 if (ucontext) {
923 mm = kmalloc(sizeof *mm, GFP_KERNEL);
924 if (!mm)
925 goto err3;
926 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
927 if (!mm2)
928 goto err4;
929
930 uresp.qid_mask = rhp->rdev.cqmask;
931 uresp.cqid = chp->cq.cqid;
932 uresp.size = chp->cq.size;
933 uresp.memsize = chp->cq.memsize;
934 spin_lock(&ucontext->mmap_lock);
935 uresp.key = ucontext->key;
936 ucontext->key += PAGE_SIZE;
937 uresp.gts_key = ucontext->key;
938 ucontext->key += PAGE_SIZE;
939 spin_unlock(&ucontext->mmap_lock);
940 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
941 if (ret)
942 goto err5;
943
944 mm->key = uresp.key;
945 mm->addr = virt_to_phys(chp->cq.queue);
946 mm->len = chp->cq.memsize;
947 insert_mmap(ucontext, mm);
948
949 mm2->key = uresp.gts_key;
950 mm2->addr = chp->cq.ugts;
951 mm2->len = PAGE_SIZE;
952 insert_mmap(ucontext, mm2);
953 }
954 PDBG("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n",
955 __func__, chp->cq.cqid, chp, chp->cq.size,
956 chp->cq.memsize,
957 (unsigned long long) chp->cq.dma_addr);
958 return &chp->ibcq;
959err5:
960 kfree(mm2);
961err4:
962 kfree(mm);
963err3:
964 remove_handle(rhp, &rhp->cqidr, chp->cq.cqid);
965err2:
966 destroy_cq(&chp->rhp->rdev, &chp->cq,
967 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
968err1:
969 kfree(chp);
970 return ERR_PTR(ret);
971}
972
973int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata)
974{
975 return -ENOSYS;
976}
977
978int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
979{
980 struct c4iw_cq *chp;
981 int ret;
982 unsigned long flag;
983
984 chp = to_c4iw_cq(ibcq);
985 spin_lock_irqsave(&chp->lock, flag);
986 ret = t4_arm_cq(&chp->cq,
987 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED);
988 spin_unlock_irqrestore(&chp->lock, flag);
989 if (ret && !(flags & IB_CQ_REPORT_MISSED_EVENTS))
990 ret = 0;
991 return ret;
992}
Linux 6.x block layer and io_uring tree(s)