[linux-2.6-block.git] / drivers / ide / pci / tc86c001.c

/*
 * drivers/ide/pci/tc86c001.c	Version 1.00	Dec 12, 2006
 *
 * Copyright (C) 2002 Toshiba Corporation
 * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>

static inline u8 tc86c001_ratemask(ide_drive_t *drive)
{
	return eighty_ninty_three(drive) ? 2 : 1;
}

static int tc86c001_tune_chipset(ide_drive_t *drive, u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long scr_port	= hwif->config_data + (drive->dn ? 0x02 : 0x00);
	u16 mode, scr		= hwif->INW(scr_port);

	speed = ide_rate_filter(tc86c001_ratemask(drive), speed);

	switch (speed) {
		case XFER_UDMA_4:	mode = 0x00c0; break;
		case XFER_UDMA_3:	mode = 0x00b0; break;
		case XFER_UDMA_2:	mode = 0x00a0; break;
		case XFER_UDMA_1:	mode = 0x0090; break;
		case XFER_UDMA_0:	mode = 0x0080; break;
		case XFER_MW_DMA_2:	mode = 0x0070; break;
		case XFER_MW_DMA_1:	mode = 0x0060; break;
		case XFER_MW_DMA_0:	mode = 0x0050; break;
		case XFER_PIO_4:	mode = 0x0400; break;
		case XFER_PIO_3:	mode = 0x0300; break;
		case XFER_PIO_2:	mode = 0x0200; break;
		case XFER_PIO_1:	mode = 0x0100; break;
		case XFER_PIO_0:
		default:		mode = 0x0000; break;
	}

	scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
	scr |= mode;
	hwif->OUTW(scr, scr_port);

	return ide_config_drive_speed(drive, speed);
}

static void tc86c001_tune_drive(ide_drive_t *drive, u8 pio)
{
	pio =  ide_get_best_pio_mode(drive, pio, 4, NULL);
	(void) tc86c001_tune_chipset(drive, XFER_PIO_0 + pio);
}

/*
 * HACKITY HACK
 *
 * This is a workaround for the limitation 5 of the TC86C001 IDE controller:
 * if a DMA transfer terminates prematurely, the controller leaves the device's
 * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
 * set the interrupt bit in the DMA status register), thus no PCI interrupt
 * will occur until a DMA transfer has been successfully completed.
 *
 * We work around this by initiating dummy, zero-length DMA transfer on
 * a DMA timeout expiration. I found no better way to do this with the current
 * IDE core than to temporarily replace a higher level driver's timer expiry
 * handler with our own backing up to that handler in case our recovery fails.
 */
static int tc86c001_timer_expiry(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_expiry_t *expiry	= ide_get_hwifdata(hwif);
	ide_hwgroup_t *hwgroup	= HWGROUP(drive);
	u8 dma_stat		= hwif->INB(hwif->dma_status);

	/* Restore a higher level driver's expiry handler first. */
	hwgroup->expiry	= expiry;

	if ((dma_stat & 5) == 1) {	/* DMA active and no interrupt */
		unsigned long sc_base	= hwif->config_data;
		unsigned long twcr_port	= sc_base + (drive->dn ? 0x06 : 0x04);
		u8 dma_cmd		= hwif->INB(hwif->dma_command);

		printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
		       "attempting recovery...\n", drive->name);

		/* Stop DMA */
		hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command);

		/* Setup the dummy DMA transfer */
		hwif->OUTW(0, sc_base + 0x0a);	/* Sector Count */
		hwif->OUTW(0, twcr_port);	/* Transfer Word Count 1 or 2 */

		/* Start the dummy DMA transfer */
		hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
		hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */

		/*
		 * If an interrupt was pending, it should come thru shortly.
		 * If not, a higher level driver's expiry handler should
		 * eventually cause some kind of recovery from the DMA stall.
		 */
		return WAIT_MIN_SLEEP;
	}

	/* Chain to the restored expiry handler if DMA wasn't active. */
	if (likely(expiry != NULL))
		return expiry(drive);

	/* If there was no handler, "emulate" that for ide_timer_expiry()... */
	return -1;
}

static void tc86c001_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwgroup_t *hwgroup	= HWGROUP(drive);
	unsigned long sc_base	= hwif->config_data;
	unsigned long twcr_port	= sc_base + (drive->dn ? 0x06 : 0x04);
	unsigned long nsectors	= hwgroup->rq->nr_sectors;

	/*
	 * We have to manually load the sector count and size into
	 * the appropriate system control registers for DMA to work
	 * with LBA48 and ATAPI devices...
	 */
	hwif->OUTW(nsectors, sc_base + 0x0a);	/* Sector Count */
	hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */

	/* Install our timeout expiry hook, saving the current handler... */
	ide_set_hwifdata(hwif, hwgroup->expiry);
	hwgroup->expiry = &tc86c001_timer_expiry;

	ide_dma_start(drive);
}

static int tc86c001_busproc(ide_drive_t *drive, int state)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long sc_base	= hwif->config_data;
	u16 scr1;

	/* System Control 1 Register bit 11 (ATA Hard Reset) read */
	scr1 = hwif->INW(sc_base + 0x00);

	switch (state) {
		case BUSSTATE_ON:
			if (!(scr1 & 0x0800))
				return 0;
			scr1 &= ~0x0800;

			hwif->drives[0].failures = hwif->drives[1].failures = 0;
			break;
		case BUSSTATE_OFF:
			if (scr1 & 0x0800)
				return 0;
			scr1 |= 0x0800;

			hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
			hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
			break;
		default:
			return -EINVAL;
	}

	/* System Control 1 Register bit 11 (ATA Hard Reset) write */
	hwif->OUTW(scr1, sc_base + 0x00);
	return 0;
}

static int config_chipset_for_dma(ide_drive_t *drive)
{
	u8 speed = ide_dma_speed(drive, tc86c001_ratemask(drive));

	if (!speed)
		return 0;

	(void) tc86c001_tune_chipset(drive, speed);
	return ide_dma_enable(drive);
}

static int tc86c001_config_drive_xfer_rate(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);

	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
		return hwif->ide_dma_on(drive);

	if (ide_use_fast_pio(drive)) {
		tc86c001_tune_drive(drive, 255);
		return hwif->ide_dma_off_quietly(drive);
	}
	/* IORDY not supported */
	return 0;
}

static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
{
	unsigned long sc_base	= pci_resource_start(hwif->pci_dev, 5);
	u16 scr1		= hwif->INW(sc_base + 0x00);;

	/* System Control 1 Register bit 15 (Soft Reset) set */
	hwif->OUTW(scr1 |  0x8000, sc_base + 0x00);

	/* System Control 1 Register bit 14 (FIFO Reset) set */
	hwif->OUTW(scr1 |  0x4000, sc_base + 0x00);

	/* System Control 1 Register: reset clear */
	hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00);

	/* Store the system control register base for convenience... */
	hwif->config_data = sc_base;

	hwif->tuneproc	= &tc86c001_tune_drive;
	hwif->speedproc = &tc86c001_tune_chipset;
	hwif->busproc	= &tc86c001_busproc;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	/*
	 * Sector Count Control Register bits 0 and 1 set:
	 * software sets Sector Count Register for master and slave device
	 */
	hwif->OUTW(0x0003, sc_base + 0x0c);

	/* Sector Count Register limit */
	hwif->rqsize	 = 0xffff;

	hwif->atapi_dma  = 1;
	hwif->ultra_mask = 0x1f;
	hwif->mwdma_mask = 0x07;

	hwif->ide_dma_check	= &tc86c001_config_drive_xfer_rate;
	hwif->dma_start 	= &tc86c001_dma_start;

	if (!hwif->udma_four) {
		/*
		 * System Control  1 Register bit 13 (PDIAGN):
		 * 0=80-pin cable, 1=40-pin cable
		 */
		scr1 = hwif->INW(sc_base + 0x00);
		hwif->udma_four = (scr1 & 0x2000) ? 0 : 1;
	}

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
}

static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
							const char *name)
{
	int err = pci_request_region(dev, 5, name);

	if (err)
		printk(KERN_ERR "%s: system control regs already in use", name);
	return err;
}

static ide_pci_device_t tc86c001_chipset __devinitdata = {
	.name		= "TC86C001",
	.init_chipset	= init_chipset_tc86c001,
	.init_hwif	= init_hwif_tc86c001,
	.channels	= 1,
	.autodma	= AUTODMA,
	.bootable	= OFF_BOARD
};

static int __devinit tc86c001_init_one(struct pci_dev *dev,
				       const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &tc86c001_chipset);
}

static struct pci_device_id tc86c001_pci_tbl[] = {
	{ PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);

static struct pci_driver driver = {
	.name		= "TC86C001",
	.id_table	= tc86c001_pci_tbl,
	.probe		= tc86c001_init_one
};

static int __init tc86c001_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}
module_init(tc86c001_ide_init);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
33dced2e SS	1	/*
	2	* drivers/ide/pci/tc86c001.c Version 1.00 Dec 12, 2006
	3	*
	4	* Copyright (C) 2002 Toshiba Corporation
	5	* Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/pci.h>
	14	#include <linux/ide.h>
	15
	16	static inline u8 tc86c001_ratemask(ide_drive_t *drive)
	17	{
	18	return eighty_ninty_three(drive) ? 2 : 1;
	19	}
	20
	21	static int tc86c001_tune_chipset(ide_drive_t *drive, u8 speed)
	22	{
	23	ide_hwif_t *hwif = HWIF(drive);
	24	unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
	25	u16 mode, scr = hwif->INW(scr_port);
	26
	27	speed = ide_rate_filter(tc86c001_ratemask(drive), speed);
	28
	29	switch (speed) {
	30	case XFER_UDMA_4: mode = 0x00c0; break;
	31	case XFER_UDMA_3: mode = 0x00b0; break;
	32	case XFER_UDMA_2: mode = 0x00a0; break;
	33	case XFER_UDMA_1: mode = 0x0090; break;
	34	case XFER_UDMA_0: mode = 0x0080; break;
	35	case XFER_MW_DMA_2: mode = 0x0070; break;
	36	case XFER_MW_DMA_1: mode = 0x0060; break;
	37	case XFER_MW_DMA_0: mode = 0x0050; break;
	38	case XFER_PIO_4: mode = 0x0400; break;
	39	case XFER_PIO_3: mode = 0x0300; break;
	40	case XFER_PIO_2: mode = 0x0200; break;
	41	case XFER_PIO_1: mode = 0x0100; break;
	42	case XFER_PIO_0:
	43	default: mode = 0x0000; break;
	44	}
	45
	46	scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
	47	scr \|= mode;
	48	hwif->OUTW(scr, scr_port);
	49
	50	return ide_config_drive_speed(drive, speed);
	51	}
	52
	53	static void tc86c001_tune_drive(ide_drive_t *drive, u8 pio)
	54	{
	55	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	56	(void) tc86c001_tune_chipset(drive, XFER_PIO_0 + pio);
	57	}
	58
	59	/*
	60	* HACKITY HACK
	61	*
	62	* This is a workaround for the limitation 5 of the TC86C001 IDE controller:
	63	* if a DMA transfer terminates prematurely, the controller leaves the device's
	64	* interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
65	* set the interrupt bit in the DMA status register), thus no PCI interrupt
66	* will occur until a DMA transfer has been successfully completed.
67	*
68	* We work around this by initiating dummy, zero-length DMA transfer on
69	* a DMA timeout expiration. I found no better way to do this with the current
70	* IDE core than to temporarily replace a higher level driver's timer expiry
71	* handler with our own backing up to that handler in case our recovery fails.
72	*/
73	static int tc86c001_timer_expiry(ide_drive_t *drive)
74	{
75	ide_hwif_t *hwif = HWIF(drive);
76	ide_expiry_t *expiry = ide_get_hwifdata(hwif);
77	ide_hwgroup_t *hwgroup = HWGROUP(drive);
78	u8 dma_stat = hwif->INB(hwif->dma_status);
79
80	/* Restore a higher level driver's expiry handler first. */
81	hwgroup->expiry = expiry;
82
83	if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */
84	unsigned long sc_base = hwif->config_data;
85	unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
86	u8 dma_cmd = hwif->INB(hwif->dma_command);
87
88	printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
89	"attempting recovery...\n", drive->name);
90
91	/* Stop DMA */
92	hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command);
93
94	/* Setup the dummy DMA transfer */
95	hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */
96	hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */
97
98	/* Start the dummy DMA transfer */
99	hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
100	hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */
101
102	/*
103	* If an interrupt was pending, it should come thru shortly.
104	* If not, a higher level driver's expiry handler should
105	* eventually cause some kind of recovery from the DMA stall.
106	*/
107	return WAIT_MIN_SLEEP;
108	}
109
110	/* Chain to the restored expiry handler if DMA wasn't active. */
111	if (likely(expiry != NULL))
112	return expiry(drive);
113
114	/* If there was no handler, "emulate" that for ide_timer_expiry()... */
115	return -1;
116	}
117
118	static void tc86c001_dma_start(ide_drive_t *drive)
119	{
120	ide_hwif_t *hwif = HWIF(drive);
121	ide_hwgroup_t *hwgroup = HWGROUP(drive);
122	unsigned long sc_base = hwif->config_data;
123	unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
124	unsigned long nsectors = hwgroup->rq->nr_sectors;
125
126	/*
127	* We have to manually load the sector count and size into
128	* the appropriate system control registers for DMA to work
129	* with LBA48 and ATAPI devices...
130	*/
131	hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */
132	hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
133
134	/* Install our timeout expiry hook, saving the current handler... */
135	ide_set_hwifdata(hwif, hwgroup->expiry);
136	hwgroup->expiry = &tc86c001_timer_expiry;
137
138	ide_dma_start(drive);
139	}
140
141	static int tc86c001_busproc(ide_drive_t *drive, int state)
142	{
143	ide_hwif_t *hwif = HWIF(drive);
144	unsigned long sc_base = hwif->config_data;
145	u16 scr1;
146
147	/* System Control 1 Register bit 11 (ATA Hard Reset) read */
148	scr1 = hwif->INW(sc_base + 0x00);
149
150	switch (state) {
151	case BUSSTATE_ON:
152	if (!(scr1 & 0x0800))
153	return 0;
154	scr1 &= ~0x0800;
155
156	hwif->drives[0].failures = hwif->drives[1].failures = 0;
157	break;
158	case BUSSTATE_OFF:
159	if (scr1 & 0x0800)
160	return 0;
161	scr1 \|= 0x0800;
162
163	hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
164	hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
165	break;
166	default:
167	return -EINVAL;
168	}
169
170	/* System Control 1 Register bit 11 (ATA Hard Reset) write */
171	hwif->OUTW(scr1, sc_base + 0x00);
172	return 0;
173	}
174
175	static int config_chipset_for_dma(ide_drive_t *drive)
176	{
177	u8 speed = ide_dma_speed(drive, tc86c001_ratemask(drive));
178
179	if (!speed)
180	return 0;
181
182	(void) tc86c001_tune_chipset(drive, speed);
183	return ide_dma_enable(drive);
184	}
185
186	static int tc86c001_config_drive_xfer_rate(ide_drive_t *drive)
187	{
188	ide_hwif_t *hwif = HWIF(drive);
33dced2e	189
7569e8dc BZ	190	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
7569e8dc BZ	191	return hwif->ide_dma_on(drive);
33dced2e	192
7569e8dc	193	if (ide_use_fast_pio(drive)) {
33dced2e SS	194	tc86c001_tune_drive(drive, 255);
	195	return hwif->ide_dma_off_quietly(drive);
	196	}
	197	/* IORDY not supported */
	198	return 0;
	199	}
	200
e8ab7f53	201	static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
33dced2e SS	202	{
	203	unsigned long sc_base = pci_resource_start(hwif->pci_dev, 5);
	204	u16 scr1 = hwif->INW(sc_base + 0x00);;
	205
	206	/* System Control 1 Register bit 15 (Soft Reset) set */
	207	hwif->OUTW(scr1 \| 0x8000, sc_base + 0x00);
	208
	209	/* System Control 1 Register bit 14 (FIFO Reset) set */
	210	hwif->OUTW(scr1 \| 0x4000, sc_base + 0x00);
	211
	212	/* System Control 1 Register: reset clear */
	213	hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00);
	214
	215	/* Store the system control register base for convenience... */
	216	hwif->config_data = sc_base;
	217
	218	hwif->tuneproc = &tc86c001_tune_drive;
	219	hwif->speedproc = &tc86c001_tune_chipset;
	220	hwif->busproc = &tc86c001_busproc;
	221
	222	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
	223
	224	if (!hwif->dma_base)
	225	return;
	226
	227	/*
	228	* Sector Count Control Register bits 0 and 1 set:
	229	* software sets Sector Count Register for master and slave device
	230	*/
	231	hwif->OUTW(0x0003, sc_base + 0x0c);
	232
	233	/* Sector Count Register limit */
	234	hwif->rqsize = 0xffff;
	235
	236	hwif->atapi_dma = 1;
	237	hwif->ultra_mask = 0x1f;
	238	hwif->mwdma_mask = 0x07;
	239
	240	hwif->ide_dma_check = &tc86c001_config_drive_xfer_rate;
	241	hwif->dma_start = &tc86c001_dma_start;
	242
	243	if (!hwif->udma_four) {
	244	/*
	245	* System Control 1 Register bit 13 (PDIAGN):
	246	* 0=80-pin cable, 1=40-pin cable
	247	*/
	248	scr1 = hwif->INW(sc_base + 0x00);
	249	hwif->udma_four = (scr1 & 0x2000) ? 0 : 1;
	250	}
	251
	252	if (!noautodma)
	253	hwif->autodma = 1;
	254	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
	255	}
	256
ba59c4b8 AM	257	static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
ba59c4b8 AM	258	const char *name)
33dced2e SS	259	{
	260	int err = pci_request_region(dev, 5, name);
	261
	262	if (err)
	263	printk(KERN_ERR "%s: system control regs already in use", name);
	264	return err;
	265	}
	266
	267	static ide_pci_device_t tc86c001_chipset __devinitdata = {
	268	.name = "TC86C001",
	269	.init_chipset = init_chipset_tc86c001,
	270	.init_hwif = init_hwif_tc86c001,
	271	.channels = 1,
	272	.autodma = AUTODMA,
	273	.bootable = OFF_BOARD
	274	};
	275
	276	static int __devinit tc86c001_init_one(struct pci_dev *dev,
	277	const struct pci_device_id *id)
	278	{
	279	return ide_setup_pci_device(dev, &tc86c001_chipset);
	280	}
	281
	282	static struct pci_device_id tc86c001_pci_tbl[] = {
	283	{ PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
	284	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	285	{ 0, }
	286	};
	287	MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);
	288
	289	static struct pci_driver driver = {
	290	.name = "TC86C001",
	291	.id_table = tc86c001_pci_tbl,
	292	.probe = tc86c001_init_one
	293	};
	294
a534b68d	295	static int __init tc86c001_ide_init(void)
33dced2e SS	296	{
	297	return ide_pci_register_driver(&driver);
	298	}
	299	module_init(tc86c001_ide_init);
	300
	301	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	302	MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
	303	MODULE_LICENSE("GPL");