[linux-2.6-block.git] / drivers / ide / pci / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <mlord@pobox.com>
 * Copyright (C) 1998		Eddie C. Dost <ecd@skynet.be>
 * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

static unsigned long superio_ide_status[2];
static unsigned long superio_ide_select[2];
static unsigned long superio_ide_dma_status[2];

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	if (port == superio_ide_status[0] ||
	    port == superio_ide_status[1] ||
	    port == superio_ide_select[0] ||
	    port == superio_ide_select[1] ||
	    port == superio_ide_dma_status[0] ||
	    port == superio_ide_dma_status[1]) {
		u8 tmp;
		int retries = SUPERIO_IDE_MAX_RETRIES;

		/* printk(" [ reading port 0x%x with retry ] ", port); */

		do {
			tmp = inb(port);
			if (tmp == 0)
				udelay(50);
		} while (tmp == 0 && retries-- > 0);

		return tmp;
	}

	return inb(port);
}

static u8 superio_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->io_ports.status_addr);
}

static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
{
	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	struct ide_taskfile *tf = &task->tf;

	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
		u16 data = inw(io_ports->data_addr);

		tf->data = data & 0xff;
		tf->hob_data = (data >> 8) & 0xff;
	}

	/* be sure we're looking at the low order bits */
	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);

	if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
		tf->feature = inb(io_ports->feature_addr);
	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
		tf->nsect  = inb(io_ports->nsect_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
		tf->lbal   = inb(io_ports->lbal_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
		tf->lbam   = inb(io_ports->lbam_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
		tf->lbah   = inb(io_ports->lbah_addr);
	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
		tf->device = superio_ide_inb(io_ports->device_addr);

	if (task->tf_flags & IDE_TFLAG_LBA48) {
		outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);

		if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
			tf->hob_feature = inb(io_ports->feature_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
			tf->hob_nsect   = inb(io_ports->nsect_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
			tf->hob_lbal    = inb(io_ports->lbal_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
			tf->hob_lbam    = inb(io_ports->lbam_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
			tf->hob_lbah    = inb(io_ports->lbah_addr);
	}
}

static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 base, dmabase;
	u8 port = hwif->channel, tmp;

	base = pci_resource_start(pdev, port * 2) & ~3;
	dmabase = pci_resource_start(pdev, 4) & ~3;

	superio_ide_status[port] = base + 7;
	superio_ide_select[port] = base + 6;
	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	outb(tmp | 0x66, superio_ide_dma_status[port]);

	hwif->read_status	  = superio_read_status;
	hwif->read_sff_dma_status = superio_read_sff_dma_status;

	hwif->tf_read = superio_tf_read;

	/* We need to override inb to workaround a SuperIO errata */
	hwif->INB = superio_ide_inb;
}

static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_SLOT(dev->devfn) == 0xE)
		/* Built-in - assume it's under superio. */
		superio_ide_init_iops(hwif);
}
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to drive->present)
 * the IRQ associated with the port (HWIF(drive)),
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);
	new = drive->present ? (new & ~bit) : (new | bit);

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + drive->select.b.unit       + (hwif->channel << 1));
	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive (drive, drive->using_dma);
}

static int ns87415_dma_end(ide_drive_t *drive)
{
	ide_hwif_t      *hwif = HWIF(drive);
	u8 dma_stat = 0, dma_cmd = 0;

	drive->waiting_for_dma = 0;
	dma_stat = hwif->read_sff_dma_status(hwif);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int ns87415_dma_setup(ide_drive_t *drive)
{
	/* select DMA xfer */
	ns87415_prepare_drive(drive, 1);
	if (!ide_dma_setup(drive))
		return 0;
	/* DMA failed: select PIO xfer */
	ns87415_prepare_drive(drive, 0);
	return 1;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond to
		 *      SELECT_DRIVE() properly during first ide_probe_port().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports.ctl_addr);
		udelay(10);
		outb(8, hwif->io_ports.ctl_addr);
		do {
			udelay(50);
			stat = hwif->read_status(hwif);
                	if (stat == 0xff)
                        	break;
        	} while ((stat & BUSY_STAT) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
		hwif->irq = hwif->mate->irq;	/* share IRQ with mate */

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_port_ops ns87415_port_ops = {
	.selectproc		= ns87415_selectproc,
};

static const struct ide_dma_ops ns87415_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ns87415_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= ns87415_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timeout		= ide_dma_timeout,
};

static const struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= "NS87415",
#ifdef CONFIG_SUPERIO
	.init_iops	= init_iops_ns87415,
#endif
	.init_hwif	= init_hwif_ns87415,
	.port_ops	= &ns87415_port_ops,
	.dma_ops	= &ns87415_dma_ops,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &ns87415_chipset);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(ns87415_ide_init);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
	3	* Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
	4	* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <davem@redhat.com>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
1da177e4	13	#include <linux/interrupt.h>
1da177e4 LT	14	#include <linux/hdreg.h>
	15	#include <linux/pci.h>
	16	#include <linux/delay.h>
	17	#include <linux/ide.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/io.h>
	21
	22	#ifdef CONFIG_SUPERIO
	23	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	24	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	25	* which use the integrated NS87514 cell for CD-ROM support.
	26	* i.e we have to support for CD-ROM installs.
	27	* See drivers/parisc/superio.c for more gory details.
	28	*/
	29	#include <asm/superio.h>
	30
	31	static unsigned long superio_ide_status[2];
	32	static unsigned long superio_ide_select[2];
	33	static unsigned long superio_ide_dma_status[2];
	34
	35	#define SUPERIO_IDE_MAX_RETRIES 25
	36
	37	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	38	* registers, IDE status register and the IDE select register need to be
	39	* retried
	40	*/
	41	static u8 superio_ide_inb (unsigned long port)
	42	{
	43	if (port == superio_ide_status[0] \|\|
	44	port == superio_ide_status[1] \|\|
	45	port == superio_ide_select[0] \|\|
	46	port == superio_ide_select[1] \|\|
	47	port == superio_ide_dma_status[0] \|\|
	48	port == superio_ide_dma_status[1]) {
	49	u8 tmp;
	50	int retries = SUPERIO_IDE_MAX_RETRIES;
	51
	52	/* printk(" [ reading port 0x%x with retry ] ", port); */
	53
	54	do {
	55	tmp = inb(port);
	56	if (tmp == 0)
	57	udelay(50);
	58	} while (tmp == 0 && retries-- > 0);
	59
	60	return tmp;
	61	}
	62
	63	return inb(port);
	64	}
	65
b73c7ee2 BZ	66	static u8 superio_read_status(ide_hwif_t *hwif)
	67	{
	68	return superio_ide_inb(hwif->io_ports.status_addr);
	69	}
	70
b2f951aa BZ	71	static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
b2f951aa BZ	72	{
cab7f8ed	73	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
b2f951aa BZ	74	}
b2f951aa BZ	75
ea23b8ba BZ	76	static void superio_tf_read(ide_drive_t drive, ide_task_t task)
	77	{
	78	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	79	struct ide_taskfile *tf = &task->tf;
	80
	81	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
	82	u16 data = inw(io_ports->data_addr);
	83
	84	tf->data = data & 0xff;
	85	tf->hob_data = (data >> 8) & 0xff;
	86	}
	87
	88	/* be sure we're looking at the low order bits */
ff074883	89	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
ea23b8ba	90
92eb4380 BZ	91	if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
92eb4380 BZ	92	tf->feature = inb(io_ports->feature_addr);
ea23b8ba BZ	93	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
	94	tf->nsect = inb(io_ports->nsect_addr);
	95	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
	96	tf->lbal = inb(io_ports->lbal_addr);
	97	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
	98	tf->lbam = inb(io_ports->lbam_addr);
	99	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
	100	tf->lbah = inb(io_ports->lbah_addr);
	101	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
	102	tf->device = superio_ide_inb(io_ports->device_addr);
	103
	104	if (task->tf_flags & IDE_TFLAG_LBA48) {
ff074883	105	outb(ATA_DEVCTL_OBS \| 0x80, io_ports->ctl_addr);
ea23b8ba BZ	106
	107	if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
	108	tf->hob_feature = inb(io_ports->feature_addr);
	109	if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
	110	tf->hob_nsect = inb(io_ports->nsect_addr);
	111	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
	112	tf->hob_lbal = inb(io_ports->lbal_addr);
	113	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
	114	tf->hob_lbam = inb(io_ports->lbam_addr);
	115	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
	116	tf->hob_lbah = inb(io_ports->lbah_addr);
	117	}
	118	}
	119
1da177e4 LT	120	static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
1da177e4 LT	121	{
36501650	122	struct pci_dev *pdev = to_pci_dev(hwif->dev);
1da177e4	123	u32 base, dmabase;
36501650	124	u8 port = hwif->channel, tmp;
1da177e4 LT	125
	126	base = pci_resource_start(pdev, port * 2) & ~3;
	127	dmabase = pci_resource_start(pdev, 4) & ~3;
	128
4c3032d8 BZ	129	superio_ide_status[port] = base + 7;
4c3032d8 BZ	130	superio_ide_select[port] = base + 6;
1da177e4 LT	131	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
	132
	133	/* Clear error/interrupt, enable dma */
	134	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	135	outb(tmp \| 0x66, superio_ide_dma_status[port]);
	136
b73c7ee2	137	hwif->read_status = superio_read_status;
b2f951aa BZ	138	hwif->read_sff_dma_status = superio_read_sff_dma_status;
b2f951aa BZ	139
ea23b8ba BZ	140	hwif->tf_read = superio_tf_read;
ea23b8ba BZ	141
1da177e4 LT	142	/* We need to override inb to workaround a SuperIO errata */
	143	hwif->INB = superio_ide_inb;
	144	}
	145
	146	static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
	147	{
36501650 BZ	148	struct pci_dev *dev = to_pci_dev(hwif->dev);
	149
	150	if (PCI_SLOT(dev->devfn) == 0xE)
1da177e4 LT	151	/* Built-in - assume it's under superio. */
1da177e4 LT	152	superio_ide_init_iops(hwif);
1da177e4 LT	153	}
	154	#endif
	155
	156	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	157
	158	/*
	159	* This routine either enables/disables (according to drive->present)
	160	* the IRQ associated with the port (HWIF(drive)),
	161	* and selects either PIO or DMA handshaking for the next I/O operation.
	162	*/
	163	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	164	{
	165	ide_hwif_t *hwif = HWIF(drive);
36501650	166	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	167	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	168	unsigned long flags;
	169
	170	local_irq_save(flags);
	171	new = *old;
	172
	173	/* Adjust IRQ enable bit */
	174	bit = 1 << (8 + hwif->channel);
	175	new = drive->present ? (new & ~bit) : (new \| bit);
	176
	177	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	178	bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
	179	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	180	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	181
	182	if (new != *old) {
	183	unsigned char stat;
	184
	185	/*
	186	* Don't change DMA engine settings while Write Buffers
	187	* are busy.
	188	*/
	189	(void) pci_read_config_byte(dev, 0x43, &stat);
	190	while (stat & 0x03) {
	191	udelay(1);
	192	(void) pci_read_config_byte(dev, 0x43, &stat);
	193	}
	194
	195	*old = new;
	196	(void) pci_write_config_dword(dev, 0x40, new);
	197
	198	/*
	199	* And let things settle...
	200	*/
	201	udelay(10);
	202	}
	203
	204	local_irq_restore(flags);
	205	}
	206
	207	static void ns87415_selectproc (ide_drive_t *drive)
	208	{
	209	ns87415_prepare_drive (drive, drive->using_dma);
	210	}
	211
5e37bdc0	212	static int ns87415_dma_end(ide_drive_t *drive)
1da177e4 LT	213	{
	214	ide_hwif_t *hwif = HWIF(drive);
	215	u8 dma_stat = 0, dma_cmd = 0;
	216
	217	drive->waiting_for_dma = 0;
b2f951aa	218	dma_stat = hwif->read_sff_dma_status(hwif);
cab7f8ed BZ	219	/* get DMA command mode */
cab7f8ed BZ	220	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	221	/* stop DMA */
cab7f8ed	222	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	223	/* from ERRATA: clear the INTR & ERROR bits */
cab7f8ed BZ	224	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
cab7f8ed BZ	225	outb(dma_cmd \| 6, hwif->dma_base + ATA_DMA_CMD);
1da177e4 LT	226	/* and free any DMA resources */
	227	ide_destroy_dmatable(drive);
	228	/* verify good DMA status */
	229	return (dma_stat & 7) != 4;
	230	}
	231
5e37bdc0	232	static int ns87415_dma_setup(ide_drive_t *drive)
1da177e4 LT	233	{
	234	/* select DMA xfer */
	235	ns87415_prepare_drive(drive, 1);
	236	if (!ide_dma_setup(drive))
	237	return 0;
	238	/* DMA failed: select PIO xfer */
	239	ns87415_prepare_drive(drive, 0);
	240	return 1;
	241	}
	242
c20530ed	243	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	244	{
36501650	245	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	246	unsigned int ctrl, using_inta;
	247	u8 progif;
	248	#ifdef __sparc_v9__
	249	int timeout;
	250	u8 stat;
	251	#endif
	252
1da177e4 LT	253	/*
	254	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	255	* Also, leave IRQ masked during drive probing, to prevent infinite
	256	* interrupts from a potentially floating INTA..
	257	*
	258	* IRQs get unmasked in selectproc when drive is first used.
	259	*/
	260	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	261	(void) pci_read_config_byte(dev, 0x09, &progif);
	262	/* is irq in "native" mode? */
	263	using_inta = progif & (1 << (hwif->channel << 1));
	264	if (!using_inta)
	265	using_inta = ctrl & (1 << (4 + hwif->channel));
	266	if (hwif->mate) {
	267	hwif->select_data = hwif->mate->select_data;
	268	} else {
	269	hwif->select_data = (unsigned long)
	270	&ns87415_control[ns87415_count++];
	271	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	272	if (using_inta)
	273	ctrl &= ~(1 << 6); /* unmask INTA */
	274	((unsigned int )hwif->select_data) = ctrl;
	275	(void) pci_write_config_dword(dev, 0x40, ctrl);
	276
	277	/*
	278	* Set prefetch size to 512 bytes for both ports,
	279	* but don't turn on/off prefetching here.
	280	*/
	281	pci_write_config_byte(dev, 0x55, 0xee);
	282
	283	#ifdef __sparc_v9__
	284	/*
9d501529 BZ	285	* XXX: Reset the device, if we don't it will not respond to
9d501529 BZ	286	* SELECT_DRIVE() properly during first ide_probe_port().
1da177e4 LT	287	*/
1da177e4 LT	288	timeout = 10000;
4c3032d8	289	outb(12, hwif->io_ports.ctl_addr);
1da177e4	290	udelay(10);
4c3032d8	291	outb(8, hwif->io_ports.ctl_addr);
1da177e4 LT	292	do {
1da177e4 LT	293	udelay(50);
b73c7ee2	294	stat = hwif->read_status(hwif);
1da177e4 LT	295	if (stat == 0xff)
	296	break;
	297	} while ((stat & BUSY_STAT) && --timeout);
	298	#endif
	299	}
	300
	301	if (!using_inta)
a861beb1	302	hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
1da177e4 LT	303	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
	304	hwif->irq = hwif->mate->irq; /* share IRQ with mate */
	305
	306	if (!hwif->dma_base)
	307	return;
	308
cab7f8ed	309	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	310	}
1da177e4 LT	311
ac95beed BZ	312	static const struct ide_port_ops ns87415_port_ops = {
	313	.selectproc = ns87415_selectproc,
	314	};
	315
f37afdac BZ	316	static const struct ide_dma_ops ns87415_dma_ops = {
f37afdac BZ	317	.dma_host_set = ide_dma_host_set,
5e37bdc0	318	.dma_setup = ns87415_dma_setup,
f37afdac BZ	319	.dma_exec_cmd = ide_dma_exec_cmd,
f37afdac BZ	320	.dma_start = ide_dma_start,
5e37bdc0	321	.dma_end = ns87415_dma_end,
f37afdac BZ	322	.dma_test_irq = ide_dma_test_irq,
	323	.dma_lost_irq = ide_dma_lost_irq,
	324	.dma_timeout = ide_dma_timeout,
5e37bdc0 BZ	325	};
5e37bdc0 BZ	326
85620436	327	static const struct ide_port_info ns87415_chipset __devinitdata = {
1da177e4 LT	328	.name = "NS87415",
	329	#ifdef CONFIG_SUPERIO
	330	.init_iops = init_iops_ns87415,
	331	#endif
	332	.init_hwif = init_hwif_ns87415,
ac95beed	333	.port_ops = &ns87415_port_ops,
5e37bdc0	334	.dma_ops = &ns87415_dma_ops,
33c1002e	335	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
5e71d9c5	336	IDE_HFLAG_NO_ATAPI_DMA,
1da177e4 LT	337	};
	338
	339	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	340	{
	341	return ide_setup_pci_device(dev, &ns87415_chipset);
	342	}
	343
9cbcc5e3 BZ	344	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	345	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	346	{ 0, },
	347	};
	348	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	349
	350	static struct pci_driver driver = {
	351	.name = "NS87415_IDE",
	352	.id_table = ns87415_pci_tbl,
	353	.probe = ns87415_init_one,
	354	};
	355
82ab1eec	356	static int __init ns87415_ide_init(void)
1da177e4 LT	357	{
	358	return ide_pci_register_driver(&driver);
	359	}
	360
	361	module_init(ns87415_ide_init);
	362
	363	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	364	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	365	MODULE_LICENSE("GPL");