[linux-block.git] / drivers / ide / palm_bk3710.c

/*
 * Palmchip bk3710 IDE controller
 *
 * Copyright (C) 2006 Texas Instruments.
 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>

/* Offset of the primary interface registers */
#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0

/* Primary Control Offset */
#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6

#define BK3710_BMICP		0x00
#define BK3710_BMISP		0x02
#define BK3710_BMIDTP		0x04
#define BK3710_IDETIMP		0x40
#define BK3710_IDESTATUS	0x47
#define BK3710_UDMACTL		0x48
#define BK3710_MISCCTL		0x50
#define BK3710_REGSTB		0x54
#define BK3710_REGRCVR		0x58
#define BK3710_DATSTB		0x5C
#define BK3710_DATRCVR		0x60
#define BK3710_DMASTB		0x64
#define BK3710_DMARCVR		0x68
#define BK3710_UDMASTB		0x6C
#define BK3710_UDMATRP		0x70
#define BK3710_UDMAENV		0x74
#define BK3710_IORDYTMP		0x78

static unsigned ideclk_period; /* in nanoseconds */

struct palm_bk3710_udmatiming {
	unsigned int rptime;	/* tRP -- Ready to pause time (nsec) */
	unsigned int cycletime;	/* tCYCTYP2/2 -- avg Cycle Time (nsec) */
				/* tENV is always a minimum of 20 nsec */
};

static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
	{ 160, 240 / 2 },	/* UDMA Mode 0 */
	{ 125, 160 / 2 },	/* UDMA Mode 1 */
	{ 100, 120 / 2 },	/* UDMA Mode 2 */
	{ 100,  90 / 2 },	/* UDMA Mode 3 */
	{ 100,  60 / 2 },	/* UDMA Mode 4 */
	{  85,  40 / 2 },	/* UDMA Mode 5 */
};

static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
				    unsigned int mode)
{
	u8 tenv, trp, t0;
	u32 val32;
	u16 val16;

	/* DMA Data Setup */
	t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
			  ideclk_period) - 1;
	tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
	trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
			   ideclk_period) - 1;

	/* udmastb Ultra DMA Access Strobe Width */
	val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
	val32 |= (t0 << (dev ? 8 : 0));
	writel(val32, base + BK3710_UDMASTB);

	/* udmatrp Ultra DMA Ready to Pause Time */
	val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
	val32 |= (trp << (dev ? 8 : 0));
	writel(val32, base + BK3710_UDMATRP);

	/* udmaenv Ultra DMA envelop Time */
	val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
	val32 |= (tenv << (dev ? 8 : 0));
	writel(val32, base + BK3710_UDMAENV);

	/* Enable UDMA for Device */
	val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
	writew(val16, base + BK3710_UDMACTL);
}

static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
				   unsigned short min_cycle,
				   unsigned int mode)
{
	u8 td, tkw, t0;
	u32 val32;
	u16 val16;
	struct ide_timing *t;
	int cycletime;

	t = ide_timing_find_mode(mode);
	cycletime = max_t(int, t->cycle, min_cycle);

	/* DMA Data Setup */
	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
	td = DIV_ROUND_UP(t->active, ideclk_period);
	tkw = t0 - td - 1;
	td -= 1;

	val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
	val32 |= (td << (dev ? 8 : 0));
	writel(val32, base + BK3710_DMASTB);

	val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
	val32 |= (tkw << (dev ? 8 : 0));
	writel(val32, base + BK3710_DMARCVR);

	/* Disable UDMA for Device */
	val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
	writew(val16, base + BK3710_UDMACTL);
}

static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
				   unsigned int dev, unsigned int cycletime,
				   unsigned int mode)
{
	u8 t2, t2i, t0;
	u32 val32;
	struct ide_timing *t;

	t = ide_timing_find_mode(XFER_PIO_0 + mode);

	/* PIO Data Setup */
	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
	t2 = DIV_ROUND_UP(t->active, ideclk_period);

	t2i = t0 - t2 - 1;
	t2 -= 1;

	val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
	val32 |= (t2 << (dev ? 8 : 0));
	writel(val32, base + BK3710_DATSTB);

	val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
	val32 |= (t2i << (dev ? 8 : 0));
	writel(val32, base + BK3710_DATRCVR);

	if (mate) {
		u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);

		if (mode2 < mode)
			mode = mode2;
	}

	/* TASKFILE Setup */
	t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
	t2 = DIV_ROUND_UP(t->act8b, ideclk_period);

	t2i = t0 - t2 - 1;
	t2 -= 1;

	val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
	val32 |= (t2 << (dev ? 8 : 0));
	writel(val32, base + BK3710_REGSTB);

	val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
	val32 |= (t2i << (dev ? 8 : 0));
	writel(val32, base + BK3710_REGRCVR);
}

static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
{
	int is_slave = drive->dn & 1;
	void __iomem *base = (void *)drive->hwif->dma_base;

	if (xferspeed >= XFER_UDMA_0) {
		palm_bk3710_setudmamode(base, is_slave,
					xferspeed - XFER_UDMA_0);
	} else {
		palm_bk3710_setdmamode(base, is_slave,
				       drive->id[ATA_ID_EIDE_DMA_MIN],
				       xferspeed);
	}
}

static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
{
	unsigned int cycle_time;
	int is_slave = drive->dn & 1;
	ide_drive_t *mate;
	void __iomem *base = (void *)drive->hwif->dma_base;

	/*
	 * Obtain the drive PIO data for tuning the Palm Chip registers
	 */
	cycle_time = ide_pio_cycle_time(drive, pio);
	mate = ide_get_pair_dev(drive);
	palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
}

static void __devinit palm_bk3710_chipinit(void __iomem *base)
{
	/*
	 * REVISIT:  the ATA reset signal needs to be managed through a
	 * GPIO, which means it should come from platform_data.  Until
	 * we get and use such information, we have to trust that things
	 * have been reset before we get here.
	 */

	/*
	 * Program the IDETIMP Register Value based on the following assumptions
	 *
	 * (ATA_IDETIMP_IDEEN		, ENABLE ) |
	 * (ATA_IDETIMP_PREPOST1	, DISABLE) |
	 * (ATA_IDETIMP_PREPOST0	, DISABLE) |
	 *
	 * DM6446 silicon rev 2.1 and earlier have no observed net benefit
	 * from enabling prefetch/postwrite.
	 */
	writew(BIT(15), base + BK3710_IDETIMP);

	/*
	 * UDMACTL Ultra-ATA DMA Control
	 * (ATA_UDMACTL_UDMAP1	, 0 ) |
	 * (ATA_UDMACTL_UDMAP0	, 0 )
	 *
	 */
	writew(0, base + BK3710_UDMACTL);

	/*
	 * MISCCTL Miscellaneous Conrol Register
	 * (ATA_MISCCTL_HWNHLD1P	, 1 cycle)
	 * (ATA_MISCCTL_HWNHLD0P	, 1 cycle)
	 * (ATA_MISCCTL_TIMORIDE	, 1)
	 */
	writel(0x001, base + BK3710_MISCCTL);

	/*
	 * IORDYTMP IORDY Timer for Primary Register
	 * (ATA_IORDYTMP_IORDYTMP     , 0xffff  )
	 */
	writel(0xFFFF, base + BK3710_IORDYTMP);

	/*
	 * Configure BMISP Register
	 * (ATA_BMISP_DMAEN1	, DISABLE )	|
	 * (ATA_BMISP_DMAEN0	, DISABLE )	|
	 * (ATA_BMISP_IORDYINT	, CLEAR)	|
	 * (ATA_BMISP_INTRSTAT	, CLEAR)	|
	 * (ATA_BMISP_DMAERROR	, CLEAR)
	 */
	writew(0, base + BK3710_BMISP);

	palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
	palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
}

static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
{
	return ATA_CBL_PATA80;
}

static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
					  const struct ide_port_info *d)
{
	printk(KERN_INFO "    %s: MMIO-DMA\n", hwif->name);

	if (ide_allocate_dma_engine(hwif))
		return -1;

	hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;

	return 0;
}

static const struct ide_port_ops palm_bk3710_ports_ops = {
	.set_pio_mode		= palm_bk3710_set_pio_mode,
	.set_dma_mode		= palm_bk3710_set_dma_mode,
	.cable_detect		= palm_bk3710_cable_detect,
};

static struct ide_port_info __devinitdata palm_bk3710_port_info = {
	.init_dma		= palm_bk3710_init_dma,
	.port_ops		= &palm_bk3710_ports_ops,
	.dma_ops		= &sff_dma_ops,
	.host_flags		= IDE_HFLAG_MMIO,
	.pio_mask		= ATA_PIO4,
	.mwdma_mask		= ATA_MWDMA2,
	.chipset		= ide_palm3710,
};

static int __init palm_bk3710_probe(struct platform_device *pdev)
{
	struct clk *clk;
	struct resource *mem, *irq;
	void __iomem *base;
	unsigned long rate, mem_size;
	int i, rc;
	struct ide_hw hw, *hws[] = { &hw };

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return -ENODEV;

	clk_enable(clk);
	rate = clk_get_rate(clk);

	/* NOTE:  round *down* to meet minimum timings; we count in clocks */
	ideclk_period = 1000000000UL / rate;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (mem == NULL) {
		printk(KERN_ERR "failed to get memory region resource\n");
		return -ENODEV;
	}

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (irq == NULL) {
		printk(KERN_ERR "failed to get IRQ resource\n");
		return -ENODEV;
	}

	mem_size = mem->end - mem->start + 1;
	if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) {
		printk(KERN_ERR "failed to request memory region\n");
		return -EBUSY;
	}

	base = ioremap(mem->start, mem_size);
	if (!base) {
		printk(KERN_ERR "failed to map IO memory\n");
		release_mem_region(mem->start, mem_size);
		return -ENOMEM;
	}

	/* Configure the Palm Chip controller */
	palm_bk3710_chipinit(base);

	memset(&hw, 0, sizeof(hw));
	for (i = 0; i < IDE_NR_PORTS - 2; i++)
		hw.io_ports_array[i] = (unsigned long)
				(base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
	hw.io_ports.ctl_addr = (unsigned long)
			(base + IDE_PALM_ATA_PRI_CTL_OFFSET);
	hw.irq = irq->start;
	hw.dev = &pdev->dev;

	palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
							     ATA_UDMA5;

	/* Register the IDE interface with Linux */
	rc = ide_host_add(&palm_bk3710_port_info, hws, 1, NULL);
	if (rc)
		goto out;

	return 0;
out:
	printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
	return rc;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:palm_bk3710");

static struct platform_driver platform_bk_driver = {
	.driver = {
		.name = "palm_bk3710",
		.owner = THIS_MODULE,
	},
};

static int __init palm_bk3710_init(void)
{
	return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
}

module_init(palm_bk3710_init);
MODULE_LICENSE("GPL");
Commit	Line	Data
7c7e92a9 AS	1	/*
	2	* Palmchip bk3710 IDE controller
	3	*
	4	* Copyright (C) 2006 Texas Instruments.
	5	* Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* ----------------------------------------------------------------------------
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	22	* ----------------------------------------------------------------------------
	23	*
	24	*/
	25
	26	#include <linux/types.h>
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/ioport.h>
7c7e92a9 AS	30	#include <linux/ide.h>
	31	#include <linux/delay.h>
	32	#include <linux/init.h>
	33	#include <linux/clk.h>
	34	#include <linux/platform_device.h>
	35
	36	/* Offset of the primary interface registers */
	37	#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
	38
	39	/* Primary Control Offset */
	40	#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
	41
7c7e92a9 AS	42	#define BK3710_BMICP 0x00
	43	#define BK3710_BMISP 0x02
	44	#define BK3710_BMIDTP 0x04
7c7e92a9	45	#define BK3710_IDETIMP 0x40
7c7e92a9 AS	46	#define BK3710_IDESTATUS 0x47
7c7e92a9 AS	47	#define BK3710_UDMACTL 0x48
7c7e92a9 AS	48	#define BK3710_MISCCTL 0x50
	49	#define BK3710_REGSTB 0x54
	50	#define BK3710_REGRCVR 0x58
	51	#define BK3710_DATSTB 0x5C
	52	#define BK3710_DATRCVR 0x60
	53	#define BK3710_DMASTB 0x64
	54	#define BK3710_DMARCVR 0x68
	55	#define BK3710_UDMASTB 0x6C
	56	#define BK3710_UDMATRP 0x70
	57	#define BK3710_UDMAENV 0x74
	58	#define BK3710_IORDYTMP 0x78
7c7e92a9	59
ffab6cf4	60	static unsigned ideclk_period; /* in nanoseconds */
7c7e92a9	61
db2f38c2 DB	62	struct palm_bk3710_udmatiming {
	63	unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
	64	unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
	65	/* tENV is always a minimum of 20 nsec */
	66	};
	67
7c7e92a9	68	static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
d7f51435 BZ	69	{ 160, 240 / 2 }, /* UDMA Mode 0 */
	70	{ 125, 160 / 2 }, /* UDMA Mode 1 */
	71	{ 100, 120 / 2 }, /* UDMA Mode 2 */
	72	{ 100, 90 / 2 }, /* UDMA Mode 3 */
	73	{ 100, 60 / 2 }, /* UDMA Mode 4 */
	74	{ 85, 40 / 2 }, /* UDMA Mode 5 */
7c7e92a9 AS	75	};
7c7e92a9 AS	76
7c7e92a9 AS	77	static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
	78	unsigned int mode)
	79	{
	80	u8 tenv, trp, t0;
	81	u32 val32;
	82	u16 val16;
	83
	84	/* DMA Data Setup */
00fe8b7a	85	t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
ffab6cf4 SS	86	ideclk_period) - 1;
ffab6cf4 SS	87	tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
00fe8b7a	88	trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
ffab6cf4	89	ideclk_period) - 1;
7c7e92a9	90
7c7e92a9 AS	91	/* udmastb Ultra DMA Access Strobe Width */
	92	val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
	93	val32 \|= (t0 << (dev ? 8 : 0));
	94	writel(val32, base + BK3710_UDMASTB);
	95
	96	/* udmatrp Ultra DMA Ready to Pause Time */
	97	val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
	98	val32 \|= (trp << (dev ? 8 : 0));
	99	writel(val32, base + BK3710_UDMATRP);
	100
	101	/* udmaenv Ultra DMA envelop Time */
	102	val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
	103	val32 \|= (tenv << (dev ? 8 : 0));
	104	writel(val32, base + BK3710_UDMAENV);
	105
	106	/* Enable UDMA for Device */
	107	val16 = readw(base + BK3710_UDMACTL) \| (1 << dev);
	108	writew(val16, base + BK3710_UDMACTL);
	109	}
	110
	111	static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
	112	unsigned short min_cycle,
	113	unsigned int mode)
	114	{
	115	u8 td, tkw, t0;
	116	u32 val32;
	117	u16 val16;
	118	struct ide_timing *t;
	119	int cycletime;
	120
	121	t = ide_timing_find_mode(mode);
	122	cycletime = max_t(int, t->cycle, min_cycle);
	123
	124	/* DMA Data Setup */
ffab6cf4 SS	125	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
ffab6cf4 SS	126	td = DIV_ROUND_UP(t->active, ideclk_period);
7c7e92a9 AS	127	tkw = t0 - td - 1;
	128	td -= 1;
	129
	130	val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
	131	val32 \|= (td << (dev ? 8 : 0));
	132	writel(val32, base + BK3710_DMASTB);
	133
	134	val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
	135	val32 \|= (tkw << (dev ? 8 : 0));
	136	writel(val32, base + BK3710_DMARCVR);
	137
	138	/* Disable UDMA for Device */
	139	val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
	140	writew(val16, base + BK3710_UDMACTL);
	141	}
	142
	143	static void palm_bk3710_setpiomode(void __iomem base, ide_drive_t mate,
	144	unsigned int dev, unsigned int cycletime,
	145	unsigned int mode)
	146	{
	147	u8 t2, t2i, t0;
	148	u32 val32;
	149	struct ide_timing *t;
	150
33e86019 DB	151	t = ide_timing_find_mode(XFER_PIO_0 + mode);
33e86019 DB	152
7c7e92a9	153	/* PIO Data Setup */
ffab6cf4	154	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
33e86019	155	t2 = DIV_ROUND_UP(t->active, ideclk_period);
7c7e92a9 AS	156
	157	t2i = t0 - t2 - 1;
	158	t2 -= 1;
	159
	160	val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
	161	val32 \|= (t2 << (dev ? 8 : 0));
	162	writel(val32, base + BK3710_DATSTB);
	163
	164	val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
	165	val32 \|= (t2i << (dev ? 8 : 0));
	166	writel(val32, base + BK3710_DATRCVR);
	167
7e59ea21	168	if (mate) {
7c7e92a9 AS	169	u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
	170
	171	if (mode2 < mode)
	172	mode = mode2;
	173	}
	174
	175	/* TASKFILE Setup */
ffab6cf4 SS	176	t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
ffab6cf4 SS	177	t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
7c7e92a9 AS	178
	179	t2i = t0 - t2 - 1;
	180	t2 -= 1;
	181
	182	val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
	183	val32 \|= (t2 << (dev ? 8 : 0));
	184	writel(val32, base + BK3710_REGSTB);
	185
	186	val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
	187	val32 \|= (t2i << (dev ? 8 : 0));
	188	writel(val32, base + BK3710_REGRCVR);
	189	}
	190
	191	static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
	192	{
	193	int is_slave = drive->dn & 1;
	194	void __iomem base = (void )drive->hwif->dma_base;
	195
	196	if (xferspeed >= XFER_UDMA_0) {
	197	palm_bk3710_setudmamode(base, is_slave,
	198	xferspeed - XFER_UDMA_0);
	199	} else {
4dde4492 BZ	200	palm_bk3710_setdmamode(base, is_slave,
4dde4492 BZ	201	drive->id[ATA_ID_EIDE_DMA_MIN],
7c7e92a9 AS	202	xferspeed);
	203	}
	204	}
	205
	206	static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
	207	{
	208	unsigned int cycle_time;
	209	int is_slave = drive->dn & 1;
	210	ide_drive_t *mate;
	211	void __iomem base = (void )drive->hwif->dma_base;
	212
	213	/*
	214	* Obtain the drive PIO data for tuning the Palm Chip registers
	215	*/
	216	cycle_time = ide_pio_cycle_time(drive, pio);
7e59ea21	217	mate = ide_get_pair_dev(drive);
7c7e92a9 AS	218	palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
	219	}
	220
	221	static void __devinit palm_bk3710_chipinit(void __iomem *base)
	222	{
	223	/*
33e86019 DB	224	* REVISIT: the ATA reset signal needs to be managed through a
	225	* GPIO, which means it should come from platform_data. Until
	226	* we get and use such information, we have to trust that things
	227	* have been reset before we get here.
7c7e92a9	228	*/
7c7e92a9 AS	229
	230	/*
	231	* Program the IDETIMP Register Value based on the following assumptions
	232	*
	233	* (ATA_IDETIMP_IDEEN , ENABLE ) \|
7c7e92a9	234	* (ATA_IDETIMP_PREPOST1 , DISABLE) \|
7c7e92a9	235	* (ATA_IDETIMP_PREPOST0 , DISABLE) \|
33e86019 DB	236	*
	237	* DM6446 silicon rev 2.1 and earlier have no observed net benefit
	238	* from enabling prefetch/postwrite.
7c7e92a9	239	*/
33e86019	240	writew(BIT(15), base + BK3710_IDETIMP);
7c7e92a9 AS	241
	242	/*
	243	* UDMACTL Ultra-ATA DMA Control
	244	* (ATA_UDMACTL_UDMAP1 , 0 ) \|
	245	* (ATA_UDMACTL_UDMAP0 , 0 )
	246	*
	247	*/
	248	writew(0, base + BK3710_UDMACTL);
	249
	250	/*
	251	* MISCCTL Miscellaneous Conrol Register
33e86019 DB	252	* (ATA_MISCCTL_HWNHLD1P , 1 cycle)
33e86019 DB	253	* (ATA_MISCCTL_HWNHLD0P , 1 cycle)
7c7e92a9 AS	254	* (ATA_MISCCTL_TIMORIDE , 1)
7c7e92a9 AS	255	*/
33e86019	256	writel(0x001, base + BK3710_MISCCTL);
7c7e92a9 AS	257
	258	/*
	259	* IORDYTMP IORDY Timer for Primary Register
	260	* (ATA_IORDYTMP_IORDYTMP , 0xffff )
	261	*/
	262	writel(0xFFFF, base + BK3710_IORDYTMP);
	263
	264	/*
	265	* Configure BMISP Register
	266	* (ATA_BMISP_DMAEN1 , DISABLE ) \|
	267	* (ATA_BMISP_DMAEN0 , DISABLE ) \|
	268	* (ATA_BMISP_IORDYINT , CLEAR) \|
	269	* (ATA_BMISP_INTRSTAT , CLEAR) \|
	270	* (ATA_BMISP_DMAERROR , CLEAR)
	271	*/
	272	writew(0, base + BK3710_BMISP);
	273
	274	palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
	275	palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
	276	}
c79b60dd	277
f454cbe8	278	static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
c79b60dd BZ	279	{
	280	return ATA_CBL_PATA80;
	281	}
	282
b552a2c1 BZ	283	static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
	284	const struct ide_port_info *d)
	285	{
b552a2c1 BZ	286	printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
	287
	288	if (ide_allocate_dma_engine(hwif))
	289	return -1;
	290
81e8d5a3 BZ	291	hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
81e8d5a3 BZ	292
b552a2c1 BZ	293	return 0;
	294	}
	295
ac95beed BZ	296	static const struct ide_port_ops palm_bk3710_ports_ops = {
	297	.set_pio_mode = palm_bk3710_set_pio_mode,
	298	.set_dma_mode = palm_bk3710_set_dma_mode,
	299	.cable_detect = palm_bk3710_cable_detect,
	300	};
c79b60dd	301
a0f403bc	302	static struct ide_port_info __devinitdata palm_bk3710_port_info = {
b552a2c1	303	.init_dma = palm_bk3710_init_dma,
ac95beed	304	.port_ops = &palm_bk3710_ports_ops,
3f023b01	305	.dma_ops = &sff_dma_ops,
c5dd43ec	306	.host_flags = IDE_HFLAG_MMIO,
c79b60dd	307	.pio_mask = ATA_PIO4,
c79b60dd	308	.mwdma_mask = ATA_MWDMA2,
29e52cf7	309	.chipset = ide_palm3710,
c79b60dd BZ	310	};
c79b60dd BZ	311
bfc2f01f	312	static int __init palm_bk3710_probe(struct platform_device *pdev)
7c7e92a9	313	{
ffab6cf4	314	struct clk *clk;
7c7e92a9	315	struct resource mem, irq;
ef183f6b	316	void __iomem *base;
13b8860d	317	unsigned long rate, mem_size;
6f904d01	318	int i, rc;
9f36d314	319	struct ide_hw hw, *hws[] = { &hw };
7c7e92a9	320
468b5ef8	321	clk = clk_get(&pdev->dev, NULL);
ffab6cf4	322	if (IS_ERR(clk))
7c7e92a9 AS	323	return -ENODEV;
7c7e92a9 AS	324
ffab6cf4 SS	325	clk_enable(clk);
ffab6cf4 SS	326	rate = clk_get_rate(clk);
ffab6cf4	327
33e86019 DB	328	/* NOTE: round down to meet minimum timings; we count in clocks */
33e86019 DB	329	ideclk_period = 1000000000UL / rate;
7c7e92a9 AS	330
	331	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	332	if (mem == NULL) {
	333	printk(KERN_ERR "failed to get memory region resource\n");
	334	return -ENODEV;
	335	}
ce42a549	336
7c7e92a9 AS	337	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	338	if (irq == NULL) {
	339	printk(KERN_ERR "failed to get IRQ resource\n");
	340	return -ENODEV;
	341	}
	342
13b8860d KH	343	mem_size = mem->end - mem->start + 1;
13b8860d KH	344	if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) {
ce42a549 SS	345	printk(KERN_ERR "failed to request memory region\n");
	346	return -EBUSY;
	347	}
	348
13b8860d KH	349	base = ioremap(mem->start, mem_size);
	350	if (!base) {
	351	printk(KERN_ERR "failed to map IO memory\n");
	352	release_mem_region(mem->start, mem_size);
	353	return -ENOMEM;
	354	}
7c7e92a9 AS	355
7c7e92a9 AS	356	/* Configure the Palm Chip controller */
ef183f6b	357	palm_bk3710_chipinit(base);
7c7e92a9	358
33e86019	359	memset(&hw, 0, sizeof(hw));
7824bc6b	360	for (i = 0; i < IDE_NR_PORTS - 2; i++)
ef183f6b DB	361	hw.io_ports_array[i] = (unsigned long)
	362	(base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
	363	hw.io_ports.ctl_addr = (unsigned long)
	364	(base + IDE_PALM_ATA_PRI_CTL_OFFSET);
7824bc6b	365	hw.irq = irq->start;
bfc2f01f	366	hw.dev = &pdev->dev;
7c7e92a9	367
a0f403bc SS	368	palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
	369	ATA_UDMA5;
	370
33e86019	371	/* Register the IDE interface with Linux */
dca39830	372	rc = ide_host_add(&palm_bk3710_port_info, hws, 1, NULL);
6f904d01	373	if (rc)
7824bc6b BZ	374	goto out;
7824bc6b BZ	375
7c7e92a9	376	return 0;
7824bc6b BZ	377	out:
7824bc6b BZ	378	printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
6f904d01	379	return rc;
7c7e92a9 AS	380	}
7c7e92a9 AS	381
458622fc KS	382	/* work with hotplug and coldplug */
	383	MODULE_ALIAS("platform:palm_bk3710");
	384
7c7e92a9 AS	385	static struct platform_driver platform_bk_driver = {
	386	.driver = {
	387	.name = "palm_bk3710",
458622fc	388	.owner = THIS_MODULE,
7c7e92a9	389	},
7c7e92a9 AS	390	};
	391
	392	static int __init palm_bk3710_init(void)
	393	{
bfc2f01f	394	return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
7c7e92a9 AS	395	}
	396
	397	module_init(palm_bk3710_init);
	398	MODULE_LICENSE("GPL");