Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
58f189fc | 2 | * Q40 I/O port IDE Driver |
1da177e4 LT |
3 | * |
4 | * (c) Richard Zidlicky | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive for | |
8 | * more details. | |
9 | * | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/types.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/blkdev.h> | |
17 | #include <linux/hdreg.h> | |
18 | ||
19 | #include <linux/ide.h> | |
20 | ||
21 | /* | |
22 | * Bases of the IDE interfaces | |
23 | */ | |
24 | ||
25 | #define Q40IDE_NUM_HWIFS 2 | |
26 | ||
27 | #define PCIDE_BASE1 0x1f0 | |
28 | #define PCIDE_BASE2 0x170 | |
29 | #define PCIDE_BASE3 0x1e8 | |
30 | #define PCIDE_BASE4 0x168 | |
31 | #define PCIDE_BASE5 0x1e0 | |
32 | #define PCIDE_BASE6 0x160 | |
33 | ||
34 | static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = { | |
35 | PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5, | |
36 | PCIDE_BASE6 */ | |
37 | }; | |
38 | ||
39 | ||
40 | /* | |
41 | * Offsets from one of the above bases | |
42 | */ | |
43 | ||
44 | /* used to do addr translation here but it is easier to do in setup ports */ | |
45 | /*#define IDE_OFF_B(x) ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/ | |
46 | ||
47 | #define IDE_OFF_B(x) ((unsigned long)((IDE_##x##_OFFSET))) | |
48 | #define IDE_OFF_W(x) ((unsigned long)((IDE_##x##_OFFSET))) | |
49 | ||
50 | static const int pcide_offsets[IDE_NR_PORTS] = { | |
51 | IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR), | |
52 | IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS), | |
53 | 518/*IDE_OFF(CMD)*/ | |
54 | }; | |
55 | ||
56 | static int q40ide_default_irq(unsigned long base) | |
57 | { | |
58 | switch (base) { | |
59 | case 0x1f0: return 14; | |
60 | case 0x170: return 15; | |
61 | case 0x1e8: return 11; | |
62 | default: | |
63 | return 0; | |
64 | } | |
65 | } | |
66 | ||
67 | ||
68 | /* | |
29dd5975 | 69 | * Addresses are pretranslated for Q40 ISA access. |
1da177e4 LT |
70 | */ |
71 | void q40_ide_setup_ports ( hw_regs_t *hw, | |
72 | unsigned long base, int *offsets, | |
73 | unsigned long ctrl, unsigned long intr, | |
74 | ide_ack_intr_t *ack_intr, | |
1da177e4 LT |
75 | int irq) |
76 | { | |
77 | int i; | |
78 | ||
2c3e0262 | 79 | memset(hw, 0, sizeof(hw_regs_t)); |
1da177e4 LT |
80 | for (i = 0; i < IDE_NR_PORTS; i++) { |
81 | /* BIG FAT WARNING: | |
82 | assumption: only DATA port is ever used in 16 bit mode */ | |
4c3032d8 BZ |
83 | if (i == 0) |
84 | hw->io_ports_array[i] = Q40_ISA_IO_W(base + offsets[i]); | |
1da177e4 | 85 | else |
4c3032d8 | 86 | hw->io_ports_array[i] = Q40_ISA_IO_B(base + offsets[i]); |
1da177e4 | 87 | } |
86f3a492 | 88 | |
1da177e4 | 89 | hw->irq = irq; |
1da177e4 | 90 | hw->ack_intr = ack_intr; |
1da177e4 LT |
91 | } |
92 | ||
93 | ||
94 | ||
95 | /* | |
96 | * the static array is needed to have the name reported in /proc/ioports, | |
96de0e25 | 97 | * hwif->name unfortunately isn't available yet |
1da177e4 LT |
98 | */ |
99 | static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={ | |
100 | "ide0", "ide1" | |
101 | }; | |
102 | ||
103 | /* | |
104 | * Probe for Q40 IDE interfaces | |
105 | */ | |
106 | ||
ade2daf9 | 107 | static int __init q40ide_init(void) |
1da177e4 LT |
108 | { |
109 | int i; | |
110 | ide_hwif_t *hwif; | |
1da177e4 | 111 | const char *name; |
8ac4ce74 | 112 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
113 | |
114 | if (!MACH_IS_Q40) | |
ade2daf9 | 115 | return -ENODEV; |
1da177e4 | 116 | |
c99c92c5 BZ |
117 | printk(KERN_INFO "ide: Q40 IDE controller\n"); |
118 | ||
1da177e4 LT |
119 | for (i = 0; i < Q40IDE_NUM_HWIFS; i++) { |
120 | hw_regs_t hw; | |
121 | ||
122 | name = q40_ide_names[i]; | |
123 | if (!request_region(pcide_bases[i], 8, name)) { | |
124 | printk("could not reserve ports %lx-%lx for %s\n", | |
125 | pcide_bases[i],pcide_bases[i]+8,name); | |
126 | continue; | |
127 | } | |
128 | if (!request_region(pcide_bases[i]+0x206, 1, name)) { | |
129 | printk("could not reserve port %lx for %s\n", | |
130 | pcide_bases[i]+0x206,name); | |
131 | release_region(pcide_bases[i], 8); | |
132 | continue; | |
133 | } | |
134 | q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets, | |
135 | pcide_bases[i]+0x206, | |
136 | 0, NULL, | |
137 | // m68kide_iops, | |
138 | q40ide_default_irq(pcide_bases[i])); | |
cbb010c1 | 139 | |
59bff5ba | 140 | hwif = ide_find_port(); |
cbb010c1 BZ |
141 | if (hwif) { |
142 | ide_init_port_data(hwif, hwif->index); | |
143 | ide_init_port_hw(hwif, &hw); | |
8ac4ce74 BZ |
144 | |
145 | idx[i] = hwif->index; | |
cbb010c1 | 146 | } |
1da177e4 | 147 | } |
8ac4ce74 | 148 | |
c413b9b9 | 149 | ide_device_add(idx, NULL); |
ade2daf9 BZ |
150 | |
151 | return 0; | |
1da177e4 LT |
152 | } |
153 | ||
ade2daf9 | 154 | module_init(q40ide_init); |
f743d04d AB |
155 | |
156 | MODULE_LICENSE("GPL"); |