[linux-block.git] / drivers / ide / cy82c693.c

/*
 *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
 *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
 *
 * CYPRESS CY82C693 chipset IDE controller
 *
 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
 * Writing the driver was quite simple, since most of the job is
 * done by the generic pci-ide support.
 * The hard part was finding the CY82C693's datasheet on Cypress's
 * web page :-(. But Altavista solved this problem :-).
 *
 *
 * Notes:
 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
 *   a large and fast disk - the results look great, so I'd say the
 *   driver is working fine :-)
 *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
 * - this is my first linux driver, so there's probably a lot  of room
 *   for optimizations and bug fixing, so feel free to do it.
 * - if using PIO mode it's a good idea to set the PIO mode and
 *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
 * - I had some problems with my IBM DHEA with PIO modes < 2
 *   (lost interrupts) ?????
 * - first tests with DMA look okay, they seem to work, but there is a
 *   problem with sound - the BusMaster IDE TimeOut should fixed this
 *
 * Ancient History:
 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
 * ASK@1999-01-23: v0.33 made a few minor code clean ups
 *                       removed DMA clock speed setting by default
 *                       added boot message
 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
 *                       added support to set DMA Controller Clock Speed
 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
 *                       on some drives.
 * ASK@1998-10-29: v0.3 added support to set DMA modes
 * ASK@1998-10-28: v0.2 added support to set PIO modes
 * ASK@1998-10-27: v0.1 first version - chipset detection
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cy82c693"

/*
 *	The following are used to debug the driver.
 */
#define CY82C693_DEBUG_INFO	0

/*
 *	NOTE: the value for busmaster timeout is tricky and I got it by
 *	trial and error!  By using a to low value will cause DMA timeouts
 *	and drop IDE performance, and by using a to high value will cause
 *	audio playback to scatter.
 *	If you know a better value or how to calc it, please let me know.
 */

/* twice the value written in cy82c693ub datasheet */
#define BUSMASTER_TIMEOUT	0x50
/*
 * the value above was tested on my machine and it seems to work okay
 */

/* here are the offset definitions for the registers */
#define CY82_IDE_CMDREG		0x04
#define CY82_IDE_ADDRSETUP	0x48
#define CY82_IDE_MASTER_IOR	0x4C
#define CY82_IDE_MASTER_IOW	0x4D
#define CY82_IDE_SLAVE_IOR	0x4E
#define CY82_IDE_SLAVE_IOW	0x4F
#define CY82_IDE_MASTER_8BIT	0x50
#define CY82_IDE_SLAVE_8BIT	0x51

#define CY82_INDEX_PORT		0x22
#define CY82_DATA_PORT		0x23

#define CY82_INDEX_CHANNEL0	0x30
#define CY82_INDEX_CHANNEL1	0x31
#define CY82_INDEX_TIMEOUT	0x32

/* the min and max PCI bus speed in MHz - from datasheet */
#define CY82C963_MIN_BUS_SPEED	25
#define CY82C963_MAX_BUS_SPEED	33

/* the struct for the PIO mode timings */
typedef struct pio_clocks_s {
	u8	address_time;	/* Address setup (clocks) */
	u8	time_16r;	/* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_16w;	/* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	u8	time_8;		/* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
} pio_clocks_t;

/*
 * calc clocks using bus_speed
 * returns (rounded up) time in bus clocks for time in ns
 */
static int calc_clk(int time, int bus_speed)
{
	int clocks;

	clocks = (time*bus_speed+999)/1000 - 1;

	if (clocks < 0)
		clocks = 0;

	if (clocks > 0x0F)
		clocks = 0x0F;

	return clocks;
}

/*
 * compute the values for the clock registers for PIO
 * mode and pci_clk [MHz] speed
 *
 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 *
 */
static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
{
	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
	int clk1, clk2;
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;

	/* we don't check against CY82C693's min and max speed,
	 * so you can play with the idebus=xx parameter
	 */

	/* let's calc the address setup time clocks */
	p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);

	/* let's calc the active and recovery time clocks */
	clk1 = calc_clk(t->active, bus_speed);

	/* calc recovery timing */
	clk2 = t->cycle - t->active - t->setup;

	clk2 = calc_clk(clk2, bus_speed);

	clk1 = (clk1<<4)|clk2;	/* combine active and recovery clocks */

	/* note: we use the same values for 16bit IOR and IOW
	 *	those are all the same, since I don't have other
	 *	timings than those from ide-lib.c
	 */

	p_pclk->time_16r = (u8)clk1;
	p_pclk->time_16w = (u8)clk1;

	/* what are good values for 8bit ?? */
	p_pclk->time_8 = (u8)clk1;
}

/*
 * set DMA mode a specific channel for CY82C693
 */

static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;

	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;

	data = (mode & 3) | (single << 2);

	outb(index, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
		drive->name, hwif->channel, drive->dn & 1, mode & 3, single);
#endif /* CY82C693_DEBUG_INFO */

	/*
	 * note: below we set the value for Bus Master IDE TimeOut Register
	 * I'm not absolutly sure what this does, but it solved my problem
	 * with IDE DMA and sound, so I now can play sound and work with
	 * my IDE driver at the same time :-)
	 *
	 * If you know the correct (best) value for this register please
	 * let me know - ASK
	 */

	data = BUSMASTER_TIMEOUT;
	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
		drive->name, data);
#endif /* CY82C693_DEBUG_INFO */
}

static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	pio_clocks_t pclk;
	unsigned int addrCtrl;

	/* select primary or secondary channel */
	if (hwif->index > 0) {  /* drive is on the secondary channel */
		dev = pci_get_slot(dev->bus, dev->devfn+1);
		if (!dev) {
			printk(KERN_ERR "%s: tune_drive: "
				"Cannot find secondary interface!\n",
				drive->name);
			return;
		}
	}

	/* let's calc the values for this PIO mode */
	compute_clocks(pio, &pclk);

	/* now let's write  the clocks registers */
	if ((drive->dn & 1) == 0) {
		/*
		 * set master drive
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF);
		addrCtrl |= (unsigned int)pclk.address_time;
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);

		addrCtrl &= 0xF;
	} else {
		/*
		 * set slave drive
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF0);
		addrCtrl |= ((unsigned int)pclk.address_time<<4);
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);

		addrCtrl >>= 4;
		addrCtrl &= 0xF;
	}

#if CY82C693_DEBUG_INFO
	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
		"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
		drive->name, hwif->channel, drive->dn & 1,
		addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
#endif /* CY82C693_DEBUG_INFO */
}

static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
{
	static ide_hwif_t *primary;
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_FUNC(dev->devfn) == 1)
		primary = hwif;
	else {
		hwif->mate = primary;
		hwif->channel = 1;
	}
}

static const struct ide_port_ops cy82c693_port_ops = {
	.set_pio_mode		= cy82c693_set_pio_mode,
	.set_dma_mode		= cy82c693_set_dma_mode,
};

static const struct ide_port_info cy82c693_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_iops	= init_iops_cy82c693,
	.port_ops	= &cy82c693_port_ops,
	.host_flags	= IDE_HFLAG_SINGLE,
	.pio_mask	= ATA_PIO4,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *dev2;
	int ret = -ENODEV;

	/* CY82C693 is more than only a IDE controller.
	   Function 1 is primary IDE channel, function 2 - secondary. */
	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	    PCI_FUNC(dev->devfn) == 1) {
		dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
		ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
		if (ret)
			pci_dev_put(dev2);
	}
	return ret;
}

static void __devexit cy82c693_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;

	ide_pci_remove(dev);
	pci_dev_put(dev2);
}

static const struct pci_device_id cy82c693_pci_tbl[] = {
	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);

static struct pci_driver cy82c693_pci_driver = {
	.name		= "Cypress_IDE",
	.id_table	= cy82c693_pci_tbl,
	.probe		= cy82c693_init_one,
	.remove		= __devexit_p(cy82c693_remove),
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cy82c693_ide_init(void)
{
	return ide_pci_register_driver(&cy82c693_pci_driver);
}

static void __exit cy82c693_ide_exit(void)
{
	pci_unregister_driver(&cy82c693_pci_driver);
}

module_init(cy82c693_ide_init);
module_exit(cy82c693_ide_exit);

MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
	3	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
	4	*
	5	* CYPRESS CY82C693 chipset IDE controller
	6	*
	7	* The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
	8	* Writing the driver was quite simple, since most of the job is
175f354b	9	* done by the generic pci-ide support.
1da177e4 LT	10	* The hard part was finding the CY82C693's datasheet on Cypress's
	11	* web page :-(. But Altavista solved this problem :-).
	12	*
	13	*
	14	* Notes:
	15	* - I recently got a 16.8G IBM DTTA, so I was able to test it with
	16	* a large and fast disk - the results look great, so I'd say the
	17	* driver is working fine :-)
175f354b PC	18	* hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
175f354b PC	19	* - this is my first linux driver, so there's probably a lot of room
1da177e4	20	* for optimizations and bug fixing, so feel free to do it.
175f354b	21	* - if using PIO mode it's a good idea to set the PIO mode and
1da177e4 LT	22	* 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
	23	* - I had some problems with my IBM DHEA with PIO modes < 2
	24	* (lost interrupts) ?????
	25	* - first tests with DMA look okay, they seem to work, but there is a
	26	* problem with sound - the BusMaster IDE TimeOut should fixed this
	27	*
	28	* Ancient History:
	29	* AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
	30	* ASK@1999-01-23: v0.33 made a few minor code clean ups
	31	* removed DMA clock speed setting by default
	32	* added boot message
	33	* ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
	34	* added support to set DMA Controller Clock Speed
	35	* ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
	36	* on some drives.
	37	* ASK@1998-10-29: v0.3 added support to set DMA modes
	38	* ASK@1998-10-28: v0.2 added support to set PIO modes
	39	* ASK@1998-10-27: v0.1 first version - chipset detection
	40	*
	41	*/
	42
1da177e4 LT	43	#include <linux/module.h>
	44	#include <linux/types.h>
	45	#include <linux/pci.h>
1da177e4 LT	46	#include <linux/ide.h>
	47	#include <linux/init.h>
	48
	49	#include <asm/io.h>
	50
ced3ec8a BZ	51	#define DRV_NAME "cy82c693"
ced3ec8a BZ	52
1da177e4 LT	53	/*
	54	* The following are used to debug the driver.
	55	*/
1da177e4 LT	56	#define CY82C693_DEBUG_INFO 0
1da177e4 LT	57
1da177e4 LT	58	/*
	59	* NOTE: the value for busmaster timeout is tricky and I got it by
	60	* trial and error! By using a to low value will cause DMA timeouts
	61	* and drop IDE performance, and by using a to high value will cause
	62	* audio playback to scatter.
	63	* If you know a better value or how to calc it, please let me know.
	64	*/
	65
	66	/* twice the value written in cy82c693ub datasheet */
	67	#define BUSMASTER_TIMEOUT 0x50
	68	/*
	69	* the value above was tested on my machine and it seems to work okay
	70	*/
	71
	72	/* here are the offset definitions for the registers */
	73	#define CY82_IDE_CMDREG 0x04
	74	#define CY82_IDE_ADDRSETUP 0x48
	75	#define CY82_IDE_MASTER_IOR 0x4C
	76	#define CY82_IDE_MASTER_IOW 0x4D
	77	#define CY82_IDE_SLAVE_IOR 0x4E
	78	#define CY82_IDE_SLAVE_IOW 0x4F
	79	#define CY82_IDE_MASTER_8BIT 0x50
	80	#define CY82_IDE_SLAVE_8BIT 0x51
	81
	82	#define CY82_INDEX_PORT 0x22
	83	#define CY82_DATA_PORT 0x23
	84
1da177e4 LT	85	#define CY82_INDEX_CHANNEL0 0x30
	86	#define CY82_INDEX_CHANNEL1 0x31
	87	#define CY82_INDEX_TIMEOUT 0x32
	88
1da177e4 LT	89	/* the min and max PCI bus speed in MHz - from datasheet */
	90	#define CY82C963_MIN_BUS_SPEED 25
	91	#define CY82C963_MAX_BUS_SPEED 33
	92
	93	/* the struct for the PIO mode timings */
	94	typedef struct pio_clocks_s {
	95	u8 address_time; /* Address setup (clocks) */
	96	u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
	97	u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
	98	u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
	99	} pio_clocks_t;
	100
	101	/*
	102	* calc clocks using bus_speed
	103	* returns (rounded up) time in bus clocks for time in ns
	104	*/
175f354b	105	static int calc_clk(int time, int bus_speed)
1da177e4 LT	106	{
	107	int clocks;
	108
175f354b	109	clocks = (time*bus_speed+999)/1000 - 1;
1da177e4 LT	110
	111	if (clocks < 0)
	112	clocks = 0;
	113
	114	if (clocks > 0x0F)
	115	clocks = 0x0F;
	116
	117	return clocks;
	118	}
	119
	120	/*
	121	* compute the values for the clock registers for PIO
	122	* mode and pci_clk [MHz] speed
	123	*
	124	* NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
	125	* for mode 3 and 4 drives 8 and 16-bit timings are the same
	126	*
175f354b PC	127	*/
175f354b PC	128	static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
1da177e4	129	{
713a590d	130	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
1da177e4	131	int clk1, clk2;
30e5ee4d	132	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
1da177e4 LT	133
	134	/* we don't check against CY82C693's min and max speed,
	135	* so you can play with the idebus=xx parameter
	136	*/
	137
1da177e4	138	/* let's calc the address setup time clocks */
713a590d	139	p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
1da177e4 LT	140
1da177e4 LT	141	/* let's calc the active and recovery time clocks */
713a590d	142	clk1 = calc_clk(t->active, bus_speed);
1da177e4 LT	143
1da177e4 LT	144	/* calc recovery timing */
713a590d	145	clk2 = t->cycle - t->active - t->setup;
1da177e4 LT	146
	147	clk2 = calc_clk(clk2, bus_speed);
	148
	149	clk1 = (clk1<<4)\|clk2; /* combine active and recovery clocks */
	150
	151	/* note: we use the same values for 16bit IOR and IOW
175f354b	152	* those are all the same, since I don't have other
1da177e4 LT	153	* timings than those from ide-lib.c
	154	*/
	155
	156	p_pclk->time_16r = (u8)clk1;
	157	p_pclk->time_16w = (u8)clk1;
	158
	159	/* what are good values for 8bit ?? */
	160	p_pclk->time_8 = (u8)clk1;
	161	}
	162
	163	/*
	164	* set DMA mode a specific channel for CY82C693
	165	*/
	166
8704de8f	167	static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
1da177e4	168	{
8704de8f BZ	169	ide_hwif_t *hwif = drive->hwif;
8704de8f BZ	170	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
1da177e4	171
8704de8f	172	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
1da177e4	173
8704de8f	174	data = (mode & 3) \| (single << 2);
1da177e4	175
0ecdca26 BZ	176	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	177	outb(data, CY82_DATA_PORT);
1da177e4 LT	178
	179	#if CY82C693_DEBUG_INFO
	180	printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
123995b9	181	drive->name, hwif->channel, drive->dn & 1, mode & 3, single);
1da177e4 LT	182	#endif /* CY82C693_DEBUG_INFO */
1da177e4 LT	183
175f354b	184	/*
1da177e4 LT	185	* note: below we set the value for Bus Master IDE TimeOut Register
	186	* I'm not absolutly sure what this does, but it solved my problem
	187	* with IDE DMA and sound, so I now can play sound and work with
	188	* my IDE driver at the same time :-)
	189	*
	190	* If you know the correct (best) value for this register please
	191	* let me know - ASK
	192	*/
	193
	194	data = BUSMASTER_TIMEOUT;
0ecdca26 BZ	195	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
0ecdca26 BZ	196	outb(data, CY82_DATA_PORT);
1da177e4	197
175f354b PC	198	#if CY82C693_DEBUG_INFO
175f354b PC	199	printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
1da177e4 LT	200	drive->name, data);
	201	#endif /* CY82C693_DEBUG_INFO */
	202	}
	203
26bcb879	204	static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	205	{
898ec223	206	ide_hwif_t *hwif = drive->hwif;
36501650	207	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	208	pio_clocks_t pclk;
	209	unsigned int addrCtrl;
	210
	211	/* select primary or secondary channel */
	212	if (hwif->index > 0) { /* drive is on the secondary channel */
652aa162	213	dev = pci_get_slot(dev->bus, dev->devfn+1);
1da177e4 LT	214	if (!dev) {
	215	printk(KERN_ERR "%s: tune_drive: "
	216	"Cannot find secondary interface!\n",
	217	drive->name);
	218	return;
	219	}
	220	}
	221
1da177e4 LT	222	/* let's calc the values for this PIO mode */
	223	compute_clocks(pio, &pclk);
	224
	225	/* now let's write the clocks registers */
123995b9	226	if ((drive->dn & 1) == 0) {
1da177e4 LT	227	/*
	228	* set master drive
	229	* address setup control register
	230	* is 32 bit !!!
175f354b	231	*/
1da177e4	232	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
175f354b	233
1da177e4 LT	234	addrCtrl &= (~0xF);
	235	addrCtrl \|= (unsigned int)pclk.address_time;
	236	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	237
	238	/* now let's set the remaining registers */
	239	pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
	240	pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
	241	pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
175f354b	242
1da177e4 LT	243	addrCtrl &= 0xF;
	244	} else {
	245	/*
	246	* set slave drive
	247	* address setup control register
	248	* is 32 bit !!!
175f354b	249	*/
1da177e4 LT	250	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	251
	252	addrCtrl &= (~0xF0);
	253	addrCtrl \|= ((unsigned int)pclk.address_time<<4);
	254	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	255
	256	/* now let's set the remaining registers */
	257	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
	258	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
	259	pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
	260
	261	addrCtrl >>= 4;
	262	addrCtrl &= 0xF;
175f354b	263	}
1da177e4 LT	264
	265	#if CY82C693_DEBUG_INFO
	266	printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
	267	"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
123995b9	268	drive->name, hwif->channel, drive->dn & 1,
1da177e4 LT	269	addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
	270	#endif /* CY82C693_DEBUG_INFO */
	271	}
	272
e851b620	273	static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
1da177e4	274	{
f32d26ae	275	static ide_hwif_t *primary;
36501650	276	struct pci_dev *dev = to_pci_dev(hwif->dev);
f32d26ae	277
36501650	278	if (PCI_FUNC(dev->devfn) == 1)
1da177e4 LT	279	primary = hwif;
	280	else {
	281	hwif->mate = primary;
	282	hwif->channel = 1;
	283	}
	284	}
	285
ac95beed BZ	286	static const struct ide_port_ops cy82c693_port_ops = {
	287	.set_pio_mode = cy82c693_set_pio_mode,
	288	.set_dma_mode = cy82c693_set_dma_mode,
	289	};
	290
85620436	291	static const struct ide_port_info cy82c693_chipset __devinitdata = {
ced3ec8a	292	.name = DRV_NAME,
7b77d864	293	.init_iops = init_iops_cy82c693,
ac95beed	294	.port_ops = &cy82c693_port_ops,
951784b6	295	.host_flags = IDE_HFLAG_SINGLE,
4099d143	296	.pio_mask = ATA_PIO4,
8704de8f BZ	297	.swdma_mask = ATA_SWDMA2,
8704de8f BZ	298	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	299	};
	300
	301	static int __devinit cy82c693_init_one(struct pci_dev dev, const struct pci_device_id id)
	302	{
1da177e4 LT	303	struct pci_dev *dev2;
	304	int ret = -ENODEV;
	305
	306	/* CY82C693 is more than only a IDE controller.
	307	Function 1 is primary IDE channel, function 2 - secondary. */
175f354b	308	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
1da177e4	309	PCI_FUNC(dev->devfn) == 1) {
652aa162	310	dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
6cdf6eb3	311	ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
cd68841b BZ	312	if (ret)
cd68841b BZ	313	pci_dev_put(dev2);
1da177e4 LT	314	}
	315	return ret;
	316	}
	317
cd68841b BZ	318	static void __devexit cy82c693_remove(struct pci_dev *dev)
	319	{
	320	struct ide_host *host = pci_get_drvdata(dev);
	321	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
	322
	323	ide_pci_remove(dev);
	324	pci_dev_put(dev2);
	325	}
	326
9cbcc5e3 BZ	327	static const struct pci_device_id cy82c693_pci_tbl[] = {
9cbcc5e3 BZ	328	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
1da177e4 LT	329	{ 0, },
	330	};
	331	MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
	332
a9ab09e2	333	static struct pci_driver cy82c693_pci_driver = {
1da177e4 LT	334	.name = "Cypress_IDE",
	335	.id_table = cy82c693_pci_tbl,
	336	.probe = cy82c693_init_one,
a69999e2	337	.remove = __devexit_p(cy82c693_remove),
feb22b7f BZ	338	.suspend = ide_pci_suspend,
feb22b7f BZ	339	.resume = ide_pci_resume,
1da177e4 LT	340	};
1da177e4 LT	341
82ab1eec	342	static int __init cy82c693_ide_init(void)
1da177e4	343	{
a9ab09e2	344	return ide_pci_register_driver(&cy82c693_pci_driver);
1da177e4 LT	345	}
1da177e4 LT	346
cd68841b BZ	347	static void __exit cy82c693_ide_exit(void)
cd68841b BZ	348	{
a9ab09e2	349	pci_unregister_driver(&cy82c693_pci_driver);
cd68841b BZ	350	}
cd68841b BZ	351
1da177e4	352	module_init(cy82c693_ide_init);
cd68841b	353	module_exit(cy82c693_ide_exit);
1da177e4 LT	354
	355	MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
	356	MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
	357	MODULE_LICENSE("GPL");