[linux-block.git] / drivers / ide / cs5530.c

/*
 * Copyright (C) 2000			Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2000			Mark Lord <mlord@pobox.com>
 * Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	CS5530 documentation available from National Semiconductor.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "cs5530"

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static unsigned int cs5530_pio_timings[2][5] = {
	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
};

/*
 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
 */
#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
#define CS5530_BASEREG(hwif)	(((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))

/**
 *	cs5530_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Handles setting of PIO mode for the chipset.
 *
 *	The init_hwif_cs5530() routine guarantees that all drives
 *	will have valid default PIO timings set up before we get here.
 */

static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	unsigned long basereg = CS5530_BASEREG(drive->hwif);
	unsigned int format = (inl(basereg + 4) >> 31) & 1;

	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
}

/**
 *	cs5530_udma_filter	-	UDMA filter
 *	@drive: drive
 *
 *	cs5530_udma_filter() does UDMA mask filtering for the given drive
 *	taking into the consideration capabilities of the mate device.
 *
 *	The CS5530 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 *
 *	Note: This relies on the fact we never fail from UDMA to MWDMA2
 *	but instead drop to PIO.
 */

static u8 cs5530_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = ide_get_pair_dev(drive);
	u16 *mateid;
	u8 mask = hwif->ultra_mask;

	if (mate == NULL)
		goto out;
	mateid = mate->id;

	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
		    (mateid[ATA_ID_UDMA_MODES] & 7))
			goto out;
		if (mateid[ATA_ID_MWDMA_MODES] & 7)
			mask = 0;
	}
out:
	return mask;
}

static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	unsigned long basereg;
	unsigned int reg, timings = 0;

	switch (mode) {
		case XFER_UDMA_0:	timings = 0x00921250; break;
		case XFER_UDMA_1:	timings = 0x00911140; break;
		case XFER_UDMA_2:	timings = 0x00911030; break;
		case XFER_MW_DMA_0:	timings = 0x00077771; break;
		case XFER_MW_DMA_1:	timings = 0x00012121; break;
		case XFER_MW_DMA_2:	timings = 0x00002020; break;
	}
	basereg = CS5530_BASEREG(drive->hwif);
	reg = inl(basereg + 4);			/* get drive0 config register */
	timings |= reg & 0x80000000;		/* preserve PIO format bit */
	if ((drive-> dn & 1) == 0) {		/* are we configuring drive0? */
		outl(timings, basereg + 4);	/* write drive0 config register */
	} else {
		if (timings & 0x00100000)
			reg |=  0x00100000;	/* enable UDMA timings for both drives */
		else
			reg &= ~0x00100000;	/* disable UDMA timings for both drives */
		outl(reg, basereg + 4);		/* write drive0 config register */
		outl(timings, basereg + 12);	/* write drive1 config register */
	}
}

/**
 *	init_chipset_5530	-	set up 5530 bridge
 *	@dev: PCI device
 *
 *	Initialize the cs5530 bridge for reliable IDE DMA operation.
 */

static int init_chipset_cs5530(struct pci_dev *dev)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;

	if (pci_resource_start(dev, 4) == 0)
		return -EFAULT;

	dev = NULL;
	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
		goto out;
	}
	if (!cs5530_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
		goto out;
	}

	/*
	 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	 * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	 */

	pci_set_master(cs5530_0);
	pci_try_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/* 
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

out:
	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
}

/**
 *	init_hwif_cs5530	-	initialise an IDE channel
 *	@hwif: IDE to initialize
 *
 *	This gets invoked by the IDE driver once for each channel. It
 *	performs channel-specific pre-initialization before drive probing.
 */

static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
{
	unsigned long basereg;
	u32 d0_timings;

	basereg = CS5530_BASEREG(hwif);
	d0_timings = inl(basereg + 0);
	if (CS5530_BAD_PIO(d0_timings))
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
	if (CS5530_BAD_PIO(inl(basereg + 8)))
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
}

static const struct ide_port_ops cs5530_port_ops = {
	.set_pio_mode		= cs5530_set_pio_mode,
	.set_dma_mode		= cs5530_set_dma_mode,
	.udma_filter		= cs5530_udma_filter,
};

static const struct ide_port_info cs5530_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_chipset	= init_chipset_cs5530,
	.init_hwif	= init_hwif_cs5530,
	.port_ops	= &cs5530_port_ops,
	.host_flags	= IDE_HFLAG_SERIALIZE |
			  IDE_HFLAG_POST_SET_MODE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA2,
};

static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &cs5530_chipset, NULL);
}

static const struct pci_device_id cs5530_pci_tbl[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);

static struct pci_driver cs5530_pci_driver = {
	.name		= "CS5530 IDE",
	.id_table	= cs5530_pci_tbl,
	.probe		= cs5530_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cs5530_ide_init(void)
{
	return ide_pci_register_driver(&cs5530_pci_driver);
}

static void __exit cs5530_ide_exit(void)
{
	pci_unregister_driver(&cs5530_pci_driver);
}

module_init(cs5530_ide_init);
module_exit(cs5530_ide_exit);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
1da177e4	3	* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
5fd216bb BZ	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	5	*
1da177e4 LT	6	* May be copied or modified under the terms of the GNU General Public License
	7	*
	8	* Development of this chipset driver was funded
	9	* by the nice folks at National Semiconductor.
	10	*
	11	* Documentation:
	12	* CS5530 documentation available from National Semiconductor.
	13	*/
	14
1da177e4 LT	15	#include <linux/module.h>
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/ide.h>
78829dd9	21
1da177e4	22	#include <asm/io.h>
1da177e4	23
ced3ec8a BZ	24	#define DRV_NAME "cs5530"
ced3ec8a BZ	25
1da177e4 LT	26	/*
	27	* Here are the standard PIO mode 0-4 timings for each "format".
	28	* Format-0 uses fast data reg timings, with slower command reg timings.
	29	* Format-1 uses fast timings for all registers, but won't work with all drives.
	30	*/
	31	static unsigned int cs5530_pio_timings[2][5] = {
	32	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	33	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	34	};
	35
	36	/*
	37	* After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
	38	*/
	39	#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
	40	#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
	41
	42	/**
88b2b32b	43	* cs5530_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	44	* @drive: drive
26bcb879 BZ	45	* @pio: PIO mode number
1da177e4	46	*
88b2b32b	47	* Handles setting of PIO mode for the chipset.
1da177e4	48	*
26bcb879	49	* The init_hwif_cs5530() routine guarantees that all drives
1da177e4 LT	50	* will have valid default PIO timings set up before we get here.
	51	*/
	52
26bcb879	53	static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	54	{
88b2b32b BZ	55	unsigned long basereg = CS5530_BASEREG(drive->hwif);
	56	unsigned int format = (inl(basereg + 4) >> 31) & 1;
	57
	58	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
1da177e4 LT	59	}
	60
	61	/**
5fd216bb BZ	62	* cs5530_udma_filter - UDMA filter
	63	* @drive: drive
	64	*
	65	* cs5530_udma_filter() does UDMA mask filtering for the given drive
	66	* taking into the consideration capabilities of the mate device.
	67	*
	68	* The CS5530 specifies that two drives sharing a cable cannot mix
	69	* UDMA/MDMA. It has to be one or the other, for the pair, though
	70	* different timings can still be chosen for each drive. We could
	71	* set the appropriate timing bits on the fly, but that might be
	72	* a bit confusing. So, for now we statically handle this requirement
	73	* by looking at our mate drive to see what it is capable of, before
	74	* choosing a mode for our own drive.
	75	*
	76	* Note: This relies on the fact we never fail from UDMA to MWDMA2
	77	* but instead drop to PIO.
	78	*/
	79
	80	static u8 cs5530_udma_filter(ide_drive_t *drive)
	81	{
	82	ide_hwif_t *hwif = drive->hwif;
7e59ea21	83	ide_drive_t *mate = ide_get_pair_dev(drive);
9ecab6e5	84	u16 *mateid;
5fd216bb BZ	85	u8 mask = hwif->ultra_mask;
5fd216bb BZ	86
7e59ea21	87	if (mate == NULL)
5fd216bb	88	goto out;
9ecab6e5	89	mateid = mate->id;
5fd216bb	90
48fb2688	91	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
4dde4492 BZ	92	if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
4dde4492 BZ	93	(mateid[ATA_ID_UDMA_MODES] & 7))
5fd216bb	94	goto out;
8d64fcd9	95	if (mateid[ATA_ID_MWDMA_MODES] & 7)
5fd216bb BZ	96	mask = 0;
	97	}
	98	out:
	99	return mask;
	100	}
	101
88b2b32b	102	static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
3c3f5d2c	103	{
5fd216bb	104	unsigned long basereg;
3c3f5d2c	105	unsigned int reg, timings = 0;
1da177e4	106
1da177e4 LT	107	switch (mode) {
	108	case XFER_UDMA_0: timings = 0x00921250; break;
	109	case XFER_UDMA_1: timings = 0x00911140; break;
	110	case XFER_UDMA_2: timings = 0x00911030; break;
	111	case XFER_MW_DMA_0: timings = 0x00077771; break;
	112	case XFER_MW_DMA_1: timings = 0x00012121; break;
	113	case XFER_MW_DMA_2: timings = 0x00002020; break;
1da177e4	114	}
3c3f5d2c	115	basereg = CS5530_BASEREG(drive->hwif);
0ecdca26	116	reg = inl(basereg + 4); /* get drive0 config register */
1da177e4	117	timings \|= reg & 0x80000000; /* preserve PIO format bit */
3c3f5d2c	118	if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
0ecdca26	119	outl(timings, basereg + 4); /* write drive0 config register */
1da177e4 LT	120	} else {
	121	if (timings & 0x00100000)
	122	reg \|= 0x00100000; /* enable UDMA timings for both drives */
	123	else
	124	reg &= ~0x00100000; /* disable UDMA timings for both drives */
0ecdca26 BZ	125	outl(reg, basereg + 4); /* write drive0 config register */
0ecdca26 BZ	126	outl(timings, basereg + 12); /* write drive1 config register */
1da177e4	127	}
1da177e4 LT	128	}
	129
	130	/**
	131	* init_chipset_5530 - set up 5530 bridge
	132	* @dev: PCI device
1da177e4 LT	133	*
	134	* Initialize the cs5530 bridge for reliable IDE DMA operation.
	135	*/
	136
2ed0ef54	137	static int init_chipset_cs5530(struct pci_dev *dev)
1da177e4 LT	138	{
1da177e4 LT	139	struct pci_dev master_0 = NULL, cs5530_0 = NULL;
1da177e4	140
f7b0d2df BZ	141	if (pci_resource_start(dev, 4) == 0)
	142	return -EFAULT;
	143
1da177e4	144	dev = NULL;
652aa162	145	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
1da177e4 LT	146	switch (dev->device) {
1da177e4 LT	147	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
652aa162	148	master_0 = pci_dev_get(dev);
1da177e4 LT	149	break;
1da177e4 LT	150	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
652aa162	151	cs5530_0 = pci_dev_get(dev);
1da177e4 LT	152	break;
	153	}
	154	}
	155	if (!master_0) {
a326b02b	156	printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
652aa162	157	goto out;
1da177e4 LT	158	}
1da177e4 LT	159	if (!cs5530_0) {
a326b02b	160	printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
652aa162	161	goto out;
1da177e4 LT	162	}
1da177e4 LT	163
1da177e4 LT	164	/*
	165	* Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	166	* --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	167	*/
	168
	169	pci_set_master(cs5530_0);
694625c0	170	pci_try_set_mwi(cs5530_0);
1da177e4 LT	171
	172	/*
	173	* Set PCI CacheLineSize to 16-bytes:
	174	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	175	*/
	176
	177	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	178
	179	/*
	180	* Disable trapping of UDMA register accesses (Win98 hack):
	181	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	182	*/
	183
	184	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	185
	186	/*
	187	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	188	* The other settings are what is necessary to get the register
	189	* into a sane state for IDE DMA operation.
	190	*/
	191
	192	pci_write_config_byte(master_0, 0x40, 0x1e);
	193
	194	/*
	195	* Set max PCI burst size (16-bytes seems to work best):
	196	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	197	* all others: clear bit-1 at 0x41, and do:
	198	* 128bytes: OR 0x00 at 0x41
	199	* 256bytes: OR 0x04 at 0x41
	200	* 512bytes: OR 0x08 at 0x41
	201	* 1024bytes: OR 0x0c at 0x41
	202	*/
	203
	204	pci_write_config_byte(master_0, 0x41, 0x14);
	205
	206	/*
	207	* These settings are necessary to get the chip
	208	* into a sane state for IDE DMA operation.
	209	*/
	210
	211	pci_write_config_byte(master_0, 0x42, 0x00);
	212	pci_write_config_byte(master_0, 0x43, 0xc1);
	213
652aa162 AC	214	out:
	215	pci_dev_put(master_0);
	216	pci_dev_put(cs5530_0);
1da177e4 LT	217	return 0;
	218	}
	219
	220	/**
	221	* init_hwif_cs5530 - initialise an IDE channel
	222	* @hwif: IDE to initialize
	223	*
	224	* This gets invoked by the IDE driver once for each channel. It
	225	* performs channel-specific pre-initialization before drive probing.
	226	*/
	227
88de8e99	228	static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
1da177e4 LT	229	{
	230	unsigned long basereg;
	231	u32 d0_timings;
1da177e4	232
1da177e4	233	basereg = CS5530_BASEREG(hwif);
0ecdca26	234	d0_timings = inl(basereg + 0);
93104654	235	if (CS5530_BAD_PIO(d0_timings))
0ecdca26	236	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
93104654	237	if (CS5530_BAD_PIO(inl(basereg + 8)))
0ecdca26	238	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
1da177e4 LT	239	}
1da177e4 LT	240
ac95beed BZ	241	static const struct ide_port_ops cs5530_port_ops = {
	242	.set_pio_mode = cs5530_set_pio_mode,
	243	.set_dma_mode = cs5530_set_dma_mode,
	244	.udma_filter = cs5530_udma_filter,
	245	};
	246
85620436	247	static const struct ide_port_info cs5530_chipset __devinitdata = {
ced3ec8a	248	.name = DRV_NAME,
1da177e4 LT	249	.init_chipset = init_chipset_cs5530,
1da177e4 LT	250	.init_hwif = init_hwif_cs5530,
ac95beed	251	.port_ops = &cs5530_port_ops,
1c51361a	252	.host_flags = IDE_HFLAG_SERIALIZE \|
5e71d9c5	253	IDE_HFLAG_POST_SET_MODE,
4099d143	254	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	255	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	256	.udma_mask = ATA_UDMA2,
1da177e4 LT	257	};
	258
	259	static int __devinit cs5530_init_one(struct pci_dev dev, const struct pci_device_id id)
	260	{
6cdf6eb3	261	return ide_pci_init_one(dev, &cs5530_chipset, NULL);
1da177e4 LT	262	}
1da177e4 LT	263
9cbcc5e3 BZ	264	static const struct pci_device_id cs5530_pci_tbl[] = {
9cbcc5e3 BZ	265	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
1da177e4 LT	266	{ 0, },
	267	};
	268	MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
	269
a9ab09e2	270	static struct pci_driver cs5530_pci_driver = {
1da177e4 LT	271	.name = "CS5530 IDE",
	272	.id_table = cs5530_pci_tbl,
	273	.probe = cs5530_init_one,
d16492a9	274	.remove = ide_pci_remove,
feb22b7f BZ	275	.suspend = ide_pci_suspend,
feb22b7f BZ	276	.resume = ide_pci_resume,
1da177e4 LT	277	};
1da177e4 LT	278
82ab1eec	279	static int __init cs5530_ide_init(void)
1da177e4	280	{
a9ab09e2	281	return ide_pci_register_driver(&cs5530_pci_driver);
1da177e4 LT	282	}
1da177e4 LT	283
d16492a9 BZ	284	static void __exit cs5530_ide_exit(void)
d16492a9 BZ	285	{
a9ab09e2	286	pci_unregister_driver(&cs5530_pci_driver);
d16492a9 BZ	287	}
d16492a9 BZ	288
1da177e4	289	module_init(cs5530_ide_init);
d16492a9	290	module_exit(cs5530_ide_exit);
1da177e4 LT	291
	292	MODULE_AUTHOR("Mark Lord");
	293	MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
	294	MODULE_LICENSE("GPL");