[linux-block.git] / drivers / ide / amd74xx.c

/*
 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
 * IDE driver for Linux.
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *      Andre Hedrick
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#define DRV_NAME "amd74xx"

enum {
	AMD_IDE_CONFIG		= 0x41,
	AMD_CABLE_DETECT	= 0x42,
	AMD_DRIVE_TIMING	= 0x48,
	AMD_8BIT_TIMING		= 0x4e,
	AMD_ADDRESS_SETUP	= 0x4c,
	AMD_UDMA_TIMING		= 0x50,
};

static unsigned int amd_80w;
static unsigned int amd_clock;

static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };

static inline u8 amd_offset(struct pci_dev *dev)
{
	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
}

/*
 * amd_set_speed() writes timing values to the chipset registers
 */

static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
			  struct ide_timing *timing)
{
	u8 t = 0, offset = amd_offset(dev);

	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);

	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
		((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
		((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));

	switch (udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
	case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
	case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
	default: return;
	}

	pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
}

/*
 * amd_set_drive() computes timing values and configures the chipset
 * to a desired transfer mode.  It also can be called by upper layers.
 */

static void amd_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	ide_drive_t *peer = ide_get_pair_dev(drive);
	struct ide_timing t, p;
	int T, UT;
	u8 udma_mask = hwif->ultra_mask;

	T = 1000000000 / amd_clock;
	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;

	amd_set_speed(dev, drive->dn, udma_mask, &t);
}

/*
 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
 */

static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	amd_set_drive(drive, XFER_PIO_0 + pio);
}

static void amd7409_cable_detect(struct pci_dev *dev)
{
	/* no host side cable detection */
	amd_80w = 0x03;
}

static void amd7411_cable_detect(struct pci_dev *dev)
{
	int i;
	u32 u = 0;
	u8 t = 0, offset = amd_offset(dev);

	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
	amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
	for (i = 24; i >= 0; i -= 8)
		if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
			printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
				"cable bits correctly. Enabling workaround.\n",
				pci_name(dev));
			amd_80w |= (1 << (1 - (i >> 4)));
		}
}

/*
 * The initialization callback.  Initialize drive independent registers.
 */

static int init_chipset_amd74xx(struct pci_dev *dev)
{
	u8 t = 0, offset = amd_offset(dev);

/*
 * Check 80-wire cable presence.
 */

	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
		; /* no UDMA > 2 */
	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
		 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
		amd7409_cable_detect(dev);
	else
		amd7411_cable_detect(dev);

/*
 * Take care of prefetch & postwrite.
 */

	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
	/*
	 * Check for broken FIFO support.
	 */
	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
		t &= 0x0f;
	else
		t |= 0xf0;
	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);

	return 0;
}

static u8 amd_cable_detect(ide_hwif_t *hwif)
{
	if ((amd_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops amd_port_ops = {
	.set_pio_mode		= amd_set_pio_mode,
	.set_dma_mode		= amd_set_drive,
	.cable_detect		= amd_cable_detect,
};

#define IDE_HFLAGS_AMD \
	(IDE_HFLAG_PIO_NO_BLACKLIST | \
	 IDE_HFLAG_POST_SET_MODE | \
	 IDE_HFLAG_IO_32BIT | \
	 IDE_HFLAG_UNMASK_IRQS)

#define DECLARE_AMD_DEV(swdma, udma)				\
	{								\
		.name		= DRV_NAME,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},	\
		.port_ops	= &amd_port_ops,			\
		.host_flags	= IDE_HFLAGS_AMD,			\
		.pio_mask	= ATA_PIO5,				\
		.swdma_mask	= swdma,				\
		.mwdma_mask	= ATA_MWDMA2,				\
		.udma_mask	= udma,					\
	}

#define DECLARE_NV_DEV(udma)					\
	{								\
		.name		= DRV_NAME,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.enablebits	= {{0x50,0x02,0x02}, {0x50,0x01,0x01}},	\
		.port_ops	= &amd_port_ops,			\
		.host_flags	= IDE_HFLAGS_AMD,			\
		.pio_mask	= ATA_PIO5,				\
		.swdma_mask	= ATA_SWDMA2,				\
		.mwdma_mask	= ATA_MWDMA2,				\
		.udma_mask	= udma,					\
	}

static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
	/* 0: AMD7401 */	DECLARE_AMD_DEV(0x00, ATA_UDMA2),
	/* 1: AMD7409 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
	/* 2: AMD7411/7441 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
	/* 3: AMD8111 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),

	/* 4: NFORCE */		DECLARE_NV_DEV(ATA_UDMA5),
	/* 5: >= NFORCE2 */	DECLARE_NV_DEV(ATA_UDMA6),

	/* 6: AMD5536 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
};

static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = amd74xx_chipsets[idx];

	/*
	 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
	 */
	if (idx == 1) {
		if (dev->revision <= 7)
			d.swdma_mask = 0;
		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
	} else if (idx == 3) {
		if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
		    dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
			d.udma_mask = ATA_UDMA5;
	}

	/*
	 * It seems that on some nVidia controllers using AltStatus
	 * register can be unreliable so default to Status register
	 * if the device is in Compatibility Mode.
	 */
	if (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
	    ide_pci_is_in_compatibility_mode(dev))
		d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS;

	printk(KERN_INFO "%s %s: UDMA%s controller\n",
		d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]);

	/*
	* Determine the system bus clock.
	*/
	amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;

	switch (amd_clock) {
	case 33000: amd_clock = 33333; break;
	case 37000: amd_clock = 37500; break;
	case 41000: amd_clock = 41666; break;
	}

	if (amd_clock < 20000 || amd_clock > 50000) {
		printk(KERN_WARNING "%s: User given PCI clock speed impossible"
				    " (%d), using 33 MHz instead.\n",
				    d.name, amd_clock);
		amd_clock = 33333;
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id amd74xx_pci_tbl[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		 0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		 1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		 2 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		 2 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		 3 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	 4 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	 5 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA),	 5 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	 5 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2),	 5 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	 5 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		 6 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);

static struct pci_driver amd74xx_pci_driver = {
	.name		= "AMD_IDE",
	.id_table	= amd74xx_pci_tbl,
	.probe		= amd74xx_probe,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init amd74xx_ide_init(void)
{
	return ide_pci_register_driver(&amd74xx_pci_driver);
}

static void __exit amd74xx_ide_exit(void)
{
	pci_unregister_driver(&amd74xx_pci_driver);
}

module_init(amd74xx_ide_init);
module_exit(amd74xx_ide_exit);

MODULE_AUTHOR("Vojtech Pavlik");
MODULE_DESCRIPTION("AMD PCI IDE driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
	3	* IDE driver for Linux.
	4	*
	5	* Copyright (c) 2000-2002 Vojtech Pavlik
6636487e	6	* Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	*
	8	* Based on the work of:
	9	* Andre Hedrick
	10	*/
	11
	12	/*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License version 2 as published by
	15	* the Free Software Foundation.
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
1da177e4 LT	19	#include <linux/kernel.h>
1da177e4 LT	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/ide.h>
1da177e4	23
ced3ec8a BZ	24	#define DRV_NAME "amd74xx"
ced3ec8a BZ	25
993da8f9 BZ	26	enum {
	27	AMD_IDE_CONFIG = 0x41,
	28	AMD_CABLE_DETECT = 0x42,
	29	AMD_DRIVE_TIMING = 0x48,
	30	AMD_8BIT_TIMING = 0x4e,
	31	AMD_ADDRESS_SETUP = 0x4c,
	32	AMD_UDMA_TIMING = 0x50,
1da177e4 LT	33	};
1da177e4 LT	34
1da177e4 LT	35	static unsigned int amd_80w;
	36	static unsigned int amd_clock;
	37
75b1d975	38	static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4 LT	39	static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
1da177e4 LT	40
993da8f9 BZ	41	static inline u8 amd_offset(struct pci_dev *dev)
	42	{
	43	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
	44	}
	45
1da177e4 LT	46	/*
	47	* amd_set_speed() writes timing values to the chipset registers
	48	*/
	49
993da8f9 BZ	50	static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
993da8f9 BZ	51	struct ide_timing *timing)
1da177e4	52	{
993da8f9	53	u8 t = 0, offset = amd_offset(dev);
1da177e4	54
993da8f9	55	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
d6cddd3c	56	t = (t & ~(3 << ((3 - dn) << 1))) \| ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
993da8f9	57	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
1da177e4	58
993da8f9	59	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
d6cddd3c	60	((clamp_val(timing->act8b, 1, 16) - 1) << 4) \| (clamp_val(timing->rec8b, 1, 16) - 1));
1da177e4	61
993da8f9	62	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
d6cddd3c	63	((clamp_val(timing->active, 1, 16) - 1) << 4) \| (clamp_val(timing->recover, 1, 16) - 1));
1da177e4	64
993da8f9	65	switch (udma_mask) {
d6cddd3c HH	66	case ATA_UDMA2: t = timing->udma ? (0xc0 \| (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	67	case ATA_UDMA4: t = timing->udma ? (0xc0 \| amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
	68	case ATA_UDMA5: t = timing->udma ? (0xc0 \| amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
	69	case ATA_UDMA6: t = timing->udma ? (0xc0 \| amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
75b1d975	70	default: return;
1da177e4 LT	71	}
1da177e4 LT	72
993da8f9	73	pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
1da177e4 LT	74	}
	75
	76	/*
88b2b32b BZ	77	* amd_set_drive() computes timing values and configures the chipset
88b2b32b BZ	78	* to a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	79	*/
1da177e4 LT	80
88b2b32b	81	static void amd_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4	82	{
993da8f9	83	ide_hwif_t *hwif = drive->hwif;
36501650	84	struct pci_dev *dev = to_pci_dev(hwif->dev);
bca4ff16	85	ide_drive_t *peer = ide_get_pair_dev(drive);
1da177e4 LT	86	struct ide_timing t, p;
1da177e4 LT	87	int T, UT;
993da8f9	88	u8 udma_mask = hwif->ultra_mask;
1da177e4	89
1da177e4	90	T = 1000000000 / amd_clock;
993da8f9	91	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
1da177e4 LT	92
	93	ide_timing_compute(drive, speed, &t, T, UT);
	94
bca4ff16	95	if (peer) {
1da177e4 LT	96	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	97	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	98	}
	99
	100	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	101	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
	102
36501650	103	amd_set_speed(dev, drive->dn, udma_mask, &t);
1da177e4 LT	104	}
	105
	106	/*
26bcb879	107	* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
1da177e4 LT	108	*/
1da177e4 LT	109
26bcb879	110	static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	111	{
26bcb879	112	amd_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	113	}
1da177e4 LT	114
feb22b7f	115	static void amd7409_cable_detect(struct pci_dev *dev)
993da8f9 BZ	116	{
	117	/* no host side cable detection */
	118	amd_80w = 0x03;
	119	}
1da177e4	120
feb22b7f	121	static void amd7411_cable_detect(struct pci_dev *dev)
1da177e4	122	{
1da177e4	123	int i;
993da8f9 BZ	124	u32 u = 0;
	125	u8 t = 0, offset = amd_offset(dev);
	126
	127	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
	128	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
	129	amd_80w = ((t & 0x3) ? 1 : 0) \| ((t & 0xc) ? 2 : 0);
	130	for (i = 24; i >= 0; i -= 8)
	131	if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
a326b02b BZ	132	printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
	133	"cable bits correctly. Enabling workaround.\n",
	134	pci_name(dev));
993da8f9 BZ	135	amd_80w \|= (1 << (1 - (i >> 4)));
	136	}
	137	}
1da177e4 LT	138
1da177e4 LT	139	/*
993da8f9	140	* The initialization callback. Initialize drive independent registers.
1da177e4 LT	141	*/
1da177e4 LT	142
2ed0ef54	143	static int init_chipset_amd74xx(struct pci_dev *dev)
993da8f9 BZ	144	{
993da8f9 BZ	145	u8 t = 0, offset = amd_offset(dev);
1da177e4 LT	146
	147	/*
	148	* Check 80-wire cable presence.
	149	*/
	150
993da8f9 BZ	151	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	152	dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
	153	; /* no UDMA > 2 */
	154	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	155	dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
a326b02b	156	amd7409_cable_detect(dev);
993da8f9	157	else
a326b02b	158	amd7411_cable_detect(dev);
1da177e4 LT	159
	160	/*
	161	* Take care of prefetch & postwrite.
	162	*/
	163
993da8f9 BZ	164	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
	165	/*
	166	* Check for broken FIFO support.
	167	*/
	168	if (dev->vendor == PCI_VENDOR_ID_AMD &&
43a12216	169	dev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
993da8f9 BZ	170	t &= 0x0f;
	171	else
	172	t \|= 0xf0;
	173	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
1da177e4	174
2ed0ef54	175	return 0;
1da177e4 LT	176	}
1da177e4 LT	177
f454cbe8	178	static u8 amd_cable_detect(ide_hwif_t *hwif)
bfa14b42 BZ	179	{
	180	if ((amd_80w >> hwif->channel) & 1)
	181	return ATA_CBL_PATA80;
	182	else
	183	return ATA_CBL_PATA40;
	184	}
	185
ac95beed BZ	186	static const struct ide_port_ops amd_port_ops = {
	187	.set_pio_mode = amd_set_pio_mode,
	188	.set_dma_mode = amd_set_drive,
	189	.cable_detect = amd_cable_detect,
	190	};
	191
caea7602 BZ	192	#define IDE_HFLAGS_AMD \
caea7602 BZ	193	(IDE_HFLAG_PIO_NO_BLACKLIST \| \
caea7602 BZ	194	IDE_HFLAG_POST_SET_MODE \| \
caea7602 BZ	195	IDE_HFLAG_IO_32BIT \| \
5e71d9c5	196	IDE_HFLAG_UNMASK_IRQS)
caea7602	197
ced3ec8a	198	#define DECLARE_AMD_DEV(swdma, udma) \
1da177e4	199	{ \
ced3ec8a	200	.name = DRV_NAME, \
1da177e4	201	.init_chipset = init_chipset_amd74xx, \
1da177e4	202	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
ac95beed	203	.port_ops = &amd_port_ops, \
caea7602	204	.host_flags = IDE_HFLAGS_AMD, \
4099d143	205	.pio_mask = ATA_PIO5, \
993da8f9	206	.swdma_mask = swdma, \
5f8b6c34	207	.mwdma_mask = ATA_MWDMA2, \
993da8f9	208	.udma_mask = udma, \
1da177e4 LT	209	}
1da177e4 LT	210
ced3ec8a	211	#define DECLARE_NV_DEV(udma) \
1da177e4	212	{ \
ced3ec8a	213	.name = DRV_NAME, \
1da177e4	214	.init_chipset = init_chipset_amd74xx, \
1da177e4	215	.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
ac95beed	216	.port_ops = &amd_port_ops, \
caea7602	217	.host_flags = IDE_HFLAGS_AMD, \
4099d143	218	.pio_mask = ATA_PIO5, \
5f8b6c34 BZ	219	.swdma_mask = ATA_SWDMA2, \
5f8b6c34 BZ	220	.mwdma_mask = ATA_MWDMA2, \
993da8f9	221	.udma_mask = udma, \
1da177e4 LT	222	}
1da177e4 LT	223
85620436	224	static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
ced3ec8a BZ	225	/* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2),
	226	/* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
	227	/* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
	228	/* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),
	229
	230	/* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5),
	231	/* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6),
	232
	233	/* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
1da177e4 LT	234	};
	235
	236	static int __devinit amd74xx_probe(struct pci_dev dev, const struct pci_device_id id)
	237	{
993da8f9 BZ	238	struct ide_port_info d;
	239	u8 idx = id->driver_data;
	240
	241	d = amd74xx_chipsets[idx];
	242
	243	/*
	244	* Check for bad SWDMA and incorrectly wired Serenade mainboards.
	245	*/
	246	if (idx == 1) {
	247	if (dev->revision <= 7)
	248	d.swdma_mask = 0;
8ac2b42a	249	d.host_flags \|= IDE_HFLAG_CLEAR_SIMPLEX;
ced3ec8a	250	} else if (idx == 3) {
993da8f9 BZ	251	if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	252	dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
	253	d.udma_mask = ATA_UDMA5;
1da177e4	254	}
993da8f9	255
6636487e BZ	256	/*
	257	* It seems that on some nVidia controllers using AltStatus
	258	* register can be unreliable so default to Status register
	259	* if the device is in Compatibility Mode.
	260	*/
	261	if (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
	262	ide_pci_is_in_compatibility_mode(dev))
	263	d.host_flags \|= IDE_HFLAG_BROKEN_ALTSTATUS;
	264
28cfd8af BZ	265	printk(KERN_INFO "%s %s: UDMA%s controller\n",
28cfd8af BZ	266	d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]);
993da8f9	267
d51f19c8 BZ	268	/*
	269	* Determine the system bus clock.
	270	*/
	271	amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
	272
	273	switch (amd_clock) {
	274	case 33000: amd_clock = 33333; break;
	275	case 37000: amd_clock = 37500; break;
	276	case 41000: amd_clock = 41666; break;
	277	}
	278
	279	if (amd_clock < 20000 \|\| amd_clock > 50000) {
	280	printk(KERN_WARNING "%s: User given PCI clock speed impossible"
	281	" (%d), using 33 MHz instead.\n",
	282	d.name, amd_clock);
	283	amd_clock = 33333;
	284	}
	285
6cdf6eb3	286	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	287	}
1da177e4 LT	288
9cbcc5e3 BZ	289	static const struct pci_device_id amd74xx_pci_tbl[] = {
	290	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	291	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	292	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
ced3ec8a BZ	293	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 },
	294	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 },
	295	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 },
	296	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 },
	297	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 },
1da177e4	298	#ifdef CONFIG_BLK_DEV_IDE_SATA
ced3ec8a	299	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 },
1da177e4	300	#endif
ced3ec8a BZ	301	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 },
ced3ec8a BZ	302	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 },
1da177e4	303	#ifdef CONFIG_BLK_DEV_IDE_SATA
ced3ec8a BZ	304	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 },
ced3ec8a BZ	305	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 },
1da177e4	306	#endif
ced3ec8a BZ	307	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 },
	308	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 },
	309	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 },
	310	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 },
	311	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 },
	312	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 },
	313	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 },
	314	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 },
	315	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 },
	316	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 },
1da177e4 LT	317	{ 0, },
	318	};
	319	MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
	320
a9ab09e2	321	static struct pci_driver amd74xx_pci_driver = {
1da177e4 LT	322	.name = "AMD_IDE",
	323	.id_table = amd74xx_pci_tbl,
	324	.probe = amd74xx_probe,
b2509ac1	325	.remove = ide_pci_remove,
feb22b7f BZ	326	.suspend = ide_pci_suspend,
feb22b7f BZ	327	.resume = ide_pci_resume,
1da177e4 LT	328	};
1da177e4 LT	329
82ab1eec	330	static int __init amd74xx_ide_init(void)
1da177e4	331	{
a9ab09e2	332	return ide_pci_register_driver(&amd74xx_pci_driver);
1da177e4 LT	333	}
1da177e4 LT	334
b2509ac1 BZ	335	static void __exit amd74xx_ide_exit(void)
b2509ac1 BZ	336	{
a9ab09e2	337	pci_unregister_driver(&amd74xx_pci_driver);
b2509ac1 BZ	338	}
b2509ac1 BZ	339
1da177e4	340	module_init(amd74xx_ide_init);
b2509ac1	341	module_exit(amd74xx_ide_exit);
1da177e4 LT	342
	343	MODULE_AUTHOR("Vojtech Pavlik");
	344	MODULE_DESCRIPTION("AMD PCI IDE driver");
	345	MODULE_LICENSE("GPL");