Commit | Line | Data |
---|---|---|
13f35ac1 NH |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * Copyright(c) 2012 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * GPL LICENSE SUMMARY | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
13f35ac1 NH |
17 | * The full GNU General Public License is included in this distribution |
18 | * in the file called LICENSE.GPL. | |
19 | * | |
20 | * BSD LICENSE | |
21 | * | |
22 | * Redistribution and use in source and binary forms, with or without | |
23 | * modification, are permitted provided that the following conditions | |
24 | * are met: | |
25 | * | |
26 | * * Redistributions of source code must retain the above copyright | |
27 | * notice, this list of conditions and the following disclaimer. | |
28 | * * Redistributions in binary form must reproduce the above copyright | |
29 | * notice, this list of conditions and the following disclaimer in | |
30 | * the documentation and/or other materials provided with the | |
31 | * distribution. | |
32 | * * Neither the name of Intel Corporation nor the names of its | |
33 | * contributors may be used to endorse or promote products derived | |
34 | * from this software without specific prior written permission. | |
35 | * | |
36 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
37 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
38 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
39 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
40 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
41 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
42 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
43 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
44 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
45 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
46 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
47 | */ | |
48 | ||
49 | /* | |
50 | * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor | |
51 | * S12xx Product Family. | |
52 | * | |
53 | * Features supported by this driver: | |
54 | * Hardware PEC yes | |
55 | * Block buffer yes | |
56 | * Block process call transaction no | |
57 | * Slave mode no | |
58 | */ | |
59 | ||
60 | #include <linux/module.h> | |
13f35ac1 NH |
61 | #include <linux/pci.h> |
62 | #include <linux/kernel.h> | |
63 | #include <linux/stddef.h> | |
64 | #include <linux/completion.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/i2c.h> | |
67 | #include <linux/acpi.h> | |
68 | #include <linux/interrupt.h> | |
69 | ||
70 | #include <asm-generic/io-64-nonatomic-lo-hi.h> | |
71 | ||
72 | /* PCI Address Constants */ | |
73 | #define SMBBAR 0 | |
74 | ||
75 | /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ | |
76 | #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 | |
77 | #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a | |
488b9269 | 78 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 |
13f35ac1 | 79 | |
8b57cebe | 80 | #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ |
13f35ac1 NH |
81 | #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ |
82 | ||
83 | /* Hardware Descriptor Constants - Control Field */ | |
84 | #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ | |
85 | #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ | |
86 | #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ | |
87 | #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ | |
88 | #define ISMT_DESC_I2C 0x20 /* I2C Enable */ | |
89 | #define ISMT_DESC_INT 0x40 /* Interrupt */ | |
90 | #define ISMT_DESC_SOE 0x80 /* Stop On Error */ | |
91 | ||
92 | /* Hardware Descriptor Constants - Status Field */ | |
93 | #define ISMT_DESC_SCS 0x01 /* Success */ | |
94 | #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ | |
95 | #define ISMT_DESC_NAK 0x08 /* NAK Received */ | |
96 | #define ISMT_DESC_CRC 0x10 /* CRC Error */ | |
97 | #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ | |
98 | #define ISMT_DESC_COL 0x40 /* Collisions */ | |
99 | #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ | |
100 | ||
101 | /* Macros */ | |
102 | #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) | |
103 | ||
104 | /* iSMT General Register address offsets (SMBBAR + <addr>) */ | |
105 | #define ISMT_GR_GCTRL 0x000 /* General Control */ | |
106 | #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ | |
107 | #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ | |
108 | #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ | |
109 | #define ISMT_GR_ERRSTS 0x018 /* Error Status */ | |
110 | #define ISMT_GR_ERRINFO 0x01c /* Error Information */ | |
111 | ||
112 | /* iSMT Master Registers */ | |
113 | #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ | |
114 | #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ | |
115 | #define ISMT_MSTR_MSTS 0x10c /* Master Status */ | |
116 | #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ | |
117 | #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ | |
118 | ||
119 | /* iSMT Miscellaneous Registers */ | |
120 | #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ | |
121 | ||
122 | /* General Control Register (GCTRL) bit definitions */ | |
123 | #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ | |
124 | #define ISMT_GCTRL_KILL 0x08 /* Kill */ | |
125 | #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ | |
126 | ||
127 | /* Master Control Register (MCTRL) bit definitions */ | |
128 | #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ | |
129 | #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ | |
130 | #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ | |
131 | ||
132 | /* Master Status Register (MSTS) bit definitions */ | |
133 | #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ | |
134 | #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ | |
135 | #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ | |
136 | #define ISMT_MSTS_IP 0x01 /* In Progress */ | |
137 | ||
138 | /* Master Descriptor Size (MDS) bit definitions */ | |
139 | #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ | |
140 | ||
141 | /* SMBus PHY Global Timing Register (SPGT) bit definitions */ | |
142 | #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ | |
143 | #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ | |
144 | #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ | |
145 | #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ | |
146 | #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ | |
147 | ||
148 | ||
149 | /* MSI Control Register (MSICTL) bit definitions */ | |
150 | #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ | |
151 | ||
152 | /* iSMT Hardware Descriptor */ | |
153 | struct ismt_desc { | |
154 | u8 tgtaddr_rw; /* target address & r/w bit */ | |
155 | u8 wr_len_cmd; /* write length in bytes or a command */ | |
156 | u8 rd_len; /* read length */ | |
157 | u8 control; /* control bits */ | |
158 | u8 status; /* status bits */ | |
159 | u8 retry; /* collision retry and retry count */ | |
160 | u8 rxbytes; /* received bytes */ | |
161 | u8 txbytes; /* transmitted bytes */ | |
162 | u32 dptr_low; /* lower 32 bit of the data pointer */ | |
163 | u32 dptr_high; /* upper 32 bit of the data pointer */ | |
164 | } __packed; | |
165 | ||
166 | struct ismt_priv { | |
167 | struct i2c_adapter adapter; | |
168 | void *smba; /* PCI BAR */ | |
169 | struct pci_dev *pci_dev; | |
170 | struct ismt_desc *hw; /* descriptor virt base addr */ | |
171 | dma_addr_t io_rng_dma; /* descriptor HW base addr */ | |
172 | u8 head; /* ring buffer head pointer */ | |
173 | struct completion cmp; /* interrupt completion */ | |
174 | u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */ | |
175 | bool using_msi; /* type of interrupt flag */ | |
176 | }; | |
177 | ||
178 | /** | |
179 | * ismt_ids - PCI device IDs supported by this driver | |
180 | */ | |
392debf1 | 181 | static const struct pci_device_id ismt_ids[] = { |
13f35ac1 NH |
182 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, |
183 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, | |
488b9269 | 184 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, |
13f35ac1 NH |
185 | { 0, } |
186 | }; | |
187 | ||
188 | MODULE_DEVICE_TABLE(pci, ismt_ids); | |
189 | ||
190 | /* Bus speed control bits for slow debuggers - refer to the docs for usage */ | |
191 | static unsigned int bus_speed; | |
192 | module_param(bus_speed, uint, S_IRUGO); | |
193 | MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); | |
194 | ||
195 | /** | |
196 | * __ismt_desc_dump() - dump the contents of a specific descriptor | |
197 | */ | |
198 | static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) | |
199 | { | |
200 | ||
201 | dev_dbg(dev, "Descriptor struct: %p\n", desc); | |
202 | dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); | |
203 | dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); | |
204 | dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); | |
205 | dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); | |
206 | dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); | |
207 | dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); | |
208 | dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); | |
209 | dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); | |
210 | dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); | |
211 | dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); | |
212 | } | |
213 | /** | |
214 | * ismt_desc_dump() - dump the contents of a descriptor for debug purposes | |
215 | * @priv: iSMT private data | |
216 | */ | |
217 | static void ismt_desc_dump(struct ismt_priv *priv) | |
218 | { | |
219 | struct device *dev = &priv->pci_dev->dev; | |
220 | struct ismt_desc *desc = &priv->hw[priv->head]; | |
221 | ||
222 | dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); | |
223 | __ismt_desc_dump(dev, desc); | |
224 | } | |
225 | ||
226 | /** | |
227 | * ismt_gen_reg_dump() - dump the iSMT General Registers | |
228 | * @priv: iSMT private data | |
229 | */ | |
230 | static void ismt_gen_reg_dump(struct ismt_priv *priv) | |
231 | { | |
232 | struct device *dev = &priv->pci_dev->dev; | |
233 | ||
234 | dev_dbg(dev, "Dump of the iSMT General Registers\n"); | |
235 | dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", | |
236 | priv->smba + ISMT_GR_GCTRL, | |
237 | readl(priv->smba + ISMT_GR_GCTRL)); | |
238 | dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", | |
239 | priv->smba + ISMT_GR_SMTICL, | |
240 | (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); | |
241 | dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", | |
242 | priv->smba + ISMT_GR_ERRINTMSK, | |
243 | readl(priv->smba + ISMT_GR_ERRINTMSK)); | |
244 | dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", | |
245 | priv->smba + ISMT_GR_ERRAERMSK, | |
246 | readl(priv->smba + ISMT_GR_ERRAERMSK)); | |
247 | dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", | |
248 | priv->smba + ISMT_GR_ERRSTS, | |
249 | readl(priv->smba + ISMT_GR_ERRSTS)); | |
250 | dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", | |
251 | priv->smba + ISMT_GR_ERRINFO, | |
252 | readl(priv->smba + ISMT_GR_ERRINFO)); | |
253 | } | |
254 | ||
255 | /** | |
256 | * ismt_mstr_reg_dump() - dump the iSMT Master Registers | |
257 | * @priv: iSMT private data | |
258 | */ | |
259 | static void ismt_mstr_reg_dump(struct ismt_priv *priv) | |
260 | { | |
261 | struct device *dev = &priv->pci_dev->dev; | |
262 | ||
263 | dev_dbg(dev, "Dump of the iSMT Master Registers\n"); | |
264 | dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", | |
265 | priv->smba + ISMT_MSTR_MDBA, | |
266 | (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); | |
267 | dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", | |
268 | priv->smba + ISMT_MSTR_MCTRL, | |
269 | readl(priv->smba + ISMT_MSTR_MCTRL)); | |
270 | dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", | |
271 | priv->smba + ISMT_MSTR_MSTS, | |
272 | readl(priv->smba + ISMT_MSTR_MSTS)); | |
273 | dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", | |
274 | priv->smba + ISMT_MSTR_MDS, | |
275 | readl(priv->smba + ISMT_MSTR_MDS)); | |
276 | dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", | |
277 | priv->smba + ISMT_MSTR_RPOLICY, | |
278 | readl(priv->smba + ISMT_MSTR_RPOLICY)); | |
279 | dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", | |
280 | priv->smba + ISMT_SPGT, | |
281 | readl(priv->smba + ISMT_SPGT)); | |
282 | } | |
283 | ||
284 | /** | |
285 | * ismt_submit_desc() - add a descriptor to the ring | |
286 | * @priv: iSMT private data | |
287 | */ | |
288 | static void ismt_submit_desc(struct ismt_priv *priv) | |
289 | { | |
290 | uint fmhp; | |
291 | uint val; | |
292 | ||
293 | ismt_desc_dump(priv); | |
294 | ismt_gen_reg_dump(priv); | |
295 | ismt_mstr_reg_dump(priv); | |
296 | ||
297 | /* Set the FMHP (Firmware Master Head Pointer)*/ | |
298 | fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; | |
299 | val = readl(priv->smba + ISMT_MSTR_MCTRL); | |
300 | writel((val & ~ISMT_MCTRL_FMHP) | fmhp, | |
301 | priv->smba + ISMT_MSTR_MCTRL); | |
302 | ||
303 | /* Set the start bit */ | |
304 | val = readl(priv->smba + ISMT_MSTR_MCTRL); | |
305 | writel(val | ISMT_MCTRL_SS, | |
306 | priv->smba + ISMT_MSTR_MCTRL); | |
307 | } | |
308 | ||
309 | /** | |
310 | * ismt_process_desc() - handle the completion of the descriptor | |
311 | * @desc: the iSMT hardware descriptor | |
312 | * @data: data buffer from the upper layer | |
313 | * @priv: ismt_priv struct holding our dma buffer | |
314 | * @size: SMBus transaction type | |
315 | * @read_write: flag to indicate if this is a read or write | |
316 | */ | |
317 | static int ismt_process_desc(const struct ismt_desc *desc, | |
318 | union i2c_smbus_data *data, | |
319 | struct ismt_priv *priv, int size, | |
320 | char read_write) | |
321 | { | |
322 | u8 *dma_buffer = priv->dma_buffer; | |
323 | ||
324 | dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); | |
325 | __ismt_desc_dump(&priv->pci_dev->dev, desc); | |
326 | ||
327 | if (desc->status & ISMT_DESC_SCS) { | |
328 | if (read_write == I2C_SMBUS_WRITE && | |
329 | size != I2C_SMBUS_PROC_CALL) | |
330 | return 0; | |
331 | ||
332 | switch (size) { | |
333 | case I2C_SMBUS_BYTE: | |
334 | case I2C_SMBUS_BYTE_DATA: | |
335 | data->byte = dma_buffer[0]; | |
336 | break; | |
337 | case I2C_SMBUS_WORD_DATA: | |
338 | case I2C_SMBUS_PROC_CALL: | |
339 | data->word = dma_buffer[0] | (dma_buffer[1] << 8); | |
340 | break; | |
341 | case I2C_SMBUS_BLOCK_DATA: | |
001cebf0 | 342 | case I2C_SMBUS_I2C_BLOCK_DATA: |
13f35ac1 NH |
343 | memcpy(&data->block[1], dma_buffer, desc->rxbytes); |
344 | data->block[0] = desc->rxbytes; | |
345 | break; | |
346 | } | |
347 | return 0; | |
348 | } | |
349 | ||
350 | if (likely(desc->status & ISMT_DESC_NAK)) | |
351 | return -ENXIO; | |
352 | ||
353 | if (desc->status & ISMT_DESC_CRC) | |
354 | return -EBADMSG; | |
355 | ||
356 | if (desc->status & ISMT_DESC_COL) | |
357 | return -EAGAIN; | |
358 | ||
359 | if (desc->status & ISMT_DESC_LPR) | |
360 | return -EPROTO; | |
361 | ||
362 | if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) | |
363 | return -ETIMEDOUT; | |
364 | ||
365 | return -EIO; | |
366 | } | |
367 | ||
368 | /** | |
369 | * ismt_access() - process an SMBus command | |
370 | * @adap: the i2c host adapter | |
371 | * @addr: address of the i2c/SMBus target | |
372 | * @flags: command options | |
373 | * @read_write: read from or write to device | |
374 | * @command: the i2c/SMBus command to issue | |
375 | * @size: SMBus transaction type | |
376 | * @data: read/write data buffer | |
377 | */ | |
378 | static int ismt_access(struct i2c_adapter *adap, u16 addr, | |
379 | unsigned short flags, char read_write, u8 command, | |
380 | int size, union i2c_smbus_data *data) | |
381 | { | |
382 | int ret; | |
1abdd5d9 | 383 | unsigned long time_left; |
13f35ac1 NH |
384 | dma_addr_t dma_addr = 0; /* address of the data buffer */ |
385 | u8 dma_size = 0; | |
386 | enum dma_data_direction dma_direction = 0; | |
387 | struct ismt_desc *desc; | |
388 | struct ismt_priv *priv = i2c_get_adapdata(adap); | |
389 | struct device *dev = &priv->pci_dev->dev; | |
390 | ||
391 | desc = &priv->hw[priv->head]; | |
bf416910 JR |
392 | |
393 | /* Initialize the DMA buffer */ | |
394 | memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer)); | |
13f35ac1 NH |
395 | |
396 | /* Initialize the descriptor */ | |
397 | memset(desc, 0, sizeof(struct ismt_desc)); | |
398 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); | |
399 | ||
400 | /* Initialize common control bits */ | |
401 | if (likely(priv->using_msi)) | |
402 | desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; | |
403 | else | |
404 | desc->control = ISMT_DESC_FAIR; | |
405 | ||
406 | if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) | |
407 | && (size != I2C_SMBUS_I2C_BLOCK_DATA)) | |
408 | desc->control |= ISMT_DESC_PEC; | |
409 | ||
410 | switch (size) { | |
411 | case I2C_SMBUS_QUICK: | |
412 | dev_dbg(dev, "I2C_SMBUS_QUICK\n"); | |
413 | break; | |
414 | ||
415 | case I2C_SMBUS_BYTE: | |
416 | if (read_write == I2C_SMBUS_WRITE) { | |
417 | /* | |
418 | * Send Byte | |
419 | * The command field contains the write data | |
420 | */ | |
421 | dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); | |
422 | desc->control |= ISMT_DESC_CWRL; | |
423 | desc->wr_len_cmd = command; | |
424 | } else { | |
425 | /* Receive Byte */ | |
426 | dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); | |
427 | dma_size = 1; | |
428 | dma_direction = DMA_FROM_DEVICE; | |
429 | desc->rd_len = 1; | |
430 | } | |
431 | break; | |
432 | ||
433 | case I2C_SMBUS_BYTE_DATA: | |
434 | if (read_write == I2C_SMBUS_WRITE) { | |
435 | /* | |
436 | * Write Byte | |
437 | * Command plus 1 data byte | |
438 | */ | |
439 | dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); | |
440 | desc->wr_len_cmd = 2; | |
441 | dma_size = 2; | |
442 | dma_direction = DMA_TO_DEVICE; | |
443 | priv->dma_buffer[0] = command; | |
444 | priv->dma_buffer[1] = data->byte; | |
445 | } else { | |
446 | /* Read Byte */ | |
447 | dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); | |
448 | desc->control |= ISMT_DESC_CWRL; | |
449 | desc->wr_len_cmd = command; | |
450 | desc->rd_len = 1; | |
451 | dma_size = 1; | |
452 | dma_direction = DMA_FROM_DEVICE; | |
453 | } | |
454 | break; | |
455 | ||
456 | case I2C_SMBUS_WORD_DATA: | |
457 | if (read_write == I2C_SMBUS_WRITE) { | |
458 | /* Write Word */ | |
459 | dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); | |
460 | desc->wr_len_cmd = 3; | |
461 | dma_size = 3; | |
462 | dma_direction = DMA_TO_DEVICE; | |
463 | priv->dma_buffer[0] = command; | |
464 | priv->dma_buffer[1] = data->word & 0xff; | |
465 | priv->dma_buffer[2] = data->word >> 8; | |
466 | } else { | |
467 | /* Read Word */ | |
468 | dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); | |
469 | desc->wr_len_cmd = command; | |
470 | desc->control |= ISMT_DESC_CWRL; | |
471 | desc->rd_len = 2; | |
472 | dma_size = 2; | |
473 | dma_direction = DMA_FROM_DEVICE; | |
474 | } | |
475 | break; | |
476 | ||
477 | case I2C_SMBUS_PROC_CALL: | |
478 | dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); | |
479 | desc->wr_len_cmd = 3; | |
480 | desc->rd_len = 2; | |
481 | dma_size = 3; | |
482 | dma_direction = DMA_BIDIRECTIONAL; | |
483 | priv->dma_buffer[0] = command; | |
484 | priv->dma_buffer[1] = data->word & 0xff; | |
485 | priv->dma_buffer[2] = data->word >> 8; | |
486 | break; | |
487 | ||
488 | case I2C_SMBUS_BLOCK_DATA: | |
489 | if (read_write == I2C_SMBUS_WRITE) { | |
490 | /* Block Write */ | |
491 | dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); | |
492 | dma_size = data->block[0] + 1; | |
493 | dma_direction = DMA_TO_DEVICE; | |
494 | desc->wr_len_cmd = dma_size; | |
495 | desc->control |= ISMT_DESC_BLK; | |
496 | priv->dma_buffer[0] = command; | |
979bbf7b | 497 | memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1); |
13f35ac1 NH |
498 | } else { |
499 | /* Block Read */ | |
500 | dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); | |
501 | dma_size = I2C_SMBUS_BLOCK_MAX; | |
502 | dma_direction = DMA_FROM_DEVICE; | |
503 | desc->rd_len = dma_size; | |
504 | desc->wr_len_cmd = command; | |
505 | desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); | |
506 | } | |
507 | break; | |
508 | ||
001cebf0 | 509 | case I2C_SMBUS_I2C_BLOCK_DATA: |
510 | /* Make sure the length is valid */ | |
511 | if (data->block[0] < 1) | |
512 | data->block[0] = 1; | |
513 | ||
514 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
515 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
516 | ||
517 | if (read_write == I2C_SMBUS_WRITE) { | |
518 | /* i2c Block Write */ | |
519 | dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n"); | |
520 | dma_size = data->block[0] + 1; | |
521 | dma_direction = DMA_TO_DEVICE; | |
522 | desc->wr_len_cmd = dma_size; | |
523 | desc->control |= ISMT_DESC_I2C; | |
524 | priv->dma_buffer[0] = command; | |
979bbf7b | 525 | memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1); |
001cebf0 | 526 | } else { |
527 | /* i2c Block Read */ | |
528 | dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n"); | |
529 | dma_size = data->block[0]; | |
530 | dma_direction = DMA_FROM_DEVICE; | |
531 | desc->rd_len = dma_size; | |
532 | desc->wr_len_cmd = command; | |
533 | desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL); | |
534 | /* | |
535 | * Per the "Table 15-15. I2C Commands", | |
536 | * in the External Design Specification (EDS), | |
537 | * (Document Number: 508084, Revision: 2.0), | |
538 | * the _rw bit must be 0 | |
539 | */ | |
540 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0); | |
541 | } | |
542 | break; | |
543 | ||
13f35ac1 NH |
544 | default: |
545 | dev_err(dev, "Unsupported transaction %d\n", | |
546 | size); | |
547 | return -EOPNOTSUPP; | |
548 | } | |
549 | ||
550 | /* map the data buffer */ | |
551 | if (dma_size != 0) { | |
552 | dev_dbg(dev, " dev=%p\n", dev); | |
553 | dev_dbg(dev, " data=%p\n", data); | |
554 | dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer); | |
555 | dev_dbg(dev, " dma_size=%d\n", dma_size); | |
556 | dev_dbg(dev, " dma_direction=%d\n", dma_direction); | |
557 | ||
558 | dma_addr = dma_map_single(dev, | |
559 | priv->dma_buffer, | |
560 | dma_size, | |
561 | dma_direction); | |
562 | ||
563 | if (dma_mapping_error(dev, dma_addr)) { | |
564 | dev_err(dev, "Error in mapping dma buffer %p\n", | |
565 | priv->dma_buffer); | |
566 | return -EIO; | |
567 | } | |
568 | ||
569 | dev_dbg(dev, " dma_addr = 0x%016llX\n", | |
724d5eda | 570 | (unsigned long long)dma_addr); |
13f35ac1 NH |
571 | |
572 | desc->dptr_low = lower_32_bits(dma_addr); | |
573 | desc->dptr_high = upper_32_bits(dma_addr); | |
574 | } | |
575 | ||
16735d02 | 576 | reinit_completion(&priv->cmp); |
13f35ac1 NH |
577 | |
578 | /* Add the descriptor */ | |
579 | ismt_submit_desc(priv); | |
580 | ||
581 | /* Now we wait for interrupt completion, 1s */ | |
1abdd5d9 | 582 | time_left = wait_for_completion_timeout(&priv->cmp, HZ*1); |
13f35ac1 NH |
583 | |
584 | /* unmap the data buffer */ | |
585 | if (dma_size != 0) | |
586 | dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction); | |
587 | ||
1abdd5d9 | 588 | if (unlikely(!time_left)) { |
13f35ac1 NH |
589 | dev_err(dev, "completion wait timed out\n"); |
590 | ret = -ETIMEDOUT; | |
591 | goto out; | |
592 | } | |
593 | ||
594 | /* do any post processing of the descriptor here */ | |
595 | ret = ismt_process_desc(desc, data, priv, size, read_write); | |
596 | ||
597 | out: | |
598 | /* Update the ring pointer */ | |
599 | priv->head++; | |
600 | priv->head %= ISMT_DESC_ENTRIES; | |
601 | ||
602 | return ret; | |
603 | } | |
604 | ||
605 | /** | |
606 | * ismt_func() - report which i2c commands are supported by this adapter | |
607 | * @adap: the i2c host adapter | |
608 | */ | |
609 | static u32 ismt_func(struct i2c_adapter *adap) | |
610 | { | |
611 | return I2C_FUNC_SMBUS_QUICK | | |
612 | I2C_FUNC_SMBUS_BYTE | | |
613 | I2C_FUNC_SMBUS_BYTE_DATA | | |
614 | I2C_FUNC_SMBUS_WORD_DATA | | |
615 | I2C_FUNC_SMBUS_PROC_CALL | | |
616 | I2C_FUNC_SMBUS_BLOCK_DATA | | |
001cebf0 | 617 | I2C_FUNC_SMBUS_I2C_BLOCK | |
13f35ac1 NH |
618 | I2C_FUNC_SMBUS_PEC; |
619 | } | |
620 | ||
621 | /** | |
622 | * smbus_algorithm - the adapter algorithm and supported functionality | |
623 | * @smbus_xfer: the adapter algorithm | |
624 | * @functionality: functionality supported by the adapter | |
625 | */ | |
626 | static const struct i2c_algorithm smbus_algorithm = { | |
627 | .smbus_xfer = ismt_access, | |
628 | .functionality = ismt_func, | |
629 | }; | |
630 | ||
631 | /** | |
632 | * ismt_handle_isr() - interrupt handler bottom half | |
633 | * @priv: iSMT private data | |
634 | */ | |
635 | static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) | |
636 | { | |
637 | complete(&priv->cmp); | |
638 | ||
639 | return IRQ_HANDLED; | |
640 | } | |
641 | ||
642 | ||
643 | /** | |
644 | * ismt_do_interrupt() - IRQ interrupt handler | |
645 | * @vec: interrupt vector | |
646 | * @data: iSMT private data | |
647 | */ | |
648 | static irqreturn_t ismt_do_interrupt(int vec, void *data) | |
649 | { | |
650 | u32 val; | |
651 | struct ismt_priv *priv = data; | |
652 | ||
653 | /* | |
654 | * check to see it's our interrupt, return IRQ_NONE if not ours | |
655 | * since we are sharing interrupt | |
656 | */ | |
657 | val = readl(priv->smba + ISMT_MSTR_MSTS); | |
658 | ||
659 | if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) | |
660 | return IRQ_NONE; | |
661 | else | |
662 | writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, | |
663 | priv->smba + ISMT_MSTR_MSTS); | |
664 | ||
665 | return ismt_handle_isr(priv); | |
666 | } | |
667 | ||
668 | /** | |
669 | * ismt_do_msi_interrupt() - MSI interrupt handler | |
670 | * @vec: interrupt vector | |
671 | * @data: iSMT private data | |
672 | */ | |
673 | static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) | |
674 | { | |
675 | return ismt_handle_isr(data); | |
676 | } | |
677 | ||
678 | /** | |
679 | * ismt_hw_init() - initialize the iSMT hardware | |
680 | * @priv: iSMT private data | |
681 | */ | |
682 | static void ismt_hw_init(struct ismt_priv *priv) | |
683 | { | |
684 | u32 val; | |
685 | struct device *dev = &priv->pci_dev->dev; | |
686 | ||
687 | /* initialize the Master Descriptor Base Address (MDBA) */ | |
688 | writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); | |
689 | ||
690 | /* initialize the Master Control Register (MCTRL) */ | |
691 | writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); | |
692 | ||
693 | /* initialize the Master Status Register (MSTS) */ | |
694 | writel(0, priv->smba + ISMT_MSTR_MSTS); | |
695 | ||
696 | /* initialize the Master Descriptor Size (MDS) */ | |
697 | val = readl(priv->smba + ISMT_MSTR_MDS); | |
698 | writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), | |
699 | priv->smba + ISMT_MSTR_MDS); | |
700 | ||
701 | /* | |
702 | * Set the SMBus speed (could use this for slow HW debuggers) | |
703 | */ | |
704 | ||
705 | val = readl(priv->smba + ISMT_SPGT); | |
706 | ||
707 | switch (bus_speed) { | |
708 | case 0: | |
709 | break; | |
710 | ||
711 | case 80: | |
712 | dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); | |
713 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), | |
714 | priv->smba + ISMT_SPGT); | |
715 | break; | |
716 | ||
717 | case 100: | |
718 | dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); | |
719 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), | |
720 | priv->smba + ISMT_SPGT); | |
721 | break; | |
722 | ||
723 | case 400: | |
724 | dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); | |
725 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), | |
726 | priv->smba + ISMT_SPGT); | |
727 | break; | |
728 | ||
729 | case 1000: | |
730 | dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); | |
731 | writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), | |
732 | priv->smba + ISMT_SPGT); | |
733 | break; | |
734 | ||
735 | default: | |
736 | dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); | |
737 | break; | |
738 | } | |
739 | ||
740 | val = readl(priv->smba + ISMT_SPGT); | |
741 | ||
742 | switch (val & ISMT_SPGT_SPD_MASK) { | |
743 | case ISMT_SPGT_SPD_80K: | |
744 | bus_speed = 80; | |
745 | break; | |
746 | case ISMT_SPGT_SPD_100K: | |
747 | bus_speed = 100; | |
748 | break; | |
749 | case ISMT_SPGT_SPD_400K: | |
750 | bus_speed = 400; | |
751 | break; | |
752 | case ISMT_SPGT_SPD_1M: | |
753 | bus_speed = 1000; | |
754 | break; | |
755 | } | |
756 | dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); | |
757 | } | |
758 | ||
759 | /** | |
760 | * ismt_dev_init() - initialize the iSMT data structures | |
761 | * @priv: iSMT private data | |
762 | */ | |
763 | static int ismt_dev_init(struct ismt_priv *priv) | |
764 | { | |
765 | /* allocate memory for the descriptor */ | |
766 | priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, | |
767 | (ISMT_DESC_ENTRIES | |
768 | * sizeof(struct ismt_desc)), | |
769 | &priv->io_rng_dma, | |
770 | GFP_KERNEL); | |
771 | if (!priv->hw) | |
772 | return -ENOMEM; | |
773 | ||
774 | memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc))); | |
775 | ||
776 | priv->head = 0; | |
777 | init_completion(&priv->cmp); | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
782 | /** | |
783 | * ismt_int_init() - initialize interrupts | |
784 | * @priv: iSMT private data | |
785 | */ | |
786 | static int ismt_int_init(struct ismt_priv *priv) | |
787 | { | |
788 | int err; | |
789 | ||
790 | /* Try using MSI interrupts */ | |
791 | err = pci_enable_msi(priv->pci_dev); | |
792 | if (err) { | |
793 | dev_warn(&priv->pci_dev->dev, | |
794 | "Unable to use MSI interrupts, falling back to legacy\n"); | |
795 | goto intx; | |
796 | } | |
797 | ||
798 | err = devm_request_irq(&priv->pci_dev->dev, | |
799 | priv->pci_dev->irq, | |
800 | ismt_do_msi_interrupt, | |
801 | 0, | |
802 | "ismt-msi", | |
803 | priv); | |
804 | if (err) { | |
805 | pci_disable_msi(priv->pci_dev); | |
806 | goto intx; | |
807 | } | |
808 | ||
809 | priv->using_msi = true; | |
810 | goto done; | |
811 | ||
812 | /* Try using legacy interrupts */ | |
813 | intx: | |
814 | err = devm_request_irq(&priv->pci_dev->dev, | |
815 | priv->pci_dev->irq, | |
816 | ismt_do_interrupt, | |
817 | IRQF_SHARED, | |
818 | "ismt-intx", | |
819 | priv); | |
820 | if (err) { | |
821 | dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); | |
822 | return -ENODEV; | |
823 | } | |
824 | ||
825 | priv->using_msi = false; | |
826 | ||
827 | done: | |
828 | return 0; | |
829 | } | |
830 | ||
831 | static struct pci_driver ismt_driver; | |
832 | ||
833 | /** | |
834 | * ismt_probe() - probe for iSMT devices | |
835 | * @pdev: PCI-Express device | |
836 | * @id: PCI-Express device ID | |
837 | */ | |
838 | static int | |
839 | ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
840 | { | |
841 | int err; | |
842 | struct ismt_priv *priv; | |
843 | unsigned long start, len; | |
844 | ||
845 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
846 | if (!priv) | |
847 | return -ENOMEM; | |
848 | ||
849 | pci_set_drvdata(pdev, priv); | |
850 | i2c_set_adapdata(&priv->adapter, priv); | |
851 | priv->adapter.owner = THIS_MODULE; | |
852 | ||
853 | priv->adapter.class = I2C_CLASS_HWMON; | |
854 | ||
855 | priv->adapter.algo = &smbus_algorithm; | |
856 | ||
857 | /* set up the sysfs linkage to our parent device */ | |
858 | priv->adapter.dev.parent = &pdev->dev; | |
859 | ||
860 | /* number of retries on lost arbitration */ | |
861 | priv->adapter.retries = ISMT_MAX_RETRIES; | |
862 | ||
863 | priv->pci_dev = pdev; | |
864 | ||
865 | err = pcim_enable_device(pdev); | |
866 | if (err) { | |
867 | dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
868 | err); | |
869 | return err; | |
870 | } | |
871 | ||
872 | /* enable bus mastering */ | |
873 | pci_set_master(pdev); | |
874 | ||
875 | /* Determine the address of the SMBus area */ | |
876 | start = pci_resource_start(pdev, SMBBAR); | |
877 | len = pci_resource_len(pdev, SMBBAR); | |
878 | if (!start || !len) { | |
879 | dev_err(&pdev->dev, | |
880 | "SMBus base address uninitialized, upgrade BIOS\n"); | |
881 | return -ENODEV; | |
882 | } | |
883 | ||
884 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), | |
885 | "SMBus iSMT adapter at %lx", start); | |
886 | ||
887 | dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); | |
888 | dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); | |
889 | ||
890 | err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); | |
891 | if (err) { | |
892 | dev_err(&pdev->dev, "ACPI resource conflict!\n"); | |
893 | return err; | |
894 | } | |
895 | ||
896 | err = pci_request_region(pdev, SMBBAR, ismt_driver.name); | |
897 | if (err) { | |
898 | dev_err(&pdev->dev, | |
899 | "Failed to request SMBus region 0x%lx-0x%lx\n", | |
900 | start, start + len); | |
901 | return err; | |
902 | } | |
903 | ||
904 | priv->smba = pcim_iomap(pdev, SMBBAR, len); | |
905 | if (!priv->smba) { | |
906 | dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); | |
907 | err = -ENODEV; | |
908 | goto fail; | |
909 | } | |
910 | ||
911 | if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || | |
912 | (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { | |
913 | if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || | |
914 | (pci_set_consistent_dma_mask(pdev, | |
915 | DMA_BIT_MASK(32)) != 0)) { | |
916 | dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", | |
917 | pdev); | |
370257b2 | 918 | err = -ENODEV; |
13f35ac1 NH |
919 | goto fail; |
920 | } | |
921 | } | |
922 | ||
923 | err = ismt_dev_init(priv); | |
924 | if (err) | |
925 | goto fail; | |
926 | ||
927 | ismt_hw_init(priv); | |
928 | ||
929 | err = ismt_int_init(priv); | |
930 | if (err) | |
931 | goto fail; | |
932 | ||
933 | err = i2c_add_adapter(&priv->adapter); | |
934 | if (err) { | |
935 | dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n"); | |
936 | err = -ENODEV; | |
937 | goto fail; | |
938 | } | |
939 | return 0; | |
940 | ||
941 | fail: | |
942 | pci_release_region(pdev, SMBBAR); | |
943 | return err; | |
944 | } | |
945 | ||
946 | /** | |
947 | * ismt_remove() - release driver resources | |
948 | * @pdev: PCI-Express device | |
949 | */ | |
950 | static void ismt_remove(struct pci_dev *pdev) | |
951 | { | |
952 | struct ismt_priv *priv = pci_get_drvdata(pdev); | |
953 | ||
954 | i2c_del_adapter(&priv->adapter); | |
955 | pci_release_region(pdev, SMBBAR); | |
956 | } | |
957 | ||
958 | /** | |
959 | * ismt_suspend() - place the device in suspend | |
960 | * @pdev: PCI-Express device | |
961 | * @mesg: PM message | |
962 | */ | |
963 | #ifdef CONFIG_PM | |
964 | static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
965 | { | |
966 | pci_save_state(pdev); | |
967 | pci_set_power_state(pdev, pci_choose_state(pdev, mesg)); | |
968 | return 0; | |
969 | } | |
970 | ||
971 | /** | |
972 | * ismt_resume() - PCI resume code | |
973 | * @pdev: PCI-Express device | |
974 | */ | |
975 | static int ismt_resume(struct pci_dev *pdev) | |
976 | { | |
977 | pci_set_power_state(pdev, PCI_D0); | |
978 | pci_restore_state(pdev); | |
979 | return pci_enable_device(pdev); | |
980 | } | |
981 | ||
982 | #else | |
983 | ||
984 | #define ismt_suspend NULL | |
985 | #define ismt_resume NULL | |
986 | ||
987 | #endif | |
988 | ||
989 | static struct pci_driver ismt_driver = { | |
990 | .name = "ismt_smbus", | |
991 | .id_table = ismt_ids, | |
992 | .probe = ismt_probe, | |
993 | .remove = ismt_remove, | |
994 | .suspend = ismt_suspend, | |
995 | .resume = ismt_resume, | |
996 | }; | |
997 | ||
998 | module_pci_driver(ismt_driver); | |
999 | ||
1000 | MODULE_LICENSE("Dual BSD/GPL"); | |
1001 | MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); | |
1002 | MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); |