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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzi...
[linux-2.6-block.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
6df263cf 15#include <linux/io.h>
d24ecfcc
BW		 16#include <linux/mm.h>
17#include <linux/timer.h>
18#include <linux/spinlock.h>
19#include <linux/completion.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22
23#include <asm/blackfin.h>
74d362e0 24#include <asm/portmux.h>
d24ecfcc
BW		 25#include <asm/irq.h>
26
27#define POLL_TIMEOUT (2 * HZ)
28
29/* SMBus mode*/
4dd39bb1
SZ		 30#define TWI_I2C_MODE_STANDARD 1
31#define TWI_I2C_MODE_STANDARDSUB 2
32#define TWI_I2C_MODE_COMBINED 3
33#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 34
35struct bfin_twi_iface {
d24ecfcc
BW		 36 int irq;
37 spinlock_t lock;
38 char read_write;
39 u8 command;
40 u8 *transPtr;
41 int readNum;
42 int writeNum;
43 int cur_mode;
44 int manual_stop;
45 int result;
46 int timeout_count;
47 struct timer_list timeout_timer;
48 struct i2c_adapter adap;
49 struct completion complete;
4dd39bb1
SZ		 50 struct i2c_msg *pmsg;
51 int msg_num;
52 int cur_msg;
958585f5
MH		 53 u16 saved_clkdiv;
54 u16 saved_control;
aa3d0209 55 void __iomem *regs_base;
d24ecfcc
BW		 56};
57
aa3d0209
BW		 58
59#define DEFINE_TWI_REG(reg, off) \
60static inline u16 read_##reg(struct bfin_twi_iface *iface) \
61 { return bfin_read16(iface->regs_base + (off)); } \
62static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
63 { bfin_write16(iface->regs_base + (off), v); }
64
65DEFINE_TWI_REG(CLKDIV, 0x00)
66DEFINE_TWI_REG(CONTROL, 0x04)
67DEFINE_TWI_REG(SLAVE_CTL, 0x08)
68DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
69DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
70DEFINE_TWI_REG(MASTER_CTL, 0x14)
71DEFINE_TWI_REG(MASTER_STAT, 0x18)
72DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
73DEFINE_TWI_REG(INT_STAT, 0x20)
74DEFINE_TWI_REG(INT_MASK, 0x24)
75DEFINE_TWI_REG(FIFO_CTL, 0x28)
76DEFINE_TWI_REG(FIFO_STAT, 0x2C)
77DEFINE_TWI_REG(XMT_DATA8, 0x80)
78DEFINE_TWI_REG(XMT_DATA16, 0x84)
79DEFINE_TWI_REG(RCV_DATA8, 0x88)
80DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 81
74d362e0
BW		 82static const u16 pin_req[2][3] = {
83 {P_TWI0_SCL, P_TWI0_SDA, 0},
84 {P_TWI1_SCL, P_TWI1_SDA, 0},
85};
86
d24ecfcc
BW		 87static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
88{
aa3d0209
BW		 89 unsigned short twi_int_status = read_INT_STAT(iface);
90 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 91
92 if (twi_int_status & XMTSERV) {
93 /* Transmit next data */
94 if (iface->writeNum > 0) {
aa3d0209 95 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 96 iface->writeNum--;
97 }
98 /* start receive immediately after complete sending in
99 * combine mode.
100 */
4dd39bb1 101 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209
BW		 102 write_MASTER_CTL(iface,
103 read_MASTER_CTL(iface) | MDIR | RSTART);
4dd39bb1 104 else if (iface->manual_stop)
aa3d0209
BW		 105 write_MASTER_CTL(iface,
106 read_MASTER_CTL(iface) | STOP);
4dd39bb1 107 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 108 iface->cur_msg + 1 < iface->msg_num) {
109 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
110 write_MASTER_CTL(iface,
111 read_MASTER_CTL(iface) | RSTART | MDIR);
112 else
113 write_MASTER_CTL(iface,
114 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
115 }
d24ecfcc
BW		 116 SSYNC();
117 /* Clear status */
aa3d0209 118 write_INT_STAT(iface, XMTSERV);
d24ecfcc
BW		 119 SSYNC();
120 }
121 if (twi_int_status & RCVSERV) {
122 if (iface->readNum > 0) {
123 /* Receive next data */
aa3d0209 124 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 125 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
126 /* Change combine mode into sub mode after
127 * read first data.
128 */
129 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
130 /* Get read number from first byte in block
131 * combine mode.
132 */
133 if (iface->readNum == 1 && iface->manual_stop)
134 iface->readNum = *iface->transPtr + 1;
135 }
136 iface->transPtr++;
137 iface->readNum--;
138 } else if (iface->manual_stop) {
aa3d0209
BW		 139 write_MASTER_CTL(iface,
140 read_MASTER_CTL(iface) | STOP);
d24ecfcc 141 SSYNC();
4dd39bb1 142 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 143 iface->cur_msg + 1 < iface->msg_num) {
144 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
145 write_MASTER_CTL(iface,
146 read_MASTER_CTL(iface) | RSTART | MDIR);
147 else
148 write_MASTER_CTL(iface,
149 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
4dd39bb1 150 SSYNC();
d24ecfcc
BW		 151 }
152 /* Clear interrupt source */
aa3d0209 153 write_INT_STAT(iface, RCVSERV);
d24ecfcc
BW		 154 SSYNC();
155 }
156 if (twi_int_status & MERR) {
aa3d0209
BW		 157 write_INT_STAT(iface, MERR);
158 write_INT_MASK(iface, 0);
159 write_MASTER_STAT(iface, 0x3e);
160 write_MASTER_CTL(iface, 0);
d24ecfcc 161 SSYNC();
4dd39bb1 162 iface->result = -EIO;
d24ecfcc
BW		 163 /* if both err and complete int stats are set, return proper
164 * results.
165 */
166 if (twi_int_status & MCOMP) {
aa3d0209
BW		 167 write_INT_STAT(iface, MCOMP);
168 write_INT_MASK(iface, 0);
169 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 170 SSYNC();
171 /* If it is a quick transfer, only address bug no data,
172 * not an err, return 1.
173 */
174 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
175 iface->result = 1;
176 /* If address not acknowledged return -1,
177 * else return 0.
178 */
179 else if (!(mast_stat & ANAK))
180 iface->result = 0;
181 }
182 complete(&iface->complete);
183 return;
184 }
185 if (twi_int_status & MCOMP) {
aa3d0209 186 write_INT_STAT(iface, MCOMP);
d24ecfcc
BW		 187 SSYNC();
188 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
189 if (iface->readNum == 0) {
190 /* set the read number to 1 and ask for manual
191 * stop in block combine mode
192 */
193 iface->readNum = 1;
194 iface->manual_stop = 1;
aa3d0209
BW		 195 write_MASTER_CTL(iface,
196 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 197 } else {
198 /* set the readd number in other
199 * combine mode.
200 */
aa3d0209
BW		 201 write_MASTER_CTL(iface,
202 (read_MASTER_CTL(iface) &
d24ecfcc 203 (~(0xff << 6))) |
aa3d0209 204 (iface->readNum << 6));
d24ecfcc
BW		 205 }
206 /* remove restart bit and enable master receive */
aa3d0209
BW		 207 write_MASTER_CTL(iface,
208 read_MASTER_CTL(iface) & ~RSTART);
d24ecfcc 209 SSYNC();
4dd39bb1
SZ		 210 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
211 iface->cur_msg+1 < iface->msg_num) {
212 iface->cur_msg++;
213 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
214 iface->writeNum = iface->readNum =
215 iface->pmsg[iface->cur_msg].len;
216 /* Set Transmit device address */
aa3d0209 217 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 218 iface->pmsg[iface->cur_msg].addr);
219 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
220 iface->read_write = I2C_SMBUS_READ;
221 else {
222 iface->read_write = I2C_SMBUS_WRITE;
223 /* Transmit first data */
224 if (iface->writeNum > 0) {
aa3d0209 225 write_XMT_DATA8(iface,
4dd39bb1
SZ		 226 *(iface->transPtr++));
227 iface->writeNum--;
228 SSYNC();
229 }
230 }
231
232 if (iface->pmsg[iface->cur_msg].len <= 255)
57a8f32e
SZ		 233 write_MASTER_CTL(iface,
234 (read_MASTER_CTL(iface) &
235 (~(0xff << 6))) |
236 (iface->pmsg[iface->cur_msg].len << 6));
4dd39bb1 237 else {
57a8f32e
SZ		 238 write_MASTER_CTL(iface,
239 (read_MASTER_CTL(iface) |
240 (0xff << 6)));
4dd39bb1
SZ		 241 iface->manual_stop = 1;
242 }
243 /* remove restart bit and enable master receive */
aa3d0209
BW		 244 write_MASTER_CTL(iface,
245 read_MASTER_CTL(iface) & ~RSTART);
4dd39bb1 246 SSYNC();
d24ecfcc
BW		 247 } else {
248 iface->result = 1;
aa3d0209
BW		 249 write_INT_MASK(iface, 0);
250 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 251 SSYNC();
252 complete(&iface->complete);
253 }
254 }
255}
256
257/* Interrupt handler */
258static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
259{
260 struct bfin_twi_iface *iface = dev_id;
261 unsigned long flags;
262
263 spin_lock_irqsave(&iface->lock, flags);
264 del_timer(&iface->timeout_timer);
265 bfin_twi_handle_interrupt(iface);
266 spin_unlock_irqrestore(&iface->lock, flags);
267 return IRQ_HANDLED;
268}
269
270static void bfin_twi_timeout(unsigned long data)
271{
272 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
273 unsigned long flags;
274
275 spin_lock_irqsave(&iface->lock, flags);
276 bfin_twi_handle_interrupt(iface);
277 if (iface->result == 0) {
278 iface->timeout_count--;
279 if (iface->timeout_count > 0) {
280 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
281 add_timer(&iface->timeout_timer);
282 } else {
283 iface->result = -1;
284 complete(&iface->complete);
285 }
286 }
287 spin_unlock_irqrestore(&iface->lock, flags);
288}
289
290/*
291 * Generic i2c master transfer entrypoint
292 */
293static int bfin_twi_master_xfer(struct i2c_adapter *adap,
294 struct i2c_msg *msgs, int num)
295{
296 struct bfin_twi_iface *iface = adap->algo_data;
297 struct i2c_msg *pmsg;
d24ecfcc
BW		 298 int rc = 0;
299
aa3d0209 300 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 301 return -ENXIO;
302
aa3d0209 303 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 304 yield();
d24ecfcc 305
4dd39bb1
SZ		 306 iface->pmsg = msgs;
307 iface->msg_num = num;
308 iface->cur_msg = 0;
d24ecfcc 309
4dd39bb1
SZ		 310 pmsg = &msgs[0];
311 if (pmsg->flags & I2C_M_TEN) {
312 dev_err(&adap->dev, "10 bits addr not supported!\n");
313 return -EINVAL;
314 }
d24ecfcc 315
4dd39bb1
SZ		 316 iface->cur_mode = TWI_I2C_MODE_REPEAT;
317 iface->manual_stop = 0;
318 iface->transPtr = pmsg->buf;
319 iface->writeNum = iface->readNum = pmsg->len;
320 iface->result = 0;
321 iface->timeout_count = 10;
afc13b76 322 init_completion(&(iface->complete));
4dd39bb1 323 /* Set Transmit device address */
aa3d0209 324 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 325
326 /* FIFO Initiation. Data in FIFO should be
327 * discarded before start a new operation.
328 */
aa3d0209 329 write_FIFO_CTL(iface, 0x3);
4dd39bb1 330 SSYNC();
aa3d0209 331 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 332 SSYNC();
333
334 if (pmsg->flags & I2C_M_RD)
335 iface->read_write = I2C_SMBUS_READ;
336 else {
337 iface->read_write = I2C_SMBUS_WRITE;
338 /* Transmit first data */
339 if (iface->writeNum > 0) {
aa3d0209 340 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 341 iface->writeNum--;
342 SSYNC();
d24ecfcc 343 }
4dd39bb1 344 }
d24ecfcc 345
4dd39bb1 346 /* clear int stat */
aa3d0209 347 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 348
4dd39bb1 349 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 350 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 351 SSYNC();
d24ecfcc 352
4dd39bb1 353 if (pmsg->len <= 255)
aa3d0209 354 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 355 else {
aa3d0209 356 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 357 iface->manual_stop = 1;
358 }
d24ecfcc 359
4dd39bb1
SZ		 360 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
361 add_timer(&iface->timeout_timer);
d24ecfcc 362
4dd39bb1 363 /* Master enable */
aa3d0209 364 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
4dd39bb1
SZ		 365 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
366 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
367 SSYNC();
368
369 wait_for_completion(&iface->complete);
370
371 rc = iface->result;
d24ecfcc 372
4dd39bb1
SZ		 373 if (rc == 1)
374 return num;
375 else
376 return rc;
d24ecfcc
BW		 377}
378
379/*
380 * SMBus type transfer entrypoint
381 */
382
383int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
384 unsigned short flags, char read_write,
385 u8 command, int size, union i2c_smbus_data *data)
386{
387 struct bfin_twi_iface *iface = adap->algo_data;
388 int rc = 0;
389
aa3d0209 390 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 391 return -ENXIO;
392
aa3d0209 393 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 394 yield();
d24ecfcc
BW		 395
396 iface->writeNum = 0;
397 iface->readNum = 0;
398
399 /* Prepare datas & select mode */
400 switch (size) {
401 case I2C_SMBUS_QUICK:
402 iface->transPtr = NULL;
403 iface->cur_mode = TWI_I2C_MODE_STANDARD;
404 break;
405 case I2C_SMBUS_BYTE:
406 if (data == NULL)
407 iface->transPtr = NULL;
408 else {
409 if (read_write == I2C_SMBUS_READ)
410 iface->readNum = 1;
411 else
412 iface->writeNum = 1;
413 iface->transPtr = &data->byte;
414 }
415 iface->cur_mode = TWI_I2C_MODE_STANDARD;
416 break;
417 case I2C_SMBUS_BYTE_DATA:
418 if (read_write == I2C_SMBUS_READ) {
419 iface->readNum = 1;
420 iface->cur_mode = TWI_I2C_MODE_COMBINED;
421 } else {
422 iface->writeNum = 1;
423 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
424 }
425 iface->transPtr = &data->byte;
426 break;
427 case I2C_SMBUS_WORD_DATA:
428 if (read_write == I2C_SMBUS_READ) {
429 iface->readNum = 2;
430 iface->cur_mode = TWI_I2C_MODE_COMBINED;
431 } else {
432 iface->writeNum = 2;
433 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
434 }
435 iface->transPtr = (u8 *)&data->word;
436 break;
437 case I2C_SMBUS_PROC_CALL:
438 iface->writeNum = 2;
439 iface->readNum = 2;
440 iface->cur_mode = TWI_I2C_MODE_COMBINED;
441 iface->transPtr = (u8 *)&data->word;
442 break;
443 case I2C_SMBUS_BLOCK_DATA:
444 if (read_write == I2C_SMBUS_READ) {
445 iface->readNum = 0;
446 iface->cur_mode = TWI_I2C_MODE_COMBINED;
447 } else {
448 iface->writeNum = data->block[0] + 1;
449 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
450 }
451 iface->transPtr = data->block;
452 break;
e0cd2dd5
MH		 453 case I2C_SMBUS_I2C_BLOCK_DATA:
454 if (read_write == I2C_SMBUS_READ) {
455 iface->readNum = data->block[0];
456 iface->cur_mode = TWI_I2C_MODE_COMBINED;
457 } else {
458 iface->writeNum = data->block[0];
459 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
460 }
461 iface->transPtr = (u8 *)&data->block[1];
462 break;
d24ecfcc
BW		 463 default:
464 return -1;
465 }
466
467 iface->result = 0;
468 iface->manual_stop = 0;
469 iface->read_write = read_write;
470 iface->command = command;
471 iface->timeout_count = 10;
afc13b76 472 init_completion(&(iface->complete));
d24ecfcc
BW		 473
474 /* FIFO Initiation. Data in FIFO should be discarded before
475 * start a new operation.
476 */
aa3d0209 477 write_FIFO_CTL(iface, 0x3);
d24ecfcc 478 SSYNC();
aa3d0209 479 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 480
481 /* clear int stat */
aa3d0209 482 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 483
484 /* Set Transmit device address */
aa3d0209 485 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 486 SSYNC();
487
488 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
489 add_timer(&iface->timeout_timer);
490
491 switch (iface->cur_mode) {
492 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 493 write_XMT_DATA8(iface, iface->command);
494 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 495 ((iface->read_write == I2C_SMBUS_READ) ?
496 RCVSERV : XMTSERV));
497 SSYNC();
498
499 if (iface->writeNum + 1 <= 255)
aa3d0209 500 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 501 else {
aa3d0209 502 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 503 iface->manual_stop = 1;
504 }
505 /* Master enable */
aa3d0209 506 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 507 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
508 break;
509 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 510 write_XMT_DATA8(iface, iface->command);
511 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 512 SSYNC();
513
514 if (iface->writeNum > 0)
aa3d0209 515 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 516 else
aa3d0209 517 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 518 /* Master enable */
aa3d0209 519 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 520 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
521 break;
522 default:
aa3d0209 523 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 524 if (size != I2C_SMBUS_QUICK) {
525 /* Don't access xmit data register when this is a
526 * read operation.
527 */
528 if (iface->read_write != I2C_SMBUS_READ) {
529 if (iface->writeNum > 0) {
aa3d0209
BW		 530 write_XMT_DATA8(iface,
531 *(iface->transPtr++));
d24ecfcc 532 if (iface->writeNum <= 255)
aa3d0209
BW		 533 write_MASTER_CTL(iface,
534 iface->writeNum << 6);
d24ecfcc 535 else {
aa3d0209
BW		 536 write_MASTER_CTL(iface,
537 0xff << 6);
d24ecfcc
BW		 538 iface->manual_stop = 1;
539 }
540 iface->writeNum--;
541 } else {
aa3d0209
BW		 542 write_XMT_DATA8(iface, iface->command);
543 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 544 }
545 } else {
546 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 547 write_MASTER_CTL(iface,
548 iface->readNum << 6);
d24ecfcc 549 else if (iface->readNum > 255) {
aa3d0209 550 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 551 iface->manual_stop = 1;
552 } else {
553 del_timer(&iface->timeout_timer);
554 break;
555 }
556 }
557 }
aa3d0209 558 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 559 ((iface->read_write == I2C_SMBUS_READ) ?
560 RCVSERV : XMTSERV));
561 SSYNC();
562
563 /* Master enable */
aa3d0209 564 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 565 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
566 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
567 break;
568 }
569 SSYNC();
570
571 wait_for_completion(&iface->complete);
572
573 rc = (iface->result >= 0) ? 0 : -1;
574
d24ecfcc
BW		 575 return rc;
576}
577
578/*
579 * Return what the adapter supports
580 */
581static u32 bfin_twi_functionality(struct i2c_adapter *adap)
582{
583 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
584 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
585 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
e0cd2dd5 586 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
d24ecfcc
BW		 587}
588
d24ecfcc
BW		 589static struct i2c_algorithm bfin_twi_algorithm = {
590 .master_xfer = bfin_twi_master_xfer,
591 .smbus_xfer = bfin_twi_smbus_xfer,
592 .functionality = bfin_twi_functionality,
593};
594
958585f5 595static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
d24ecfcc 596{
958585f5
MH		 597 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
598
599 iface->saved_clkdiv = read_CLKDIV(iface);
600 iface->saved_control = read_CONTROL(iface);
601
602 free_irq(iface->irq, iface);
d24ecfcc
BW		 603
604 /* Disable TWI */
958585f5 605 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
d24ecfcc
BW		 606
607 return 0;
608}
609
958585f5 610static int i2c_bfin_twi_resume(struct platform_device *pdev)
d24ecfcc 611{
958585f5 612 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
d24ecfcc 613
958585f5
MH		 614 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
615 IRQF_DISABLED, pdev->name, iface);
616 if (rc) {
617 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
618 return -ENODEV;
619 }
620
621 /* Resume TWI interface clock as specified */
622 write_CLKDIV(iface, iface->saved_clkdiv);
623
624 /* Resume TWI */
625 write_CONTROL(iface, iface->saved_control);
d24ecfcc
BW		 626
627 return 0;
628}
629
aa3d0209 630static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 631{
aa3d0209 632 struct bfin_twi_iface *iface;
d24ecfcc 633 struct i2c_adapter *p_adap;
aa3d0209 634 struct resource *res;
d24ecfcc 635 int rc;
9528d1c7 636 unsigned int clkhilow;
d24ecfcc 637
aa3d0209
BW		 638 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
639 if (!iface) {
640 dev_err(&pdev->dev, "Cannot allocate memory\n");
641 rc = -ENOMEM;
642 goto out_error_nomem;
643 }
644
d24ecfcc 645 spin_lock_init(&(iface->lock));
aa3d0209
BW		 646
647 /* Find and map our resources */
648 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649 if (res == NULL) {
650 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
651 rc = -ENOENT;
652 goto out_error_get_res;
653 }
654
c6ffddea 655 iface->regs_base = ioremap(res->start, resource_size(res));
aa3d0209
BW		 656 if (iface->regs_base == NULL) {
657 dev_err(&pdev->dev, "Cannot map IO\n");
658 rc = -ENXIO;
659 goto out_error_ioremap;
660 }
661
662 iface->irq = platform_get_irq(pdev, 0);
663 if (iface->irq < 0) {
664 dev_err(&pdev->dev, "No IRQ specified\n");
665 rc = -ENOENT;
666 goto out_error_no_irq;
667 }
d24ecfcc
BW		 668
669 init_timer(&(iface->timeout_timer));
670 iface->timeout_timer.function = bfin_twi_timeout;
671 iface->timeout_timer.data = (unsigned long)iface;
672
673 p_adap = &iface->adap;
aa3d0209
BW		 674 p_adap->nr = pdev->id;
675 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 676 p_adap->algo = &bfin_twi_algorithm;
677 p_adap->algo_data = iface;
e1995f65 678 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
aa3d0209 679 p_adap->dev.parent = &pdev->dev;
d24ecfcc 680
74d362e0
BW		 681 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
682 if (rc) {
683 dev_err(&pdev->dev, "Can't setup pin mux!\n");
684 goto out_error_pin_mux;
685 }
686
d24ecfcc 687 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
aa3d0209 688 IRQF_DISABLED, pdev->name, iface);
d24ecfcc 689 if (rc) {
aa3d0209
BW		 690 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
691 rc = -ENODEV;
692 goto out_error_req_irq;
d24ecfcc
BW		 693 }
694
695 /* Set TWI internal clock as 10MHz */
aa3d0209 696 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
d24ecfcc 697
9528d1c7
MH		 698 /*
699 * We will not end up with a CLKDIV=0 because no one will specify
700 * 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100)
701 */
702 clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ;
703
d24ecfcc 704 /* Set Twi interface clock as specified */
9528d1c7 705 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
d24ecfcc
BW		 706
707 /* Enable TWI */
aa3d0209 708 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 709 SSYNC();
710
991dee59 711 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 712 if (rc < 0) {
713 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
714 goto out_error_add_adapter;
715 }
716
717 platform_set_drvdata(pdev, iface);
d24ecfcc 718
fa6ad222
BW		 719 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
720 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 721
722 return 0;
723
724out_error_add_adapter:
725 free_irq(iface->irq, iface);
726out_error_req_irq:
727out_error_no_irq:
74d362e0
BW		 728 peripheral_free_list(pin_req[pdev->id]);
729out_error_pin_mux:
aa3d0209
BW		 730 iounmap(iface->regs_base);
731out_error_ioremap:
732out_error_get_res:
733 kfree(iface);
734out_error_nomem:
d24ecfcc
BW		 735 return rc;
736}
737
738static int i2c_bfin_twi_remove(struct platform_device *pdev)
739{
740 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
741
742 platform_set_drvdata(pdev, NULL);
743
744 i2c_del_adapter(&(iface->adap));
745 free_irq(iface->irq, iface);
74d362e0 746 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 747 iounmap(iface->regs_base);
748 kfree(iface);
d24ecfcc
BW		 749
750 return 0;
751}
752
753static struct platform_driver i2c_bfin_twi_driver = {
754 .probe = i2c_bfin_twi_probe,
755 .remove = i2c_bfin_twi_remove,
756 .suspend = i2c_bfin_twi_suspend,
757 .resume = i2c_bfin_twi_resume,
758 .driver = {
759 .name = "i2c-bfin-twi",
760 .owner = THIS_MODULE,
761 },
762};
763
764static int __init i2c_bfin_twi_init(void)
765{
d24ecfcc
BW		 766 return platform_driver_register(&i2c_bfin_twi_driver);
767}
768
769static void __exit i2c_bfin_twi_exit(void)
770{
771 platform_driver_unregister(&i2c_bfin_twi_driver);
772}
773
d24ecfcc
BW		 774module_init(i2c_bfin_twi_init);
775module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 776
777MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
778MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
779MODULE_LICENSE("GPL");
add8eda7 780MODULE_ALIAS("platform:i2c-bfin-twi");
Linux 6.x block layer and io_uring tree(s)