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i2c-bfin-twi: fix lost interrupts at high speeds
[linux-2.6-block.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
5a0e3ad6 15#include <linux/slab.h>
6df263cf 16#include <linux/io.h>
d24ecfcc
BW		 17#include <linux/mm.h>
18#include <linux/timer.h>
19#include <linux/spinlock.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23
24#include <asm/blackfin.h>
74d362e0 25#include <asm/portmux.h>
d24ecfcc
BW		 26#include <asm/irq.h>
27
d24ecfcc 28/* SMBus mode*/
4dd39bb1
SZ		 29#define TWI_I2C_MODE_STANDARD 1
30#define TWI_I2C_MODE_STANDARDSUB 2
31#define TWI_I2C_MODE_COMBINED 3
32#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 33
34struct bfin_twi_iface {
d24ecfcc
BW		 35 int irq;
36 spinlock_t lock;
37 char read_write;
38 u8 command;
39 u8 *transPtr;
40 int readNum;
41 int writeNum;
42 int cur_mode;
43 int manual_stop;
44 int result;
d24ecfcc
BW		 45 struct i2c_adapter adap;
46 struct completion complete;
4dd39bb1
SZ		 47 struct i2c_msg *pmsg;
48 int msg_num;
49 int cur_msg;
958585f5
MH		 50 u16 saved_clkdiv;
51 u16 saved_control;
aa3d0209 52 void __iomem *regs_base;
d24ecfcc
BW		 53};
54
aa3d0209
BW		 55
56#define DEFINE_TWI_REG(reg, off) \
57static inline u16 read_##reg(struct bfin_twi_iface *iface) \
58 { return bfin_read16(iface->regs_base + (off)); } \
59static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
60 { bfin_write16(iface->regs_base + (off), v); }
61
62DEFINE_TWI_REG(CLKDIV, 0x00)
63DEFINE_TWI_REG(CONTROL, 0x04)
64DEFINE_TWI_REG(SLAVE_CTL, 0x08)
65DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
66DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
67DEFINE_TWI_REG(MASTER_CTL, 0x14)
68DEFINE_TWI_REG(MASTER_STAT, 0x18)
69DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
70DEFINE_TWI_REG(INT_STAT, 0x20)
71DEFINE_TWI_REG(INT_MASK, 0x24)
72DEFINE_TWI_REG(FIFO_CTL, 0x28)
73DEFINE_TWI_REG(FIFO_STAT, 0x2C)
74DEFINE_TWI_REG(XMT_DATA8, 0x80)
75DEFINE_TWI_REG(XMT_DATA16, 0x84)
76DEFINE_TWI_REG(RCV_DATA8, 0x88)
77DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 78
74d362e0
BW		 79static const u16 pin_req[2][3] = {
80 {P_TWI0_SCL, P_TWI0_SDA, 0},
81 {P_TWI1_SCL, P_TWI1_SDA, 0},
82};
83
5481d075
SZ		 84static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
85 unsigned short twi_int_status)
d24ecfcc 86{
aa3d0209 87 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 88
89 if (twi_int_status & XMTSERV) {
90 /* Transmit next data */
91 if (iface->writeNum > 0) {
5481d075 92 SSYNC();
aa3d0209 93 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 94 iface->writeNum--;
95 }
96 /* start receive immediately after complete sending in
97 * combine mode.
98 */
4dd39bb1 99 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209
BW		 100 write_MASTER_CTL(iface,
101 read_MASTER_CTL(iface) | MDIR | RSTART);
4dd39bb1 102 else if (iface->manual_stop)
aa3d0209
BW		 103 write_MASTER_CTL(iface,
104 read_MASTER_CTL(iface) | STOP);
4dd39bb1 105 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 106 iface->cur_msg + 1 < iface->msg_num) {
107 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
108 write_MASTER_CTL(iface,
109 read_MASTER_CTL(iface) | RSTART | MDIR);
110 else
111 write_MASTER_CTL(iface,
112 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
113 }
d24ecfcc
BW		 114 }
115 if (twi_int_status & RCVSERV) {
116 if (iface->readNum > 0) {
117 /* Receive next data */
aa3d0209 118 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 119 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
120 /* Change combine mode into sub mode after
121 * read first data.
122 */
123 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
124 /* Get read number from first byte in block
125 * combine mode.
126 */
127 if (iface->readNum == 1 && iface->manual_stop)
128 iface->readNum = *iface->transPtr + 1;
129 }
130 iface->transPtr++;
131 iface->readNum--;
132 } else if (iface->manual_stop) {
aa3d0209
BW		 133 write_MASTER_CTL(iface,
134 read_MASTER_CTL(iface) | STOP);
4dd39bb1 135 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 136 iface->cur_msg + 1 < iface->msg_num) {
137 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
138 write_MASTER_CTL(iface,
139 read_MASTER_CTL(iface) | RSTART | MDIR);
140 else
141 write_MASTER_CTL(iface,
142 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
d24ecfcc 143 }
d24ecfcc
BW		 144 }
145 if (twi_int_status & MERR) {
aa3d0209
BW		 146 write_INT_MASK(iface, 0);
147 write_MASTER_STAT(iface, 0x3e);
148 write_MASTER_CTL(iface, 0);
4dd39bb1 149 iface->result = -EIO;
5cfafc18
MH		 150
151 if (mast_stat & LOSTARB)
152 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
153 if (mast_stat & ANAK)
154 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
155 if (mast_stat & DNAK)
156 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
157 if (mast_stat & BUFRDERR)
158 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
159 if (mast_stat & BUFWRERR)
160 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
161
d24ecfcc
BW		 162 /* if both err and complete int stats are set, return proper
163 * results.
164 */
165 if (twi_int_status & MCOMP) {
dd7319a5 166 /* If it is a quick transfer, only address without data,
d24ecfcc 167 * not an err, return 1.
dd7319a5 168 * If address is acknowledged return 1.
d24ecfcc 169 */
dd7319a5
SZ		 170 if ((iface->writeNum == 0 && (mast_stat & BUFRDERR))
171 || !(mast_stat & ANAK))
d24ecfcc 172 iface->result = 1;
d24ecfcc
BW		 173 }
174 complete(&iface->complete);
175 return;
176 }
177 if (twi_int_status & MCOMP) {
d24ecfcc
BW		 178 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
179 if (iface->readNum == 0) {
180 /* set the read number to 1 and ask for manual
181 * stop in block combine mode
182 */
183 iface->readNum = 1;
184 iface->manual_stop = 1;
aa3d0209
BW		 185 write_MASTER_CTL(iface,
186 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 187 } else {
188 /* set the readd number in other
189 * combine mode.
190 */
aa3d0209
BW		 191 write_MASTER_CTL(iface,
192 (read_MASTER_CTL(iface) &
d24ecfcc 193 (~(0xff << 6))) |
aa3d0209 194 (iface->readNum << 6));
d24ecfcc
BW		 195 }
196 /* remove restart bit and enable master receive */
aa3d0209
BW		 197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) & ~RSTART);
4dd39bb1
SZ		 199 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
200 iface->cur_msg+1 < iface->msg_num) {
201 iface->cur_msg++;
202 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
203 iface->writeNum = iface->readNum =
204 iface->pmsg[iface->cur_msg].len;
205 /* Set Transmit device address */
aa3d0209 206 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 207 iface->pmsg[iface->cur_msg].addr);
208 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
209 iface->read_write = I2C_SMBUS_READ;
210 else {
211 iface->read_write = I2C_SMBUS_WRITE;
212 /* Transmit first data */
213 if (iface->writeNum > 0) {
aa3d0209 214 write_XMT_DATA8(iface,
4dd39bb1
SZ		 215 *(iface->transPtr++));
216 iface->writeNum--;
4dd39bb1
SZ		 217 }
218 }
219
220 if (iface->pmsg[iface->cur_msg].len <= 255)
57a8f32e
SZ		 221 write_MASTER_CTL(iface,
222 (read_MASTER_CTL(iface) &
223 (~(0xff << 6))) |
224 (iface->pmsg[iface->cur_msg].len << 6));
4dd39bb1 225 else {
57a8f32e
SZ		 226 write_MASTER_CTL(iface,
227 (read_MASTER_CTL(iface) |
228 (0xff << 6)));
4dd39bb1
SZ		 229 iface->manual_stop = 1;
230 }
231 /* remove restart bit and enable master receive */
aa3d0209
BW		 232 write_MASTER_CTL(iface,
233 read_MASTER_CTL(iface) & ~RSTART);
d24ecfcc
BW		 234 } else {
235 iface->result = 1;
aa3d0209
BW		 236 write_INT_MASK(iface, 0);
237 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 238 }
239 }
dd7319a5 240 complete(&iface->complete);
d24ecfcc
BW		 241}
242
243/* Interrupt handler */
244static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
245{
246 struct bfin_twi_iface *iface = dev_id;
247 unsigned long flags;
5481d075 248 unsigned short twi_int_status;
d24ecfcc
BW		 249
250 spin_lock_irqsave(&iface->lock, flags);
5481d075
SZ		 251 while (1) {
252 twi_int_status = read_INT_STAT(iface);
253 if (!twi_int_status)
254 break;
255 /* Clear interrupt status */
256 write_INT_STAT(iface, twi_int_status);
257 bfin_twi_handle_interrupt(iface, twi_int_status);
258 SSYNC();
259 }
d24ecfcc
BW		 260 spin_unlock_irqrestore(&iface->lock, flags);
261 return IRQ_HANDLED;
262}
263
d24ecfcc 264/*
dd7319a5 265 * One i2c master transfer
d24ecfcc 266 */
dd7319a5 267static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
d24ecfcc
BW		 268 struct i2c_msg *msgs, int num)
269{
270 struct bfin_twi_iface *iface = adap->algo_data;
271 struct i2c_msg *pmsg;
d24ecfcc
BW		 272 int rc = 0;
273
aa3d0209 274 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 275 return -ENXIO;
276
aa3d0209 277 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 278 yield();
d24ecfcc 279
4dd39bb1
SZ		 280 iface->pmsg = msgs;
281 iface->msg_num = num;
282 iface->cur_msg = 0;
d24ecfcc 283
4dd39bb1
SZ		 284 pmsg = &msgs[0];
285 if (pmsg->flags & I2C_M_TEN) {
286 dev_err(&adap->dev, "10 bits addr not supported!\n");
287 return -EINVAL;
288 }
d24ecfcc 289
4dd39bb1
SZ		 290 iface->cur_mode = TWI_I2C_MODE_REPEAT;
291 iface->manual_stop = 0;
292 iface->transPtr = pmsg->buf;
293 iface->writeNum = iface->readNum = pmsg->len;
294 iface->result = 0;
afc13b76 295 init_completion(&(iface->complete));
4dd39bb1 296 /* Set Transmit device address */
aa3d0209 297 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 298
299 /* FIFO Initiation. Data in FIFO should be
300 * discarded before start a new operation.
301 */
aa3d0209 302 write_FIFO_CTL(iface, 0x3);
4dd39bb1 303 SSYNC();
aa3d0209 304 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 305 SSYNC();
306
307 if (pmsg->flags & I2C_M_RD)
308 iface->read_write = I2C_SMBUS_READ;
309 else {
310 iface->read_write = I2C_SMBUS_WRITE;
311 /* Transmit first data */
312 if (iface->writeNum > 0) {
aa3d0209 313 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 314 iface->writeNum--;
315 SSYNC();
d24ecfcc 316 }
4dd39bb1 317 }
d24ecfcc 318
4dd39bb1 319 /* clear int stat */
aa3d0209 320 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 321
4dd39bb1 322 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 323 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 324 SSYNC();
d24ecfcc 325
4dd39bb1 326 if (pmsg->len <= 255)
aa3d0209 327 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 328 else {
aa3d0209 329 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 330 iface->manual_stop = 1;
331 }
d24ecfcc 332
4dd39bb1 333 /* Master enable */
aa3d0209 334 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
4dd39bb1
SZ		 335 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
336 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
337 SSYNC();
338
dd7319a5
SZ		 339 while (!iface->result) {
340 if (!wait_for_completion_timeout(&iface->complete,
341 adap->timeout)) {
342 iface->result = -1;
343 dev_err(&adap->dev, "master transfer timeout\n");
344 }
345 }
d24ecfcc 346
dd7319a5
SZ		 347 if (iface->result == 1)
348 rc = iface->cur_msg + 1;
4dd39bb1 349 else
dd7319a5
SZ		 350 rc = iface->result;
351
352 return rc;
d24ecfcc
BW		 353}
354
355/*
dd7319a5 356 * Generic i2c master transfer entrypoint
d24ecfcc 357 */
dd7319a5
SZ		 358static int bfin_twi_master_xfer(struct i2c_adapter *adap,
359 struct i2c_msg *msgs, int num)
360{
361 int i, ret = 0;
d24ecfcc 362
dd7319a5
SZ		 363 for (i = 0; i < adap->retries; i++) {
364 ret = bfin_twi_do_master_xfer(adap, msgs, num);
365 if (ret > 0)
366 break;
367 }
368
369 return ret;
370}
371
372/*
373 * One I2C SMBus transfer
374 */
375int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
d24ecfcc
BW		 376 unsigned short flags, char read_write,
377 u8 command, int size, union i2c_smbus_data *data)
378{
379 struct bfin_twi_iface *iface = adap->algo_data;
380 int rc = 0;
381
aa3d0209 382 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 383 return -ENXIO;
384
aa3d0209 385 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 386 yield();
d24ecfcc
BW		 387
388 iface->writeNum = 0;
389 iface->readNum = 0;
390
391 /* Prepare datas & select mode */
392 switch (size) {
393 case I2C_SMBUS_QUICK:
394 iface->transPtr = NULL;
395 iface->cur_mode = TWI_I2C_MODE_STANDARD;
396 break;
397 case I2C_SMBUS_BYTE:
398 if (data == NULL)
399 iface->transPtr = NULL;
400 else {
401 if (read_write == I2C_SMBUS_READ)
402 iface->readNum = 1;
403 else
404 iface->writeNum = 1;
405 iface->transPtr = &data->byte;
406 }
407 iface->cur_mode = TWI_I2C_MODE_STANDARD;
408 break;
409 case I2C_SMBUS_BYTE_DATA:
410 if (read_write == I2C_SMBUS_READ) {
411 iface->readNum = 1;
412 iface->cur_mode = TWI_I2C_MODE_COMBINED;
413 } else {
414 iface->writeNum = 1;
415 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
416 }
417 iface->transPtr = &data->byte;
418 break;
419 case I2C_SMBUS_WORD_DATA:
420 if (read_write == I2C_SMBUS_READ) {
421 iface->readNum = 2;
422 iface->cur_mode = TWI_I2C_MODE_COMBINED;
423 } else {
424 iface->writeNum = 2;
425 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
426 }
427 iface->transPtr = (u8 *)&data->word;
428 break;
429 case I2C_SMBUS_PROC_CALL:
430 iface->writeNum = 2;
431 iface->readNum = 2;
432 iface->cur_mode = TWI_I2C_MODE_COMBINED;
433 iface->transPtr = (u8 *)&data->word;
434 break;
435 case I2C_SMBUS_BLOCK_DATA:
436 if (read_write == I2C_SMBUS_READ) {
437 iface->readNum = 0;
438 iface->cur_mode = TWI_I2C_MODE_COMBINED;
439 } else {
440 iface->writeNum = data->block[0] + 1;
441 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
442 }
443 iface->transPtr = data->block;
444 break;
e0cd2dd5
MH		 445 case I2C_SMBUS_I2C_BLOCK_DATA:
446 if (read_write == I2C_SMBUS_READ) {
447 iface->readNum = data->block[0];
448 iface->cur_mode = TWI_I2C_MODE_COMBINED;
449 } else {
450 iface->writeNum = data->block[0];
451 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
452 }
453 iface->transPtr = (u8 *)&data->block[1];
454 break;
d24ecfcc
BW		 455 default:
456 return -1;
457 }
458
459 iface->result = 0;
460 iface->manual_stop = 0;
461 iface->read_write = read_write;
462 iface->command = command;
afc13b76 463 init_completion(&(iface->complete));
d24ecfcc
BW		 464
465 /* FIFO Initiation. Data in FIFO should be discarded before
466 * start a new operation.
467 */
aa3d0209 468 write_FIFO_CTL(iface, 0x3);
d24ecfcc 469 SSYNC();
aa3d0209 470 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 471
472 /* clear int stat */
aa3d0209 473 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 474
475 /* Set Transmit device address */
aa3d0209 476 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 477 SSYNC();
478
d24ecfcc
BW		 479 switch (iface->cur_mode) {
480 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 481 write_XMT_DATA8(iface, iface->command);
482 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 483 ((iface->read_write == I2C_SMBUS_READ) ?
484 RCVSERV : XMTSERV));
485 SSYNC();
486
487 if (iface->writeNum + 1 <= 255)
aa3d0209 488 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 489 else {
aa3d0209 490 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 491 iface->manual_stop = 1;
492 }
493 /* Master enable */
aa3d0209 494 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 495 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
496 break;
497 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 498 write_XMT_DATA8(iface, iface->command);
499 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 500 SSYNC();
501
502 if (iface->writeNum > 0)
aa3d0209 503 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 504 else
aa3d0209 505 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 506 /* Master enable */
aa3d0209 507 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 508 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
509 break;
510 default:
aa3d0209 511 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 512 if (size != I2C_SMBUS_QUICK) {
513 /* Don't access xmit data register when this is a
514 * read operation.
515 */
516 if (iface->read_write != I2C_SMBUS_READ) {
517 if (iface->writeNum > 0) {
aa3d0209
BW		 518 write_XMT_DATA8(iface,
519 *(iface->transPtr++));
d24ecfcc 520 if (iface->writeNum <= 255)
aa3d0209
BW		 521 write_MASTER_CTL(iface,
522 iface->writeNum << 6);
d24ecfcc 523 else {
aa3d0209
BW		 524 write_MASTER_CTL(iface,
525 0xff << 6);
d24ecfcc
BW		 526 iface->manual_stop = 1;
527 }
528 iface->writeNum--;
529 } else {
aa3d0209
BW		 530 write_XMT_DATA8(iface, iface->command);
531 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 532 }
533 } else {
534 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 535 write_MASTER_CTL(iface,
536 iface->readNum << 6);
d24ecfcc 537 else if (iface->readNum > 255) {
aa3d0209 538 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc 539 iface->manual_stop = 1;
dd7319a5 540 } else
d24ecfcc 541 break;
d24ecfcc
BW		 542 }
543 }
aa3d0209 544 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 545 ((iface->read_write == I2C_SMBUS_READ) ?
546 RCVSERV : XMTSERV));
547 SSYNC();
548
549 /* Master enable */
aa3d0209 550 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 551 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
552 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
553 break;
554 }
555 SSYNC();
556
dd7319a5
SZ		 557 while (!iface->result) {
558 if (!wait_for_completion_timeout(&iface->complete,
559 adap->timeout)) {
560 iface->result = -1;
561 dev_err(&adap->dev, "smbus transfer timeout\n");
562 }
563 }
d24ecfcc
BW		 564
565 rc = (iface->result >= 0) ? 0 : -1;
566
d24ecfcc
BW		 567 return rc;
568}
569
dd7319a5
SZ		 570/*
571 * Generic I2C SMBus transfer entrypoint
572 */
573int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
574 unsigned short flags, char read_write,
575 u8 command, int size, union i2c_smbus_data *data)
576{
577 int i, ret = 0;
578
579 for (i = 0; i < adap->retries; i++) {
580 ret = bfin_twi_do_smbus_xfer(adap, addr, flags,
581 read_write, command, size, data);
582 if (ret == 0)
583 break;
584 }
585
586 return ret;
587}
588
d24ecfcc
BW		 589/*
590 * Return what the adapter supports
591 */
592static u32 bfin_twi_functionality(struct i2c_adapter *adap)
593{
594 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
595 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
596 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
e0cd2dd5 597 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
d24ecfcc
BW		 598}
599
d24ecfcc
BW		 600static struct i2c_algorithm bfin_twi_algorithm = {
601 .master_xfer = bfin_twi_master_xfer,
602 .smbus_xfer = bfin_twi_smbus_xfer,
603 .functionality = bfin_twi_functionality,
604};
605
958585f5 606static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
d24ecfcc 607{
958585f5
MH		 608 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
609
610 iface->saved_clkdiv = read_CLKDIV(iface);
611 iface->saved_control = read_CONTROL(iface);
612
613 free_irq(iface->irq, iface);
d24ecfcc
BW		 614
615 /* Disable TWI */
958585f5 616 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
d24ecfcc
BW		 617
618 return 0;
619}
620
958585f5 621static int i2c_bfin_twi_resume(struct platform_device *pdev)
d24ecfcc 622{
958585f5 623 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
d24ecfcc 624
958585f5
MH		 625 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
626 IRQF_DISABLED, pdev->name, iface);
627 if (rc) {
628 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
629 return -ENODEV;
630 }
631
632 /* Resume TWI interface clock as specified */
633 write_CLKDIV(iface, iface->saved_clkdiv);
634
635 /* Resume TWI */
636 write_CONTROL(iface, iface->saved_control);
d24ecfcc
BW		 637
638 return 0;
639}
640
aa3d0209 641static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 642{
aa3d0209 643 struct bfin_twi_iface *iface;
d24ecfcc 644 struct i2c_adapter *p_adap;
aa3d0209 645 struct resource *res;
d24ecfcc 646 int rc;
9528d1c7 647 unsigned int clkhilow;
d24ecfcc 648
aa3d0209
BW		 649 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
650 if (!iface) {
651 dev_err(&pdev->dev, "Cannot allocate memory\n");
652 rc = -ENOMEM;
653 goto out_error_nomem;
654 }
655
d24ecfcc 656 spin_lock_init(&(iface->lock));
aa3d0209
BW		 657
658 /* Find and map our resources */
659 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
660 if (res == NULL) {
661 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
662 rc = -ENOENT;
663 goto out_error_get_res;
664 }
665
c6ffddea 666 iface->regs_base = ioremap(res->start, resource_size(res));
aa3d0209
BW		 667 if (iface->regs_base == NULL) {
668 dev_err(&pdev->dev, "Cannot map IO\n");
669 rc = -ENXIO;
670 goto out_error_ioremap;
671 }
672
673 iface->irq = platform_get_irq(pdev, 0);
674 if (iface->irq < 0) {
675 dev_err(&pdev->dev, "No IRQ specified\n");
676 rc = -ENOENT;
677 goto out_error_no_irq;
678 }
d24ecfcc 679
d24ecfcc 680 p_adap = &iface->adap;
aa3d0209
BW		 681 p_adap->nr = pdev->id;
682 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 683 p_adap->algo = &bfin_twi_algorithm;
684 p_adap->algo_data = iface;
e1995f65 685 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
aa3d0209 686 p_adap->dev.parent = &pdev->dev;
dd7319a5
SZ		 687 p_adap->timeout = 5 * HZ;
688 p_adap->retries = 3;
d24ecfcc 689
74d362e0
BW		 690 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
691 if (rc) {
692 dev_err(&pdev->dev, "Can't setup pin mux!\n");
693 goto out_error_pin_mux;
694 }
695
d24ecfcc 696 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
aa3d0209 697 IRQF_DISABLED, pdev->name, iface);
d24ecfcc 698 if (rc) {
aa3d0209
BW		 699 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
700 rc = -ENODEV;
701 goto out_error_req_irq;
d24ecfcc
BW		 702 }
703
704 /* Set TWI internal clock as 10MHz */
ac07fb4d 705 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
d24ecfcc 706
9528d1c7
MH		 707 /*
708 * We will not end up with a CLKDIV=0 because no one will specify
ac07fb4d 709 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
9528d1c7 710 */
ac07fb4d 711 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
9528d1c7 712
d24ecfcc 713 /* Set Twi interface clock as specified */
9528d1c7 714 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
d24ecfcc
BW		 715
716 /* Enable TWI */
aa3d0209 717 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 718 SSYNC();
719
991dee59 720 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 721 if (rc < 0) {
722 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
723 goto out_error_add_adapter;
724 }
725
726 platform_set_drvdata(pdev, iface);
d24ecfcc 727
fa6ad222
BW		 728 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
729 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 730
731 return 0;
732
733out_error_add_adapter:
734 free_irq(iface->irq, iface);
735out_error_req_irq:
736out_error_no_irq:
74d362e0
BW		 737 peripheral_free_list(pin_req[pdev->id]);
738out_error_pin_mux:
aa3d0209
BW		 739 iounmap(iface->regs_base);
740out_error_ioremap:
741out_error_get_res:
742 kfree(iface);
743out_error_nomem:
d24ecfcc
BW		 744 return rc;
745}
746
747static int i2c_bfin_twi_remove(struct platform_device *pdev)
748{
749 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
750
751 platform_set_drvdata(pdev, NULL);
752
753 i2c_del_adapter(&(iface->adap));
754 free_irq(iface->irq, iface);
74d362e0 755 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 756 iounmap(iface->regs_base);
757 kfree(iface);
d24ecfcc
BW		 758
759 return 0;
760}
761
762static struct platform_driver i2c_bfin_twi_driver = {
763 .probe = i2c_bfin_twi_probe,
764 .remove = i2c_bfin_twi_remove,
765 .suspend = i2c_bfin_twi_suspend,
766 .resume = i2c_bfin_twi_resume,
767 .driver = {
768 .name = "i2c-bfin-twi",
769 .owner = THIS_MODULE,
770 },
771};
772
773static int __init i2c_bfin_twi_init(void)
774{
d24ecfcc
BW		 775 return platform_driver_register(&i2c_bfin_twi_driver);
776}
777
778static void __exit i2c_bfin_twi_exit(void)
779{
780 platform_driver_unregister(&i2c_bfin_twi_driver);
781}
782
d24ecfcc
BW		 783module_init(i2c_bfin_twi_init);
784module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 785
786MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
787MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
788MODULE_LICENSE("GPL");
add8eda7 789MODULE_ALIAS("platform:i2c-bfin-twi");
Linux 6.x block layer and io_uring tree(s)