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i2c:i2c-bfin-twi: TWI fails to restart next transfer in high system load.
[linux-2.6-block.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
5a0e3ad6 15#include <linux/slab.h>
6df263cf 16#include <linux/io.h>
d24ecfcc
BW		 17#include <linux/mm.h>
18#include <linux/timer.h>
19#include <linux/spinlock.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
540ac555 23#include <linux/delay.h>
d24ecfcc
BW		 24
25#include <asm/blackfin.h>
74d362e0 26#include <asm/portmux.h>
d24ecfcc
BW		 27#include <asm/irq.h>
28
d24ecfcc 29/* SMBus mode*/
4dd39bb1
SZ		 30#define TWI_I2C_MODE_STANDARD 1
31#define TWI_I2C_MODE_STANDARDSUB 2
32#define TWI_I2C_MODE_COMBINED 3
33#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 34
35struct bfin_twi_iface {
d24ecfcc
BW		 36 int irq;
37 spinlock_t lock;
38 char read_write;
39 u8 command;
40 u8 *transPtr;
41 int readNum;
42 int writeNum;
43 int cur_mode;
44 int manual_stop;
45 int result;
d24ecfcc
BW		 46 struct i2c_adapter adap;
47 struct completion complete;
4dd39bb1
SZ		 48 struct i2c_msg *pmsg;
49 int msg_num;
50 int cur_msg;
958585f5
MH		 51 u16 saved_clkdiv;
52 u16 saved_control;
aa3d0209 53 void __iomem *regs_base;
d24ecfcc
BW		 54};
55
aa3d0209
BW		 56
57#define DEFINE_TWI_REG(reg, off) \
58static inline u16 read_##reg(struct bfin_twi_iface *iface) \
59 { return bfin_read16(iface->regs_base + (off)); } \
60static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
61 { bfin_write16(iface->regs_base + (off), v); }
62
63DEFINE_TWI_REG(CLKDIV, 0x00)
64DEFINE_TWI_REG(CONTROL, 0x04)
65DEFINE_TWI_REG(SLAVE_CTL, 0x08)
66DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
67DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
68DEFINE_TWI_REG(MASTER_CTL, 0x14)
69DEFINE_TWI_REG(MASTER_STAT, 0x18)
70DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
71DEFINE_TWI_REG(INT_STAT, 0x20)
72DEFINE_TWI_REG(INT_MASK, 0x24)
73DEFINE_TWI_REG(FIFO_CTL, 0x28)
74DEFINE_TWI_REG(FIFO_STAT, 0x2C)
75DEFINE_TWI_REG(XMT_DATA8, 0x80)
76DEFINE_TWI_REG(XMT_DATA16, 0x84)
77DEFINE_TWI_REG(RCV_DATA8, 0x88)
78DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 79
74d362e0
BW		 80static const u16 pin_req[2][3] = {
81 {P_TWI0_SCL, P_TWI0_SDA, 0},
82 {P_TWI1_SCL, P_TWI1_SDA, 0},
83};
84
5481d075
SZ		 85static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
86 unsigned short twi_int_status)
d24ecfcc 87{
aa3d0209 88 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 89
90 if (twi_int_status & XMTSERV) {
91 /* Transmit next data */
92 if (iface->writeNum > 0) {
5481d075 93 SSYNC();
aa3d0209 94 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 95 iface->writeNum--;
96 }
97 /* start receive immediately after complete sending in
98 * combine mode.
99 */
4dd39bb1 100 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209 101 write_MASTER_CTL(iface,
28a377c7 102 read_MASTER_CTL(iface) | MDIR);
4dd39bb1 103 else if (iface->manual_stop)
aa3d0209
BW		 104 write_MASTER_CTL(iface,
105 read_MASTER_CTL(iface) | STOP);
4dd39bb1 106 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 107 iface->cur_msg + 1 < iface->msg_num) {
108 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
109 write_MASTER_CTL(iface,
28a377c7 110 read_MASTER_CTL(iface) | MDIR);
94327d00
FS		 111 else
112 write_MASTER_CTL(iface,
28a377c7 113 read_MASTER_CTL(iface) & ~MDIR);
94327d00 114 }
d24ecfcc
BW		 115 }
116 if (twi_int_status & RCVSERV) {
117 if (iface->readNum > 0) {
118 /* Receive next data */
aa3d0209 119 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 120 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
121 /* Change combine mode into sub mode after
122 * read first data.
123 */
124 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
125 /* Get read number from first byte in block
126 * combine mode.
127 */
128 if (iface->readNum == 1 && iface->manual_stop)
129 iface->readNum = *iface->transPtr + 1;
130 }
131 iface->transPtr++;
132 iface->readNum--;
a20a64d2
SZ		 133 }
134
135 if (iface->readNum == 0) {
136 if (iface->manual_stop) {
137 /* Temporary workaround to avoid possible bus stall -
138 * Flush FIFO before issuing the STOP condition
139 */
140 read_RCV_DATA16(iface);
94327d00 141 write_MASTER_CTL(iface,
a20a64d2
SZ		 142 read_MASTER_CTL(iface) | STOP);
143 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
144 iface->cur_msg + 1 < iface->msg_num) {
145 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
146 write_MASTER_CTL(iface,
28a377c7 147 read_MASTER_CTL(iface) | MDIR);
a20a64d2
SZ		 148 else
149 write_MASTER_CTL(iface,
28a377c7 150 read_MASTER_CTL(iface) & ~MDIR);
a20a64d2 151 }
d24ecfcc 152 }
d24ecfcc
BW		 153 }
154 if (twi_int_status & MERR) {
aa3d0209
BW		 155 write_INT_MASK(iface, 0);
156 write_MASTER_STAT(iface, 0x3e);
157 write_MASTER_CTL(iface, 0);
4dd39bb1 158 iface->result = -EIO;
5cfafc18
MH		 159
160 if (mast_stat & LOSTARB)
161 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
162 if (mast_stat & ANAK)
163 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
164 if (mast_stat & DNAK)
165 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
166 if (mast_stat & BUFRDERR)
167 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
168 if (mast_stat & BUFWRERR)
169 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
170
540ac555
MH		 171 /* Faulty slave devices, may drive SDA low after a transfer
172 * finishes. To release the bus this code generates up to 9
173 * extra clocks until SDA is released.
174 */
175
176 if (read_MASTER_STAT(iface) & SDASEN) {
177 int cnt = 9;
178 do {
179 write_MASTER_CTL(iface, SCLOVR);
180 udelay(6);
181 write_MASTER_CTL(iface, 0);
182 udelay(6);
183 } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
184
185 write_MASTER_CTL(iface, SDAOVR | SCLOVR);
186 udelay(6);
187 write_MASTER_CTL(iface, SDAOVR);
188 udelay(6);
189 write_MASTER_CTL(iface, 0);
190 }
191
f0ac131a
SZ		 192 /* If it is a quick transfer, only address without data,
193 * not an err, return 1.
d24ecfcc 194 */
f0ac131a
SZ		 195 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
196 iface->transPtr == NULL &&
197 (twi_int_status & MCOMP) && (mast_stat & DNAK))
198 iface->result = 1;
199
d24ecfcc
BW		 200 complete(&iface->complete);
201 return;
202 }
203 if (twi_int_status & MCOMP) {
2ee74eb9
SZ		 204 if (twi_int_status & (XMTSERV | RCVSERV) &&
205 (read_MASTER_CTL(iface) & MEN) == 0 &&
4a65163e
SZ		 206 (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
207 iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
208 iface->result = -1;
209 write_INT_MASK(iface, 0);
210 write_MASTER_CTL(iface, 0);
211 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
d24ecfcc
BW		 212 if (iface->readNum == 0) {
213 /* set the read number to 1 and ask for manual
214 * stop in block combine mode
215 */
216 iface->readNum = 1;
217 iface->manual_stop = 1;
aa3d0209
BW		 218 write_MASTER_CTL(iface,
219 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 220 } else {
221 /* set the readd number in other
222 * combine mode.
223 */
aa3d0209
BW		 224 write_MASTER_CTL(iface,
225 (read_MASTER_CTL(iface) &
d24ecfcc 226 (~(0xff << 6))) |
aa3d0209 227 (iface->readNum << 6));
d24ecfcc
BW		 228 }
229 /* remove restart bit and enable master receive */
aa3d0209
BW		 230 write_MASTER_CTL(iface,
231 read_MASTER_CTL(iface) & ~RSTART);
4dd39bb1 232 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
28a377c7 233 iface->cur_msg + 1 < iface->msg_num) {
4dd39bb1
SZ		 234 iface->cur_msg++;
235 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
236 iface->writeNum = iface->readNum =
237 iface->pmsg[iface->cur_msg].len;
238 /* Set Transmit device address */
aa3d0209 239 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 240 iface->pmsg[iface->cur_msg].addr);
241 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
242 iface->read_write = I2C_SMBUS_READ;
243 else {
244 iface->read_write = I2C_SMBUS_WRITE;
245 /* Transmit first data */
246 if (iface->writeNum > 0) {
aa3d0209 247 write_XMT_DATA8(iface,
4dd39bb1
SZ		 248 *(iface->transPtr++));
249 iface->writeNum--;
4dd39bb1
SZ		 250 }
251 }
252
a20a64d2
SZ		 253 if (iface->pmsg[iface->cur_msg].len <= 255) {
254 write_MASTER_CTL(iface,
57a8f32e
SZ		 255 (read_MASTER_CTL(iface) &
256 (~(0xff << 6))) |
a20a64d2
SZ		 257 (iface->pmsg[iface->cur_msg].len << 6));
258 iface->manual_stop = 0;
259 } else {
57a8f32e
SZ		 260 write_MASTER_CTL(iface,
261 (read_MASTER_CTL(iface) |
262 (0xff << 6)));
4dd39bb1
SZ		 263 iface->manual_stop = 1;
264 }
28a377c7
SZ		 265 /* remove restart bit before last message */
266 if (iface->cur_msg + 1 == iface->msg_num)
267 write_MASTER_CTL(iface,
268 read_MASTER_CTL(iface) & ~RSTART);
d24ecfcc
BW		 269 } else {
270 iface->result = 1;
aa3d0209
BW		 271 write_INT_MASK(iface, 0);
272 write_MASTER_CTL(iface, 0);
d24ecfcc 273 }
a20a64d2 274 complete(&iface->complete);
d24ecfcc
BW		 275 }
276}
277
278/* Interrupt handler */
279static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
280{
281 struct bfin_twi_iface *iface = dev_id;
282 unsigned long flags;
5481d075 283 unsigned short twi_int_status;
d24ecfcc
BW		 284
285 spin_lock_irqsave(&iface->lock, flags);
5481d075
SZ		 286 while (1) {
287 twi_int_status = read_INT_STAT(iface);
288 if (!twi_int_status)
289 break;
290 /* Clear interrupt status */
291 write_INT_STAT(iface, twi_int_status);
292 bfin_twi_handle_interrupt(iface, twi_int_status);
293 SSYNC();
294 }
d24ecfcc
BW		 295 spin_unlock_irqrestore(&iface->lock, flags);
296 return IRQ_HANDLED;
297}
298
d24ecfcc 299/*
dd7319a5 300 * One i2c master transfer
d24ecfcc 301 */
dd7319a5 302static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
d24ecfcc
BW		 303 struct i2c_msg *msgs, int num)
304{
305 struct bfin_twi_iface *iface = adap->algo_data;
306 struct i2c_msg *pmsg;
d24ecfcc
BW		 307 int rc = 0;
308
aa3d0209 309 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 310 return -ENXIO;
311
a25733d6
SZ		 312 if (read_MASTER_STAT(iface) & BUSBUSY)
313 return -EAGAIN;
d24ecfcc 314
4dd39bb1
SZ		 315 iface->pmsg = msgs;
316 iface->msg_num = num;
317 iface->cur_msg = 0;
d24ecfcc 318
4dd39bb1
SZ		 319 pmsg = &msgs[0];
320 if (pmsg->flags & I2C_M_TEN) {
321 dev_err(&adap->dev, "10 bits addr not supported!\n");
322 return -EINVAL;
323 }
d24ecfcc 324
28a377c7
SZ		 325 if (iface->msg_num > 1)
326 iface->cur_mode = TWI_I2C_MODE_REPEAT;
4dd39bb1
SZ		 327 iface->manual_stop = 0;
328 iface->transPtr = pmsg->buf;
329 iface->writeNum = iface->readNum = pmsg->len;
330 iface->result = 0;
afc13b76 331 init_completion(&(iface->complete));
4dd39bb1 332 /* Set Transmit device address */
aa3d0209 333 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 334
335 /* FIFO Initiation. Data in FIFO should be
336 * discarded before start a new operation.
337 */
aa3d0209 338 write_FIFO_CTL(iface, 0x3);
4dd39bb1 339 SSYNC();
aa3d0209 340 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 341 SSYNC();
342
343 if (pmsg->flags & I2C_M_RD)
344 iface->read_write = I2C_SMBUS_READ;
345 else {
346 iface->read_write = I2C_SMBUS_WRITE;
347 /* Transmit first data */
348 if (iface->writeNum > 0) {
aa3d0209 349 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 350 iface->writeNum--;
351 SSYNC();
d24ecfcc 352 }
4dd39bb1 353 }
d24ecfcc 354
4dd39bb1 355 /* clear int stat */
aa3d0209 356 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 357
4dd39bb1 358 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 359 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 360 SSYNC();
d24ecfcc 361
4dd39bb1 362 if (pmsg->len <= 255)
aa3d0209 363 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 364 else {
aa3d0209 365 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 366 iface->manual_stop = 1;
367 }
d24ecfcc 368
4dd39bb1 369 /* Master enable */
aa3d0209 370 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
28a377c7 371 (iface->msg_num > 1 ? RSTART : 0) |
4dd39bb1
SZ		 372 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
373 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
374 SSYNC();
375
dd7319a5
SZ		 376 while (!iface->result) {
377 if (!wait_for_completion_timeout(&iface->complete,
378 adap->timeout)) {
379 iface->result = -1;
380 dev_err(&adap->dev, "master transfer timeout\n");
381 }
382 }
d24ecfcc 383
dd7319a5
SZ		 384 if (iface->result == 1)
385 rc = iface->cur_msg + 1;
4dd39bb1 386 else
dd7319a5
SZ		 387 rc = iface->result;
388
389 return rc;
d24ecfcc
BW		 390}
391
392/*
dd7319a5 393 * Generic i2c master transfer entrypoint
d24ecfcc 394 */
dd7319a5
SZ		 395static int bfin_twi_master_xfer(struct i2c_adapter *adap,
396 struct i2c_msg *msgs, int num)
397{
be2f80f0 398 return bfin_twi_do_master_xfer(adap, msgs, num);
dd7319a5
SZ		 399}
400
401/*
402 * One I2C SMBus transfer
403 */
404int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
d24ecfcc
BW		 405 unsigned short flags, char read_write,
406 u8 command, int size, union i2c_smbus_data *data)
407{
408 struct bfin_twi_iface *iface = adap->algo_data;
409 int rc = 0;
410
aa3d0209 411 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 412 return -ENXIO;
413
a25733d6
SZ		 414 if (read_MASTER_STAT(iface) & BUSBUSY)
415 return -EAGAIN;
d24ecfcc
BW		 416
417 iface->writeNum = 0;
418 iface->readNum = 0;
419
420 /* Prepare datas & select mode */
421 switch (size) {
422 case I2C_SMBUS_QUICK:
423 iface->transPtr = NULL;
424 iface->cur_mode = TWI_I2C_MODE_STANDARD;
425 break;
426 case I2C_SMBUS_BYTE:
427 if (data == NULL)
428 iface->transPtr = NULL;
429 else {
430 if (read_write == I2C_SMBUS_READ)
431 iface->readNum = 1;
432 else
433 iface->writeNum = 1;
434 iface->transPtr = &data->byte;
435 }
436 iface->cur_mode = TWI_I2C_MODE_STANDARD;
437 break;
438 case I2C_SMBUS_BYTE_DATA:
439 if (read_write == I2C_SMBUS_READ) {
440 iface->readNum = 1;
441 iface->cur_mode = TWI_I2C_MODE_COMBINED;
442 } else {
443 iface->writeNum = 1;
444 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
445 }
446 iface->transPtr = &data->byte;
447 break;
448 case I2C_SMBUS_WORD_DATA:
449 if (read_write == I2C_SMBUS_READ) {
450 iface->readNum = 2;
451 iface->cur_mode = TWI_I2C_MODE_COMBINED;
452 } else {
453 iface->writeNum = 2;
454 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
455 }
456 iface->transPtr = (u8 *)&data->word;
457 break;
458 case I2C_SMBUS_PROC_CALL:
459 iface->writeNum = 2;
460 iface->readNum = 2;
461 iface->cur_mode = TWI_I2C_MODE_COMBINED;
462 iface->transPtr = (u8 *)&data->word;
463 break;
464 case I2C_SMBUS_BLOCK_DATA:
465 if (read_write == I2C_SMBUS_READ) {
466 iface->readNum = 0;
467 iface->cur_mode = TWI_I2C_MODE_COMBINED;
468 } else {
469 iface->writeNum = data->block[0] + 1;
470 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
471 }
472 iface->transPtr = data->block;
473 break;
e0cd2dd5
MH		 474 case I2C_SMBUS_I2C_BLOCK_DATA:
475 if (read_write == I2C_SMBUS_READ) {
476 iface->readNum = data->block[0];
477 iface->cur_mode = TWI_I2C_MODE_COMBINED;
478 } else {
479 iface->writeNum = data->block[0];
480 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
481 }
482 iface->transPtr = (u8 *)&data->block[1];
483 break;
d24ecfcc
BW		 484 default:
485 return -1;
486 }
487
488 iface->result = 0;
489 iface->manual_stop = 0;
490 iface->read_write = read_write;
491 iface->command = command;
afc13b76 492 init_completion(&(iface->complete));
d24ecfcc
BW		 493
494 /* FIFO Initiation. Data in FIFO should be discarded before
495 * start a new operation.
496 */
aa3d0209 497 write_FIFO_CTL(iface, 0x3);
d24ecfcc 498 SSYNC();
aa3d0209 499 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 500
501 /* clear int stat */
aa3d0209 502 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 503
504 /* Set Transmit device address */
aa3d0209 505 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 506 SSYNC();
507
d24ecfcc
BW		 508 switch (iface->cur_mode) {
509 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 510 write_XMT_DATA8(iface, iface->command);
511 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 512 ((iface->read_write == I2C_SMBUS_READ) ?
513 RCVSERV : XMTSERV));
514 SSYNC();
515
516 if (iface->writeNum + 1 <= 255)
aa3d0209 517 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 518 else {
aa3d0209 519 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 520 iface->manual_stop = 1;
521 }
522 /* Master enable */
aa3d0209 523 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 524 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
525 break;
526 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 527 write_XMT_DATA8(iface, iface->command);
528 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 529 SSYNC();
530
531 if (iface->writeNum > 0)
aa3d0209 532 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 533 else
aa3d0209 534 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 535 /* Master enable */
28a377c7 536 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
d24ecfcc
BW		 537 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
538 break;
539 default:
aa3d0209 540 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 541 if (size != I2C_SMBUS_QUICK) {
542 /* Don't access xmit data register when this is a
543 * read operation.
544 */
545 if (iface->read_write != I2C_SMBUS_READ) {
546 if (iface->writeNum > 0) {
aa3d0209
BW		 547 write_XMT_DATA8(iface,
548 *(iface->transPtr++));
d24ecfcc 549 if (iface->writeNum <= 255)
aa3d0209
BW		 550 write_MASTER_CTL(iface,
551 iface->writeNum << 6);
d24ecfcc 552 else {
aa3d0209
BW		 553 write_MASTER_CTL(iface,
554 0xff << 6);
d24ecfcc
BW		 555 iface->manual_stop = 1;
556 }
557 iface->writeNum--;
558 } else {
aa3d0209
BW		 559 write_XMT_DATA8(iface, iface->command);
560 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 561 }
562 } else {
563 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 564 write_MASTER_CTL(iface,
565 iface->readNum << 6);
d24ecfcc 566 else if (iface->readNum > 255) {
aa3d0209 567 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc 568 iface->manual_stop = 1;
dd7319a5 569 } else
d24ecfcc 570 break;
d24ecfcc
BW		 571 }
572 }
aa3d0209 573 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 574 ((iface->read_write == I2C_SMBUS_READ) ?
575 RCVSERV : XMTSERV));
576 SSYNC();
577
578 /* Master enable */
aa3d0209 579 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 580 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
581 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
582 break;
583 }
584 SSYNC();
585
dd7319a5
SZ		 586 while (!iface->result) {
587 if (!wait_for_completion_timeout(&iface->complete,
588 adap->timeout)) {
589 iface->result = -1;
590 dev_err(&adap->dev, "smbus transfer timeout\n");
591 }
592 }
d24ecfcc
BW		 593
594 rc = (iface->result >= 0) ? 0 : -1;
595
d24ecfcc
BW		 596 return rc;
597}
598
dd7319a5
SZ		 599/*
600 * Generic I2C SMBus transfer entrypoint
601 */
602int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
603 unsigned short flags, char read_write,
604 u8 command, int size, union i2c_smbus_data *data)
605{
be2f80f0 606 return bfin_twi_do_smbus_xfer(adap, addr, flags,
dd7319a5 607 read_write, command, size, data);
dd7319a5
SZ		 608}
609
d24ecfcc
BW		 610/*
611 * Return what the adapter supports
612 */
613static u32 bfin_twi_functionality(struct i2c_adapter *adap)
614{
615 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
616 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
617 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
e0cd2dd5 618 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
d24ecfcc
BW		 619}
620
d24ecfcc
BW		 621static struct i2c_algorithm bfin_twi_algorithm = {
622 .master_xfer = bfin_twi_master_xfer,
623 .smbus_xfer = bfin_twi_smbus_xfer,
624 .functionality = bfin_twi_functionality,
625};
626
85777ad2 627static int i2c_bfin_twi_suspend(struct device *dev)
d24ecfcc 628{
85777ad2 629 struct bfin_twi_iface *iface = dev_get_drvdata(dev);
958585f5
MH		 630
631 iface->saved_clkdiv = read_CLKDIV(iface);
632 iface->saved_control = read_CONTROL(iface);
633
634 free_irq(iface->irq, iface);
d24ecfcc
BW		 635
636 /* Disable TWI */
958585f5 637 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
d24ecfcc
BW		 638
639 return 0;
640}
641
85777ad2 642static int i2c_bfin_twi_resume(struct device *dev)
d24ecfcc 643{
85777ad2 644 struct bfin_twi_iface *iface = dev_get_drvdata(dev);
d24ecfcc 645
958585f5 646 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
85777ad2 647 0, to_platform_device(dev)->name, iface);
958585f5 648 if (rc) {
85777ad2 649 dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
958585f5
MH		 650 return -ENODEV;
651 }
652
653 /* Resume TWI interface clock as specified */
654 write_CLKDIV(iface, iface->saved_clkdiv);
655
656 /* Resume TWI */
657 write_CONTROL(iface, iface->saved_control);
d24ecfcc
BW		 658
659 return 0;
660}
661
85777ad2
RW		 662static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
663 i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
664
aa3d0209 665static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 666{
aa3d0209 667 struct bfin_twi_iface *iface;
d24ecfcc 668 struct i2c_adapter *p_adap;
aa3d0209 669 struct resource *res;
d24ecfcc 670 int rc;
9528d1c7 671 unsigned int clkhilow;
d24ecfcc 672
aa3d0209
BW		 673 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
674 if (!iface) {
675 dev_err(&pdev->dev, "Cannot allocate memory\n");
676 rc = -ENOMEM;
677 goto out_error_nomem;
678 }
679
d24ecfcc 680 spin_lock_init(&(iface->lock));
aa3d0209
BW		 681
682 /* Find and map our resources */
683 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
684 if (res == NULL) {
685 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
686 rc = -ENOENT;
687 goto out_error_get_res;
688 }
689
c6ffddea 690 iface->regs_base = ioremap(res->start, resource_size(res));
aa3d0209
BW		 691 if (iface->regs_base == NULL) {
692 dev_err(&pdev->dev, "Cannot map IO\n");
693 rc = -ENXIO;
694 goto out_error_ioremap;
695 }
696
697 iface->irq = platform_get_irq(pdev, 0);
698 if (iface->irq < 0) {
699 dev_err(&pdev->dev, "No IRQ specified\n");
700 rc = -ENOENT;
701 goto out_error_no_irq;
702 }
d24ecfcc 703
d24ecfcc 704 p_adap = &iface->adap;
aa3d0209
BW		 705 p_adap->nr = pdev->id;
706 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 707 p_adap->algo = &bfin_twi_algorithm;
708 p_adap->algo_data = iface;
e1995f65 709 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
aa3d0209 710 p_adap->dev.parent = &pdev->dev;
dd7319a5
SZ		 711 p_adap->timeout = 5 * HZ;
712 p_adap->retries = 3;
d24ecfcc 713
74d362e0
BW		 714 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
715 if (rc) {
716 dev_err(&pdev->dev, "Can't setup pin mux!\n");
717 goto out_error_pin_mux;
718 }
719
d24ecfcc 720 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
4311051c 721 0, pdev->name, iface);
d24ecfcc 722 if (rc) {
aa3d0209
BW		 723 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
724 rc = -ENODEV;
725 goto out_error_req_irq;
d24ecfcc
BW		 726 }
727
728 /* Set TWI internal clock as 10MHz */
ac07fb4d 729 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
d24ecfcc 730
9528d1c7
MH		 731 /*
732 * We will not end up with a CLKDIV=0 because no one will specify
ac07fb4d 733 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
9528d1c7 734 */
ac07fb4d 735 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
9528d1c7 736
d24ecfcc 737 /* Set Twi interface clock as specified */
9528d1c7 738 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
d24ecfcc
BW		 739
740 /* Enable TWI */
aa3d0209 741 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 742 SSYNC();
743
991dee59 744 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 745 if (rc < 0) {
746 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
747 goto out_error_add_adapter;
748 }
749
750 platform_set_drvdata(pdev, iface);
d24ecfcc 751
fa6ad222
BW		 752 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
753 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 754
755 return 0;
756
757out_error_add_adapter:
758 free_irq(iface->irq, iface);
759out_error_req_irq:
760out_error_no_irq:
74d362e0
BW		 761 peripheral_free_list(pin_req[pdev->id]);
762out_error_pin_mux:
aa3d0209
BW		 763 iounmap(iface->regs_base);
764out_error_ioremap:
765out_error_get_res:
766 kfree(iface);
767out_error_nomem:
d24ecfcc
BW		 768 return rc;
769}
770
771static int i2c_bfin_twi_remove(struct platform_device *pdev)
772{
773 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
774
775 platform_set_drvdata(pdev, NULL);
776
777 i2c_del_adapter(&(iface->adap));
778 free_irq(iface->irq, iface);
74d362e0 779 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 780 iounmap(iface->regs_base);
781 kfree(iface);
d24ecfcc
BW		 782
783 return 0;
784}
785
786static struct platform_driver i2c_bfin_twi_driver = {
787 .probe = i2c_bfin_twi_probe,
788 .remove = i2c_bfin_twi_remove,
d24ecfcc
BW		 789 .driver = {
790 .name = "i2c-bfin-twi",
791 .owner = THIS_MODULE,
85777ad2 792 .pm = &i2c_bfin_twi_pm,
d24ecfcc
BW		 793 },
794};
795
796static int __init i2c_bfin_twi_init(void)
797{
d24ecfcc
BW		 798 return platform_driver_register(&i2c_bfin_twi_driver);
799}
800
801static void __exit i2c_bfin_twi_exit(void)
802{
803 platform_driver_unregister(&i2c_bfin_twi_driver);
804}
805
74f56c4a 806subsys_initcall(i2c_bfin_twi_init);
d24ecfcc 807module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 808
809MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
810MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
811MODULE_LICENSE("GPL");
add8eda7 812MODULE_ALIAS("platform:i2c-bfin-twi");
Linux 6.x block layer and io_uring tree(s)