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Merge branch 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git...
[linux-2.6-block.git] / drivers / i2c / busses / i2c-bfin-twi.c
CommitLineData
d24ecfcc 1/*
bd584996 2 * Blackfin On-Chip Two Wire Interface Driver
d24ecfcc 3 *
bd584996 4 * Copyright 2005-2007 Analog Devices Inc.
d24ecfcc 5 *
bd584996 6 * Enter bugs at http://blackfin.uclinux.org/
d24ecfcc 7 *
bd584996 8 * Licensed under the GPL-2 or later.
d24ecfcc
BW		 9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
5a0e3ad6 15#include <linux/slab.h>
6df263cf 16#include <linux/io.h>
d24ecfcc
BW		 17#include <linux/mm.h>
18#include <linux/timer.h>
19#include <linux/spinlock.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
540ac555 23#include <linux/delay.h>
d24ecfcc
BW		 24
25#include <asm/blackfin.h>
74d362e0 26#include <asm/portmux.h>
d24ecfcc
BW		 27#include <asm/irq.h>
28
d24ecfcc 29/* SMBus mode*/
4dd39bb1
SZ		 30#define TWI_I2C_MODE_STANDARD 1
31#define TWI_I2C_MODE_STANDARDSUB 2
32#define TWI_I2C_MODE_COMBINED 3
33#define TWI_I2C_MODE_REPEAT 4
d24ecfcc
BW		 34
35struct bfin_twi_iface {
d24ecfcc
BW		 36 int irq;
37 spinlock_t lock;
38 char read_write;
39 u8 command;
40 u8 *transPtr;
41 int readNum;
42 int writeNum;
43 int cur_mode;
44 int manual_stop;
45 int result;
d24ecfcc
BW		 46 struct i2c_adapter adap;
47 struct completion complete;
4dd39bb1
SZ		 48 struct i2c_msg *pmsg;
49 int msg_num;
50 int cur_msg;
958585f5
MH		 51 u16 saved_clkdiv;
52 u16 saved_control;
aa3d0209 53 void __iomem *regs_base;
d24ecfcc
BW		 54};
55
aa3d0209
BW		 56
57#define DEFINE_TWI_REG(reg, off) \
58static inline u16 read_##reg(struct bfin_twi_iface *iface) \
59 { return bfin_read16(iface->regs_base + (off)); } \
60static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
61 { bfin_write16(iface->regs_base + (off), v); }
62
63DEFINE_TWI_REG(CLKDIV, 0x00)
64DEFINE_TWI_REG(CONTROL, 0x04)
65DEFINE_TWI_REG(SLAVE_CTL, 0x08)
66DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
67DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
68DEFINE_TWI_REG(MASTER_CTL, 0x14)
69DEFINE_TWI_REG(MASTER_STAT, 0x18)
70DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
71DEFINE_TWI_REG(INT_STAT, 0x20)
72DEFINE_TWI_REG(INT_MASK, 0x24)
73DEFINE_TWI_REG(FIFO_CTL, 0x28)
74DEFINE_TWI_REG(FIFO_STAT, 0x2C)
75DEFINE_TWI_REG(XMT_DATA8, 0x80)
76DEFINE_TWI_REG(XMT_DATA16, 0x84)
77DEFINE_TWI_REG(RCV_DATA8, 0x88)
78DEFINE_TWI_REG(RCV_DATA16, 0x8C)
d24ecfcc 79
74d362e0
BW		 80static const u16 pin_req[2][3] = {
81 {P_TWI0_SCL, P_TWI0_SDA, 0},
82 {P_TWI1_SCL, P_TWI1_SDA, 0},
83};
84
5481d075
SZ		 85static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
86 unsigned short twi_int_status)
d24ecfcc 87{
aa3d0209 88 unsigned short mast_stat = read_MASTER_STAT(iface);
d24ecfcc
BW		 89
90 if (twi_int_status & XMTSERV) {
91 /* Transmit next data */
92 if (iface->writeNum > 0) {
5481d075 93 SSYNC();
aa3d0209 94 write_XMT_DATA8(iface, *(iface->transPtr++));
d24ecfcc
BW		 95 iface->writeNum--;
96 }
97 /* start receive immediately after complete sending in
98 * combine mode.
99 */
4dd39bb1 100 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
aa3d0209
BW		 101 write_MASTER_CTL(iface,
102 read_MASTER_CTL(iface) | MDIR | RSTART);
4dd39bb1 103 else if (iface->manual_stop)
aa3d0209
BW		 104 write_MASTER_CTL(iface,
105 read_MASTER_CTL(iface) | STOP);
4dd39bb1 106 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 107 iface->cur_msg + 1 < iface->msg_num) {
108 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
109 write_MASTER_CTL(iface,
110 read_MASTER_CTL(iface) | RSTART | MDIR);
111 else
112 write_MASTER_CTL(iface,
113 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
114 }
d24ecfcc
BW		 115 }
116 if (twi_int_status & RCVSERV) {
117 if (iface->readNum > 0) {
118 /* Receive next data */
aa3d0209 119 *(iface->transPtr) = read_RCV_DATA8(iface);
d24ecfcc
BW		 120 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
121 /* Change combine mode into sub mode after
122 * read first data.
123 */
124 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
125 /* Get read number from first byte in block
126 * combine mode.
127 */
128 if (iface->readNum == 1 && iface->manual_stop)
129 iface->readNum = *iface->transPtr + 1;
130 }
131 iface->transPtr++;
132 iface->readNum--;
133 } else if (iface->manual_stop) {
aa3d0209
BW		 134 write_MASTER_CTL(iface,
135 read_MASTER_CTL(iface) | STOP);
4dd39bb1 136 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
94327d00
FS		 137 iface->cur_msg + 1 < iface->msg_num) {
138 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
139 write_MASTER_CTL(iface,
140 read_MASTER_CTL(iface) | RSTART | MDIR);
141 else
142 write_MASTER_CTL(iface,
143 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
d24ecfcc 144 }
d24ecfcc
BW		 145 }
146 if (twi_int_status & MERR) {
aa3d0209
BW		 147 write_INT_MASK(iface, 0);
148 write_MASTER_STAT(iface, 0x3e);
149 write_MASTER_CTL(iface, 0);
4dd39bb1 150 iface->result = -EIO;
5cfafc18
MH		 151
152 if (mast_stat & LOSTARB)
153 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
154 if (mast_stat & ANAK)
155 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
156 if (mast_stat & DNAK)
157 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
158 if (mast_stat & BUFRDERR)
159 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
160 if (mast_stat & BUFWRERR)
161 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
162
540ac555
MH		 163 /* Faulty slave devices, may drive SDA low after a transfer
164 * finishes. To release the bus this code generates up to 9
165 * extra clocks until SDA is released.
166 */
167
168 if (read_MASTER_STAT(iface) & SDASEN) {
169 int cnt = 9;
170 do {
171 write_MASTER_CTL(iface, SCLOVR);
172 udelay(6);
173 write_MASTER_CTL(iface, 0);
174 udelay(6);
175 } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
176
177 write_MASTER_CTL(iface, SDAOVR | SCLOVR);
178 udelay(6);
179 write_MASTER_CTL(iface, SDAOVR);
180 udelay(6);
181 write_MASTER_CTL(iface, 0);
182 }
183
f0ac131a
SZ		 184 /* If it is a quick transfer, only address without data,
185 * not an err, return 1.
d24ecfcc 186 */
f0ac131a
SZ		 187 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
188 iface->transPtr == NULL &&
189 (twi_int_status & MCOMP) && (mast_stat & DNAK))
190 iface->result = 1;
191
d24ecfcc
BW		 192 complete(&iface->complete);
193 return;
194 }
195 if (twi_int_status & MCOMP) {
4a65163e
SZ		 196 if ((read_MASTER_CTL(iface) & MEN) == 0 &&
197 (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
198 iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
199 iface->result = -1;
200 write_INT_MASK(iface, 0);
201 write_MASTER_CTL(iface, 0);
202 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
d24ecfcc
BW		 203 if (iface->readNum == 0) {
204 /* set the read number to 1 and ask for manual
205 * stop in block combine mode
206 */
207 iface->readNum = 1;
208 iface->manual_stop = 1;
aa3d0209
BW		 209 write_MASTER_CTL(iface,
210 read_MASTER_CTL(iface) | (0xff << 6));
d24ecfcc
BW		 211 } else {
212 /* set the readd number in other
213 * combine mode.
214 */
aa3d0209
BW		 215 write_MASTER_CTL(iface,
216 (read_MASTER_CTL(iface) &
d24ecfcc 217 (~(0xff << 6))) |
aa3d0209 218 (iface->readNum << 6));
d24ecfcc
BW		 219 }
220 /* remove restart bit and enable master receive */
aa3d0209
BW		 221 write_MASTER_CTL(iface,
222 read_MASTER_CTL(iface) & ~RSTART);
4dd39bb1
SZ		 223 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
224 iface->cur_msg+1 < iface->msg_num) {
225 iface->cur_msg++;
226 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
227 iface->writeNum = iface->readNum =
228 iface->pmsg[iface->cur_msg].len;
229 /* Set Transmit device address */
aa3d0209 230 write_MASTER_ADDR(iface,
4dd39bb1
SZ		 231 iface->pmsg[iface->cur_msg].addr);
232 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
233 iface->read_write = I2C_SMBUS_READ;
234 else {
235 iface->read_write = I2C_SMBUS_WRITE;
236 /* Transmit first data */
237 if (iface->writeNum > 0) {
aa3d0209 238 write_XMT_DATA8(iface,
4dd39bb1
SZ		 239 *(iface->transPtr++));
240 iface->writeNum--;
4dd39bb1
SZ		 241 }
242 }
243
244 if (iface->pmsg[iface->cur_msg].len <= 255)
57a8f32e
SZ		 245 write_MASTER_CTL(iface,
246 (read_MASTER_CTL(iface) &
247 (~(0xff << 6))) |
248 (iface->pmsg[iface->cur_msg].len << 6));
4dd39bb1 249 else {
57a8f32e
SZ		 250 write_MASTER_CTL(iface,
251 (read_MASTER_CTL(iface) |
252 (0xff << 6)));
4dd39bb1
SZ		 253 iface->manual_stop = 1;
254 }
255 /* remove restart bit and enable master receive */
aa3d0209
BW		 256 write_MASTER_CTL(iface,
257 read_MASTER_CTL(iface) & ~RSTART);
d24ecfcc
BW		 258 } else {
259 iface->result = 1;
aa3d0209
BW		 260 write_INT_MASK(iface, 0);
261 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 262 }
263 }
dd7319a5 264 complete(&iface->complete);
d24ecfcc
BW		 265}
266
267/* Interrupt handler */
268static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
269{
270 struct bfin_twi_iface *iface = dev_id;
271 unsigned long flags;
5481d075 272 unsigned short twi_int_status;
d24ecfcc
BW		 273
274 spin_lock_irqsave(&iface->lock, flags);
5481d075
SZ		 275 while (1) {
276 twi_int_status = read_INT_STAT(iface);
277 if (!twi_int_status)
278 break;
279 /* Clear interrupt status */
280 write_INT_STAT(iface, twi_int_status);
281 bfin_twi_handle_interrupt(iface, twi_int_status);
282 SSYNC();
283 }
d24ecfcc
BW		 284 spin_unlock_irqrestore(&iface->lock, flags);
285 return IRQ_HANDLED;
286}
287
d24ecfcc 288/*
dd7319a5 289 * One i2c master transfer
d24ecfcc 290 */
dd7319a5 291static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
d24ecfcc
BW		 292 struct i2c_msg *msgs, int num)
293{
294 struct bfin_twi_iface *iface = adap->algo_data;
295 struct i2c_msg *pmsg;
d24ecfcc
BW		 296 int rc = 0;
297
aa3d0209 298 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 299 return -ENXIO;
300
aa3d0209 301 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 302 yield();
d24ecfcc 303
4dd39bb1
SZ		 304 iface->pmsg = msgs;
305 iface->msg_num = num;
306 iface->cur_msg = 0;
d24ecfcc 307
4dd39bb1
SZ		 308 pmsg = &msgs[0];
309 if (pmsg->flags & I2C_M_TEN) {
310 dev_err(&adap->dev, "10 bits addr not supported!\n");
311 return -EINVAL;
312 }
d24ecfcc 313
4dd39bb1
SZ		 314 iface->cur_mode = TWI_I2C_MODE_REPEAT;
315 iface->manual_stop = 0;
316 iface->transPtr = pmsg->buf;
317 iface->writeNum = iface->readNum = pmsg->len;
318 iface->result = 0;
afc13b76 319 init_completion(&(iface->complete));
4dd39bb1 320 /* Set Transmit device address */
aa3d0209 321 write_MASTER_ADDR(iface, pmsg->addr);
4dd39bb1
SZ		 322
323 /* FIFO Initiation. Data in FIFO should be
324 * discarded before start a new operation.
325 */
aa3d0209 326 write_FIFO_CTL(iface, 0x3);
4dd39bb1 327 SSYNC();
aa3d0209 328 write_FIFO_CTL(iface, 0);
4dd39bb1
SZ		 329 SSYNC();
330
331 if (pmsg->flags & I2C_M_RD)
332 iface->read_write = I2C_SMBUS_READ;
333 else {
334 iface->read_write = I2C_SMBUS_WRITE;
335 /* Transmit first data */
336 if (iface->writeNum > 0) {
aa3d0209 337 write_XMT_DATA8(iface, *(iface->transPtr++));
4dd39bb1
SZ		 338 iface->writeNum--;
339 SSYNC();
d24ecfcc 340 }
4dd39bb1 341 }
d24ecfcc 342
4dd39bb1 343 /* clear int stat */
aa3d0209 344 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc 345
4dd39bb1 346 /* Interrupt mask . Enable XMT, RCV interrupt */
aa3d0209 347 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
4dd39bb1 348 SSYNC();
d24ecfcc 349
4dd39bb1 350 if (pmsg->len <= 255)
aa3d0209 351 write_MASTER_CTL(iface, pmsg->len << 6);
4dd39bb1 352 else {
aa3d0209 353 write_MASTER_CTL(iface, 0xff << 6);
4dd39bb1
SZ		 354 iface->manual_stop = 1;
355 }
d24ecfcc 356
4dd39bb1 357 /* Master enable */
aa3d0209 358 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
4dd39bb1
SZ		 359 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
360 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
361 SSYNC();
362
dd7319a5
SZ		 363 while (!iface->result) {
364 if (!wait_for_completion_timeout(&iface->complete,
365 adap->timeout)) {
366 iface->result = -1;
367 dev_err(&adap->dev, "master transfer timeout\n");
368 }
369 }
d24ecfcc 370
dd7319a5
SZ		 371 if (iface->result == 1)
372 rc = iface->cur_msg + 1;
4dd39bb1 373 else
dd7319a5
SZ		 374 rc = iface->result;
375
376 return rc;
d24ecfcc
BW		 377}
378
379/*
dd7319a5 380 * Generic i2c master transfer entrypoint
d24ecfcc 381 */
dd7319a5
SZ		 382static int bfin_twi_master_xfer(struct i2c_adapter *adap,
383 struct i2c_msg *msgs, int num)
384{
be2f80f0 385 return bfin_twi_do_master_xfer(adap, msgs, num);
dd7319a5
SZ		 386}
387
388/*
389 * One I2C SMBus transfer
390 */
391int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
d24ecfcc
BW		 392 unsigned short flags, char read_write,
393 u8 command, int size, union i2c_smbus_data *data)
394{
395 struct bfin_twi_iface *iface = adap->algo_data;
396 int rc = 0;
397
aa3d0209 398 if (!(read_CONTROL(iface) & TWI_ENA))
d24ecfcc
BW		 399 return -ENXIO;
400
aa3d0209 401 while (read_MASTER_STAT(iface) & BUSBUSY)
d24ecfcc 402 yield();
d24ecfcc
BW		 403
404 iface->writeNum = 0;
405 iface->readNum = 0;
406
407 /* Prepare datas & select mode */
408 switch (size) {
409 case I2C_SMBUS_QUICK:
410 iface->transPtr = NULL;
411 iface->cur_mode = TWI_I2C_MODE_STANDARD;
412 break;
413 case I2C_SMBUS_BYTE:
414 if (data == NULL)
415 iface->transPtr = NULL;
416 else {
417 if (read_write == I2C_SMBUS_READ)
418 iface->readNum = 1;
419 else
420 iface->writeNum = 1;
421 iface->transPtr = &data->byte;
422 }
423 iface->cur_mode = TWI_I2C_MODE_STANDARD;
424 break;
425 case I2C_SMBUS_BYTE_DATA:
426 if (read_write == I2C_SMBUS_READ) {
427 iface->readNum = 1;
428 iface->cur_mode = TWI_I2C_MODE_COMBINED;
429 } else {
430 iface->writeNum = 1;
431 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
432 }
433 iface->transPtr = &data->byte;
434 break;
435 case I2C_SMBUS_WORD_DATA:
436 if (read_write == I2C_SMBUS_READ) {
437 iface->readNum = 2;
438 iface->cur_mode = TWI_I2C_MODE_COMBINED;
439 } else {
440 iface->writeNum = 2;
441 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
442 }
443 iface->transPtr = (u8 *)&data->word;
444 break;
445 case I2C_SMBUS_PROC_CALL:
446 iface->writeNum = 2;
447 iface->readNum = 2;
448 iface->cur_mode = TWI_I2C_MODE_COMBINED;
449 iface->transPtr = (u8 *)&data->word;
450 break;
451 case I2C_SMBUS_BLOCK_DATA:
452 if (read_write == I2C_SMBUS_READ) {
453 iface->readNum = 0;
454 iface->cur_mode = TWI_I2C_MODE_COMBINED;
455 } else {
456 iface->writeNum = data->block[0] + 1;
457 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
458 }
459 iface->transPtr = data->block;
460 break;
e0cd2dd5
MH		 461 case I2C_SMBUS_I2C_BLOCK_DATA:
462 if (read_write == I2C_SMBUS_READ) {
463 iface->readNum = data->block[0];
464 iface->cur_mode = TWI_I2C_MODE_COMBINED;
465 } else {
466 iface->writeNum = data->block[0];
467 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
468 }
469 iface->transPtr = (u8 *)&data->block[1];
470 break;
d24ecfcc
BW		 471 default:
472 return -1;
473 }
474
475 iface->result = 0;
476 iface->manual_stop = 0;
477 iface->read_write = read_write;
478 iface->command = command;
afc13b76 479 init_completion(&(iface->complete));
d24ecfcc
BW		 480
481 /* FIFO Initiation. Data in FIFO should be discarded before
482 * start a new operation.
483 */
aa3d0209 484 write_FIFO_CTL(iface, 0x3);
d24ecfcc 485 SSYNC();
aa3d0209 486 write_FIFO_CTL(iface, 0);
d24ecfcc
BW		 487
488 /* clear int stat */
aa3d0209 489 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
d24ecfcc
BW		 490
491 /* Set Transmit device address */
aa3d0209 492 write_MASTER_ADDR(iface, addr);
d24ecfcc
BW		 493 SSYNC();
494
d24ecfcc
BW		 495 switch (iface->cur_mode) {
496 case TWI_I2C_MODE_STANDARDSUB:
aa3d0209
BW		 497 write_XMT_DATA8(iface, iface->command);
498 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 499 ((iface->read_write == I2C_SMBUS_READ) ?
500 RCVSERV : XMTSERV));
501 SSYNC();
502
503 if (iface->writeNum + 1 <= 255)
aa3d0209 504 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 505 else {
aa3d0209 506 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc
BW		 507 iface->manual_stop = 1;
508 }
509 /* Master enable */
aa3d0209 510 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 511 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
512 break;
513 case TWI_I2C_MODE_COMBINED:
aa3d0209
BW		 514 write_XMT_DATA8(iface, iface->command);
515 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
d24ecfcc
BW		 516 SSYNC();
517
518 if (iface->writeNum > 0)
aa3d0209 519 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
d24ecfcc 520 else
aa3d0209 521 write_MASTER_CTL(iface, 0x1 << 6);
d24ecfcc 522 /* Master enable */
aa3d0209 523 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 524 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
525 break;
526 default:
aa3d0209 527 write_MASTER_CTL(iface, 0);
d24ecfcc
BW		 528 if (size != I2C_SMBUS_QUICK) {
529 /* Don't access xmit data register when this is a
530 * read operation.
531 */
532 if (iface->read_write != I2C_SMBUS_READ) {
533 if (iface->writeNum > 0) {
aa3d0209
BW		 534 write_XMT_DATA8(iface,
535 *(iface->transPtr++));
d24ecfcc 536 if (iface->writeNum <= 255)
aa3d0209
BW		 537 write_MASTER_CTL(iface,
538 iface->writeNum << 6);
d24ecfcc 539 else {
aa3d0209
BW		 540 write_MASTER_CTL(iface,
541 0xff << 6);
d24ecfcc
BW		 542 iface->manual_stop = 1;
543 }
544 iface->writeNum--;
545 } else {
aa3d0209
BW		 546 write_XMT_DATA8(iface, iface->command);
547 write_MASTER_CTL(iface, 1 << 6);
d24ecfcc
BW		 548 }
549 } else {
550 if (iface->readNum > 0 && iface->readNum <= 255)
aa3d0209
BW		 551 write_MASTER_CTL(iface,
552 iface->readNum << 6);
d24ecfcc 553 else if (iface->readNum > 255) {
aa3d0209 554 write_MASTER_CTL(iface, 0xff << 6);
d24ecfcc 555 iface->manual_stop = 1;
dd7319a5 556 } else
d24ecfcc 557 break;
d24ecfcc
BW		 558 }
559 }
aa3d0209 560 write_INT_MASK(iface, MCOMP | MERR |
d24ecfcc
BW		 561 ((iface->read_write == I2C_SMBUS_READ) ?
562 RCVSERV : XMTSERV));
563 SSYNC();
564
565 /* Master enable */
aa3d0209 566 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
d24ecfcc
BW		 567 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
568 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
569 break;
570 }
571 SSYNC();
572
dd7319a5
SZ		 573 while (!iface->result) {
574 if (!wait_for_completion_timeout(&iface->complete,
575 adap->timeout)) {
576 iface->result = -1;
577 dev_err(&adap->dev, "smbus transfer timeout\n");
578 }
579 }
d24ecfcc
BW		 580
581 rc = (iface->result >= 0) ? 0 : -1;
582
d24ecfcc
BW		 583 return rc;
584}
585
dd7319a5
SZ		 586/*
587 * Generic I2C SMBus transfer entrypoint
588 */
589int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
590 unsigned short flags, char read_write,
591 u8 command, int size, union i2c_smbus_data *data)
592{
be2f80f0 593 return bfin_twi_do_smbus_xfer(adap, addr, flags,
dd7319a5 594 read_write, command, size, data);
dd7319a5
SZ		 595}
596
d24ecfcc
BW		 597/*
598 * Return what the adapter supports
599 */
600static u32 bfin_twi_functionality(struct i2c_adapter *adap)
601{
602 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
603 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
604 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
e0cd2dd5 605 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
d24ecfcc
BW		 606}
607
d24ecfcc
BW		 608static struct i2c_algorithm bfin_twi_algorithm = {
609 .master_xfer = bfin_twi_master_xfer,
610 .smbus_xfer = bfin_twi_smbus_xfer,
611 .functionality = bfin_twi_functionality,
612};
613
958585f5 614static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
d24ecfcc 615{
958585f5
MH		 616 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
617
618 iface->saved_clkdiv = read_CLKDIV(iface);
619 iface->saved_control = read_CONTROL(iface);
620
621 free_irq(iface->irq, iface);
d24ecfcc
BW		 622
623 /* Disable TWI */
958585f5 624 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
d24ecfcc
BW		 625
626 return 0;
627}
628
958585f5 629static int i2c_bfin_twi_resume(struct platform_device *pdev)
d24ecfcc 630{
958585f5 631 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
d24ecfcc 632
958585f5
MH		 633 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
634 IRQF_DISABLED, pdev->name, iface);
635 if (rc) {
636 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
637 return -ENODEV;
638 }
639
640 /* Resume TWI interface clock as specified */
641 write_CLKDIV(iface, iface->saved_clkdiv);
642
643 /* Resume TWI */
644 write_CONTROL(iface, iface->saved_control);
d24ecfcc
BW		 645
646 return 0;
647}
648
aa3d0209 649static int i2c_bfin_twi_probe(struct platform_device *pdev)
d24ecfcc 650{
aa3d0209 651 struct bfin_twi_iface *iface;
d24ecfcc 652 struct i2c_adapter *p_adap;
aa3d0209 653 struct resource *res;
d24ecfcc 654 int rc;
9528d1c7 655 unsigned int clkhilow;
d24ecfcc 656
aa3d0209
BW		 657 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
658 if (!iface) {
659 dev_err(&pdev->dev, "Cannot allocate memory\n");
660 rc = -ENOMEM;
661 goto out_error_nomem;
662 }
663
d24ecfcc 664 spin_lock_init(&(iface->lock));
aa3d0209
BW		 665
666 /* Find and map our resources */
667 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
668 if (res == NULL) {
669 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
670 rc = -ENOENT;
671 goto out_error_get_res;
672 }
673
c6ffddea 674 iface->regs_base = ioremap(res->start, resource_size(res));
aa3d0209
BW		 675 if (iface->regs_base == NULL) {
676 dev_err(&pdev->dev, "Cannot map IO\n");
677 rc = -ENXIO;
678 goto out_error_ioremap;
679 }
680
681 iface->irq = platform_get_irq(pdev, 0);
682 if (iface->irq < 0) {
683 dev_err(&pdev->dev, "No IRQ specified\n");
684 rc = -ENOENT;
685 goto out_error_no_irq;
686 }
d24ecfcc 687
d24ecfcc 688 p_adap = &iface->adap;
aa3d0209
BW		 689 p_adap->nr = pdev->id;
690 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
d24ecfcc
BW		 691 p_adap->algo = &bfin_twi_algorithm;
692 p_adap->algo_data = iface;
e1995f65 693 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
aa3d0209 694 p_adap->dev.parent = &pdev->dev;
dd7319a5
SZ		 695 p_adap->timeout = 5 * HZ;
696 p_adap->retries = 3;
d24ecfcc 697
74d362e0
BW		 698 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
699 if (rc) {
700 dev_err(&pdev->dev, "Can't setup pin mux!\n");
701 goto out_error_pin_mux;
702 }
703
d24ecfcc 704 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
aa3d0209 705 IRQF_DISABLED, pdev->name, iface);
d24ecfcc 706 if (rc) {
aa3d0209
BW		 707 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
708 rc = -ENODEV;
709 goto out_error_req_irq;
d24ecfcc
BW		 710 }
711
712 /* Set TWI internal clock as 10MHz */
ac07fb4d 713 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
d24ecfcc 714
9528d1c7
MH		 715 /*
716 * We will not end up with a CLKDIV=0 because no one will specify
ac07fb4d 717 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
9528d1c7 718 */
ac07fb4d 719 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
9528d1c7 720
d24ecfcc 721 /* Set Twi interface clock as specified */
9528d1c7 722 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
d24ecfcc
BW		 723
724 /* Enable TWI */
aa3d0209 725 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
d24ecfcc
BW		 726 SSYNC();
727
991dee59 728 rc = i2c_add_numbered_adapter(p_adap);
aa3d0209
BW		 729 if (rc < 0) {
730 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
731 goto out_error_add_adapter;
732 }
733
734 platform_set_drvdata(pdev, iface);
d24ecfcc 735
fa6ad222
BW		 736 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
737 "regs_base@%p\n", iface->regs_base);
aa3d0209
BW		 738
739 return 0;
740
741out_error_add_adapter:
742 free_irq(iface->irq, iface);
743out_error_req_irq:
744out_error_no_irq:
74d362e0
BW		 745 peripheral_free_list(pin_req[pdev->id]);
746out_error_pin_mux:
aa3d0209
BW		 747 iounmap(iface->regs_base);
748out_error_ioremap:
749out_error_get_res:
750 kfree(iface);
751out_error_nomem:
d24ecfcc
BW		 752 return rc;
753}
754
755static int i2c_bfin_twi_remove(struct platform_device *pdev)
756{
757 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
758
759 platform_set_drvdata(pdev, NULL);
760
761 i2c_del_adapter(&(iface->adap));
762 free_irq(iface->irq, iface);
74d362e0 763 peripheral_free_list(pin_req[pdev->id]);
aa3d0209
BW		 764 iounmap(iface->regs_base);
765 kfree(iface);
d24ecfcc
BW		 766
767 return 0;
768}
769
770static struct platform_driver i2c_bfin_twi_driver = {
771 .probe = i2c_bfin_twi_probe,
772 .remove = i2c_bfin_twi_remove,
773 .suspend = i2c_bfin_twi_suspend,
774 .resume = i2c_bfin_twi_resume,
775 .driver = {
776 .name = "i2c-bfin-twi",
777 .owner = THIS_MODULE,
778 },
779};
780
781static int __init i2c_bfin_twi_init(void)
782{
d24ecfcc
BW		 783 return platform_driver_register(&i2c_bfin_twi_driver);
784}
785
786static void __exit i2c_bfin_twi_exit(void)
787{
788 platform_driver_unregister(&i2c_bfin_twi_driver);
789}
790
74f56c4a 791subsys_initcall(i2c_bfin_twi_init);
d24ecfcc 792module_exit(i2c_bfin_twi_exit);
fa6ad222
BW		 793
794MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
795MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
796MODULE_LICENSE("GPL");
add8eda7 797MODULE_ALIAS("platform:i2c-bfin-twi");
Linux 6.x block layer and io_uring tree(s)