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Linux 2.6.24-rc6
[linux-2.6-block.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
08e7e278
JD		 8
9 Shamelessly ripped from the w83627hf driver
10 Copyright (C) 2003 Mark Studebaker
11
12 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
13 in testing and debugging this driver.
14
8dd2d2ca
JD		 15 This driver also supports the W83627EHG, which is the lead-free
16 version of the W83627EHF.
17
08e7e278
JD		 18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31
32
33 Supports the following chips:
34
657c93b1
DH		 35 Chip #vin #fan #pwm #temp chip IDs man ID
36 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
37 0x8860 0xa1
38 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
08e7e278
JD		 39*/
40
41#include <linux/module.h>
42#include <linux/init.h>
43#include <linux/slab.h>
1ea6dd38
DH		 44#include <linux/jiffies.h>
45#include <linux/platform_device.h>
943b0830 46#include <linux/hwmon.h>
412fec82 47#include <linux/hwmon-sysfs.h>
fc18d6c0 48#include <linux/hwmon-vid.h>
943b0830 49#include <linux/err.h>
9a61bf63 50#include <linux/mutex.h>
08e7e278
JD		 51#include <asm/io.h>
52#include "lm75.h"
53
1ea6dd38 54enum kinds { w83627ehf, w83627dhg };
08e7e278 55
1ea6dd38
DH		 56/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
57static const char * w83627ehf_device_names[] = {
58 "w83627ehf",
59 "w83627dhg",
60};
61
62#define DRVNAME "w83627ehf"
08e7e278 63
657c93b1 64/*
1ea6dd38 65 * Super-I/O constants and functions
657c93b1 66 */
08e7e278
JD		 67
68#define W83627EHF_LD_HWM 0x0b
69
70#define SIO_REG_LDSEL 0x07 /* Logical device select */
71#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 72#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 73#define SIO_REG_ENABLE 0x30 /* Logical device enable */
74#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 75#define SIO_REG_VID_CTRL 0xF0 /* VID control */
76#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 77
657c93b1
DH		 78#define SIO_W83627EHF_ID 0x8850
79#define SIO_W83627EHG_ID 0x8860
80#define SIO_W83627DHG_ID 0xa020
81#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 82
83static inline void
1ea6dd38 84superio_outb(int ioreg, int reg, int val)
08e7e278 85{
1ea6dd38
DH		 86 outb(reg, ioreg);
87 outb(val, ioreg + 1);
08e7e278
JD		 88}
89
90static inline int
1ea6dd38 91superio_inb(int ioreg, int reg)
08e7e278 92{
1ea6dd38
DH		 93 outb(reg, ioreg);
94 return inb(ioreg + 1);
08e7e278
JD		 95}
96
97static inline void
1ea6dd38 98superio_select(int ioreg, int ld)
08e7e278 99{
1ea6dd38
DH		 100 outb(SIO_REG_LDSEL, ioreg);
101 outb(ld, ioreg + 1);
08e7e278
JD		 102}
103
104static inline void
1ea6dd38 105superio_enter(int ioreg)
08e7e278 106{
1ea6dd38
DH		 107 outb(0x87, ioreg);
108 outb(0x87, ioreg);
08e7e278
JD		 109}
110
111static inline void
1ea6dd38 112superio_exit(int ioreg)
08e7e278 113{
1ea6dd38
DH		 114 outb(0x02, ioreg);
115 outb(0x02, ioreg + 1);
08e7e278
JD		 116}
117
118/*
119 * ISA constants
120 */
121
1a641fce
JD		 122#define IOREGION_ALIGNMENT ~7
123#define IOREGION_OFFSET 5
124#define IOREGION_LENGTH 2
1ea6dd38
DH		 125#define ADDR_REG_OFFSET 0
126#define DATA_REG_OFFSET 1
08e7e278
JD		 127
128#define W83627EHF_REG_BANK 0x4E
129#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 130
131/* Not currently used:
132 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
133 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
134 * REG_MAN_ID is at port 0x4f
135 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 136
137static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
138static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
139
cf0676fe
RM		 140/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
141#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
142 (0x554 + (((nr) - 7) * 2)))
143#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
144 (0x555 + (((nr) - 7) * 2)))
145#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
146 (0x550 + (nr) - 7))
147
08e7e278
JD		 148#define W83627EHF_REG_TEMP1 0x27
149#define W83627EHF_REG_TEMP1_HYST 0x3a
150#define W83627EHF_REG_TEMP1_OVER 0x39
151static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
152static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
153static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
154static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
155
156/* Fan clock dividers are spread over the following five registers */
157#define W83627EHF_REG_FANDIV1 0x47
158#define W83627EHF_REG_FANDIV2 0x4B
159#define W83627EHF_REG_VBAT 0x5D
160#define W83627EHF_REG_DIODE 0x59
161#define W83627EHF_REG_SMI_OVT 0x4C
162
a4589dbb
JD		 163#define W83627EHF_REG_ALARM1 0x459
164#define W83627EHF_REG_ALARM2 0x45A
165#define W83627EHF_REG_ALARM3 0x45B
166
08c79950
RM		 167/* SmartFan registers */
168/* DC or PWM output fan configuration */
169static const u8 W83627EHF_REG_PWM_ENABLE[] = {
170 0x04, /* SYS FAN0 output mode and PWM mode */
171 0x04, /* CPU FAN0 output mode and PWM mode */
172 0x12, /* AUX FAN mode */
173 0x62, /* CPU fan1 mode */
174};
175
176static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
177static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
178
179/* FAN Duty Cycle, be used to control */
180static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
181static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
182static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
183
184
185/* Advanced Fan control, some values are common for all fans */
186static const u8 W83627EHF_REG_FAN_MIN_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
187static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0C, 0x0D, 0x17, 0x66 };
188
08e7e278
JD		 189/*
190 * Conversions
191 */
192
08c79950
RM		 193/* 1 is PWM mode, output in ms */
194static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
195{
196 return mode ? 100 * reg : 400 * reg;
197}
198
199static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
200{
201 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
202 (msec + 200) / 400), 1, 255);
203}
204
08e7e278
JD		 205static inline unsigned int
206fan_from_reg(u8 reg, unsigned int div)
207{
208 if (reg == 0 || reg == 255)
209 return 0;
210 return 1350000U / (reg * div);
211}
212
213static inline unsigned int
214div_from_reg(u8 reg)
215{
216 return 1 << reg;
217}
218
219static inline int
220temp1_from_reg(s8 reg)
221{
222 return reg * 1000;
223}
224
225static inline s8
5bfedac0 226temp1_to_reg(long temp, int min, int max)
08e7e278 227{
08c79950
RM		 228 if (temp <= min)
229 return min / 1000;
230 if (temp >= max)
231 return max / 1000;
08e7e278
JD		 232 if (temp < 0)
233 return (temp - 500) / 1000;
234 return (temp + 500) / 1000;
235}
236
cf0676fe
RM		 237/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
238
239static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
240
241static inline long in_from_reg(u8 reg, u8 nr)
242{
243 return reg * scale_in[nr];
244}
245
246static inline u8 in_to_reg(u32 val, u8 nr)
247{
248 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
249}
250
08e7e278
JD		 251/*
252 * Data structures and manipulation thereof
253 */
254
255struct w83627ehf_data {
1ea6dd38
DH		 256 int addr; /* IO base of hw monitor block */
257 const char *name;
258
1beeffe4 259 struct device *hwmon_dev;
9a61bf63 260 struct mutex lock;
08e7e278 261
9a61bf63 262 struct mutex update_lock;
08e7e278
JD		 263 char valid; /* !=0 if following fields are valid */
264 unsigned long last_updated; /* In jiffies */
265
266 /* Register values */
1ea6dd38 267 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 268 u8 in[10]; /* Register value */
269 u8 in_max[10]; /* Register value */
270 u8 in_min[10]; /* Register value */
08e7e278
JD		 271 u8 fan[5];
272 u8 fan_min[5];
273 u8 fan_div[5];
274 u8 has_fan; /* some fan inputs can be disabled */
da667365 275 u8 temp_type[3];
08e7e278
JD		 276 s8 temp1;
277 s8 temp1_max;
278 s8 temp1_max_hyst;
279 s16 temp[2];
280 s16 temp_max[2];
281 s16 temp_max_hyst[2];
a4589dbb 282 u32 alarms;
08c79950
RM		 283
284 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
285 u8 pwm_enable[4]; /* 1->manual
286 2->thermal cruise (also called SmartFan I) */
287 u8 pwm[4];
288 u8 target_temp[4];
289 u8 tolerance[4];
290
291 u8 fan_min_output[4]; /* minimum fan speed */
292 u8 fan_stop_time[4];
fc18d6c0
JD		 293
294 u8 vid;
295 u8 vrm;
08e7e278
JD		 296};
297
1ea6dd38
DH		 298struct w83627ehf_sio_data {
299 int sioreg;
300 enum kinds kind;
301};
302
08e7e278
JD		 303static inline int is_word_sized(u16 reg)
304{
305 return (((reg & 0xff00) == 0x100
306 || (reg & 0xff00) == 0x200)
307 && ((reg & 0x00ff) == 0x50
308 || (reg & 0x00ff) == 0x53
309 || (reg & 0x00ff) == 0x55));
310}
311
0956895a 312/* Registers 0x50-0x5f are banked */
1ea6dd38 313static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278 314{
0956895a 315 if ((reg & 0x00f0) == 0x50) {
1ea6dd38
DH		 316 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
317 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 318 }
319}
320
0956895a 321/* Not strictly necessary, but play it safe for now */
1ea6dd38 322static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 323{
324 if (reg & 0xff00) {
1ea6dd38
DH		 325 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
326 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 327 }
328}
329
1ea6dd38 330static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 331{
08e7e278
JD		 332 int res, word_sized = is_word_sized(reg);
333
9a61bf63 334 mutex_lock(&data->lock);
08e7e278 335
1ea6dd38
DH		 336 w83627ehf_set_bank(data, reg);
337 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
338 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 339 if (word_sized) {
340 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 341 data->addr + ADDR_REG_OFFSET);
342 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 343 }
1ea6dd38 344 w83627ehf_reset_bank(data, reg);
08e7e278 345
9a61bf63 346 mutex_unlock(&data->lock);
08e7e278
JD		 347
348 return res;
349}
350
1ea6dd38 351static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 352{
08e7e278
JD		 353 int word_sized = is_word_sized(reg);
354
9a61bf63 355 mutex_lock(&data->lock);
08e7e278 356
1ea6dd38
DH		 357 w83627ehf_set_bank(data, reg);
358 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 359 if (word_sized) {
1ea6dd38 360 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 361 outb_p((reg & 0xff) + 1,
1ea6dd38 362 data->addr + ADDR_REG_OFFSET);
08e7e278 363 }
1ea6dd38
DH		 364 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
365 w83627ehf_reset_bank(data, reg);
08e7e278 366
9a61bf63 367 mutex_unlock(&data->lock);
08e7e278
JD		 368 return 0;
369}
370
371/* This function assumes that the caller holds data->update_lock */
1ea6dd38 372static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 373{
08e7e278
JD		 374 u8 reg;
375
376 switch (nr) {
377 case 0:
1ea6dd38 378 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 379 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 380 /* fan5 input control bit is write only, compute the value */
381 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 382 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
383 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 384 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 385 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 386 break;
387 case 1:
1ea6dd38 388 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 389 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 390 /* fan5 input control bit is write only, compute the value */
391 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 392 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
393 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 394 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 395 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 396 break;
397 case 2:
1ea6dd38 398 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 399 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 400 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
401 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 402 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 403 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 404 break;
405 case 3:
1ea6dd38 406 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 407 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 408 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
409 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 410 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 411 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 412 break;
413 case 4:
1ea6dd38 414 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 415 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 416 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 417 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 418 break;
419 }
420}
421
ea7be66c
MH		 422static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
423{
424 int i;
425
426 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
427 data->fan_div[0] = (i >> 4) & 0x03;
428 data->fan_div[1] = (i >> 6) & 0x03;
429 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
430 data->fan_div[2] = (i >> 6) & 0x03;
431 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
432 data->fan_div[0] |= (i >> 3) & 0x04;
433 data->fan_div[1] |= (i >> 4) & 0x04;
434 data->fan_div[2] |= (i >> 5) & 0x04;
435 if (data->has_fan & ((1 << 3) | (1 << 4))) {
436 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
437 data->fan_div[3] = i & 0x03;
438 data->fan_div[4] = ((i >> 2) & 0x03)
439 | ((i >> 5) & 0x04);
440 }
441 if (data->has_fan & (1 << 3)) {
442 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
443 data->fan_div[3] |= (i >> 5) & 0x04;
444 }
445}
446
08e7e278
JD		 447static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
448{
1ea6dd38 449 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 450 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 451 int i;
452
9a61bf63 453 mutex_lock(&data->update_lock);
08e7e278 454
6b3e4645 455 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 456 || !data->valid) {
457 /* Fan clock dividers */
ea7be66c 458 w83627ehf_update_fan_div(data);
08e7e278 459
cf0676fe 460 /* Measured voltages and limits */
1ea6dd38
DH		 461 for (i = 0; i < data->in_num; i++) {
462 data->in[i] = w83627ehf_read_value(data,
cf0676fe 463 W83627EHF_REG_IN(i));
1ea6dd38 464 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 465 W83627EHF_REG_IN_MIN(i));
1ea6dd38 466 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 467 W83627EHF_REG_IN_MAX(i));
468 }
469
08e7e278
JD		 470 /* Measured fan speeds and limits */
471 for (i = 0; i < 5; i++) {
472 if (!(data->has_fan & (1 << i)))
473 continue;
474
1ea6dd38 475 data->fan[i] = w83627ehf_read_value(data,
08e7e278 476 W83627EHF_REG_FAN[i]);
1ea6dd38 477 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 478 W83627EHF_REG_FAN_MIN[i]);
479
480 /* If we failed to measure the fan speed and clock
481 divider can be increased, let's try that for next
482 time */
483 if (data->fan[i] == 0xff
484 && data->fan_div[i] < 0x07) {
1ea6dd38 485 dev_dbg(dev, "Increasing fan%d "
08e7e278 486 "clock divider from %u to %u\n",
33725ad3 487 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 488 div_from_reg(data->fan_div[i] + 1));
489 data->fan_div[i]++;
1ea6dd38 490 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 491 /* Preserve min limit if possible */
492 if (data->fan_min[i] >= 2
493 && data->fan_min[i] != 255)
1ea6dd38 494 w83627ehf_write_value(data,
08e7e278
JD		 495 W83627EHF_REG_FAN_MIN[i],
496 (data->fan_min[i] /= 2));
497 }
498 }
499
08c79950
RM		 500 for (i = 0; i < 4; i++) {
501 /* pwmcfg, tolarance mapped for i=0, i=1 to same reg */
502 if (i != 1) {
1ea6dd38 503 pwmcfg = w83627ehf_read_value(data,
08c79950 504 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 505 tolerance = w83627ehf_read_value(data,
08c79950
RM		 506 W83627EHF_REG_TOLERANCE[i]);
507 }
508 data->pwm_mode[i] =
509 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
510 ? 0 : 1;
511 data->pwm_enable[i] =
512 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
513 & 3) + 1;
1ea6dd38 514 data->pwm[i] = w83627ehf_read_value(data,
08c79950 515 W83627EHF_REG_PWM[i]);
1ea6dd38 516 data->fan_min_output[i] = w83627ehf_read_value(data,
08c79950 517 W83627EHF_REG_FAN_MIN_OUTPUT[i]);
1ea6dd38 518 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950
RM		 519 W83627EHF_REG_FAN_STOP_TIME[i]);
520 data->target_temp[i] =
1ea6dd38 521 w83627ehf_read_value(data,
08c79950
RM		 522 W83627EHF_REG_TARGET[i]) &
523 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
524 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
525 & 0x0f;
526 }
527
08e7e278 528 /* Measured temperatures and limits */
1ea6dd38 529 data->temp1 = w83627ehf_read_value(data,
08e7e278 530 W83627EHF_REG_TEMP1);
1ea6dd38 531 data->temp1_max = w83627ehf_read_value(data,
08e7e278 532 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 533 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 534 W83627EHF_REG_TEMP1_HYST);
535 for (i = 0; i < 2; i++) {
1ea6dd38 536 data->temp[i] = w83627ehf_read_value(data,
08e7e278 537 W83627EHF_REG_TEMP[i]);
1ea6dd38 538 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 539 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 540 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 541 W83627EHF_REG_TEMP_HYST[i]);
542 }
543
1ea6dd38 544 data->alarms = w83627ehf_read_value(data,
a4589dbb 545 W83627EHF_REG_ALARM1) |
1ea6dd38 546 (w83627ehf_read_value(data,
a4589dbb 547 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 548 (w83627ehf_read_value(data,
a4589dbb
JD		 549 W83627EHF_REG_ALARM3) << 16);
550
08e7e278
JD		 551 data->last_updated = jiffies;
552 data->valid = 1;
553 }
554
9a61bf63 555 mutex_unlock(&data->update_lock);
08e7e278
JD		 556 return data;
557}
558
559/*
560 * Sysfs callback functions
561 */
cf0676fe
RM		 562#define show_in_reg(reg) \
563static ssize_t \
564show_##reg(struct device *dev, struct device_attribute *attr, \
565 char *buf) \
566{ \
567 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
568 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
569 int nr = sensor_attr->index; \
570 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
571}
572show_in_reg(in)
573show_in_reg(in_min)
574show_in_reg(in_max)
575
576#define store_in_reg(REG, reg) \
577static ssize_t \
578store_in_##reg (struct device *dev, struct device_attribute *attr, \
579 const char *buf, size_t count) \
580{ \
1ea6dd38 581 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 582 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
583 int nr = sensor_attr->index; \
584 u32 val = simple_strtoul(buf, NULL, 10); \
585 \
586 mutex_lock(&data->update_lock); \
587 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 588 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 589 data->in_##reg[nr]); \
590 mutex_unlock(&data->update_lock); \
591 return count; \
592}
593
594store_in_reg(MIN, min)
595store_in_reg(MAX, max)
596
a4589dbb
JD		 597static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
598{
599 struct w83627ehf_data *data = w83627ehf_update_device(dev);
600 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
601 int nr = sensor_attr->index;
602 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
603}
604
cf0676fe
RM		 605static struct sensor_device_attribute sda_in_input[] = {
606 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
607 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
608 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
609 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
610 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
611 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
612 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
613 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
614 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
615 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
616};
617
a4589dbb
JD		 618static struct sensor_device_attribute sda_in_alarm[] = {
619 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
620 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
621 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
622 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
623 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
624 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
625 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
626 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
627 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
628 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
629};
630
cf0676fe
RM		 631static struct sensor_device_attribute sda_in_min[] = {
632 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
633 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
634 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
635 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
636 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
637 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
638 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
639 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
640 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
641 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
642};
643
644static struct sensor_device_attribute sda_in_max[] = {
645 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
646 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
647 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
648 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
649 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
650 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
651 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
652 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
653 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
654 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
655};
656
08e7e278
JD		 657#define show_fan_reg(reg) \
658static ssize_t \
412fec82
YM		 659show_##reg(struct device *dev, struct device_attribute *attr, \
660 char *buf) \
08e7e278
JD		 661{ \
662 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 663 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
664 int nr = sensor_attr->index; \
08e7e278
JD		 665 return sprintf(buf, "%d\n", \
666 fan_from_reg(data->reg[nr], \
667 div_from_reg(data->fan_div[nr]))); \
668}
669show_fan_reg(fan);
670show_fan_reg(fan_min);
671
672static ssize_t
412fec82
YM		 673show_fan_div(struct device *dev, struct device_attribute *attr,
674 char *buf)
08e7e278
JD		 675{
676 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 677 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
678 int nr = sensor_attr->index;
679 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 680}
681
682static ssize_t
412fec82
YM		 683store_fan_min(struct device *dev, struct device_attribute *attr,
684 const char *buf, size_t count)
08e7e278 685{
1ea6dd38 686 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 687 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
688 int nr = sensor_attr->index;
08e7e278
JD		 689 unsigned int val = simple_strtoul(buf, NULL, 10);
690 unsigned int reg;
691 u8 new_div;
692
9a61bf63 693 mutex_lock(&data->update_lock);
08e7e278
JD		 694 if (!val) {
695 /* No min limit, alarm disabled */
696 data->fan_min[nr] = 255;
697 new_div = data->fan_div[nr]; /* No change */
698 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
699 } else if ((reg = 1350000U / val) >= 128 * 255) {
700 /* Speed below this value cannot possibly be represented,
701 even with the highest divider (128) */
702 data->fan_min[nr] = 254;
703 new_div = 7; /* 128 == (1 << 7) */
704 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
705 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
706 } else if (!reg) {
707 /* Speed above this value cannot possibly be represented,
708 even with the lowest divider (1) */
709 data->fan_min[nr] = 1;
710 new_div = 0; /* 1 == (1 << 0) */
711 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 712 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 713 } else {
714 /* Automatically pick the best divider, i.e. the one such
715 that the min limit will correspond to a register value
716 in the 96..192 range */
717 new_div = 0;
718 while (reg > 192 && new_div < 7) {
719 reg >>= 1;
720 new_div++;
721 }
722 data->fan_min[nr] = reg;
723 }
724
725 /* Write both the fan clock divider (if it changed) and the new
726 fan min (unconditionally) */
727 if (new_div != data->fan_div[nr]) {
158ce075
JD		 728 /* Preserve the fan speed reading */
729 if (data->fan[nr] != 0xff) {
730 if (new_div > data->fan_div[nr])
731 data->fan[nr] >>= new_div - data->fan_div[nr];
732 else if (data->fan[nr] & 0x80)
733 data->fan[nr] = 0xff;
734 else
735 data->fan[nr] <<= data->fan_div[nr] - new_div;
736 }
08e7e278
JD		 737
738 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
739 nr + 1, div_from_reg(data->fan_div[nr]),
740 div_from_reg(new_div));
741 data->fan_div[nr] = new_div;
1ea6dd38 742 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 743 /* Give the chip time to sample a new speed value */
744 data->last_updated = jiffies;
08e7e278 745 }
1ea6dd38 746 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 747 data->fan_min[nr]);
9a61bf63 748 mutex_unlock(&data->update_lock);
08e7e278
JD		 749
750 return count;
751}
752
412fec82
YM		 753static struct sensor_device_attribute sda_fan_input[] = {
754 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
755 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
756 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
757 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
758 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
759};
08e7e278 760
a4589dbb
JD		 761static struct sensor_device_attribute sda_fan_alarm[] = {
762 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
763 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
764 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
765 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
766 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
767};
768
412fec82
YM		 769static struct sensor_device_attribute sda_fan_min[] = {
770 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
771 store_fan_min, 0),
772 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
773 store_fan_min, 1),
774 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
775 store_fan_min, 2),
776 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
777 store_fan_min, 3),
778 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
779 store_fan_min, 4),
780};
08e7e278 781
412fec82
YM		 782static struct sensor_device_attribute sda_fan_div[] = {
783 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
784 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
785 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
786 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
787 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
788};
789
08e7e278
JD		 790#define show_temp1_reg(reg) \
791static ssize_t \
6f637a64
GKH		 792show_##reg(struct device *dev, struct device_attribute *attr, \
793 char *buf) \
08e7e278
JD		 794{ \
795 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
796 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
797}
798show_temp1_reg(temp1);
799show_temp1_reg(temp1_max);
800show_temp1_reg(temp1_max_hyst);
801
802#define store_temp1_reg(REG, reg) \
803static ssize_t \
6f637a64
GKH		 804store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
805 const char *buf, size_t count) \
08e7e278 806{ \
1ea6dd38 807 struct w83627ehf_data *data = dev_get_drvdata(dev); \
5bfedac0 808 long val = simple_strtol(buf, NULL, 10); \
08e7e278 809 \
9a61bf63 810 mutex_lock(&data->update_lock); \
08c79950 811 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 812 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 813 data->temp1_##reg); \
9a61bf63 814 mutex_unlock(&data->update_lock); \
08e7e278
JD		 815 return count; \
816}
817store_temp1_reg(OVER, max);
818store_temp1_reg(HYST, max_hyst);
819
08e7e278
JD		 820#define show_temp_reg(reg) \
821static ssize_t \
412fec82
YM		 822show_##reg(struct device *dev, struct device_attribute *attr, \
823 char *buf) \
08e7e278
JD		 824{ \
825 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 826 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
827 int nr = sensor_attr->index; \
08e7e278
JD		 828 return sprintf(buf, "%d\n", \
829 LM75_TEMP_FROM_REG(data->reg[nr])); \
830}
831show_temp_reg(temp);
832show_temp_reg(temp_max);
833show_temp_reg(temp_max_hyst);
834
835#define store_temp_reg(REG, reg) \
836static ssize_t \
412fec82
YM		 837store_##reg(struct device *dev, struct device_attribute *attr, \
838 const char *buf, size_t count) \
08e7e278 839{ \
1ea6dd38 840 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 841 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
842 int nr = sensor_attr->index; \
5bfedac0 843 long val = simple_strtol(buf, NULL, 10); \
08e7e278 844 \
9a61bf63 845 mutex_lock(&data->update_lock); \
08e7e278 846 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 847 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 848 data->reg[nr]); \
9a61bf63 849 mutex_unlock(&data->update_lock); \
08e7e278
JD		 850 return count; \
851}
852store_temp_reg(OVER, temp_max);
853store_temp_reg(HYST, temp_max_hyst);
854
da667365
JD		 855static ssize_t
856show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
857{
858 struct w83627ehf_data *data = w83627ehf_update_device(dev);
859 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
860 int nr = sensor_attr->index;
861 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
862}
863
412fec82
YM		 864static struct sensor_device_attribute sda_temp[] = {
865 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
866 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
867 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
868 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
869 store_temp1_max, 0),
870 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
871 store_temp_max, 0),
872 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
873 store_temp_max, 1),
874 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
875 store_temp1_max_hyst, 0),
876 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
877 store_temp_max_hyst, 0),
878 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
879 store_temp_max_hyst, 1),
a4589dbb
JD		 880 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
881 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
882 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
da667365
JD		 883 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
884 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
885 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
412fec82 886};
08e7e278 887
08c79950
RM		 888#define show_pwm_reg(reg) \
889static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
890 char *buf) \
891{ \
892 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
893 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
894 int nr = sensor_attr->index; \
895 return sprintf(buf, "%d\n", data->reg[nr]); \
896}
897
898show_pwm_reg(pwm_mode)
899show_pwm_reg(pwm_enable)
900show_pwm_reg(pwm)
901
902static ssize_t
903store_pwm_mode(struct device *dev, struct device_attribute *attr,
904 const char *buf, size_t count)
905{
1ea6dd38 906 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 907 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
908 int nr = sensor_attr->index;
909 u32 val = simple_strtoul(buf, NULL, 10);
910 u16 reg;
911
912 if (val > 1)
913 return -EINVAL;
914 mutex_lock(&data->update_lock);
1ea6dd38 915 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 916 data->pwm_mode[nr] = val;
917 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
918 if (!val)
919 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 920 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 921 mutex_unlock(&data->update_lock);
922 return count;
923}
924
925static ssize_t
926store_pwm(struct device *dev, struct device_attribute *attr,
927 const char *buf, size_t count)
928{
1ea6dd38 929 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 930 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
931 int nr = sensor_attr->index;
932 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
933
934 mutex_lock(&data->update_lock);
935 data->pwm[nr] = val;
1ea6dd38 936 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 937 mutex_unlock(&data->update_lock);
938 return count;
939}
940
941static ssize_t
942store_pwm_enable(struct device *dev, struct device_attribute *attr,
943 const char *buf, size_t count)
944{
1ea6dd38 945 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 946 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
947 int nr = sensor_attr->index;
948 u32 val = simple_strtoul(buf, NULL, 10);
949 u16 reg;
950
951 if (!val || (val > 2)) /* only modes 1 and 2 are supported */
952 return -EINVAL;
953 mutex_lock(&data->update_lock);
1ea6dd38 954 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 955 data->pwm_enable[nr] = val;
956 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
957 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 958 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 959 mutex_unlock(&data->update_lock);
960 return count;
961}
962
963
964#define show_tol_temp(reg) \
965static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
966 char *buf) \
967{ \
968 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
969 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
970 int nr = sensor_attr->index; \
971 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
972}
973
974show_tol_temp(tolerance)
975show_tol_temp(target_temp)
976
977static ssize_t
978store_target_temp(struct device *dev, struct device_attribute *attr,
979 const char *buf, size_t count)
980{
1ea6dd38 981 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 982 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
983 int nr = sensor_attr->index;
984 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
985
986 mutex_lock(&data->update_lock);
987 data->target_temp[nr] = val;
1ea6dd38 988 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 989 mutex_unlock(&data->update_lock);
990 return count;
991}
992
993static ssize_t
994store_tolerance(struct device *dev, struct device_attribute *attr,
995 const char *buf, size_t count)
996{
1ea6dd38 997 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 998 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
999 int nr = sensor_attr->index;
1000 u16 reg;
1001 /* Limit the temp to 0C - 15C */
1002 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
1003
1004 mutex_lock(&data->update_lock);
1ea6dd38 1005 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 1006 data->tolerance[nr] = val;
1007 if (nr == 1)
1008 reg = (reg & 0x0f) | (val << 4);
1009 else
1010 reg = (reg & 0xf0) | val;
1ea6dd38 1011 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 1012 mutex_unlock(&data->update_lock);
1013 return count;
1014}
1015
1016static struct sensor_device_attribute sda_pwm[] = {
1017 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1018 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1019 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1020 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1021};
1022
1023static struct sensor_device_attribute sda_pwm_mode[] = {
1024 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1025 store_pwm_mode, 0),
1026 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1027 store_pwm_mode, 1),
1028 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1029 store_pwm_mode, 2),
1030 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1031 store_pwm_mode, 3),
1032};
1033
1034static struct sensor_device_attribute sda_pwm_enable[] = {
1035 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1036 store_pwm_enable, 0),
1037 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1038 store_pwm_enable, 1),
1039 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1040 store_pwm_enable, 2),
1041 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1042 store_pwm_enable, 3),
1043};
1044
1045static struct sensor_device_attribute sda_target_temp[] = {
1046 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1047 store_target_temp, 0),
1048 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1049 store_target_temp, 1),
1050 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1051 store_target_temp, 2),
1052 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1053 store_target_temp, 3),
1054};
1055
1056static struct sensor_device_attribute sda_tolerance[] = {
1057 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1058 store_tolerance, 0),
1059 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1060 store_tolerance, 1),
1061 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1062 store_tolerance, 2),
1063 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1064 store_tolerance, 3),
1065};
1066
08c79950
RM		 1067/* Smart Fan registers */
1068
1069#define fan_functions(reg, REG) \
1070static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1071 char *buf) \
1072{ \
1073 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1074 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1075 int nr = sensor_attr->index; \
1076 return sprintf(buf, "%d\n", data->reg[nr]); \
1077}\
1078static ssize_t \
1079store_##reg(struct device *dev, struct device_attribute *attr, \
1080 const char *buf, size_t count) \
1081{\
1ea6dd38 1082 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1083 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1084 int nr = sensor_attr->index; \
1085 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1086 mutex_lock(&data->update_lock); \
1087 data->reg[nr] = val; \
1ea6dd38 1088 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1089 mutex_unlock(&data->update_lock); \
1090 return count; \
1091}
1092
1093fan_functions(fan_min_output, FAN_MIN_OUTPUT)
1094
1095#define fan_time_functions(reg, REG) \
1096static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1097 char *buf) \
1098{ \
1099 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1100 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1101 int nr = sensor_attr->index; \
1102 return sprintf(buf, "%d\n", \
1103 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1104} \
1105\
1106static ssize_t \
1107store_##reg(struct device *dev, struct device_attribute *attr, \
1108 const char *buf, size_t count) \
1109{ \
1ea6dd38 1110 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1111 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1112 int nr = sensor_attr->index; \
1113 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1114 data->pwm_mode[nr]); \
1115 mutex_lock(&data->update_lock); \
1116 data->reg[nr] = val; \
1ea6dd38 1117 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1118 mutex_unlock(&data->update_lock); \
1119 return count; \
1120} \
1121
1122fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1123
1ea6dd38
DH		 1124static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1125 char *buf)
1126{
1127 struct w83627ehf_data *data = dev_get_drvdata(dev);
1128
1129 return sprintf(buf, "%s\n", data->name);
1130}
1131static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1132
1133static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1134 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1135 store_fan_stop_time, 3),
1136 SENSOR_ATTR(pwm4_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1137 store_fan_min_output, 3),
1138};
1139
1140static struct sensor_device_attribute sda_sf3_arrays[] = {
1141 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1142 store_fan_stop_time, 0),
1143 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1144 store_fan_stop_time, 1),
1145 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1146 store_fan_stop_time, 2),
1147 SENSOR_ATTR(pwm1_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1148 store_fan_min_output, 0),
1149 SENSOR_ATTR(pwm2_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1150 store_fan_min_output, 1),
1151 SENSOR_ATTR(pwm3_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1152 store_fan_min_output, 2),
1153};
1154
fc18d6c0
JD		 1155static ssize_t
1156show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1157{
1158 struct w83627ehf_data *data = dev_get_drvdata(dev);
1159 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1160}
1161static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1162
08e7e278 1163/*
1ea6dd38 1164 * Driver and device management
08e7e278
JD		 1165 */
1166
c18beb5b
DH		 1167static void w83627ehf_device_remove_files(struct device *dev)
1168{
1169 /* some entries in the following arrays may not have been used in
1170 * device_create_file(), but device_remove_file() will ignore them */
1171 int i;
1ea6dd38 1172 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1173
1174 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1175 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1176 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1177 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1178 for (i = 0; i < data->in_num; i++) {
c18beb5b
DH		 1179 device_remove_file(dev, &sda_in_input[i].dev_attr);
1180 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1181 device_remove_file(dev, &sda_in_min[i].dev_attr);
1182 device_remove_file(dev, &sda_in_max[i].dev_attr);
1183 }
1184 for (i = 0; i < 5; i++) {
1185 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1186 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1187 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1188 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1189 }
1190 for (i = 0; i < 4; i++) {
1191 device_remove_file(dev, &sda_pwm[i].dev_attr);
1192 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1193 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1194 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1195 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1196 }
1197 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
1198 device_remove_file(dev, &sda_temp[i].dev_attr);
c18beb5b 1199
1ea6dd38 1200 device_remove_file(dev, &dev_attr_name);
fc18d6c0
JD		 1201 if (data->vid != 0x3f)
1202 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1203}
08e7e278 1204
1ea6dd38
DH		 1205/* Get the monitoring functions started */
1206static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1207{
1208 int i;
da667365 1209 u8 tmp, diode;
08e7e278
JD		 1210
1211 /* Start monitoring is needed */
1ea6dd38 1212 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1213 if (!(tmp & 0x01))
1ea6dd38 1214 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1215 tmp | 0x01);
1216
1217 /* Enable temp2 and temp3 if needed */
1218 for (i = 0; i < 2; i++) {
1ea6dd38 1219 tmp = w83627ehf_read_value(data,
08e7e278
JD		 1220 W83627EHF_REG_TEMP_CONFIG[i]);
1221 if (tmp & 0x01)
1ea6dd38 1222 w83627ehf_write_value(data,
08e7e278
JD		 1223 W83627EHF_REG_TEMP_CONFIG[i],
1224 tmp & 0xfe);
1225 }
d3130f0e
JD		 1226
1227 /* Enable VBAT monitoring if needed */
1228 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1229 if (!(tmp & 0x01))
1230 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
da667365
JD		 1231
1232 /* Get thermal sensor types */
1233 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1234 for (i = 0; i < 3; i++) {
1235 if ((tmp & (0x02 << i)))
1236 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
1237 else
1238 data->temp_type[i] = 4; /* thermistor */
1239 }
08e7e278
JD		 1240}
1241
1ea6dd38 1242static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1243{
1ea6dd38
DH		 1244 struct device *dev = &pdev->dev;
1245 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1246 struct w83627ehf_data *data;
1ea6dd38 1247 struct resource *res;
fc18d6c0 1248 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1249 int i, err = 0;
1250
1ea6dd38
DH		 1251 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1252 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1253 err = -EBUSY;
1ea6dd38
DH		 1254 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1255 (unsigned long)res->start,
1256 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1257 goto exit;
1258 }
1259
ba9c2e8d 1260 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1261 err = -ENOMEM;
1262 goto exit_release;
1263 }
08e7e278 1264
1ea6dd38 1265 data->addr = res->start;
9a61bf63 1266 mutex_init(&data->lock);
9a61bf63 1267 mutex_init(&data->update_lock);
1ea6dd38
DH		 1268 data->name = w83627ehf_device_names[sio_data->kind];
1269 platform_set_drvdata(pdev, data);
08e7e278 1270
1ea6dd38
DH		 1271 /* 627EHG and 627EHF have 10 voltage inputs; DHG has 9 */
1272 data->in_num = (sio_data->kind == w83627dhg) ? 9 : 10;
08e7e278
JD		 1273
1274 /* Initialize the chip */
1ea6dd38 1275 w83627ehf_init_device(data);
08e7e278 1276
fc18d6c0
JD		 1277 data->vrm = vid_which_vrm();
1278 superio_enter(sio_data->sioreg);
1279 /* Set VID input sensibility if needed. In theory the BIOS should
1280 have set it, but in practice it's not always the case. */
1281 en_vrm10 = superio_inb(sio_data->sioreg, SIO_REG_EN_VRM10);
1282 if ((en_vrm10 & 0x08) && data->vrm != 100) {
1283 dev_warn(dev, "Setting VID input voltage to TTL\n");
1284 superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
1285 en_vrm10 & ~0x08);
1286 } else if (!(en_vrm10 & 0x08) && data->vrm == 100) {
1287 dev_warn(dev, "Setting VID input voltage to VRM10\n");
1288 superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
1289 en_vrm10 | 0x08);
1290 }
1291 /* Read VID value */
1292 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1293 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80)
1294 data->vid = superio_inb(sio_data->sioreg, SIO_REG_VID_DATA) & 0x3f;
1295 else {
1296 dev_info(dev, "VID pins in output mode, CPU VID not "
1297 "available\n");
1298 data->vid = 0x3f;
1299 }
1300
08c79950
RM		 1301 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1302
1ea6dd38
DH		 1303 fan5pin = superio_inb(sio_data->sioreg, 0x24) & 0x2;
1304 fan4pin = superio_inb(sio_data->sioreg, 0x29) & 0x6;
1305 superio_exit(sio_data->sioreg);
08c79950 1306
08e7e278 1307 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1308 as fan on/off switches, but fan5 control is write only :/
1309 We assume that if the serial interface is disabled, designers
1310 connected fan5 as input unless they are emitting log 1, which
1311 is not the default. */
08c79950 1312
08e7e278 1313 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1314 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
08c79950 1315 if ((i & (1 << 2)) && (!fan4pin))
08e7e278 1316 data->has_fan |= (1 << 3);
14992c7e 1317 if (!(i & (1 << 1)) && (!fan5pin))
08e7e278
JD		 1318 data->has_fan |= (1 << 4);
1319
ea7be66c
MH		 1320 /* Read fan clock dividers immediately */
1321 w83627ehf_update_fan_div(data);
1322
08e7e278 1323 /* Register sysfs hooks */
08c79950 1324 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1325 if ((err = device_create_file(dev,
1326 &sda_sf3_arrays[i].dev_attr)))
1327 goto exit_remove;
08c79950
RM		 1328
1329 /* if fan4 is enabled create the sf3 files for it */
1330 if (data->has_fan & (1 << 3))
c18beb5b
DH		 1331 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1332 if ((err = device_create_file(dev,
1333 &sda_sf3_arrays_fan4[i].dev_attr)))
1334 goto exit_remove;
1335 }
08c79950 1336
1ea6dd38 1337 for (i = 0; i < data->in_num; i++)
c18beb5b
DH		 1338 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1339 || (err = device_create_file(dev,
1340 &sda_in_alarm[i].dev_attr))
1341 || (err = device_create_file(dev,
1342 &sda_in_min[i].dev_attr))
1343 || (err = device_create_file(dev,
1344 &sda_in_max[i].dev_attr)))
1345 goto exit_remove;
cf0676fe 1346
412fec82 1347 for (i = 0; i < 5; i++) {
08c79950 1348 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1349 if ((err = device_create_file(dev,
1350 &sda_fan_input[i].dev_attr))
1351 || (err = device_create_file(dev,
1352 &sda_fan_alarm[i].dev_attr))
1353 || (err = device_create_file(dev,
1354 &sda_fan_div[i].dev_attr))
1355 || (err = device_create_file(dev,
1356 &sda_fan_min[i].dev_attr)))
1357 goto exit_remove;
1358 if (i < 4 && /* w83627ehf only has 4 pwm */
1359 ((err = device_create_file(dev,
1360 &sda_pwm[i].dev_attr))
1361 || (err = device_create_file(dev,
1362 &sda_pwm_mode[i].dev_attr))
1363 || (err = device_create_file(dev,
1364 &sda_pwm_enable[i].dev_attr))
1365 || (err = device_create_file(dev,
1366 &sda_target_temp[i].dev_attr))
1367 || (err = device_create_file(dev,
1368 &sda_tolerance[i].dev_attr))))
1369 goto exit_remove;
08c79950 1370 }
08e7e278 1371 }
08c79950 1372
412fec82 1373 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
c18beb5b
DH		 1374 if ((err = device_create_file(dev, &sda_temp[i].dev_attr)))
1375 goto exit_remove;
1376
1ea6dd38
DH		 1377 err = device_create_file(dev, &dev_attr_name);
1378 if (err)
1379 goto exit_remove;
1380
fc18d6c0
JD		 1381 if (data->vid != 0x3f) {
1382 err = device_create_file(dev, &dev_attr_cpu0_vid);
1383 if (err)
1384 goto exit_remove;
1385 }
1386
1beeffe4
TJ		 1387 data->hwmon_dev = hwmon_device_register(dev);
1388 if (IS_ERR(data->hwmon_dev)) {
1389 err = PTR_ERR(data->hwmon_dev);
c18beb5b
DH		 1390 goto exit_remove;
1391 }
08e7e278
JD		 1392
1393 return 0;
1394
c18beb5b
DH		 1395exit_remove:
1396 w83627ehf_device_remove_files(dev);
08e7e278 1397 kfree(data);
1ea6dd38 1398 platform_set_drvdata(pdev, NULL);
08e7e278 1399exit_release:
1ea6dd38 1400 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1401exit:
1402 return err;
1403}
1404
1ea6dd38 1405static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1406{
1ea6dd38 1407 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1408
1beeffe4 1409 hwmon_device_unregister(data->hwmon_dev);
1ea6dd38
DH		 1410 w83627ehf_device_remove_files(&pdev->dev);
1411 release_region(data->addr, IOREGION_LENGTH);
1412 platform_set_drvdata(pdev, NULL);
943b0830 1413 kfree(data);
08e7e278
JD		 1414
1415 return 0;
1416}
1417
1ea6dd38 1418static struct platform_driver w83627ehf_driver = {
cdaf7934 1419 .driver = {
87218842 1420 .owner = THIS_MODULE,
1ea6dd38 1421 .name = DRVNAME,
cdaf7934 1422 },
1ea6dd38
DH		 1423 .probe = w83627ehf_probe,
1424 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1425};
1426
1ea6dd38
DH		 1427/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1428static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1429 struct w83627ehf_sio_data *sio_data)
08e7e278 1430{
1ea6dd38
DH		 1431 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1432 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1433 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
1434
08e7e278 1435 u16 val;
1ea6dd38 1436 const char *sio_name;
08e7e278 1437
1ea6dd38 1438 superio_enter(sioaddr);
08e7e278 1439
1ea6dd38
DH		 1440 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1441 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1442 switch (val & SIO_ID_MASK) {
657c93b1 1443 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1444 sio_data->kind = w83627ehf;
1445 sio_name = sio_name_W83627EHF;
1446 break;
657c93b1 1447 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1448 sio_data->kind = w83627ehf;
1449 sio_name = sio_name_W83627EHG;
1450 break;
1451 case SIO_W83627DHG_ID:
1452 sio_data->kind = w83627dhg;
1453 sio_name = sio_name_W83627DHG;
657c93b1
DH		 1454 break;
1455 default:
9f66036b
JD		 1456 if (val != 0xffff)
1457 pr_debug(DRVNAME ": unsupported chip ID: 0x%04x\n",
1458 val);
1ea6dd38 1459 superio_exit(sioaddr);
08e7e278
JD		 1460 return -ENODEV;
1461 }
1462
1ea6dd38
DH		 1463 /* We have a known chip, find the HWM I/O address */
1464 superio_select(sioaddr, W83627EHF_LD_HWM);
1465 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1466 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1467 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1468 if (*addr == 0) {
475ef855
DH		 1469 printk(KERN_ERR DRVNAME ": Refusing to enable a Super-I/O "
1470 "device with a base I/O port 0.\n");
1ea6dd38 1471 superio_exit(sioaddr);
08e7e278
JD		 1472 return -ENODEV;
1473 }
1474
1475 /* Activate logical device if needed */
1ea6dd38 1476 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855
DH		 1477 if (!(val & 0x01)) {
1478 printk(KERN_WARNING DRVNAME ": Forcibly enabling Super-I/O. "
1479 "Sensor is probably unusable.\n");
1ea6dd38 1480 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1481 }
1ea6dd38
DH		 1482
1483 superio_exit(sioaddr);
1484 pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
1485 sio_data->sioreg = sioaddr;
08e7e278 1486
08e7e278
JD		 1487 return 0;
1488}
1489
1ea6dd38
DH		 1490/* when Super-I/O functions move to a separate file, the Super-I/O
1491 * bus will manage the lifetime of the device and this module will only keep
1492 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1493 * must keep track of the device */
1494static struct platform_device *pdev;
1495
08e7e278
JD		 1496static int __init sensors_w83627ehf_init(void)
1497{
1ea6dd38
DH		 1498 int err;
1499 unsigned short address;
1500 struct resource res;
1501 struct w83627ehf_sio_data sio_data;
1502
1503 /* initialize sio_data->kind and sio_data->sioreg.
1504 *
1505 * when Super-I/O functions move to a separate file, the Super-I/O
1506 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1507 * w83627ehf hardware monitor, and call probe() */
1508 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1509 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1510 return -ENODEV;
1511
1ea6dd38
DH		 1512 err = platform_driver_register(&w83627ehf_driver);
1513 if (err)
1514 goto exit;
1515
1516 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1517 err = -ENOMEM;
1518 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1519 goto exit_unregister;
1520 }
1521
1522 err = platform_device_add_data(pdev, &sio_data,
1523 sizeof(struct w83627ehf_sio_data));
1524 if (err) {
1525 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1526 goto exit_device_put;
1527 }
1528
1529 memset(&res, 0, sizeof(res));
1530 res.name = DRVNAME;
1531 res.start = address + IOREGION_OFFSET;
1532 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1533 res.flags = IORESOURCE_IO;
1534 err = platform_device_add_resources(pdev, &res, 1);
1535 if (err) {
1536 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1537 "(%d)\n", err);
1538 goto exit_device_put;
1539 }
1540
1541 /* platform_device_add calls probe() */
1542 err = platform_device_add(pdev);
1543 if (err) {
1544 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1545 err);
1546 goto exit_device_put;
1547 }
1548
1549 return 0;
1550
1551exit_device_put:
1552 platform_device_put(pdev);
1553exit_unregister:
1554 platform_driver_unregister(&w83627ehf_driver);
1555exit:
1556 return err;
08e7e278
JD		 1557}
1558
1559static void __exit sensors_w83627ehf_exit(void)
1560{
1ea6dd38
DH		 1561 platform_device_unregister(pdev);
1562 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1563}
1564
1565MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1566MODULE_DESCRIPTION("W83627EHF driver");
1567MODULE_LICENSE("GPL");
1568
1569module_init(sensors_w83627ehf_init);
1570module_exit(sensors_w83627ehf_exit);
Linux 6.x block layer and io_uring tree(s)