projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hwmon/w83627ehf: Convert to a platform driver
[linux-2.6-block.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
08e7e278
JD		 8
9 Shamelessly ripped from the w83627hf driver
10 Copyright (C) 2003 Mark Studebaker
11
12 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
13 in testing and debugging this driver.
14
8dd2d2ca
JD		 15 This driver also supports the W83627EHG, which is the lead-free
16 version of the W83627EHF.
17
08e7e278
JD		 18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31
32
33 Supports the following chips:
34
657c93b1
DH		 35 Chip #vin #fan #pwm #temp chip IDs man ID
36 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
37 0x8860 0xa1
38 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
08e7e278
JD		 39*/
40
41#include <linux/module.h>
42#include <linux/init.h>
43#include <linux/slab.h>
1ea6dd38
DH		 44#include <linux/jiffies.h>
45#include <linux/platform_device.h>
943b0830 46#include <linux/hwmon.h>
412fec82 47#include <linux/hwmon-sysfs.h>
943b0830 48#include <linux/err.h>
9a61bf63 49#include <linux/mutex.h>
08e7e278
JD		 50#include <asm/io.h>
51#include "lm75.h"
52
1ea6dd38 53enum kinds { w83627ehf, w83627dhg };
08e7e278 54
1ea6dd38
DH		 55/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
56static const char * w83627ehf_device_names[] = {
57 "w83627ehf",
58 "w83627dhg",
59};
60
61#define DRVNAME "w83627ehf"
08e7e278 62
657c93b1 63/*
1ea6dd38 64 * Super-I/O constants and functions
657c93b1 65 */
08e7e278
JD		 66
67#define W83627EHF_LD_HWM 0x0b
68
69#define SIO_REG_LDSEL 0x07 /* Logical device select */
70#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
71#define SIO_REG_ENABLE 0x30 /* Logical device enable */
72#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
73
657c93b1
DH		 74#define SIO_W83627EHF_ID 0x8850
75#define SIO_W83627EHG_ID 0x8860
76#define SIO_W83627DHG_ID 0xa020
77#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 78
79static inline void
1ea6dd38 80superio_outb(int ioreg, int reg, int val)
08e7e278 81{
1ea6dd38
DH		 82 outb(reg, ioreg);
83 outb(val, ioreg + 1);
08e7e278
JD		 84}
85
86static inline int
1ea6dd38 87superio_inb(int ioreg, int reg)
08e7e278 88{
1ea6dd38
DH		 89 outb(reg, ioreg);
90 return inb(ioreg + 1);
08e7e278
JD		 91}
92
93static inline void
1ea6dd38 94superio_select(int ioreg, int ld)
08e7e278 95{
1ea6dd38
DH		 96 outb(SIO_REG_LDSEL, ioreg);
97 outb(ld, ioreg + 1);
08e7e278
JD		 98}
99
100static inline void
1ea6dd38 101superio_enter(int ioreg)
08e7e278 102{
1ea6dd38
DH		 103 outb(0x87, ioreg);
104 outb(0x87, ioreg);
08e7e278
JD		 105}
106
107static inline void
1ea6dd38 108superio_exit(int ioreg)
08e7e278 109{
1ea6dd38
DH		 110 outb(0x02, ioreg);
111 outb(0x02, ioreg + 1);
08e7e278
JD		 112}
113
114/*
115 * ISA constants
116 */
117
1a641fce
JD		 118#define IOREGION_ALIGNMENT ~7
119#define IOREGION_OFFSET 5
120#define IOREGION_LENGTH 2
1ea6dd38
DH		 121#define ADDR_REG_OFFSET 0
122#define DATA_REG_OFFSET 1
08e7e278
JD		 123
124#define W83627EHF_REG_BANK 0x4E
125#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 126
127/* Not currently used:
128 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
129 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
130 * REG_MAN_ID is at port 0x4f
131 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 132
133static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
134static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
135
cf0676fe
RM		 136/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
137#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
138 (0x554 + (((nr) - 7) * 2)))
139#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
140 (0x555 + (((nr) - 7) * 2)))
141#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
142 (0x550 + (nr) - 7))
143
08e7e278
JD		 144#define W83627EHF_REG_TEMP1 0x27
145#define W83627EHF_REG_TEMP1_HYST 0x3a
146#define W83627EHF_REG_TEMP1_OVER 0x39
147static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
148static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
149static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
150static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
151
152/* Fan clock dividers are spread over the following five registers */
153#define W83627EHF_REG_FANDIV1 0x47
154#define W83627EHF_REG_FANDIV2 0x4B
155#define W83627EHF_REG_VBAT 0x5D
156#define W83627EHF_REG_DIODE 0x59
157#define W83627EHF_REG_SMI_OVT 0x4C
158
a4589dbb
JD		 159#define W83627EHF_REG_ALARM1 0x459
160#define W83627EHF_REG_ALARM2 0x45A
161#define W83627EHF_REG_ALARM3 0x45B
162
08c79950
RM		 163/* SmartFan registers */
164/* DC or PWM output fan configuration */
165static const u8 W83627EHF_REG_PWM_ENABLE[] = {
166 0x04, /* SYS FAN0 output mode and PWM mode */
167 0x04, /* CPU FAN0 output mode and PWM mode */
168 0x12, /* AUX FAN mode */
169 0x62, /* CPU fan1 mode */
170};
171
172static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
173static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
174
175/* FAN Duty Cycle, be used to control */
176static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
177static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
178static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
179
180
181/* Advanced Fan control, some values are common for all fans */
182static const u8 W83627EHF_REG_FAN_MIN_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
183static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0C, 0x0D, 0x17, 0x66 };
184
08e7e278
JD		 185/*
186 * Conversions
187 */
188
08c79950
RM		 189/* 1 is PWM mode, output in ms */
190static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
191{
192 return mode ? 100 * reg : 400 * reg;
193}
194
195static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
196{
197 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
198 (msec + 200) / 400), 1, 255);
199}
200
08e7e278
JD		 201static inline unsigned int
202fan_from_reg(u8 reg, unsigned int div)
203{
204 if (reg == 0 || reg == 255)
205 return 0;
206 return 1350000U / (reg * div);
207}
208
209static inline unsigned int
210div_from_reg(u8 reg)
211{
212 return 1 << reg;
213}
214
215static inline int
216temp1_from_reg(s8 reg)
217{
218 return reg * 1000;
219}
220
221static inline s8
08c79950 222temp1_to_reg(int temp, int min, int max)
08e7e278 223{
08c79950
RM		 224 if (temp <= min)
225 return min / 1000;
226 if (temp >= max)
227 return max / 1000;
08e7e278
JD		 228 if (temp < 0)
229 return (temp - 500) / 1000;
230 return (temp + 500) / 1000;
231}
232
cf0676fe
RM		 233/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
234
235static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
236
237static inline long in_from_reg(u8 reg, u8 nr)
238{
239 return reg * scale_in[nr];
240}
241
242static inline u8 in_to_reg(u32 val, u8 nr)
243{
244 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
245}
246
08e7e278
JD		 247/*
248 * Data structures and manipulation thereof
249 */
250
251struct w83627ehf_data {
1ea6dd38
DH		 252 int addr; /* IO base of hw monitor block */
253 const char *name;
254
943b0830 255 struct class_device *class_dev;
9a61bf63 256 struct mutex lock;
08e7e278 257
9a61bf63 258 struct mutex update_lock;
08e7e278
JD		 259 char valid; /* !=0 if following fields are valid */
260 unsigned long last_updated; /* In jiffies */
261
262 /* Register values */
1ea6dd38 263 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 264 u8 in[10]; /* Register value */
265 u8 in_max[10]; /* Register value */
266 u8 in_min[10]; /* Register value */
08e7e278
JD		 267 u8 fan[5];
268 u8 fan_min[5];
269 u8 fan_div[5];
270 u8 has_fan; /* some fan inputs can be disabled */
271 s8 temp1;
272 s8 temp1_max;
273 s8 temp1_max_hyst;
274 s16 temp[2];
275 s16 temp_max[2];
276 s16 temp_max_hyst[2];
a4589dbb 277 u32 alarms;
08c79950
RM		 278
279 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
280 u8 pwm_enable[4]; /* 1->manual
281 2->thermal cruise (also called SmartFan I) */
282 u8 pwm[4];
283 u8 target_temp[4];
284 u8 tolerance[4];
285
286 u8 fan_min_output[4]; /* minimum fan speed */
287 u8 fan_stop_time[4];
08e7e278
JD		 288};
289
1ea6dd38
DH		 290struct w83627ehf_sio_data {
291 int sioreg;
292 enum kinds kind;
293};
294
08e7e278
JD		 295static inline int is_word_sized(u16 reg)
296{
297 return (((reg & 0xff00) == 0x100
298 || (reg & 0xff00) == 0x200)
299 && ((reg & 0x00ff) == 0x50
300 || (reg & 0x00ff) == 0x53
301 || (reg & 0x00ff) == 0x55));
302}
303
304/* We assume that the default bank is 0, thus the following two functions do
305 nothing for registers which live in bank 0. For others, they respectively
306 set the bank register to the correct value (before the register is
307 accessed), and back to 0 (afterwards). */
1ea6dd38 308static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 309{
310 if (reg & 0xff00) {
1ea6dd38
DH		 311 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
312 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 313 }
314}
315
1ea6dd38 316static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 317{
318 if (reg & 0xff00) {
1ea6dd38
DH		 319 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
320 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 321 }
322}
323
1ea6dd38 324static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 325{
08e7e278
JD		 326 int res, word_sized = is_word_sized(reg);
327
9a61bf63 328 mutex_lock(&data->lock);
08e7e278 329
1ea6dd38
DH		 330 w83627ehf_set_bank(data, reg);
331 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
332 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 333 if (word_sized) {
334 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 335 data->addr + ADDR_REG_OFFSET);
336 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 337 }
1ea6dd38 338 w83627ehf_reset_bank(data, reg);
08e7e278 339
9a61bf63 340 mutex_unlock(&data->lock);
08e7e278
JD		 341
342 return res;
343}
344
1ea6dd38 345static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 346{
08e7e278
JD		 347 int word_sized = is_word_sized(reg);
348
9a61bf63 349 mutex_lock(&data->lock);
08e7e278 350
1ea6dd38
DH		 351 w83627ehf_set_bank(data, reg);
352 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 353 if (word_sized) {
1ea6dd38 354 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 355 outb_p((reg & 0xff) + 1,
1ea6dd38 356 data->addr + ADDR_REG_OFFSET);
08e7e278 357 }
1ea6dd38
DH		 358 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
359 w83627ehf_reset_bank(data, reg);
08e7e278 360
9a61bf63 361 mutex_unlock(&data->lock);
08e7e278
JD		 362 return 0;
363}
364
365/* This function assumes that the caller holds data->update_lock */
1ea6dd38 366static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 367{
08e7e278
JD		 368 u8 reg;
369
370 switch (nr) {
371 case 0:
1ea6dd38 372 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 373 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 374 /* fan5 input control bit is write only, compute the value */
375 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 376 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
377 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 378 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 379 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 380 break;
381 case 1:
1ea6dd38 382 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 383 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 384 /* fan5 input control bit is write only, compute the value */
385 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 386 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
387 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 388 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 389 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 390 break;
391 case 2:
1ea6dd38 392 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 393 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 394 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
395 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 396 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 397 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 398 break;
399 case 3:
1ea6dd38 400 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 401 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 402 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
403 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 404 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 405 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 406 break;
407 case 4:
1ea6dd38 408 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 409 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 410 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 411 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 412 break;
413 }
414}
415
416static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
417{
1ea6dd38 418 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 419 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 420 int i;
421
9a61bf63 422 mutex_lock(&data->update_lock);
08e7e278
JD		 423
424 if (time_after(jiffies, data->last_updated + HZ)
425 || !data->valid) {
426 /* Fan clock dividers */
1ea6dd38 427 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
08e7e278
JD		 428 data->fan_div[0] = (i >> 4) & 0x03;
429 data->fan_div[1] = (i >> 6) & 0x03;
1ea6dd38 430 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
08e7e278 431 data->fan_div[2] = (i >> 6) & 0x03;
1ea6dd38 432 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
08e7e278
JD		 433 data->fan_div[0] |= (i >> 3) & 0x04;
434 data->fan_div[1] |= (i >> 4) & 0x04;
435 data->fan_div[2] |= (i >> 5) & 0x04;
436 if (data->has_fan & ((1 << 3) | (1 << 4))) {
1ea6dd38 437 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
08e7e278
JD		 438 data->fan_div[3] = i & 0x03;
439 data->fan_div[4] = ((i >> 2) & 0x03)
440 | ((i >> 5) & 0x04);
441 }
442 if (data->has_fan & (1 << 3)) {
1ea6dd38 443 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
08e7e278
JD		 444 data->fan_div[3] |= (i >> 5) & 0x04;
445 }
446
cf0676fe 447 /* Measured voltages and limits */
1ea6dd38
DH		 448 for (i = 0; i < data->in_num; i++) {
449 data->in[i] = w83627ehf_read_value(data,
cf0676fe 450 W83627EHF_REG_IN(i));
1ea6dd38 451 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 452 W83627EHF_REG_IN_MIN(i));
1ea6dd38 453 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 454 W83627EHF_REG_IN_MAX(i));
455 }
456
08e7e278
JD		 457 /* Measured fan speeds and limits */
458 for (i = 0; i < 5; i++) {
459 if (!(data->has_fan & (1 << i)))
460 continue;
461
1ea6dd38 462 data->fan[i] = w83627ehf_read_value(data,
08e7e278 463 W83627EHF_REG_FAN[i]);
1ea6dd38 464 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 465 W83627EHF_REG_FAN_MIN[i]);
466
467 /* If we failed to measure the fan speed and clock
468 divider can be increased, let's try that for next
469 time */
470 if (data->fan[i] == 0xff
471 && data->fan_div[i] < 0x07) {
1ea6dd38 472 dev_dbg(dev, "Increasing fan%d "
08e7e278 473 "clock divider from %u to %u\n",
33725ad3 474 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 475 div_from_reg(data->fan_div[i] + 1));
476 data->fan_div[i]++;
1ea6dd38 477 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 478 /* Preserve min limit if possible */
479 if (data->fan_min[i] >= 2
480 && data->fan_min[i] != 255)
1ea6dd38 481 w83627ehf_write_value(data,
08e7e278
JD		 482 W83627EHF_REG_FAN_MIN[i],
483 (data->fan_min[i] /= 2));
484 }
485 }
486
08c79950
RM		 487 for (i = 0; i < 4; i++) {
488 /* pwmcfg, tolarance mapped for i=0, i=1 to same reg */
489 if (i != 1) {
1ea6dd38 490 pwmcfg = w83627ehf_read_value(data,
08c79950 491 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 492 tolerance = w83627ehf_read_value(data,
08c79950
RM		 493 W83627EHF_REG_TOLERANCE[i]);
494 }
495 data->pwm_mode[i] =
496 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
497 ? 0 : 1;
498 data->pwm_enable[i] =
499 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
500 & 3) + 1;
1ea6dd38 501 data->pwm[i] = w83627ehf_read_value(data,
08c79950 502 W83627EHF_REG_PWM[i]);
1ea6dd38 503 data->fan_min_output[i] = w83627ehf_read_value(data,
08c79950 504 W83627EHF_REG_FAN_MIN_OUTPUT[i]);
1ea6dd38 505 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950
RM		 506 W83627EHF_REG_FAN_STOP_TIME[i]);
507 data->target_temp[i] =
1ea6dd38 508 w83627ehf_read_value(data,
08c79950
RM		 509 W83627EHF_REG_TARGET[i]) &
510 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
511 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
512 & 0x0f;
513 }
514
08e7e278 515 /* Measured temperatures and limits */
1ea6dd38 516 data->temp1 = w83627ehf_read_value(data,
08e7e278 517 W83627EHF_REG_TEMP1);
1ea6dd38 518 data->temp1_max = w83627ehf_read_value(data,
08e7e278 519 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 520 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 521 W83627EHF_REG_TEMP1_HYST);
522 for (i = 0; i < 2; i++) {
1ea6dd38 523 data->temp[i] = w83627ehf_read_value(data,
08e7e278 524 W83627EHF_REG_TEMP[i]);
1ea6dd38 525 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 526 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 527 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 528 W83627EHF_REG_TEMP_HYST[i]);
529 }
530
1ea6dd38 531 data->alarms = w83627ehf_read_value(data,
a4589dbb 532 W83627EHF_REG_ALARM1) |
1ea6dd38 533 (w83627ehf_read_value(data,
a4589dbb 534 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 535 (w83627ehf_read_value(data,
a4589dbb
JD		 536 W83627EHF_REG_ALARM3) << 16);
537
08e7e278
JD		 538 data->last_updated = jiffies;
539 data->valid = 1;
540 }
541
9a61bf63 542 mutex_unlock(&data->update_lock);
08e7e278
JD		 543 return data;
544}
545
546/*
547 * Sysfs callback functions
548 */
cf0676fe
RM		 549#define show_in_reg(reg) \
550static ssize_t \
551show_##reg(struct device *dev, struct device_attribute *attr, \
552 char *buf) \
553{ \
554 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
555 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
556 int nr = sensor_attr->index; \
557 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
558}
559show_in_reg(in)
560show_in_reg(in_min)
561show_in_reg(in_max)
562
563#define store_in_reg(REG, reg) \
564static ssize_t \
565store_in_##reg (struct device *dev, struct device_attribute *attr, \
566 const char *buf, size_t count) \
567{ \
1ea6dd38 568 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 569 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
570 int nr = sensor_attr->index; \
571 u32 val = simple_strtoul(buf, NULL, 10); \
572 \
573 mutex_lock(&data->update_lock); \
574 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 575 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 576 data->in_##reg[nr]); \
577 mutex_unlock(&data->update_lock); \
578 return count; \
579}
580
581store_in_reg(MIN, min)
582store_in_reg(MAX, max)
583
a4589dbb
JD		 584static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
585{
586 struct w83627ehf_data *data = w83627ehf_update_device(dev);
587 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
588 int nr = sensor_attr->index;
589 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
590}
591
cf0676fe
RM		 592static struct sensor_device_attribute sda_in_input[] = {
593 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
594 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
595 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
596 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
597 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
598 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
599 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
600 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
601 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
602 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
603};
604
a4589dbb
JD		 605static struct sensor_device_attribute sda_in_alarm[] = {
606 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
607 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
608 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
609 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
610 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
611 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
612 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
613 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
614 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
615 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
616};
617
cf0676fe
RM		 618static struct sensor_device_attribute sda_in_min[] = {
619 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
620 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
621 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
622 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
623 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
624 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
625 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
626 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
627 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
628 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
629};
630
631static struct sensor_device_attribute sda_in_max[] = {
632 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
633 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
634 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
635 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
636 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
637 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
638 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
639 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
640 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
641 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
642};
643
08e7e278
JD		 644#define show_fan_reg(reg) \
645static ssize_t \
412fec82
YM		 646show_##reg(struct device *dev, struct device_attribute *attr, \
647 char *buf) \
08e7e278
JD		 648{ \
649 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 650 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
651 int nr = sensor_attr->index; \
08e7e278
JD		 652 return sprintf(buf, "%d\n", \
653 fan_from_reg(data->reg[nr], \
654 div_from_reg(data->fan_div[nr]))); \
655}
656show_fan_reg(fan);
657show_fan_reg(fan_min);
658
659static ssize_t
412fec82
YM		 660show_fan_div(struct device *dev, struct device_attribute *attr,
661 char *buf)
08e7e278
JD		 662{
663 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 664 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
665 int nr = sensor_attr->index;
666 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 667}
668
669static ssize_t
412fec82
YM		 670store_fan_min(struct device *dev, struct device_attribute *attr,
671 const char *buf, size_t count)
08e7e278 672{
1ea6dd38 673 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 674 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
675 int nr = sensor_attr->index;
08e7e278
JD		 676 unsigned int val = simple_strtoul(buf, NULL, 10);
677 unsigned int reg;
678 u8 new_div;
679
9a61bf63 680 mutex_lock(&data->update_lock);
08e7e278
JD		 681 if (!val) {
682 /* No min limit, alarm disabled */
683 data->fan_min[nr] = 255;
684 new_div = data->fan_div[nr]; /* No change */
685 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
686 } else if ((reg = 1350000U / val) >= 128 * 255) {
687 /* Speed below this value cannot possibly be represented,
688 even with the highest divider (128) */
689 data->fan_min[nr] = 254;
690 new_div = 7; /* 128 == (1 << 7) */
691 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
692 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
693 } else if (!reg) {
694 /* Speed above this value cannot possibly be represented,
695 even with the lowest divider (1) */
696 data->fan_min[nr] = 1;
697 new_div = 0; /* 1 == (1 << 0) */
698 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 699 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 700 } else {
701 /* Automatically pick the best divider, i.e. the one such
702 that the min limit will correspond to a register value
703 in the 96..192 range */
704 new_div = 0;
705 while (reg > 192 && new_div < 7) {
706 reg >>= 1;
707 new_div++;
708 }
709 data->fan_min[nr] = reg;
710 }
711
712 /* Write both the fan clock divider (if it changed) and the new
713 fan min (unconditionally) */
714 if (new_div != data->fan_div[nr]) {
158ce075
JD		 715 /* Preserve the fan speed reading */
716 if (data->fan[nr] != 0xff) {
717 if (new_div > data->fan_div[nr])
718 data->fan[nr] >>= new_div - data->fan_div[nr];
719 else if (data->fan[nr] & 0x80)
720 data->fan[nr] = 0xff;
721 else
722 data->fan[nr] <<= data->fan_div[nr] - new_div;
723 }
08e7e278
JD		 724
725 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
726 nr + 1, div_from_reg(data->fan_div[nr]),
727 div_from_reg(new_div));
728 data->fan_div[nr] = new_div;
1ea6dd38 729 w83627ehf_write_fan_div(data, nr);
08e7e278 730 }
1ea6dd38 731 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 732 data->fan_min[nr]);
9a61bf63 733 mutex_unlock(&data->update_lock);
08e7e278
JD		 734
735 return count;
736}
737
412fec82
YM		 738static struct sensor_device_attribute sda_fan_input[] = {
739 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
740 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
741 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
742 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
743 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
744};
08e7e278 745
a4589dbb
JD		 746static struct sensor_device_attribute sda_fan_alarm[] = {
747 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
748 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
749 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
750 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
751 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
752};
753
412fec82
YM		 754static struct sensor_device_attribute sda_fan_min[] = {
755 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
756 store_fan_min, 0),
757 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
758 store_fan_min, 1),
759 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
760 store_fan_min, 2),
761 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
762 store_fan_min, 3),
763 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
764 store_fan_min, 4),
765};
08e7e278 766
412fec82
YM		 767static struct sensor_device_attribute sda_fan_div[] = {
768 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
769 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
770 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
771 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
772 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
773};
774
08e7e278
JD		 775#define show_temp1_reg(reg) \
776static ssize_t \
6f637a64
GKH		 777show_##reg(struct device *dev, struct device_attribute *attr, \
778 char *buf) \
08e7e278
JD		 779{ \
780 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
781 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
782}
783show_temp1_reg(temp1);
784show_temp1_reg(temp1_max);
785show_temp1_reg(temp1_max_hyst);
786
787#define store_temp1_reg(REG, reg) \
788static ssize_t \
6f637a64
GKH		 789store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
790 const char *buf, size_t count) \
08e7e278 791{ \
1ea6dd38 792 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08e7e278
JD		 793 u32 val = simple_strtoul(buf, NULL, 10); \
794 \
9a61bf63 795 mutex_lock(&data->update_lock); \
08c79950 796 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 797 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 798 data->temp1_##reg); \
9a61bf63 799 mutex_unlock(&data->update_lock); \
08e7e278
JD		 800 return count; \
801}
802store_temp1_reg(OVER, max);
803store_temp1_reg(HYST, max_hyst);
804
08e7e278
JD		 805#define show_temp_reg(reg) \
806static ssize_t \
412fec82
YM		 807show_##reg(struct device *dev, struct device_attribute *attr, \
808 char *buf) \
08e7e278
JD		 809{ \
810 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 811 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
812 int nr = sensor_attr->index; \
08e7e278
JD		 813 return sprintf(buf, "%d\n", \
814 LM75_TEMP_FROM_REG(data->reg[nr])); \
815}
816show_temp_reg(temp);
817show_temp_reg(temp_max);
818show_temp_reg(temp_max_hyst);
819
820#define store_temp_reg(REG, reg) \
821static ssize_t \
412fec82
YM		 822store_##reg(struct device *dev, struct device_attribute *attr, \
823 const char *buf, size_t count) \
08e7e278 824{ \
1ea6dd38 825 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 826 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
827 int nr = sensor_attr->index; \
08e7e278
JD		 828 u32 val = simple_strtoul(buf, NULL, 10); \
829 \
9a61bf63 830 mutex_lock(&data->update_lock); \
08e7e278 831 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 832 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 833 data->reg[nr]); \
9a61bf63 834 mutex_unlock(&data->update_lock); \
08e7e278
JD		 835 return count; \
836}
837store_temp_reg(OVER, temp_max);
838store_temp_reg(HYST, temp_max_hyst);
839
412fec82
YM		 840static struct sensor_device_attribute sda_temp[] = {
841 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
842 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
843 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
844 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
845 store_temp1_max, 0),
846 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
847 store_temp_max, 0),
848 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
849 store_temp_max, 1),
850 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
851 store_temp1_max_hyst, 0),
852 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
853 store_temp_max_hyst, 0),
854 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
855 store_temp_max_hyst, 1),
a4589dbb
JD		 856 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
857 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
858 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
412fec82 859};
08e7e278 860
08c79950
RM		 861#define show_pwm_reg(reg) \
862static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
863 char *buf) \
864{ \
865 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
866 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
867 int nr = sensor_attr->index; \
868 return sprintf(buf, "%d\n", data->reg[nr]); \
869}
870
871show_pwm_reg(pwm_mode)
872show_pwm_reg(pwm_enable)
873show_pwm_reg(pwm)
874
875static ssize_t
876store_pwm_mode(struct device *dev, struct device_attribute *attr,
877 const char *buf, size_t count)
878{
1ea6dd38 879 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 880 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
881 int nr = sensor_attr->index;
882 u32 val = simple_strtoul(buf, NULL, 10);
883 u16 reg;
884
885 if (val > 1)
886 return -EINVAL;
887 mutex_lock(&data->update_lock);
1ea6dd38 888 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 889 data->pwm_mode[nr] = val;
890 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
891 if (!val)
892 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 893 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 894 mutex_unlock(&data->update_lock);
895 return count;
896}
897
898static ssize_t
899store_pwm(struct device *dev, struct device_attribute *attr,
900 const char *buf, size_t count)
901{
1ea6dd38 902 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 903 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
904 int nr = sensor_attr->index;
905 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
906
907 mutex_lock(&data->update_lock);
908 data->pwm[nr] = val;
1ea6dd38 909 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 910 mutex_unlock(&data->update_lock);
911 return count;
912}
913
914static ssize_t
915store_pwm_enable(struct device *dev, struct device_attribute *attr,
916 const char *buf, size_t count)
917{
1ea6dd38 918 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 919 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
920 int nr = sensor_attr->index;
921 u32 val = simple_strtoul(buf, NULL, 10);
922 u16 reg;
923
924 if (!val || (val > 2)) /* only modes 1 and 2 are supported */
925 return -EINVAL;
926 mutex_lock(&data->update_lock);
1ea6dd38 927 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 928 data->pwm_enable[nr] = val;
929 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
930 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 931 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 932 mutex_unlock(&data->update_lock);
933 return count;
934}
935
936
937#define show_tol_temp(reg) \
938static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
939 char *buf) \
940{ \
941 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
942 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
943 int nr = sensor_attr->index; \
944 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
945}
946
947show_tol_temp(tolerance)
948show_tol_temp(target_temp)
949
950static ssize_t
951store_target_temp(struct device *dev, struct device_attribute *attr,
952 const char *buf, size_t count)
953{
1ea6dd38 954 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 955 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
956 int nr = sensor_attr->index;
957 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
958
959 mutex_lock(&data->update_lock);
960 data->target_temp[nr] = val;
1ea6dd38 961 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 962 mutex_unlock(&data->update_lock);
963 return count;
964}
965
966static ssize_t
967store_tolerance(struct device *dev, struct device_attribute *attr,
968 const char *buf, size_t count)
969{
1ea6dd38 970 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 971 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
972 int nr = sensor_attr->index;
973 u16 reg;
974 /* Limit the temp to 0C - 15C */
975 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
976
977 mutex_lock(&data->update_lock);
1ea6dd38 978 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 979 data->tolerance[nr] = val;
980 if (nr == 1)
981 reg = (reg & 0x0f) | (val << 4);
982 else
983 reg = (reg & 0xf0) | val;
1ea6dd38 984 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 985 mutex_unlock(&data->update_lock);
986 return count;
987}
988
989static struct sensor_device_attribute sda_pwm[] = {
990 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
991 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
992 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
993 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
994};
995
996static struct sensor_device_attribute sda_pwm_mode[] = {
997 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
998 store_pwm_mode, 0),
999 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1000 store_pwm_mode, 1),
1001 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1002 store_pwm_mode, 2),
1003 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1004 store_pwm_mode, 3),
1005};
1006
1007static struct sensor_device_attribute sda_pwm_enable[] = {
1008 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1009 store_pwm_enable, 0),
1010 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1011 store_pwm_enable, 1),
1012 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1013 store_pwm_enable, 2),
1014 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1015 store_pwm_enable, 3),
1016};
1017
1018static struct sensor_device_attribute sda_target_temp[] = {
1019 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1020 store_target_temp, 0),
1021 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1022 store_target_temp, 1),
1023 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1024 store_target_temp, 2),
1025 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1026 store_target_temp, 3),
1027};
1028
1029static struct sensor_device_attribute sda_tolerance[] = {
1030 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1031 store_tolerance, 0),
1032 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1033 store_tolerance, 1),
1034 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1035 store_tolerance, 2),
1036 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1037 store_tolerance, 3),
1038};
1039
08c79950
RM		 1040/* Smart Fan registers */
1041
1042#define fan_functions(reg, REG) \
1043static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1044 char *buf) \
1045{ \
1046 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1047 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1048 int nr = sensor_attr->index; \
1049 return sprintf(buf, "%d\n", data->reg[nr]); \
1050}\
1051static ssize_t \
1052store_##reg(struct device *dev, struct device_attribute *attr, \
1053 const char *buf, size_t count) \
1054{\
1ea6dd38 1055 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1056 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1057 int nr = sensor_attr->index; \
1058 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1059 mutex_lock(&data->update_lock); \
1060 data->reg[nr] = val; \
1ea6dd38 1061 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1062 mutex_unlock(&data->update_lock); \
1063 return count; \
1064}
1065
1066fan_functions(fan_min_output, FAN_MIN_OUTPUT)
1067
1068#define fan_time_functions(reg, REG) \
1069static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1070 char *buf) \
1071{ \
1072 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1073 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1074 int nr = sensor_attr->index; \
1075 return sprintf(buf, "%d\n", \
1076 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1077} \
1078\
1079static ssize_t \
1080store_##reg(struct device *dev, struct device_attribute *attr, \
1081 const char *buf, size_t count) \
1082{ \
1ea6dd38 1083 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1084 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1085 int nr = sensor_attr->index; \
1086 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1087 data->pwm_mode[nr]); \
1088 mutex_lock(&data->update_lock); \
1089 data->reg[nr] = val; \
1ea6dd38 1090 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1091 mutex_unlock(&data->update_lock); \
1092 return count; \
1093} \
1094
1095fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1096
1ea6dd38
DH		 1097static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1098 char *buf)
1099{
1100 struct w83627ehf_data *data = dev_get_drvdata(dev);
1101
1102 return sprintf(buf, "%s\n", data->name);
1103}
1104static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1105
1106static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1107 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1108 store_fan_stop_time, 3),
1109 SENSOR_ATTR(pwm4_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1110 store_fan_min_output, 3),
1111};
1112
1113static struct sensor_device_attribute sda_sf3_arrays[] = {
1114 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1115 store_fan_stop_time, 0),
1116 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1117 store_fan_stop_time, 1),
1118 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1119 store_fan_stop_time, 2),
1120 SENSOR_ATTR(pwm1_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1121 store_fan_min_output, 0),
1122 SENSOR_ATTR(pwm2_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1123 store_fan_min_output, 1),
1124 SENSOR_ATTR(pwm3_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1125 store_fan_min_output, 2),
1126};
1127
08e7e278 1128/*
1ea6dd38 1129 * Driver and device management
08e7e278
JD		 1130 */
1131
c18beb5b
DH		 1132static void w83627ehf_device_remove_files(struct device *dev)
1133{
1134 /* some entries in the following arrays may not have been used in
1135 * device_create_file(), but device_remove_file() will ignore them */
1136 int i;
1ea6dd38 1137 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1138
1139 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1140 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1141 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1142 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1143 for (i = 0; i < data->in_num; i++) {
c18beb5b
DH		 1144 device_remove_file(dev, &sda_in_input[i].dev_attr);
1145 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1146 device_remove_file(dev, &sda_in_min[i].dev_attr);
1147 device_remove_file(dev, &sda_in_max[i].dev_attr);
1148 }
1149 for (i = 0; i < 5; i++) {
1150 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1151 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1152 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1153 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1154 }
1155 for (i = 0; i < 4; i++) {
1156 device_remove_file(dev, &sda_pwm[i].dev_attr);
1157 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1158 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1159 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1160 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1161 }
1162 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
1163 device_remove_file(dev, &sda_temp[i].dev_attr);
c18beb5b 1164
1ea6dd38
DH		 1165 device_remove_file(dev, &dev_attr_name);
1166}
08e7e278 1167
1ea6dd38
DH		 1168/* Get the monitoring functions started */
1169static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1170{
1171 int i;
1172 u8 tmp;
1173
1174 /* Start monitoring is needed */
1ea6dd38 1175 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1176 if (!(tmp & 0x01))
1ea6dd38 1177 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1178 tmp | 0x01);
1179
1180 /* Enable temp2 and temp3 if needed */
1181 for (i = 0; i < 2; i++) {
1ea6dd38 1182 tmp = w83627ehf_read_value(data,
08e7e278
JD		 1183 W83627EHF_REG_TEMP_CONFIG[i]);
1184 if (tmp & 0x01)
1ea6dd38 1185 w83627ehf_write_value(data,
08e7e278
JD		 1186 W83627EHF_REG_TEMP_CONFIG[i],
1187 tmp & 0xfe);
1188 }
1189}
1190
1ea6dd38 1191static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1192{
1ea6dd38
DH		 1193 struct device *dev = &pdev->dev;
1194 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1195 struct w83627ehf_data *data;
1ea6dd38 1196 struct resource *res;
08c79950 1197 u8 fan4pin, fan5pin;
08e7e278
JD		 1198 int i, err = 0;
1199
1ea6dd38
DH		 1200 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1201 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1202 err = -EBUSY;
1ea6dd38
DH		 1203 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1204 (unsigned long)res->start,
1205 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1206 goto exit;
1207 }
1208
ba9c2e8d 1209 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1210 err = -ENOMEM;
1211 goto exit_release;
1212 }
08e7e278 1213
1ea6dd38 1214 data->addr = res->start;
9a61bf63 1215 mutex_init(&data->lock);
9a61bf63 1216 mutex_init(&data->update_lock);
1ea6dd38
DH		 1217 data->name = w83627ehf_device_names[sio_data->kind];
1218 platform_set_drvdata(pdev, data);
08e7e278 1219
1ea6dd38
DH		 1220 /* 627EHG and 627EHF have 10 voltage inputs; DHG has 9 */
1221 data->in_num = (sio_data->kind == w83627dhg) ? 9 : 10;
08e7e278
JD		 1222
1223 /* Initialize the chip */
1ea6dd38 1224 w83627ehf_init_device(data);
08e7e278
JD		 1225
1226 /* A few vars need to be filled upon startup */
1227 for (i = 0; i < 5; i++)
1ea6dd38 1228 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 1229 W83627EHF_REG_FAN_MIN[i]);
1230
08c79950
RM		 1231 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1232
1ea6dd38
DH		 1233 superio_enter(sio_data->sioreg);
1234 fan5pin = superio_inb(sio_data->sioreg, 0x24) & 0x2;
1235 fan4pin = superio_inb(sio_data->sioreg, 0x29) & 0x6;
1236 superio_exit(sio_data->sioreg);
08c79950 1237
08e7e278 1238 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1239 as fan on/off switches, but fan5 control is write only :/
1240 We assume that if the serial interface is disabled, designers
1241 connected fan5 as input unless they are emitting log 1, which
1242 is not the default. */
08c79950 1243
08e7e278 1244 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1245 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
08c79950 1246 if ((i & (1 << 2)) && (!fan4pin))
08e7e278 1247 data->has_fan |= (1 << 3);
14992c7e 1248 if (!(i & (1 << 1)) && (!fan5pin))
08e7e278
JD		 1249 data->has_fan |= (1 << 4);
1250
1251 /* Register sysfs hooks */
08c79950 1252 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1253 if ((err = device_create_file(dev,
1254 &sda_sf3_arrays[i].dev_attr)))
1255 goto exit_remove;
08c79950
RM		 1256
1257 /* if fan4 is enabled create the sf3 files for it */
1258 if (data->has_fan & (1 << 3))
c18beb5b
DH		 1259 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1260 if ((err = device_create_file(dev,
1261 &sda_sf3_arrays_fan4[i].dev_attr)))
1262 goto exit_remove;
1263 }
08c79950 1264
1ea6dd38 1265 for (i = 0; i < data->in_num; i++)
c18beb5b
DH		 1266 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1267 || (err = device_create_file(dev,
1268 &sda_in_alarm[i].dev_attr))
1269 || (err = device_create_file(dev,
1270 &sda_in_min[i].dev_attr))
1271 || (err = device_create_file(dev,
1272 &sda_in_max[i].dev_attr)))
1273 goto exit_remove;
cf0676fe 1274
412fec82 1275 for (i = 0; i < 5; i++) {
08c79950 1276 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1277 if ((err = device_create_file(dev,
1278 &sda_fan_input[i].dev_attr))
1279 || (err = device_create_file(dev,
1280 &sda_fan_alarm[i].dev_attr))
1281 || (err = device_create_file(dev,
1282 &sda_fan_div[i].dev_attr))
1283 || (err = device_create_file(dev,
1284 &sda_fan_min[i].dev_attr)))
1285 goto exit_remove;
1286 if (i < 4 && /* w83627ehf only has 4 pwm */
1287 ((err = device_create_file(dev,
1288 &sda_pwm[i].dev_attr))
1289 || (err = device_create_file(dev,
1290 &sda_pwm_mode[i].dev_attr))
1291 || (err = device_create_file(dev,
1292 &sda_pwm_enable[i].dev_attr))
1293 || (err = device_create_file(dev,
1294 &sda_target_temp[i].dev_attr))
1295 || (err = device_create_file(dev,
1296 &sda_tolerance[i].dev_attr))))
1297 goto exit_remove;
08c79950 1298 }
08e7e278 1299 }
08c79950 1300
412fec82 1301 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
c18beb5b
DH		 1302 if ((err = device_create_file(dev, &sda_temp[i].dev_attr)))
1303 goto exit_remove;
1304
1ea6dd38
DH		 1305 err = device_create_file(dev, &dev_attr_name);
1306 if (err)
1307 goto exit_remove;
1308
c18beb5b
DH		 1309 data->class_dev = hwmon_device_register(dev);
1310 if (IS_ERR(data->class_dev)) {
1311 err = PTR_ERR(data->class_dev);
1312 goto exit_remove;
1313 }
08e7e278
JD		 1314
1315 return 0;
1316
c18beb5b
DH		 1317exit_remove:
1318 w83627ehf_device_remove_files(dev);
08e7e278 1319 kfree(data);
1ea6dd38 1320 platform_set_drvdata(pdev, NULL);
08e7e278 1321exit_release:
1ea6dd38 1322 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1323exit:
1324 return err;
1325}
1326
1ea6dd38 1327static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1328{
1ea6dd38 1329 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1330
943b0830 1331 hwmon_device_unregister(data->class_dev);
1ea6dd38
DH		 1332 w83627ehf_device_remove_files(&pdev->dev);
1333 release_region(data->addr, IOREGION_LENGTH);
1334 platform_set_drvdata(pdev, NULL);
943b0830 1335 kfree(data);
08e7e278
JD		 1336
1337 return 0;
1338}
1339
1ea6dd38 1340static struct platform_driver w83627ehf_driver = {
cdaf7934 1341 .driver = {
87218842 1342 .owner = THIS_MODULE,
1ea6dd38 1343 .name = DRVNAME,
cdaf7934 1344 },
1ea6dd38
DH		 1345 .probe = w83627ehf_probe,
1346 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1347};
1348
1ea6dd38
DH		 1349/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1350static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1351 struct w83627ehf_sio_data *sio_data)
08e7e278 1352{
1ea6dd38
DH		 1353 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1354 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1355 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
1356
08e7e278 1357 u16 val;
1ea6dd38 1358 const char *sio_name;
08e7e278 1359
1ea6dd38 1360 superio_enter(sioaddr);
08e7e278 1361
1ea6dd38
DH		 1362 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1363 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1364 switch (val & SIO_ID_MASK) {
657c93b1 1365 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1366 sio_data->kind = w83627ehf;
1367 sio_name = sio_name_W83627EHF;
1368 break;
657c93b1 1369 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1370 sio_data->kind = w83627ehf;
1371 sio_name = sio_name_W83627EHG;
1372 break;
1373 case SIO_W83627DHG_ID:
1374 sio_data->kind = w83627dhg;
1375 sio_name = sio_name_W83627DHG;
657c93b1
DH		 1376 break;
1377 default:
1ea6dd38 1378 pr_info(DRVNAME ": unsupported chip ID: 0x%04x\n",
657c93b1 1379 val);
1ea6dd38 1380 superio_exit(sioaddr);
08e7e278
JD		 1381 return -ENODEV;
1382 }
1383
1ea6dd38
DH		 1384 /* We have a known chip, find the HWM I/O address */
1385 superio_select(sioaddr, W83627EHF_LD_HWM);
1386 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1387 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1388 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1389 if (*addr == 0) {
1ea6dd38 1390 superio_exit(sioaddr);
08e7e278
JD		 1391 return -ENODEV;
1392 }
1393
1394 /* Activate logical device if needed */
1ea6dd38 1395 val = superio_inb(sioaddr, SIO_REG_ENABLE);
08e7e278 1396 if (!(val & 0x01))
1ea6dd38
DH		 1397 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
1398
1399 superio_exit(sioaddr);
1400 pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
1401 sio_data->sioreg = sioaddr;
08e7e278 1402
08e7e278
JD		 1403 return 0;
1404}
1405
1ea6dd38
DH		 1406/* when Super-I/O functions move to a separate file, the Super-I/O
1407 * bus will manage the lifetime of the device and this module will only keep
1408 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1409 * must keep track of the device */
1410static struct platform_device *pdev;
1411
08e7e278
JD		 1412static int __init sensors_w83627ehf_init(void)
1413{
1ea6dd38
DH		 1414 int err;
1415 unsigned short address;
1416 struct resource res;
1417 struct w83627ehf_sio_data sio_data;
1418
1419 /* initialize sio_data->kind and sio_data->sioreg.
1420 *
1421 * when Super-I/O functions move to a separate file, the Super-I/O
1422 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1423 * w83627ehf hardware monitor, and call probe() */
1424 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1425 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1426 return -ENODEV;
1427
1ea6dd38
DH		 1428 err = platform_driver_register(&w83627ehf_driver);
1429 if (err)
1430 goto exit;
1431
1432 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1433 err = -ENOMEM;
1434 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1435 goto exit_unregister;
1436 }
1437
1438 err = platform_device_add_data(pdev, &sio_data,
1439 sizeof(struct w83627ehf_sio_data));
1440 if (err) {
1441 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1442 goto exit_device_put;
1443 }
1444
1445 memset(&res, 0, sizeof(res));
1446 res.name = DRVNAME;
1447 res.start = address + IOREGION_OFFSET;
1448 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1449 res.flags = IORESOURCE_IO;
1450 err = platform_device_add_resources(pdev, &res, 1);
1451 if (err) {
1452 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1453 "(%d)\n", err);
1454 goto exit_device_put;
1455 }
1456
1457 /* platform_device_add calls probe() */
1458 err = platform_device_add(pdev);
1459 if (err) {
1460 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1461 err);
1462 goto exit_device_put;
1463 }
1464
1465 return 0;
1466
1467exit_device_put:
1468 platform_device_put(pdev);
1469exit_unregister:
1470 platform_driver_unregister(&w83627ehf_driver);
1471exit:
1472 return err;
08e7e278
JD		 1473}
1474
1475static void __exit sensors_w83627ehf_exit(void)
1476{
1ea6dd38
DH		 1477 platform_device_unregister(pdev);
1478 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1479}
1480
1481MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1482MODULE_DESCRIPTION("W83627EHF driver");
1483MODULE_LICENSE("GPL");
1484
1485module_init(sensors_w83627ehf_init);
1486module_exit(sensors_w83627ehf_exit);
Linux 6.x block layer and io_uring tree(s)