drm/vmwgfx: Replace SurfaceDMA usage with SurfaceCopy in 2D VMs
[linux-2.6-block.git] / drivers / gpu / drm / vmwgfx / vmwgfx_execbuf.c
CommitLineData
fb1d9738
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1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_drv.h"
29#include "vmwgfx_reg.h"
760285e7
DH
30#include <drm/ttm/ttm_bo_api.h>
31#include <drm/ttm/ttm_placement.h>
fb1d9738 32
c0951b79
TH
33#define VMW_RES_HT_ORDER 12
34
35/**
36 * struct vmw_resource_relocation - Relocation info for resources
37 *
38 * @head: List head for the software context's relocation list.
39 * @res: Non-ref-counted pointer to the resource.
40 * @offset: Offset of 4 byte entries into the command buffer where the
41 * id that needs fixup is located.
42 */
43struct vmw_resource_relocation {
44 struct list_head head;
45 const struct vmw_resource *res;
46 unsigned long offset;
47};
48
49/**
50 * struct vmw_resource_val_node - Validation info for resources
51 *
52 * @head: List head for the software context's resource list.
53 * @hash: Hash entry for quick resouce to val_node lookup.
54 * @res: Ref-counted pointer to the resource.
55 * @switch_backup: Boolean whether to switch backup buffer on unreserve.
56 * @new_backup: Refcounted pointer to the new backup buffer.
b5c3b1a6
TH
57 * @staged_bindings: If @res is a context, tracks bindings set up during
58 * the command batch. Otherwise NULL.
c0951b79
TH
59 * @new_backup_offset: New backup buffer offset if @new_backup is non-NUll.
60 * @first_usage: Set to true the first time the resource is referenced in
61 * the command stream.
62 * @no_buffer_needed: Resources do not need to allocate buffer backup on
63 * reservation. The command stream will provide one.
64 */
65struct vmw_resource_val_node {
66 struct list_head head;
67 struct drm_hash_item hash;
68 struct vmw_resource *res;
69 struct vmw_dma_buffer *new_backup;
b5c3b1a6 70 struct vmw_ctx_binding_state *staged_bindings;
c0951b79
TH
71 unsigned long new_backup_offset;
72 bool first_usage;
73 bool no_buffer_needed;
74};
75
c373d4ea
TH
76/**
77 * struct vmw_cmd_entry - Describe a command for the verifier
78 *
79 * @user_allow: Whether allowed from the execbuf ioctl.
80 * @gb_disable: Whether disabled if guest-backed objects are available.
81 * @gb_enable: Whether enabled iff guest-backed objects are available.
82 */
83struct vmw_cmd_entry {
84 int (*func) (struct vmw_private *, struct vmw_sw_context *,
85 SVGA3dCmdHeader *);
86 bool user_allow;
87 bool gb_disable;
88 bool gb_enable;
89};
90
91#define VMW_CMD_DEF(_cmd, _func, _user_allow, _gb_disable, _gb_enable) \
92 [(_cmd) - SVGA_3D_CMD_BASE] = {(_func), (_user_allow),\
93 (_gb_disable), (_gb_enable)}
94
c0951b79
TH
95/**
96 * vmw_resource_unreserve - unreserve resources previously reserved for
97 * command submission.
98 *
99 * @list_head: list of resources to unreserve.
100 * @backoff: Whether command submission failed.
101 */
102static void vmw_resource_list_unreserve(struct list_head *list,
103 bool backoff)
104{
105 struct vmw_resource_val_node *val;
106
107 list_for_each_entry(val, list, head) {
108 struct vmw_resource *res = val->res;
109 struct vmw_dma_buffer *new_backup =
110 backoff ? NULL : val->new_backup;
111
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TH
112 /*
113 * Transfer staged context bindings to the
114 * persistent context binding tracker.
115 */
b5c3b1a6 116 if (unlikely(val->staged_bindings)) {
76c7d18b
TH
117 if (!backoff) {
118 vmw_context_binding_state_transfer
119 (val->res, val->staged_bindings);
120 }
b5c3b1a6
TH
121 kfree(val->staged_bindings);
122 val->staged_bindings = NULL;
123 }
c0951b79
TH
124 vmw_resource_unreserve(res, new_backup,
125 val->new_backup_offset);
126 vmw_dmabuf_unreference(&val->new_backup);
127 }
128}
129
130
131/**
132 * vmw_resource_val_add - Add a resource to the software context's
133 * resource list if it's not already on it.
134 *
135 * @sw_context: Pointer to the software context.
136 * @res: Pointer to the resource.
137 * @p_node On successful return points to a valid pointer to a
138 * struct vmw_resource_val_node, if non-NULL on entry.
139 */
140static int vmw_resource_val_add(struct vmw_sw_context *sw_context,
141 struct vmw_resource *res,
142 struct vmw_resource_val_node **p_node)
143{
144 struct vmw_resource_val_node *node;
145 struct drm_hash_item *hash;
146 int ret;
147
148 if (likely(drm_ht_find_item(&sw_context->res_ht, (unsigned long) res,
149 &hash) == 0)) {
150 node = container_of(hash, struct vmw_resource_val_node, hash);
151 node->first_usage = false;
152 if (unlikely(p_node != NULL))
153 *p_node = node;
154 return 0;
155 }
156
157 node = kzalloc(sizeof(*node), GFP_KERNEL);
158 if (unlikely(node == NULL)) {
159 DRM_ERROR("Failed to allocate a resource validation "
160 "entry.\n");
161 return -ENOMEM;
162 }
163
164 node->hash.key = (unsigned long) res;
165 ret = drm_ht_insert_item(&sw_context->res_ht, &node->hash);
166 if (unlikely(ret != 0)) {
167 DRM_ERROR("Failed to initialize a resource validation "
168 "entry.\n");
169 kfree(node);
170 return ret;
171 }
172 list_add_tail(&node->head, &sw_context->resource_list);
173 node->res = vmw_resource_reference(res);
174 node->first_usage = true;
175
176 if (unlikely(p_node != NULL))
177 *p_node = node;
178
179 return 0;
180}
181
30f82d81
TH
182/**
183 * vmw_resource_context_res_add - Put resources previously bound to a context on
184 * the validation list
185 *
186 * @dev_priv: Pointer to a device private structure
187 * @sw_context: Pointer to a software context used for this command submission
188 * @ctx: Pointer to the context resource
189 *
190 * This function puts all resources that were previously bound to @ctx on
191 * the resource validation list. This is part of the context state reemission
192 */
193static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
194 struct vmw_sw_context *sw_context,
195 struct vmw_resource *ctx)
196{
197 struct list_head *binding_list;
198 struct vmw_ctx_binding *entry;
199 int ret = 0;
200 struct vmw_resource *res;
201
202 mutex_lock(&dev_priv->binding_mutex);
203 binding_list = vmw_context_binding_list(ctx);
204
205 list_for_each_entry(entry, binding_list, ctx_list) {
206 res = vmw_resource_reference_unless_doomed(entry->bi.res);
207 if (unlikely(res == NULL))
208 continue;
209
210 ret = vmw_resource_val_add(sw_context, entry->bi.res, NULL);
211 vmw_resource_unreference(&res);
212 if (unlikely(ret != 0))
213 break;
214 }
215
216 mutex_unlock(&dev_priv->binding_mutex);
217 return ret;
218}
219
c0951b79
TH
220/**
221 * vmw_resource_relocation_add - Add a relocation to the relocation list
222 *
223 * @list: Pointer to head of relocation list.
224 * @res: The resource.
225 * @offset: Offset into the command buffer currently being parsed where the
226 * id that needs fixup is located. Granularity is 4 bytes.
227 */
228static int vmw_resource_relocation_add(struct list_head *list,
229 const struct vmw_resource *res,
230 unsigned long offset)
231{
232 struct vmw_resource_relocation *rel;
233
234 rel = kmalloc(sizeof(*rel), GFP_KERNEL);
235 if (unlikely(rel == NULL)) {
236 DRM_ERROR("Failed to allocate a resource relocation.\n");
237 return -ENOMEM;
238 }
239
240 rel->res = res;
241 rel->offset = offset;
242 list_add_tail(&rel->head, list);
243
244 return 0;
245}
246
247/**
248 * vmw_resource_relocations_free - Free all relocations on a list
249 *
250 * @list: Pointer to the head of the relocation list.
251 */
252static void vmw_resource_relocations_free(struct list_head *list)
253{
254 struct vmw_resource_relocation *rel, *n;
255
256 list_for_each_entry_safe(rel, n, list, head) {
257 list_del(&rel->head);
258 kfree(rel);
259 }
260}
261
262/**
263 * vmw_resource_relocations_apply - Apply all relocations on a list
264 *
265 * @cb: Pointer to the start of the command buffer bein patch. This need
266 * not be the same buffer as the one being parsed when the relocation
267 * list was built, but the contents must be the same modulo the
268 * resource ids.
269 * @list: Pointer to the head of the relocation list.
270 */
271static void vmw_resource_relocations_apply(uint32_t *cb,
272 struct list_head *list)
273{
274 struct vmw_resource_relocation *rel;
275
d5bde956
TH
276 list_for_each_entry(rel, list, head) {
277 if (likely(rel->res != NULL))
278 cb[rel->offset] = rel->res->id;
279 else
280 cb[rel->offset] = SVGA_3D_CMD_NOP;
281 }
c0951b79
TH
282}
283
fb1d9738
JB
284static int vmw_cmd_invalid(struct vmw_private *dev_priv,
285 struct vmw_sw_context *sw_context,
286 SVGA3dCmdHeader *header)
287{
288 return capable(CAP_SYS_ADMIN) ? : -EINVAL;
289}
290
291static int vmw_cmd_ok(struct vmw_private *dev_priv,
292 struct vmw_sw_context *sw_context,
293 SVGA3dCmdHeader *header)
294{
295 return 0;
296}
297
e2fa3a76
TH
298/**
299 * vmw_bo_to_validate_list - add a bo to a validate list
300 *
301 * @sw_context: The software context used for this command submission batch.
302 * @bo: The buffer object to add.
96c5f0df 303 * @validate_as_mob: Validate this buffer as a MOB.
e2fa3a76
TH
304 * @p_val_node: If non-NULL Will be updated with the validate node number
305 * on return.
306 *
307 * Returns -EINVAL if the limit of number of buffer objects per command
308 * submission is reached.
309 */
310static int vmw_bo_to_validate_list(struct vmw_sw_context *sw_context,
311 struct ttm_buffer_object *bo,
96c5f0df 312 bool validate_as_mob,
e2fa3a76
TH
313 uint32_t *p_val_node)
314{
315 uint32_t val_node;
c0951b79 316 struct vmw_validate_buffer *vval_buf;
e2fa3a76 317 struct ttm_validate_buffer *val_buf;
c0951b79
TH
318 struct drm_hash_item *hash;
319 int ret;
e2fa3a76 320
c0951b79
TH
321 if (likely(drm_ht_find_item(&sw_context->res_ht, (unsigned long) bo,
322 &hash) == 0)) {
323 vval_buf = container_of(hash, struct vmw_validate_buffer,
324 hash);
96c5f0df
TH
325 if (unlikely(vval_buf->validate_as_mob != validate_as_mob)) {
326 DRM_ERROR("Inconsistent buffer usage.\n");
327 return -EINVAL;
328 }
c0951b79
TH
329 val_buf = &vval_buf->base;
330 val_node = vval_buf - sw_context->val_bufs;
331 } else {
332 val_node = sw_context->cur_val_buf;
333 if (unlikely(val_node >= VMWGFX_MAX_VALIDATIONS)) {
334 DRM_ERROR("Max number of DMA buffers per submission "
335 "exceeded.\n");
336 return -EINVAL;
337 }
338 vval_buf = &sw_context->val_bufs[val_node];
339 vval_buf->hash.key = (unsigned long) bo;
340 ret = drm_ht_insert_item(&sw_context->res_ht, &vval_buf->hash);
341 if (unlikely(ret != 0)) {
342 DRM_ERROR("Failed to initialize a buffer validation "
343 "entry.\n");
344 return ret;
345 }
346 ++sw_context->cur_val_buf;
347 val_buf = &vval_buf->base;
e2fa3a76 348 val_buf->bo = ttm_bo_reference(bo);
ae9c0af2 349 val_buf->shared = false;
e2fa3a76 350 list_add_tail(&val_buf->head, &sw_context->validate_nodes);
96c5f0df 351 vval_buf->validate_as_mob = validate_as_mob;
e2fa3a76
TH
352 }
353
e2fa3a76
TH
354 if (p_val_node)
355 *p_val_node = val_node;
356
357 return 0;
358}
359
c0951b79
TH
360/**
361 * vmw_resources_reserve - Reserve all resources on the sw_context's
362 * resource list.
363 *
364 * @sw_context: Pointer to the software context.
365 *
366 * Note that since vmware's command submission currently is protected by
367 * the cmdbuf mutex, no fancy deadlock avoidance is required for resources,
368 * since only a single thread at once will attempt this.
369 */
370static int vmw_resources_reserve(struct vmw_sw_context *sw_context)
fb1d9738 371{
c0951b79 372 struct vmw_resource_val_node *val;
fb1d9738
JB
373 int ret;
374
c0951b79
TH
375 list_for_each_entry(val, &sw_context->resource_list, head) {
376 struct vmw_resource *res = val->res;
fb1d9738 377
c0951b79
TH
378 ret = vmw_resource_reserve(res, val->no_buffer_needed);
379 if (unlikely(ret != 0))
380 return ret;
381
382 if (res->backup) {
383 struct ttm_buffer_object *bo = &res->backup->base;
384
385 ret = vmw_bo_to_validate_list
96c5f0df
TH
386 (sw_context, bo,
387 vmw_resource_needs_backup(res), NULL);
c0951b79
TH
388
389 if (unlikely(ret != 0))
390 return ret;
391 }
fb1d9738 392 }
c0951b79
TH
393 return 0;
394}
fb1d9738 395
c0951b79
TH
396/**
397 * vmw_resources_validate - Validate all resources on the sw_context's
398 * resource list.
399 *
400 * @sw_context: Pointer to the software context.
401 *
402 * Before this function is called, all resource backup buffers must have
403 * been validated.
404 */
405static int vmw_resources_validate(struct vmw_sw_context *sw_context)
406{
407 struct vmw_resource_val_node *val;
408 int ret;
409
410 list_for_each_entry(val, &sw_context->resource_list, head) {
411 struct vmw_resource *res = val->res;
f18c8840 412
c0951b79
TH
413 ret = vmw_resource_validate(res);
414 if (unlikely(ret != 0)) {
415 if (ret != -ERESTARTSYS)
416 DRM_ERROR("Failed to validate resource.\n");
417 return ret;
418 }
419 }
f18c8840 420 return 0;
fb1d9738
JB
421}
422
18e4a466
TH
423
424/**
425 * vmw_cmd_res_reloc_add - Add a resource to a software context's
426 * relocation- and validation lists.
427 *
428 * @dev_priv: Pointer to a struct vmw_private identifying the device.
429 * @sw_context: Pointer to the software context.
430 * @res_type: Resource type.
431 * @id_loc: Pointer to where the id that needs translation is located.
432 * @res: Valid pointer to a struct vmw_resource.
433 * @p_val: If non null, a pointer to the struct vmw_resource_validate_node
434 * used for this resource is returned here.
435 */
436static int vmw_cmd_res_reloc_add(struct vmw_private *dev_priv,
437 struct vmw_sw_context *sw_context,
438 enum vmw_res_type res_type,
439 uint32_t *id_loc,
440 struct vmw_resource *res,
441 struct vmw_resource_val_node **p_val)
442{
443 int ret;
444 struct vmw_resource_val_node *node;
445
446 *p_val = NULL;
447 ret = vmw_resource_relocation_add(&sw_context->res_relocations,
448 res,
449 id_loc - sw_context->buf_start);
450 if (unlikely(ret != 0))
9f9cb84f 451 return ret;
18e4a466
TH
452
453 ret = vmw_resource_val_add(sw_context, res, &node);
454 if (unlikely(ret != 0))
9f9cb84f 455 return ret;
18e4a466
TH
456
457 if (res_type == vmw_res_context && dev_priv->has_mob &&
458 node->first_usage) {
459
460 /*
461 * Put contexts first on the list to be able to exit
462 * list traversal for contexts early.
463 */
464 list_del(&node->head);
465 list_add(&node->head, &sw_context->resource_list);
466
467 ret = vmw_resource_context_res_add(dev_priv, sw_context, res);
468 if (unlikely(ret != 0))
9f9cb84f 469 return ret;
18e4a466
TH
470 node->staged_bindings =
471 kzalloc(sizeof(*node->staged_bindings), GFP_KERNEL);
472 if (node->staged_bindings == NULL) {
473 DRM_ERROR("Failed to allocate context binding "
474 "information.\n");
9f9cb84f 475 return -ENOMEM;
18e4a466
TH
476 }
477 INIT_LIST_HEAD(&node->staged_bindings->list);
478 }
479
480 if (p_val)
481 *p_val = node;
482
9f9cb84f 483 return 0;
18e4a466
TH
484}
485
486
c0951b79 487/**
18e4a466 488 * vmw_cmd_res_check - Check that a resource is present and if so, put it
c0951b79
TH
489 * on the resource validate list unless it's already there.
490 *
491 * @dev_priv: Pointer to a device private structure.
492 * @sw_context: Pointer to the software context.
493 * @res_type: Resource type.
494 * @converter: User-space visisble type specific information.
d5bde956 495 * @id_loc: Pointer to the location in the command buffer currently being
c0951b79 496 * parsed from where the user-space resource id handle is located.
d5bde956
TH
497 * @p_val: Pointer to pointer to resource validalidation node. Populated
498 * on exit.
c0951b79 499 */
d5bde956 500static int
18e4a466
TH
501vmw_cmd_res_check(struct vmw_private *dev_priv,
502 struct vmw_sw_context *sw_context,
503 enum vmw_res_type res_type,
504 const struct vmw_user_resource_conv *converter,
505 uint32_t *id_loc,
506 struct vmw_resource_val_node **p_val)
fb1d9738 507{
c0951b79
TH
508 struct vmw_res_cache_entry *rcache =
509 &sw_context->res_cache[res_type];
be38ab6e 510 struct vmw_resource *res;
c0951b79
TH
511 struct vmw_resource_val_node *node;
512 int ret;
be38ab6e 513
18e4a466 514 if (*id_loc == SVGA3D_INVALID_ID) {
b5c3b1a6
TH
515 if (p_val)
516 *p_val = NULL;
517 if (res_type == vmw_res_context) {
518 DRM_ERROR("Illegal context invalid id.\n");
519 return -EINVAL;
520 }
7a73ba74 521 return 0;
b5c3b1a6 522 }
7a73ba74 523
c0951b79
TH
524 /*
525 * Fastpath in case of repeated commands referencing the same
526 * resource
527 */
7a73ba74 528
18e4a466 529 if (likely(rcache->valid && *id_loc == rcache->handle)) {
c0951b79
TH
530 const struct vmw_resource *res = rcache->res;
531
532 rcache->node->first_usage = false;
533 if (p_val)
534 *p_val = rcache->node;
535
536 return vmw_resource_relocation_add
537 (&sw_context->res_relocations, res,
d5bde956 538 id_loc - sw_context->buf_start);
be38ab6e
TH
539 }
540
c0951b79 541 ret = vmw_user_resource_lookup_handle(dev_priv,
d5bde956 542 sw_context->fp->tfile,
18e4a466 543 *id_loc,
c0951b79
TH
544 converter,
545 &res);
5bb39e81 546 if (unlikely(ret != 0)) {
c0951b79 547 DRM_ERROR("Could not find or use resource 0x%08x.\n",
18e4a466 548 (unsigned) *id_loc);
c0951b79 549 dump_stack();
5bb39e81
TH
550 return ret;
551 }
552
c0951b79
TH
553 rcache->valid = true;
554 rcache->res = res;
18e4a466 555 rcache->handle = *id_loc;
c0951b79 556
18e4a466
TH
557 ret = vmw_cmd_res_reloc_add(dev_priv, sw_context, res_type, id_loc,
558 res, &node);
c0951b79
TH
559 if (unlikely(ret != 0))
560 goto out_no_reloc;
f18c8840 561
c0951b79
TH
562 rcache->node = node;
563 if (p_val)
564 *p_val = node;
565 vmw_resource_unreference(&res);
f18c8840 566 return 0;
c0951b79
TH
567
568out_no_reloc:
569 BUG_ON(sw_context->error_resource != NULL);
570 sw_context->error_resource = res;
571
572 return ret;
fb1d9738
JB
573}
574
30f82d81
TH
575/**
576 * vmw_rebind_contexts - Rebind all resources previously bound to
577 * referenced contexts.
578 *
579 * @sw_context: Pointer to the software context.
580 *
581 * Rebind context binding points that have been scrubbed because of eviction.
582 */
583static int vmw_rebind_contexts(struct vmw_sw_context *sw_context)
584{
585 struct vmw_resource_val_node *val;
586 int ret;
587
588 list_for_each_entry(val, &sw_context->resource_list, head) {
18e4a466
TH
589 if (unlikely(!val->staged_bindings))
590 break;
30f82d81
TH
591
592 ret = vmw_context_rebind_all(val->res);
593 if (unlikely(ret != 0)) {
594 if (ret != -ERESTARTSYS)
595 DRM_ERROR("Failed to rebind context.\n");
596 return ret;
597 }
598 }
599
600 return 0;
601}
602
c0951b79
TH
603/**
604 * vmw_cmd_cid_check - Check a command header for valid context information.
605 *
606 * @dev_priv: Pointer to a device private structure.
607 * @sw_context: Pointer to the software context.
608 * @header: A command header with an embedded user-space context handle.
609 *
610 * Convenience function: Call vmw_cmd_res_check with the user-space context
611 * handle embedded in @header.
612 */
613static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
614 struct vmw_sw_context *sw_context,
615 SVGA3dCmdHeader *header)
616{
617 struct vmw_cid_cmd {
618 SVGA3dCmdHeader header;
8e67bbbc 619 uint32_t cid;
c0951b79
TH
620 } *cmd;
621
622 cmd = container_of(header, struct vmw_cid_cmd, header);
623 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
624 user_context_converter, &cmd->cid, NULL);
625}
fb1d9738
JB
626
627static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,
628 struct vmw_sw_context *sw_context,
629 SVGA3dCmdHeader *header)
630{
631 struct vmw_sid_cmd {
632 SVGA3dCmdHeader header;
633 SVGA3dCmdSetRenderTarget body;
634 } *cmd;
b5c3b1a6 635 struct vmw_resource_val_node *ctx_node;
173fb7d4 636 struct vmw_resource_val_node *res_node;
fb1d9738
JB
637 int ret;
638
b5c3b1a6
TH
639 cmd = container_of(header, struct vmw_sid_cmd, header);
640
641 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
642 user_context_converter, &cmd->body.cid,
643 &ctx_node);
fb1d9738
JB
644 if (unlikely(ret != 0))
645 return ret;
646
c0951b79
TH
647 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
648 user_surface_converter,
173fb7d4 649 &cmd->body.target.sid, &res_node);
b5c3b1a6
TH
650 if (unlikely(ret != 0))
651 return ret;
652
653 if (dev_priv->has_mob) {
654 struct vmw_ctx_bindinfo bi;
655
656 bi.ctx = ctx_node->res;
173fb7d4 657 bi.res = res_node ? res_node->res : NULL;
b5c3b1a6
TH
658 bi.bt = vmw_ctx_binding_rt;
659 bi.i1.rt_type = cmd->body.type;
660 return vmw_context_binding_add(ctx_node->staged_bindings, &bi);
661 }
662
663 return 0;
fb1d9738
JB
664}
665
666static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
667 struct vmw_sw_context *sw_context,
668 SVGA3dCmdHeader *header)
669{
670 struct vmw_sid_cmd {
671 SVGA3dCmdHeader header;
672 SVGA3dCmdSurfaceCopy body;
673 } *cmd;
674 int ret;
675
676 cmd = container_of(header, struct vmw_sid_cmd, header);
c9146cd9 677
f89c6c32
SY
678 if (!(sw_context->quirks & VMW_QUIRK_SRC_SID_OK)) {
679 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
680 user_surface_converter,
681 &cmd->body.src.sid, NULL);
682 if (ret != 0)
683 return ret;
684 }
685
686 if (sw_context->quirks & VMW_QUIRK_DST_SID_OK)
c9146cd9
TH
687 return 0;
688
c0951b79
TH
689 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
690 user_surface_converter,
691 &cmd->body.dest.sid, NULL);
fb1d9738
JB
692}
693
694static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
695 struct vmw_sw_context *sw_context,
696 SVGA3dCmdHeader *header)
697{
698 struct vmw_sid_cmd {
699 SVGA3dCmdHeader header;
700 SVGA3dCmdSurfaceStretchBlt body;
701 } *cmd;
702 int ret;
703
704 cmd = container_of(header, struct vmw_sid_cmd, header);
c0951b79
TH
705 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
706 user_surface_converter,
707 &cmd->body.src.sid, NULL);
fb1d9738
JB
708 if (unlikely(ret != 0))
709 return ret;
c0951b79
TH
710 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
711 user_surface_converter,
712 &cmd->body.dest.sid, NULL);
fb1d9738
JB
713}
714
715static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
716 struct vmw_sw_context *sw_context,
717 SVGA3dCmdHeader *header)
718{
719 struct vmw_sid_cmd {
720 SVGA3dCmdHeader header;
721 SVGA3dCmdBlitSurfaceToScreen body;
722 } *cmd;
723
724 cmd = container_of(header, struct vmw_sid_cmd, header);
0cff60c6 725
c0951b79
TH
726 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
727 user_surface_converter,
728 &cmd->body.srcImage.sid, NULL);
fb1d9738
JB
729}
730
731static int vmw_cmd_present_check(struct vmw_private *dev_priv,
732 struct vmw_sw_context *sw_context,
733 SVGA3dCmdHeader *header)
734{
735 struct vmw_sid_cmd {
736 SVGA3dCmdHeader header;
737 SVGA3dCmdPresent body;
738 } *cmd;
739
5bb39e81 740
fb1d9738 741 cmd = container_of(header, struct vmw_sid_cmd, header);
0cff60c6 742
c0951b79
TH
743 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
744 user_surface_converter, &cmd->body.sid,
745 NULL);
fb1d9738
JB
746}
747
e2fa3a76
TH
748/**
749 * vmw_query_bo_switch_prepare - Prepare to switch pinned buffer for queries.
750 *
751 * @dev_priv: The device private structure.
e2fa3a76
TH
752 * @new_query_bo: The new buffer holding query results.
753 * @sw_context: The software context used for this command submission.
754 *
755 * This function checks whether @new_query_bo is suitable for holding
756 * query results, and if another buffer currently is pinned for query
757 * results. If so, the function prepares the state of @sw_context for
758 * switching pinned buffers after successful submission of the current
c0951b79 759 * command batch.
e2fa3a76
TH
760 */
761static int vmw_query_bo_switch_prepare(struct vmw_private *dev_priv,
e2fa3a76
TH
762 struct ttm_buffer_object *new_query_bo,
763 struct vmw_sw_context *sw_context)
764{
c0951b79
TH
765 struct vmw_res_cache_entry *ctx_entry =
766 &sw_context->res_cache[vmw_res_context];
e2fa3a76 767 int ret;
c0951b79
TH
768
769 BUG_ON(!ctx_entry->valid);
770 sw_context->last_query_ctx = ctx_entry->res;
e2fa3a76
TH
771
772 if (unlikely(new_query_bo != sw_context->cur_query_bo)) {
773
774 if (unlikely(new_query_bo->num_pages > 4)) {
775 DRM_ERROR("Query buffer too large.\n");
776 return -EINVAL;
777 }
778
779 if (unlikely(sw_context->cur_query_bo != NULL)) {
c0951b79 780 sw_context->needs_post_query_barrier = true;
e2fa3a76
TH
781 ret = vmw_bo_to_validate_list(sw_context,
782 sw_context->cur_query_bo,
96c5f0df 783 dev_priv->has_mob, NULL);
e2fa3a76
TH
784 if (unlikely(ret != 0))
785 return ret;
786 }
787 sw_context->cur_query_bo = new_query_bo;
788
789 ret = vmw_bo_to_validate_list(sw_context,
790 dev_priv->dummy_query_bo,
96c5f0df 791 dev_priv->has_mob, NULL);
e2fa3a76
TH
792 if (unlikely(ret != 0))
793 return ret;
794
795 }
796
e2fa3a76
TH
797 return 0;
798}
799
800
801/**
802 * vmw_query_bo_switch_commit - Finalize switching pinned query buffer
803 *
804 * @dev_priv: The device private structure.
805 * @sw_context: The software context used for this command submission batch.
806 *
807 * This function will check if we're switching query buffers, and will then,
e2fa3a76
TH
808 * issue a dummy occlusion query wait used as a query barrier. When the fence
809 * object following that query wait has signaled, we are sure that all
c0951b79 810 * preceding queries have finished, and the old query buffer can be unpinned.
e2fa3a76
TH
811 * However, since both the new query buffer and the old one are fenced with
812 * that fence, we can do an asynchronus unpin now, and be sure that the
813 * old query buffer won't be moved until the fence has signaled.
814 *
815 * As mentioned above, both the new - and old query buffers need to be fenced
816 * using a sequence emitted *after* calling this function.
817 */
818static void vmw_query_bo_switch_commit(struct vmw_private *dev_priv,
819 struct vmw_sw_context *sw_context)
820{
e2fa3a76
TH
821 /*
822 * The validate list should still hold references to all
823 * contexts here.
824 */
825
c0951b79
TH
826 if (sw_context->needs_post_query_barrier) {
827 struct vmw_res_cache_entry *ctx_entry =
828 &sw_context->res_cache[vmw_res_context];
829 struct vmw_resource *ctx;
830 int ret;
e2fa3a76 831
c0951b79
TH
832 BUG_ON(!ctx_entry->valid);
833 ctx = ctx_entry->res;
e2fa3a76
TH
834
835 ret = vmw_fifo_emit_dummy_query(dev_priv, ctx->id);
836
837 if (unlikely(ret != 0))
838 DRM_ERROR("Out of fifo space for dummy query.\n");
839 }
840
841 if (dev_priv->pinned_bo != sw_context->cur_query_bo) {
842 if (dev_priv->pinned_bo) {
843 vmw_bo_pin(dev_priv->pinned_bo, false);
844 ttm_bo_unref(&dev_priv->pinned_bo);
845 }
846
c0951b79
TH
847 if (!sw_context->needs_post_query_barrier) {
848 vmw_bo_pin(sw_context->cur_query_bo, true);
e2fa3a76 849
c0951b79
TH
850 /*
851 * We pin also the dummy_query_bo buffer so that we
852 * don't need to validate it when emitting
853 * dummy queries in context destroy paths.
854 */
e2fa3a76 855
c0951b79
TH
856 vmw_bo_pin(dev_priv->dummy_query_bo, true);
857 dev_priv->dummy_query_bo_pinned = true;
e2fa3a76 858
c0951b79
TH
859 BUG_ON(sw_context->last_query_ctx == NULL);
860 dev_priv->query_cid = sw_context->last_query_ctx->id;
861 dev_priv->query_cid_valid = true;
862 dev_priv->pinned_bo =
863 ttm_bo_reference(sw_context->cur_query_bo);
864 }
e2fa3a76
TH
865 }
866}
867
ddcda24e
TH
868/**
869 * vmw_translate_mob_pointer - Prepare to translate a user-space buffer
870 * handle to a MOB id.
871 *
872 * @dev_priv: Pointer to a device private structure.
873 * @sw_context: The software context used for this command batch validation.
874 * @id: Pointer to the user-space handle to be translated.
875 * @vmw_bo_p: Points to a location that, on successful return will carry
876 * a reference-counted pointer to the DMA buffer identified by the
877 * user-space handle in @id.
878 *
879 * This function saves information needed to translate a user-space buffer
880 * handle to a MOB id. The translation does not take place immediately, but
881 * during a call to vmw_apply_relocations(). This function builds a relocation
882 * list and a list of buffers to validate. The former needs to be freed using
883 * either vmw_apply_relocations() or vmw_free_relocations(). The latter
884 * needs to be freed using vmw_clear_validations.
885 */
886static int vmw_translate_mob_ptr(struct vmw_private *dev_priv,
887 struct vmw_sw_context *sw_context,
888 SVGAMobId *id,
889 struct vmw_dma_buffer **vmw_bo_p)
890{
891 struct vmw_dma_buffer *vmw_bo = NULL;
892 struct ttm_buffer_object *bo;
893 uint32_t handle = *id;
894 struct vmw_relocation *reloc;
895 int ret;
896
d5bde956 897 ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo);
ddcda24e
TH
898 if (unlikely(ret != 0)) {
899 DRM_ERROR("Could not find or use MOB buffer.\n");
da5efffc
CIK
900 ret = -EINVAL;
901 goto out_no_reloc;
ddcda24e
TH
902 }
903 bo = &vmw_bo->base;
904
905 if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
906 DRM_ERROR("Max number relocations per submission"
907 " exceeded\n");
908 ret = -EINVAL;
909 goto out_no_reloc;
910 }
911
912 reloc = &sw_context->relocs[sw_context->cur_reloc++];
913 reloc->mob_loc = id;
914 reloc->location = NULL;
915
916 ret = vmw_bo_to_validate_list(sw_context, bo, true, &reloc->index);
917 if (unlikely(ret != 0))
918 goto out_no_reloc;
919
920 *vmw_bo_p = vmw_bo;
921 return 0;
922
923out_no_reloc:
924 vmw_dmabuf_unreference(&vmw_bo);
da5efffc 925 *vmw_bo_p = NULL;
ddcda24e
TH
926 return ret;
927}
928
e2fa3a76 929/**
c0951b79
TH
930 * vmw_translate_guest_pointer - Prepare to translate a user-space buffer
931 * handle to a valid SVGAGuestPtr
e2fa3a76 932 *
c0951b79
TH
933 * @dev_priv: Pointer to a device private structure.
934 * @sw_context: The software context used for this command batch validation.
935 * @ptr: Pointer to the user-space handle to be translated.
936 * @vmw_bo_p: Points to a location that, on successful return will carry
937 * a reference-counted pointer to the DMA buffer identified by the
938 * user-space handle in @id.
e2fa3a76 939 *
c0951b79
TH
940 * This function saves information needed to translate a user-space buffer
941 * handle to a valid SVGAGuestPtr. The translation does not take place
942 * immediately, but during a call to vmw_apply_relocations().
943 * This function builds a relocation list and a list of buffers to validate.
944 * The former needs to be freed using either vmw_apply_relocations() or
945 * vmw_free_relocations(). The latter needs to be freed using
946 * vmw_clear_validations.
e2fa3a76 947 */
4e4ddd47
TH
948static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,
949 struct vmw_sw_context *sw_context,
950 SVGAGuestPtr *ptr,
951 struct vmw_dma_buffer **vmw_bo_p)
fb1d9738 952{
fb1d9738
JB
953 struct vmw_dma_buffer *vmw_bo = NULL;
954 struct ttm_buffer_object *bo;
4e4ddd47 955 uint32_t handle = ptr->gmrId;
fb1d9738 956 struct vmw_relocation *reloc;
4e4ddd47 957 int ret;
fb1d9738 958
d5bde956 959 ret = vmw_user_dmabuf_lookup(sw_context->fp->tfile, handle, &vmw_bo);
fb1d9738
JB
960 if (unlikely(ret != 0)) {
961 DRM_ERROR("Could not find or use GMR region.\n");
da5efffc
CIK
962 ret = -EINVAL;
963 goto out_no_reloc;
fb1d9738
JB
964 }
965 bo = &vmw_bo->base;
966
967 if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
4e4ddd47 968 DRM_ERROR("Max number relocations per submission"
fb1d9738
JB
969 " exceeded\n");
970 ret = -EINVAL;
971 goto out_no_reloc;
972 }
973
974 reloc = &sw_context->relocs[sw_context->cur_reloc++];
4e4ddd47 975 reloc->location = ptr;
fb1d9738 976
96c5f0df 977 ret = vmw_bo_to_validate_list(sw_context, bo, false, &reloc->index);
e2fa3a76 978 if (unlikely(ret != 0))
fb1d9738 979 goto out_no_reloc;
fb1d9738 980
4e4ddd47
TH
981 *vmw_bo_p = vmw_bo;
982 return 0;
983
984out_no_reloc:
985 vmw_dmabuf_unreference(&vmw_bo);
da5efffc 986 *vmw_bo_p = NULL;
4e4ddd47
TH
987 return ret;
988}
989
ddcda24e
TH
990/**
991 * vmw_cmd_begin_gb_query - validate a SVGA_3D_CMD_BEGIN_GB_QUERY command.
992 *
993 * @dev_priv: Pointer to a device private struct.
994 * @sw_context: The software context used for this command submission.
995 * @header: Pointer to the command header in the command stream.
996 */
997static int vmw_cmd_begin_gb_query(struct vmw_private *dev_priv,
998 struct vmw_sw_context *sw_context,
999 SVGA3dCmdHeader *header)
1000{
1001 struct vmw_begin_gb_query_cmd {
1002 SVGA3dCmdHeader header;
1003 SVGA3dCmdBeginGBQuery q;
1004 } *cmd;
1005
1006 cmd = container_of(header, struct vmw_begin_gb_query_cmd,
1007 header);
1008
1009 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1010 user_context_converter, &cmd->q.cid,
1011 NULL);
1012}
1013
c0951b79
TH
1014/**
1015 * vmw_cmd_begin_query - validate a SVGA_3D_CMD_BEGIN_QUERY command.
1016 *
1017 * @dev_priv: Pointer to a device private struct.
1018 * @sw_context: The software context used for this command submission.
1019 * @header: Pointer to the command header in the command stream.
1020 */
1021static int vmw_cmd_begin_query(struct vmw_private *dev_priv,
1022 struct vmw_sw_context *sw_context,
1023 SVGA3dCmdHeader *header)
1024{
1025 struct vmw_begin_query_cmd {
1026 SVGA3dCmdHeader header;
1027 SVGA3dCmdBeginQuery q;
1028 } *cmd;
1029
1030 cmd = container_of(header, struct vmw_begin_query_cmd,
1031 header);
1032
ddcda24e
TH
1033 if (unlikely(dev_priv->has_mob)) {
1034 struct {
1035 SVGA3dCmdHeader header;
1036 SVGA3dCmdBeginGBQuery q;
1037 } gb_cmd;
1038
1039 BUG_ON(sizeof(gb_cmd) != sizeof(*cmd));
1040
1041 gb_cmd.header.id = SVGA_3D_CMD_BEGIN_GB_QUERY;
1042 gb_cmd.header.size = cmd->header.size;
1043 gb_cmd.q.cid = cmd->q.cid;
1044 gb_cmd.q.type = cmd->q.type;
1045
1046 memcpy(cmd, &gb_cmd, sizeof(*cmd));
1047 return vmw_cmd_begin_gb_query(dev_priv, sw_context, header);
1048 }
1049
c0951b79
TH
1050 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1051 user_context_converter, &cmd->q.cid,
1052 NULL);
1053}
1054
ddcda24e
TH
1055/**
1056 * vmw_cmd_end_gb_query - validate a SVGA_3D_CMD_END_GB_QUERY command.
1057 *
1058 * @dev_priv: Pointer to a device private struct.
1059 * @sw_context: The software context used for this command submission.
1060 * @header: Pointer to the command header in the command stream.
1061 */
1062static int vmw_cmd_end_gb_query(struct vmw_private *dev_priv,
1063 struct vmw_sw_context *sw_context,
1064 SVGA3dCmdHeader *header)
1065{
1066 struct vmw_dma_buffer *vmw_bo;
1067 struct vmw_query_cmd {
1068 SVGA3dCmdHeader header;
1069 SVGA3dCmdEndGBQuery q;
1070 } *cmd;
1071 int ret;
1072
1073 cmd = container_of(header, struct vmw_query_cmd, header);
1074 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
1075 if (unlikely(ret != 0))
1076 return ret;
1077
1078 ret = vmw_translate_mob_ptr(dev_priv, sw_context,
1079 &cmd->q.mobid,
1080 &vmw_bo);
1081 if (unlikely(ret != 0))
1082 return ret;
1083
1084 ret = vmw_query_bo_switch_prepare(dev_priv, &vmw_bo->base, sw_context);
1085
1086 vmw_dmabuf_unreference(&vmw_bo);
1087 return ret;
1088}
1089
c0951b79
TH
1090/**
1091 * vmw_cmd_end_query - validate a SVGA_3D_CMD_END_QUERY command.
1092 *
1093 * @dev_priv: Pointer to a device private struct.
1094 * @sw_context: The software context used for this command submission.
1095 * @header: Pointer to the command header in the command stream.
1096 */
4e4ddd47
TH
1097static int vmw_cmd_end_query(struct vmw_private *dev_priv,
1098 struct vmw_sw_context *sw_context,
1099 SVGA3dCmdHeader *header)
1100{
1101 struct vmw_dma_buffer *vmw_bo;
1102 struct vmw_query_cmd {
1103 SVGA3dCmdHeader header;
1104 SVGA3dCmdEndQuery q;
1105 } *cmd;
1106 int ret;
1107
1108 cmd = container_of(header, struct vmw_query_cmd, header);
ddcda24e
TH
1109 if (dev_priv->has_mob) {
1110 struct {
1111 SVGA3dCmdHeader header;
1112 SVGA3dCmdEndGBQuery q;
1113 } gb_cmd;
1114
1115 BUG_ON(sizeof(gb_cmd) != sizeof(*cmd));
1116
1117 gb_cmd.header.id = SVGA_3D_CMD_END_GB_QUERY;
1118 gb_cmd.header.size = cmd->header.size;
1119 gb_cmd.q.cid = cmd->q.cid;
1120 gb_cmd.q.type = cmd->q.type;
1121 gb_cmd.q.mobid = cmd->q.guestResult.gmrId;
1122 gb_cmd.q.offset = cmd->q.guestResult.offset;
1123
1124 memcpy(cmd, &gb_cmd, sizeof(*cmd));
1125 return vmw_cmd_end_gb_query(dev_priv, sw_context, header);
1126 }
1127
4e4ddd47
TH
1128 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
1129 if (unlikely(ret != 0))
1130 return ret;
1131
1132 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
1133 &cmd->q.guestResult,
1134 &vmw_bo);
1135 if (unlikely(ret != 0))
1136 return ret;
1137
c0951b79 1138 ret = vmw_query_bo_switch_prepare(dev_priv, &vmw_bo->base, sw_context);
e2fa3a76 1139
4e4ddd47 1140 vmw_dmabuf_unreference(&vmw_bo);
e2fa3a76 1141 return ret;
4e4ddd47 1142}
fb1d9738 1143
ddcda24e
TH
1144/**
1145 * vmw_cmd_wait_gb_query - validate a SVGA_3D_CMD_WAIT_GB_QUERY command.
1146 *
1147 * @dev_priv: Pointer to a device private struct.
1148 * @sw_context: The software context used for this command submission.
1149 * @header: Pointer to the command header in the command stream.
1150 */
1151static int vmw_cmd_wait_gb_query(struct vmw_private *dev_priv,
1152 struct vmw_sw_context *sw_context,
1153 SVGA3dCmdHeader *header)
1154{
1155 struct vmw_dma_buffer *vmw_bo;
1156 struct vmw_query_cmd {
1157 SVGA3dCmdHeader header;
1158 SVGA3dCmdWaitForGBQuery q;
1159 } *cmd;
1160 int ret;
1161
1162 cmd = container_of(header, struct vmw_query_cmd, header);
1163 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
1164 if (unlikely(ret != 0))
1165 return ret;
1166
1167 ret = vmw_translate_mob_ptr(dev_priv, sw_context,
1168 &cmd->q.mobid,
1169 &vmw_bo);
1170 if (unlikely(ret != 0))
1171 return ret;
1172
1173 vmw_dmabuf_unreference(&vmw_bo);
1174 return 0;
1175}
1176
1177/**
c0951b79
TH
1178 * vmw_cmd_wait_query - validate a SVGA_3D_CMD_WAIT_QUERY command.
1179 *
1180 * @dev_priv: Pointer to a device private struct.
1181 * @sw_context: The software context used for this command submission.
1182 * @header: Pointer to the command header in the command stream.
1183 */
4e4ddd47
TH
1184static int vmw_cmd_wait_query(struct vmw_private *dev_priv,
1185 struct vmw_sw_context *sw_context,
1186 SVGA3dCmdHeader *header)
1187{
1188 struct vmw_dma_buffer *vmw_bo;
1189 struct vmw_query_cmd {
1190 SVGA3dCmdHeader header;
1191 SVGA3dCmdWaitForQuery q;
1192 } *cmd;
1193 int ret;
1194
1195 cmd = container_of(header, struct vmw_query_cmd, header);
ddcda24e
TH
1196 if (dev_priv->has_mob) {
1197 struct {
1198 SVGA3dCmdHeader header;
1199 SVGA3dCmdWaitForGBQuery q;
1200 } gb_cmd;
1201
1202 BUG_ON(sizeof(gb_cmd) != sizeof(*cmd));
1203
1204 gb_cmd.header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
1205 gb_cmd.header.size = cmd->header.size;
1206 gb_cmd.q.cid = cmd->q.cid;
1207 gb_cmd.q.type = cmd->q.type;
1208 gb_cmd.q.mobid = cmd->q.guestResult.gmrId;
1209 gb_cmd.q.offset = cmd->q.guestResult.offset;
1210
1211 memcpy(cmd, &gb_cmd, sizeof(*cmd));
1212 return vmw_cmd_wait_gb_query(dev_priv, sw_context, header);
1213 }
1214
4e4ddd47
TH
1215 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
1216 if (unlikely(ret != 0))
1217 return ret;
1218
1219 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
1220 &cmd->q.guestResult,
1221 &vmw_bo);
1222 if (unlikely(ret != 0))
1223 return ret;
1224
1225 vmw_dmabuf_unreference(&vmw_bo);
1226 return 0;
1227}
1228
4e4ddd47
TH
1229static int vmw_cmd_dma(struct vmw_private *dev_priv,
1230 struct vmw_sw_context *sw_context,
1231 SVGA3dCmdHeader *header)
1232{
1233 struct vmw_dma_buffer *vmw_bo = NULL;
4e4ddd47
TH
1234 struct vmw_surface *srf = NULL;
1235 struct vmw_dma_cmd {
1236 SVGA3dCmdHeader header;
1237 SVGA3dCmdSurfaceDMA dma;
1238 } *cmd;
1239 int ret;
cbd75e97
TH
1240 SVGA3dCmdSurfaceDMASuffix *suffix;
1241 uint32_t bo_size;
4e4ddd47
TH
1242
1243 cmd = container_of(header, struct vmw_dma_cmd, header);
cbd75e97
TH
1244 suffix = (SVGA3dCmdSurfaceDMASuffix *)((unsigned long) &cmd->dma +
1245 header->size - sizeof(*suffix));
1246
1247 /* Make sure device and verifier stays in sync. */
1248 if (unlikely(suffix->suffixSize != sizeof(*suffix))) {
1249 DRM_ERROR("Invalid DMA suffix size.\n");
1250 return -EINVAL;
1251 }
1252
4e4ddd47
TH
1253 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
1254 &cmd->dma.guest.ptr,
1255 &vmw_bo);
1256 if (unlikely(ret != 0))
1257 return ret;
1258
cbd75e97
TH
1259 /* Make sure DMA doesn't cross BO boundaries. */
1260 bo_size = vmw_bo->base.num_pages * PAGE_SIZE;
1261 if (unlikely(cmd->dma.guest.ptr.offset > bo_size)) {
1262 DRM_ERROR("Invalid DMA offset.\n");
1263 return -EINVAL;
1264 }
1265
1266 bo_size -= cmd->dma.guest.ptr.offset;
1267 if (unlikely(suffix->maximumOffset > bo_size))
1268 suffix->maximumOffset = bo_size;
1269
f89c6c32 1270 if (sw_context->quirks & VMW_QUIRK_DST_SID_OK)
c9146cd9
TH
1271 goto out_no_surface;
1272
c0951b79
TH
1273 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1274 user_surface_converter, &cmd->dma.host.sid,
1275 NULL);
5bb39e81 1276 if (unlikely(ret != 0)) {
c0951b79
TH
1277 if (unlikely(ret != -ERESTARTSYS))
1278 DRM_ERROR("could not find surface for DMA.\n");
1279 goto out_no_surface;
5bb39e81
TH
1280 }
1281
c0951b79 1282 srf = vmw_res_to_srf(sw_context->res_cache[vmw_res_surface].res);
f18c8840 1283
d5bde956
TH
1284 vmw_kms_cursor_snoop(srf, sw_context->fp->tfile, &vmw_bo->base,
1285 header);
fb1d9738 1286
c0951b79 1287out_no_surface:
fb1d9738
JB
1288 vmw_dmabuf_unreference(&vmw_bo);
1289 return ret;
1290}
1291
7a73ba74
TH
1292static int vmw_cmd_draw(struct vmw_private *dev_priv,
1293 struct vmw_sw_context *sw_context,
1294 SVGA3dCmdHeader *header)
1295{
1296 struct vmw_draw_cmd {
1297 SVGA3dCmdHeader header;
1298 SVGA3dCmdDrawPrimitives body;
1299 } *cmd;
1300 SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)(
1301 (unsigned long)header + sizeof(*cmd));
1302 SVGA3dPrimitiveRange *range;
1303 uint32_t i;
1304 uint32_t maxnum;
1305 int ret;
1306
1307 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
1308 if (unlikely(ret != 0))
1309 return ret;
1310
1311 cmd = container_of(header, struct vmw_draw_cmd, header);
1312 maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl);
1313
1314 if (unlikely(cmd->body.numVertexDecls > maxnum)) {
1315 DRM_ERROR("Illegal number of vertex declarations.\n");
1316 return -EINVAL;
1317 }
1318
1319 for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) {
c0951b79
TH
1320 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1321 user_surface_converter,
1322 &decl->array.surfaceId, NULL);
7a73ba74
TH
1323 if (unlikely(ret != 0))
1324 return ret;
1325 }
1326
1327 maxnum = (header->size - sizeof(cmd->body) -
1328 cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range);
1329 if (unlikely(cmd->body.numRanges > maxnum)) {
1330 DRM_ERROR("Illegal number of index ranges.\n");
1331 return -EINVAL;
1332 }
1333
1334 range = (SVGA3dPrimitiveRange *) decl;
1335 for (i = 0; i < cmd->body.numRanges; ++i, ++range) {
c0951b79
TH
1336 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1337 user_surface_converter,
1338 &range->indexArray.surfaceId, NULL);
7a73ba74
TH
1339 if (unlikely(ret != 0))
1340 return ret;
1341 }
1342 return 0;
1343}
1344
1345
1346static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
1347 struct vmw_sw_context *sw_context,
1348 SVGA3dCmdHeader *header)
1349{
1350 struct vmw_tex_state_cmd {
1351 SVGA3dCmdHeader header;
1352 SVGA3dCmdSetTextureState state;
b5c3b1a6 1353 } *cmd;
7a73ba74
TH
1354
1355 SVGA3dTextureState *last_state = (SVGA3dTextureState *)
1356 ((unsigned long) header + header->size + sizeof(header));
1357 SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
1358 ((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
b5c3b1a6 1359 struct vmw_resource_val_node *ctx_node;
173fb7d4 1360 struct vmw_resource_val_node *res_node;
7a73ba74
TH
1361 int ret;
1362
b5c3b1a6
TH
1363 cmd = container_of(header, struct vmw_tex_state_cmd,
1364 header);
1365
1366 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1367 user_context_converter, &cmd->state.cid,
1368 &ctx_node);
7a73ba74
TH
1369 if (unlikely(ret != 0))
1370 return ret;
1371
1372 for (; cur_state < last_state; ++cur_state) {
1373 if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
1374 continue;
1375
c0951b79
TH
1376 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1377 user_surface_converter,
173fb7d4 1378 &cur_state->value, &res_node);
7a73ba74
TH
1379 if (unlikely(ret != 0))
1380 return ret;
b5c3b1a6
TH
1381
1382 if (dev_priv->has_mob) {
1383 struct vmw_ctx_bindinfo bi;
1384
1385 bi.ctx = ctx_node->res;
173fb7d4 1386 bi.res = res_node ? res_node->res : NULL;
b5c3b1a6
TH
1387 bi.bt = vmw_ctx_binding_tex;
1388 bi.i1.texture_stage = cur_state->stage;
1389 vmw_context_binding_add(ctx_node->staged_bindings,
1390 &bi);
1391 }
7a73ba74
TH
1392 }
1393
1394 return 0;
1395}
1396
4084fb89
JB
1397static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv,
1398 struct vmw_sw_context *sw_context,
1399 void *buf)
1400{
1401 struct vmw_dma_buffer *vmw_bo;
1402 int ret;
1403
1404 struct {
1405 uint32_t header;
1406 SVGAFifoCmdDefineGMRFB body;
1407 } *cmd = buf;
1408
1409 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
1410 &cmd->body.ptr,
1411 &vmw_bo);
1412 if (unlikely(ret != 0))
1413 return ret;
1414
1415 vmw_dmabuf_unreference(&vmw_bo);
1416
1417 return ret;
1418}
1419
a97e2192
TH
1420/**
1421 * vmw_cmd_switch_backup - Utility function to handle backup buffer switching
1422 *
1423 * @dev_priv: Pointer to a device private struct.
1424 * @sw_context: The software context being used for this batch.
1425 * @res_type: The resource type.
1426 * @converter: Information about user-space binding for this resource type.
1427 * @res_id: Pointer to the user-space resource handle in the command stream.
1428 * @buf_id: Pointer to the user-space backup buffer handle in the command
1429 * stream.
1430 * @backup_offset: Offset of backup into MOB.
1431 *
1432 * This function prepares for registering a switch of backup buffers
1433 * in the resource metadata just prior to unreserving.
1434 */
1435static int vmw_cmd_switch_backup(struct vmw_private *dev_priv,
1436 struct vmw_sw_context *sw_context,
1437 enum vmw_res_type res_type,
1438 const struct vmw_user_resource_conv
1439 *converter,
1440 uint32_t *res_id,
1441 uint32_t *buf_id,
1442 unsigned long backup_offset)
1443{
1444 int ret;
1445 struct vmw_dma_buffer *dma_buf;
1446 struct vmw_resource_val_node *val_node;
1447
1448 ret = vmw_cmd_res_check(dev_priv, sw_context, res_type,
1449 converter, res_id, &val_node);
1450 if (unlikely(ret != 0))
1451 return ret;
1452
1453 ret = vmw_translate_mob_ptr(dev_priv, sw_context, buf_id, &dma_buf);
1454 if (unlikely(ret != 0))
1455 return ret;
1456
1457 if (val_node->first_usage)
1458 val_node->no_buffer_needed = true;
1459
1460 vmw_dmabuf_unreference(&val_node->new_backup);
1461 val_node->new_backup = dma_buf;
1462 val_node->new_backup_offset = backup_offset;
1463
1464 return 0;
1465}
1466
1467/**
1468 * vmw_cmd_bind_gb_surface - Validate an SVGA_3D_CMD_BIND_GB_SURFACE
1469 * command
1470 *
1471 * @dev_priv: Pointer to a device private struct.
1472 * @sw_context: The software context being used for this batch.
1473 * @header: Pointer to the command header in the command stream.
1474 */
1475static int vmw_cmd_bind_gb_surface(struct vmw_private *dev_priv,
1476 struct vmw_sw_context *sw_context,
1477 SVGA3dCmdHeader *header)
1478{
1479 struct vmw_bind_gb_surface_cmd {
1480 SVGA3dCmdHeader header;
1481 SVGA3dCmdBindGBSurface body;
1482 } *cmd;
1483
1484 cmd = container_of(header, struct vmw_bind_gb_surface_cmd, header);
1485
1486 return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_surface,
1487 user_surface_converter,
1488 &cmd->body.sid, &cmd->body.mobid,
1489 0);
1490}
1491
1492/**
1493 * vmw_cmd_update_gb_image - Validate an SVGA_3D_CMD_UPDATE_GB_IMAGE
1494 * command
1495 *
1496 * @dev_priv: Pointer to a device private struct.
1497 * @sw_context: The software context being used for this batch.
1498 * @header: Pointer to the command header in the command stream.
1499 */
1500static int vmw_cmd_update_gb_image(struct vmw_private *dev_priv,
1501 struct vmw_sw_context *sw_context,
1502 SVGA3dCmdHeader *header)
1503{
1504 struct vmw_gb_surface_cmd {
1505 SVGA3dCmdHeader header;
1506 SVGA3dCmdUpdateGBImage body;
1507 } *cmd;
1508
1509 cmd = container_of(header, struct vmw_gb_surface_cmd, header);
1510
f89c6c32
SY
1511 if (sw_context->quirks & VMW_QUIRK_SRC_SID_OK)
1512 return 0;
1513
a97e2192
TH
1514 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1515 user_surface_converter,
1516 &cmd->body.image.sid, NULL);
1517}
1518
1519/**
1520 * vmw_cmd_update_gb_surface - Validate an SVGA_3D_CMD_UPDATE_GB_SURFACE
1521 * command
1522 *
1523 * @dev_priv: Pointer to a device private struct.
1524 * @sw_context: The software context being used for this batch.
1525 * @header: Pointer to the command header in the command stream.
1526 */
1527static int vmw_cmd_update_gb_surface(struct vmw_private *dev_priv,
1528 struct vmw_sw_context *sw_context,
1529 SVGA3dCmdHeader *header)
1530{
1531 struct vmw_gb_surface_cmd {
1532 SVGA3dCmdHeader header;
1533 SVGA3dCmdUpdateGBSurface body;
1534 } *cmd;
1535
1536 cmd = container_of(header, struct vmw_gb_surface_cmd, header);
1537
1538 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1539 user_surface_converter,
1540 &cmd->body.sid, NULL);
1541}
1542
1543/**
1544 * vmw_cmd_readback_gb_image - Validate an SVGA_3D_CMD_READBACK_GB_IMAGE
1545 * command
1546 *
1547 * @dev_priv: Pointer to a device private struct.
1548 * @sw_context: The software context being used for this batch.
1549 * @header: Pointer to the command header in the command stream.
1550 */
1551static int vmw_cmd_readback_gb_image(struct vmw_private *dev_priv,
1552 struct vmw_sw_context *sw_context,
1553 SVGA3dCmdHeader *header)
1554{
1555 struct vmw_gb_surface_cmd {
1556 SVGA3dCmdHeader header;
1557 SVGA3dCmdReadbackGBImage body;
1558 } *cmd;
1559
1560 cmd = container_of(header, struct vmw_gb_surface_cmd, header);
1561
1562 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1563 user_surface_converter,
1564 &cmd->body.image.sid, NULL);
1565}
1566
1567/**
1568 * vmw_cmd_readback_gb_surface - Validate an SVGA_3D_CMD_READBACK_GB_SURFACE
1569 * command
1570 *
1571 * @dev_priv: Pointer to a device private struct.
1572 * @sw_context: The software context being used for this batch.
1573 * @header: Pointer to the command header in the command stream.
1574 */
1575static int vmw_cmd_readback_gb_surface(struct vmw_private *dev_priv,
1576 struct vmw_sw_context *sw_context,
1577 SVGA3dCmdHeader *header)
1578{
1579 struct vmw_gb_surface_cmd {
1580 SVGA3dCmdHeader header;
1581 SVGA3dCmdReadbackGBSurface body;
1582 } *cmd;
1583
1584 cmd = container_of(header, struct vmw_gb_surface_cmd, header);
1585
1586 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1587 user_surface_converter,
1588 &cmd->body.sid, NULL);
1589}
1590
1591/**
1592 * vmw_cmd_invalidate_gb_image - Validate an SVGA_3D_CMD_INVALIDATE_GB_IMAGE
1593 * command
1594 *
1595 * @dev_priv: Pointer to a device private struct.
1596 * @sw_context: The software context being used for this batch.
1597 * @header: Pointer to the command header in the command stream.
1598 */
1599static int vmw_cmd_invalidate_gb_image(struct vmw_private *dev_priv,
1600 struct vmw_sw_context *sw_context,
1601 SVGA3dCmdHeader *header)
1602{
1603 struct vmw_gb_surface_cmd {
1604 SVGA3dCmdHeader header;
1605 SVGA3dCmdInvalidateGBImage body;
1606 } *cmd;
1607
1608 cmd = container_of(header, struct vmw_gb_surface_cmd, header);
1609
1610 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1611 user_surface_converter,
1612 &cmd->body.image.sid, NULL);
1613}
1614
1615/**
1616 * vmw_cmd_invalidate_gb_surface - Validate an
1617 * SVGA_3D_CMD_INVALIDATE_GB_SURFACE command
1618 *
1619 * @dev_priv: Pointer to a device private struct.
1620 * @sw_context: The software context being used for this batch.
1621 * @header: Pointer to the command header in the command stream.
1622 */
1623static int vmw_cmd_invalidate_gb_surface(struct vmw_private *dev_priv,
1624 struct vmw_sw_context *sw_context,
1625 SVGA3dCmdHeader *header)
1626{
1627 struct vmw_gb_surface_cmd {
1628 SVGA3dCmdHeader header;
1629 SVGA3dCmdInvalidateGBSurface body;
1630 } *cmd;
1631
1632 cmd = container_of(header, struct vmw_gb_surface_cmd, header);
1633
1634 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
1635 user_surface_converter,
1636 &cmd->body.sid, NULL);
1637}
1638
d5bde956
TH
1639
1640/**
1641 * vmw_cmd_shader_define - Validate an SVGA_3D_CMD_SHADER_DEFINE
1642 * command
1643 *
1644 * @dev_priv: Pointer to a device private struct.
1645 * @sw_context: The software context being used for this batch.
1646 * @header: Pointer to the command header in the command stream.
1647 */
1648static int vmw_cmd_shader_define(struct vmw_private *dev_priv,
1649 struct vmw_sw_context *sw_context,
1650 SVGA3dCmdHeader *header)
1651{
1652 struct vmw_shader_define_cmd {
1653 SVGA3dCmdHeader header;
1654 SVGA3dCmdDefineShader body;
1655 } *cmd;
1656 int ret;
1657 size_t size;
18e4a466 1658 struct vmw_resource_val_node *val;
d5bde956
TH
1659
1660 cmd = container_of(header, struct vmw_shader_define_cmd,
1661 header);
1662
1663 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1664 user_context_converter, &cmd->body.cid,
18e4a466 1665 &val);
d5bde956
TH
1666 if (unlikely(ret != 0))
1667 return ret;
1668
1669 if (unlikely(!dev_priv->has_mob))
1670 return 0;
1671
1672 size = cmd->header.size - sizeof(cmd->body);
18e4a466
TH
1673 ret = vmw_compat_shader_add(dev_priv,
1674 vmw_context_res_man(val->res),
d5bde956
TH
1675 cmd->body.shid, cmd + 1,
1676 cmd->body.type, size,
18e4a466 1677 &sw_context->staged_cmd_res);
d5bde956
TH
1678 if (unlikely(ret != 0))
1679 return ret;
1680
1681 return vmw_resource_relocation_add(&sw_context->res_relocations,
1682 NULL, &cmd->header.id -
1683 sw_context->buf_start);
1684
1685 return 0;
1686}
1687
1688/**
1689 * vmw_cmd_shader_destroy - Validate an SVGA_3D_CMD_SHADER_DESTROY
1690 * command
1691 *
1692 * @dev_priv: Pointer to a device private struct.
1693 * @sw_context: The software context being used for this batch.
1694 * @header: Pointer to the command header in the command stream.
1695 */
1696static int vmw_cmd_shader_destroy(struct vmw_private *dev_priv,
1697 struct vmw_sw_context *sw_context,
1698 SVGA3dCmdHeader *header)
1699{
1700 struct vmw_shader_destroy_cmd {
1701 SVGA3dCmdHeader header;
1702 SVGA3dCmdDestroyShader body;
1703 } *cmd;
1704 int ret;
18e4a466 1705 struct vmw_resource_val_node *val;
d5bde956
TH
1706
1707 cmd = container_of(header, struct vmw_shader_destroy_cmd,
1708 header);
1709
1710 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1711 user_context_converter, &cmd->body.cid,
18e4a466 1712 &val);
d5bde956
TH
1713 if (unlikely(ret != 0))
1714 return ret;
1715
1716 if (unlikely(!dev_priv->has_mob))
1717 return 0;
1718
18e4a466 1719 ret = vmw_compat_shader_remove(vmw_context_res_man(val->res),
d5bde956
TH
1720 cmd->body.shid,
1721 cmd->body.type,
18e4a466 1722 &sw_context->staged_cmd_res);
d5bde956
TH
1723 if (unlikely(ret != 0))
1724 return ret;
1725
1726 return vmw_resource_relocation_add(&sw_context->res_relocations,
1727 NULL, &cmd->header.id -
1728 sw_context->buf_start);
1729
1730 return 0;
1731}
1732
c0951b79
TH
1733/**
1734 * vmw_cmd_set_shader - Validate an SVGA_3D_CMD_SET_SHADER
1735 * command
1736 *
1737 * @dev_priv: Pointer to a device private struct.
1738 * @sw_context: The software context being used for this batch.
1739 * @header: Pointer to the command header in the command stream.
1740 */
1741static int vmw_cmd_set_shader(struct vmw_private *dev_priv,
1742 struct vmw_sw_context *sw_context,
1743 SVGA3dCmdHeader *header)
1744{
1745 struct vmw_set_shader_cmd {
1746 SVGA3dCmdHeader header;
1747 SVGA3dCmdSetShader body;
1748 } *cmd;
18e4a466
TH
1749 struct vmw_resource_val_node *ctx_node, *res_node = NULL;
1750 struct vmw_ctx_bindinfo bi;
1751 struct vmw_resource *res = NULL;
c0951b79
TH
1752 int ret;
1753
1754 cmd = container_of(header, struct vmw_set_shader_cmd,
1755 header);
1756
b5c3b1a6
TH
1757 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1758 user_context_converter, &cmd->body.cid,
1759 &ctx_node);
c0951b79
TH
1760 if (unlikely(ret != 0))
1761 return ret;
1762
18e4a466
TH
1763 if (!dev_priv->has_mob)
1764 return 0;
1765
1766 if (cmd->body.shid != SVGA3D_INVALID_ID) {
1767 res = vmw_compat_shader_lookup
1768 (vmw_context_res_man(ctx_node->res),
1769 cmd->body.shid,
1770 cmd->body.type);
1771
1772 if (!IS_ERR(res)) {
1773 ret = vmw_cmd_res_reloc_add(dev_priv, sw_context,
1774 vmw_res_shader,
1775 &cmd->body.shid, res,
1776 &res_node);
1777 vmw_resource_unreference(&res);
1778 if (unlikely(ret != 0))
1779 return ret;
1780 }
1781 }
1782
1783 if (!res_node) {
1784 ret = vmw_cmd_res_check(dev_priv, sw_context,
1785 vmw_res_shader,
1786 user_shader_converter,
1787 &cmd->body.shid, &res_node);
b5c3b1a6
TH
1788 if (unlikely(ret != 0))
1789 return ret;
b5c3b1a6 1790 }
c74c162f 1791
18e4a466
TH
1792 bi.ctx = ctx_node->res;
1793 bi.res = res_node ? res_node->res : NULL;
1794 bi.bt = vmw_ctx_binding_shader;
1795 bi.i1.shader_type = cmd->body.type;
1796 return vmw_context_binding_add(ctx_node->staged_bindings, &bi);
c0951b79
TH
1797}
1798
0ccbbae4
TH
1799/**
1800 * vmw_cmd_set_shader_const - Validate an SVGA_3D_CMD_SET_SHADER_CONST
1801 * command
1802 *
1803 * @dev_priv: Pointer to a device private struct.
1804 * @sw_context: The software context being used for this batch.
1805 * @header: Pointer to the command header in the command stream.
1806 */
1807static int vmw_cmd_set_shader_const(struct vmw_private *dev_priv,
1808 struct vmw_sw_context *sw_context,
1809 SVGA3dCmdHeader *header)
1810{
1811 struct vmw_set_shader_const_cmd {
1812 SVGA3dCmdHeader header;
1813 SVGA3dCmdSetShaderConst body;
1814 } *cmd;
1815 int ret;
1816
1817 cmd = container_of(header, struct vmw_set_shader_const_cmd,
1818 header);
1819
1820 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_context,
1821 user_context_converter, &cmd->body.cid,
1822 NULL);
1823 if (unlikely(ret != 0))
1824 return ret;
1825
1826 if (dev_priv->has_mob)
1827 header->id = SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE;
1828
1829 return 0;
1830}
1831
c74c162f
TH
1832/**
1833 * vmw_cmd_bind_gb_shader - Validate an SVGA_3D_CMD_BIND_GB_SHADER
1834 * command
1835 *
1836 * @dev_priv: Pointer to a device private struct.
1837 * @sw_context: The software context being used for this batch.
1838 * @header: Pointer to the command header in the command stream.
1839 */
1840static int vmw_cmd_bind_gb_shader(struct vmw_private *dev_priv,
1841 struct vmw_sw_context *sw_context,
1842 SVGA3dCmdHeader *header)
1843{
1844 struct vmw_bind_gb_shader_cmd {
1845 SVGA3dCmdHeader header;
1846 SVGA3dCmdBindGBShader body;
1847 } *cmd;
1848
1849 cmd = container_of(header, struct vmw_bind_gb_shader_cmd,
1850 header);
1851
1852 return vmw_cmd_switch_backup(dev_priv, sw_context, vmw_res_shader,
1853 user_shader_converter,
1854 &cmd->body.shid, &cmd->body.mobid,
1855 cmd->body.offsetInBytes);
1856}
1857
4084fb89
JB
1858static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
1859 struct vmw_sw_context *sw_context,
1860 void *buf, uint32_t *size)
1861{
1862 uint32_t size_remaining = *size;
4084fb89
JB
1863 uint32_t cmd_id;
1864
1865 cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
1866 switch (cmd_id) {
1867 case SVGA_CMD_UPDATE:
1868 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdUpdate);
4084fb89
JB
1869 break;
1870 case SVGA_CMD_DEFINE_GMRFB:
1871 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdDefineGMRFB);
1872 break;
1873 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
1874 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
1875 break;
1876 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
1877 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
1878 break;
1879 default:
1880 DRM_ERROR("Unsupported SVGA command: %u.\n", cmd_id);
1881 return -EINVAL;
1882 }
1883
1884 if (*size > size_remaining) {
1885 DRM_ERROR("Invalid SVGA command (size mismatch):"
1886 " %u.\n", cmd_id);
1887 return -EINVAL;
1888 }
1889
0cff60c6 1890 if (unlikely(!sw_context->kernel)) {
4084fb89
JB
1891 DRM_ERROR("Kernel only SVGA command: %u.\n", cmd_id);
1892 return -EPERM;
1893 }
1894
1895 if (cmd_id == SVGA_CMD_DEFINE_GMRFB)
1896 return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf);
1897
1898 return 0;
1899}
fb1d9738 1900
4fbd9d2e 1901static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
c373d4ea
TH
1902 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid,
1903 false, false, false),
1904 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid,
1905 false, false, false),
1906 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_COPY, &vmw_cmd_surface_copy_check,
1907 true, false, false),
1908 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_STRETCHBLT, &vmw_cmd_stretch_blt_check,
1909 true, false, false),
1910 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DMA, &vmw_cmd_dma,
1911 true, false, false),
1912 VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DEFINE, &vmw_cmd_invalid,
1913 false, false, false),
1914 VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DESTROY, &vmw_cmd_invalid,
1915 false, false, false),
1916 VMW_CMD_DEF(SVGA_3D_CMD_SETTRANSFORM, &vmw_cmd_cid_check,
1917 true, false, false),
1918 VMW_CMD_DEF(SVGA_3D_CMD_SETZRANGE, &vmw_cmd_cid_check,
1919 true, false, false),
1920 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check,
1921 true, false, false),
fb1d9738 1922 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET,
c373d4ea
TH
1923 &vmw_cmd_set_render_target_check, true, false, false),
1924 VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state,
1925 true, false, false),
1926 VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check,
1927 true, false, false),
1928 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check,
1929 true, false, false),
1930 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check,
1931 true, false, false),
1932 VMW_CMD_DEF(SVGA_3D_CMD_SETVIEWPORT, &vmw_cmd_cid_check,
1933 true, false, false),
1934 VMW_CMD_DEF(SVGA_3D_CMD_SETCLIPPLANE, &vmw_cmd_cid_check,
1935 true, false, false),
1936 VMW_CMD_DEF(SVGA_3D_CMD_CLEAR, &vmw_cmd_cid_check,
1937 true, false, false),
1938 VMW_CMD_DEF(SVGA_3D_CMD_PRESENT, &vmw_cmd_present_check,
1939 false, false, false),
d5bde956
TH
1940 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DEFINE, &vmw_cmd_shader_define,
1941 true, false, false),
1942 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_shader_destroy,
1943 true, false, false),
c373d4ea
TH
1944 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_set_shader,
1945 true, false, false),
0ccbbae4
TH
1946 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_set_shader_const,
1947 true, false, false),
c373d4ea
TH
1948 VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw,
1949 true, false, false),
1950 VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check,
1951 true, false, false),
1952 VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_begin_query,
1953 true, false, false),
1954 VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query,
1955 true, false, false),
1956 VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query,
1957 true, false, false),
1958 VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok,
1959 true, false, false),
fb1d9738 1960 VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN,
c373d4ea
TH
1961 &vmw_cmd_blt_surf_screen_check, false, false, false),
1962 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE_V2, &vmw_cmd_invalid,
1963 false, false, false),
1964 VMW_CMD_DEF(SVGA_3D_CMD_GENERATE_MIPMAPS, &vmw_cmd_invalid,
1965 false, false, false),
1966 VMW_CMD_DEF(SVGA_3D_CMD_ACTIVATE_SURFACE, &vmw_cmd_invalid,
1967 false, false, false),
1968 VMW_CMD_DEF(SVGA_3D_CMD_DEACTIVATE_SURFACE, &vmw_cmd_invalid,
1969 false, false, false),
1970 VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid,
1971 false, false, false),
1972 VMW_CMD_DEF(SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE, &vmw_cmd_invalid,
1973 false, false, false),
1974 VMW_CMD_DEF(SVGA_3D_CMD_OPEN_CONTEXT_SURFACE, &vmw_cmd_invalid,
1975 false, false, false),
1976 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_BITBLT, &vmw_cmd_invalid,
1977 false, false, false),
1978 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_TRANSBLT, &vmw_cmd_invalid,
1979 false, false, false),
1980 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_STRETCHBLT, &vmw_cmd_invalid,
1981 false, false, false),
1982 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_COLORFILL, &vmw_cmd_invalid,
1983 false, false, false),
1984 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_ALPHABLEND, &vmw_cmd_invalid,
1985 false, false, false),
1986 VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND, &vmw_cmd_invalid,
1987 false, false, false),
1988 VMW_CMD_DEF(SVGA_3D_CMD_SET_OTABLE_BASE, &vmw_cmd_invalid,
1989 false, false, true),
1990 VMW_CMD_DEF(SVGA_3D_CMD_READBACK_OTABLE, &vmw_cmd_invalid,
1991 false, false, true),
1992 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_MOB, &vmw_cmd_invalid,
1993 false, false, true),
1994 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_MOB, &vmw_cmd_invalid,
1995 false, false, true),
1996 VMW_CMD_DEF(SVGA_3D_CMD_REDEFINE_GB_MOB, &vmw_cmd_invalid,
1997 false, false, true),
1998 VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING, &vmw_cmd_invalid,
1999 false, false, true),
2000 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE, &vmw_cmd_invalid,
2001 false, false, true),
2002 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SURFACE, &vmw_cmd_invalid,
2003 false, false, true),
2004 VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SURFACE, &vmw_cmd_bind_gb_surface,
2005 true, false, true),
2006 VMW_CMD_DEF(SVGA_3D_CMD_COND_BIND_GB_SURFACE, &vmw_cmd_invalid,
2007 false, false, true),
2008 VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_IMAGE, &vmw_cmd_update_gb_image,
2009 true, false, true),
a97e2192 2010 VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_SURFACE,
c373d4ea 2011 &vmw_cmd_update_gb_surface, true, false, true),
a97e2192 2012 VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_IMAGE,
c373d4ea 2013 &vmw_cmd_readback_gb_image, true, false, true),
a97e2192 2014 VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_SURFACE,
c373d4ea 2015 &vmw_cmd_readback_gb_surface, true, false, true),
a97e2192 2016 VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_IMAGE,
c373d4ea 2017 &vmw_cmd_invalidate_gb_image, true, false, true),
a97e2192 2018 VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_SURFACE,
c373d4ea
TH
2019 &vmw_cmd_invalidate_gb_surface, true, false, true),
2020 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_CONTEXT, &vmw_cmd_invalid,
2021 false, false, true),
2022 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_CONTEXT, &vmw_cmd_invalid,
2023 false, false, true),
2024 VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_CONTEXT, &vmw_cmd_invalid,
2025 false, false, true),
2026 VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_CONTEXT, &vmw_cmd_invalid,
2027 false, false, true),
2028 VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT, &vmw_cmd_invalid,
2029 false, false, true),
2030 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SHADER, &vmw_cmd_invalid,
2031 false, false, true),
2032 VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SHADER, &vmw_cmd_bind_gb_shader,
2033 true, false, true),
2034 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SHADER, &vmw_cmd_invalid,
2035 false, false, true),
f2a0dcb1 2036 VMW_CMD_DEF(SVGA_3D_CMD_SET_OTABLE_BASE64, &vmw_cmd_invalid,
8ba07315 2037 false, false, false),
c373d4ea
TH
2038 VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_GB_QUERY, &vmw_cmd_begin_gb_query,
2039 true, false, true),
2040 VMW_CMD_DEF(SVGA_3D_CMD_END_GB_QUERY, &vmw_cmd_end_gb_query,
2041 true, false, true),
2042 VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_GB_QUERY, &vmw_cmd_wait_gb_query,
2043 true, false, true),
2044 VMW_CMD_DEF(SVGA_3D_CMD_NOP, &vmw_cmd_ok,
2045 true, false, true),
2046 VMW_CMD_DEF(SVGA_3D_CMD_ENABLE_GART, &vmw_cmd_invalid,
2047 false, false, true),
2048 VMW_CMD_DEF(SVGA_3D_CMD_DISABLE_GART, &vmw_cmd_invalid,
2049 false, false, true),
2050 VMW_CMD_DEF(SVGA_3D_CMD_MAP_MOB_INTO_GART, &vmw_cmd_invalid,
2051 false, false, true),
2052 VMW_CMD_DEF(SVGA_3D_CMD_UNMAP_GART_RANGE, &vmw_cmd_invalid,
2053 false, false, true),
2054 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET, &vmw_cmd_invalid,
2055 false, false, true),
2056 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET, &vmw_cmd_invalid,
2057 false, false, true),
2058 VMW_CMD_DEF(SVGA_3D_CMD_BIND_GB_SCREENTARGET, &vmw_cmd_invalid,
2059 false, false, true),
2060 VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET, &vmw_cmd_invalid,
2061 false, false, true),
2062 VMW_CMD_DEF(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL, &vmw_cmd_invalid,
2063 false, false, true),
2064 VMW_CMD_DEF(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL, &vmw_cmd_invalid,
2065 false, false, true),
2066 VMW_CMD_DEF(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE, &vmw_cmd_cid_check,
2067 true, false, true)
fb1d9738
JB
2068};
2069
2070static int vmw_cmd_check(struct vmw_private *dev_priv,
2071 struct vmw_sw_context *sw_context,
2072 void *buf, uint32_t *size)
2073{
2074 uint32_t cmd_id;
7a73ba74 2075 uint32_t size_remaining = *size;
fb1d9738
JB
2076 SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf;
2077 int ret;
c373d4ea
TH
2078 const struct vmw_cmd_entry *entry;
2079 bool gb = dev_priv->capabilities & SVGA_CAP_GBOBJECTS;
fb1d9738 2080
4084fb89
JB
2081 cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
2082 /* Handle any none 3D commands */
2083 if (unlikely(cmd_id < SVGA_CMD_MAX))
2084 return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size);
2085
fb1d9738
JB
2086
2087 cmd_id = le32_to_cpu(header->id);
2088 *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader);
2089
2090 cmd_id -= SVGA_3D_CMD_BASE;
7a73ba74 2091 if (unlikely(*size > size_remaining))
c373d4ea 2092 goto out_invalid;
7a73ba74 2093
fb1d9738 2094 if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE))
c373d4ea
TH
2095 goto out_invalid;
2096
2097 entry = &vmw_cmd_entries[cmd_id];
36e952c1
TH
2098 if (unlikely(!entry->func))
2099 goto out_invalid;
2100
c373d4ea
TH
2101 if (unlikely(!entry->user_allow && !sw_context->kernel))
2102 goto out_privileged;
2103
2104 if (unlikely(entry->gb_disable && gb))
2105 goto out_old;
2106
2107 if (unlikely(entry->gb_enable && !gb))
2108 goto out_new;
fb1d9738 2109
c373d4ea 2110 ret = entry->func(dev_priv, sw_context, header);
fb1d9738 2111 if (unlikely(ret != 0))
c373d4ea 2112 goto out_invalid;
fb1d9738
JB
2113
2114 return 0;
c373d4ea
TH
2115out_invalid:
2116 DRM_ERROR("Invalid SVGA3D command: %d\n",
2117 cmd_id + SVGA_3D_CMD_BASE);
2118 return -EINVAL;
2119out_privileged:
2120 DRM_ERROR("Privileged SVGA3D command: %d\n",
2121 cmd_id + SVGA_3D_CMD_BASE);
2122 return -EPERM;
2123out_old:
2124 DRM_ERROR("Deprecated (disallowed) SVGA3D command: %d\n",
2125 cmd_id + SVGA_3D_CMD_BASE);
2126 return -EINVAL;
2127out_new:
2128 DRM_ERROR("SVGA3D command: %d not supported by virtual hardware.\n",
fb1d9738
JB
2129 cmd_id + SVGA_3D_CMD_BASE);
2130 return -EINVAL;
2131}
2132
2133static int vmw_cmd_check_all(struct vmw_private *dev_priv,
2134 struct vmw_sw_context *sw_context,
922ade0d 2135 void *buf,
be38ab6e 2136 uint32_t size)
fb1d9738
JB
2137{
2138 int32_t cur_size = size;
2139 int ret;
2140
c0951b79
TH
2141 sw_context->buf_start = buf;
2142
fb1d9738 2143 while (cur_size > 0) {
7a73ba74 2144 size = cur_size;
fb1d9738
JB
2145 ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);
2146 if (unlikely(ret != 0))
2147 return ret;
2148 buf = (void *)((unsigned long) buf + size);
2149 cur_size -= size;
2150 }
2151
2152 if (unlikely(cur_size != 0)) {
2153 DRM_ERROR("Command verifier out of sync.\n");
2154 return -EINVAL;
2155 }
2156
2157 return 0;
2158}
2159
2160static void vmw_free_relocations(struct vmw_sw_context *sw_context)
2161{
2162 sw_context->cur_reloc = 0;
2163}
2164
2165static void vmw_apply_relocations(struct vmw_sw_context *sw_context)
2166{
2167 uint32_t i;
2168 struct vmw_relocation *reloc;
2169 struct ttm_validate_buffer *validate;
2170 struct ttm_buffer_object *bo;
2171
2172 for (i = 0; i < sw_context->cur_reloc; ++i) {
2173 reloc = &sw_context->relocs[i];
c0951b79 2174 validate = &sw_context->val_bufs[reloc->index].base;
fb1d9738 2175 bo = validate->bo;
c0951b79
TH
2176 switch (bo->mem.mem_type) {
2177 case TTM_PL_VRAM:
135cba0d
TH
2178 reloc->location->offset += bo->offset;
2179 reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
c0951b79
TH
2180 break;
2181 case VMW_PL_GMR:
135cba0d 2182 reloc->location->gmrId = bo->mem.start;
c0951b79 2183 break;
ddcda24e
TH
2184 case VMW_PL_MOB:
2185 *reloc->mob_loc = bo->mem.start;
2186 break;
c0951b79
TH
2187 default:
2188 BUG();
2189 }
fb1d9738
JB
2190 }
2191 vmw_free_relocations(sw_context);
2192}
2193
c0951b79
TH
2194/**
2195 * vmw_resource_list_unrefererence - Free up a resource list and unreference
2196 * all resources referenced by it.
2197 *
2198 * @list: The resource list.
2199 */
2200static void vmw_resource_list_unreference(struct list_head *list)
2201{
2202 struct vmw_resource_val_node *val, *val_next;
2203
2204 /*
2205 * Drop references to resources held during command submission.
2206 */
2207
2208 list_for_each_entry_safe(val, val_next, list, head) {
2209 list_del_init(&val->head);
2210 vmw_resource_unreference(&val->res);
b5c3b1a6
TH
2211 if (unlikely(val->staged_bindings))
2212 kfree(val->staged_bindings);
c0951b79
TH
2213 kfree(val);
2214 }
2215}
2216
fb1d9738
JB
2217static void vmw_clear_validations(struct vmw_sw_context *sw_context)
2218{
c0951b79
TH
2219 struct vmw_validate_buffer *entry, *next;
2220 struct vmw_resource_val_node *val;
fb1d9738 2221
be38ab6e
TH
2222 /*
2223 * Drop references to DMA buffers held during command submission.
2224 */
fb1d9738 2225 list_for_each_entry_safe(entry, next, &sw_context->validate_nodes,
c0951b79
TH
2226 base.head) {
2227 list_del(&entry->base.head);
2228 ttm_bo_unref(&entry->base.bo);
2229 (void) drm_ht_remove_item(&sw_context->res_ht, &entry->hash);
fb1d9738
JB
2230 sw_context->cur_val_buf--;
2231 }
2232 BUG_ON(sw_context->cur_val_buf != 0);
be38ab6e 2233
c0951b79
TH
2234 list_for_each_entry(val, &sw_context->resource_list, head)
2235 (void) drm_ht_remove_item(&sw_context->res_ht, &val->hash);
fb1d9738
JB
2236}
2237
2238static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
96c5f0df
TH
2239 struct ttm_buffer_object *bo,
2240 bool validate_as_mob)
fb1d9738
JB
2241{
2242 int ret;
2243
e2fa3a76
TH
2244
2245 /*
2246 * Don't validate pinned buffers.
2247 */
2248
2249 if (bo == dev_priv->pinned_bo ||
2250 (bo == dev_priv->dummy_query_bo &&
2251 dev_priv->dummy_query_bo_pinned))
2252 return 0;
2253
96c5f0df
TH
2254 if (validate_as_mob)
2255 return ttm_bo_validate(bo, &vmw_mob_placement, true, false);
2256
8ba5152a 2257 /**
135cba0d
TH
2258 * Put BO in VRAM if there is space, otherwise as a GMR.
2259 * If there is no space in VRAM and GMR ids are all used up,
2260 * start evicting GMRs to make room. If the DMA buffer can't be
2261 * used as a GMR, this will return -ENOMEM.
8ba5152a
TH
2262 */
2263
97a875cb 2264 ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, true, false);
3d3a5b32 2265 if (likely(ret == 0 || ret == -ERESTARTSYS))
fb1d9738
JB
2266 return ret;
2267
8ba5152a
TH
2268 /**
2269 * If that failed, try VRAM again, this time evicting
2270 * previous contents.
2271 */
fb1d9738 2272
135cba0d 2273 DRM_INFO("Falling through to VRAM.\n");
97a875cb 2274 ret = ttm_bo_validate(bo, &vmw_vram_placement, true, false);
fb1d9738
JB
2275 return ret;
2276}
2277
fb1d9738
JB
2278static int vmw_validate_buffers(struct vmw_private *dev_priv,
2279 struct vmw_sw_context *sw_context)
2280{
c0951b79 2281 struct vmw_validate_buffer *entry;
fb1d9738
JB
2282 int ret;
2283
c0951b79 2284 list_for_each_entry(entry, &sw_context->validate_nodes, base.head) {
96c5f0df
TH
2285 ret = vmw_validate_single_buffer(dev_priv, entry->base.bo,
2286 entry->validate_as_mob);
fb1d9738
JB
2287 if (unlikely(ret != 0))
2288 return ret;
2289 }
2290 return 0;
2291}
2292
be38ab6e
TH
2293static int vmw_resize_cmd_bounce(struct vmw_sw_context *sw_context,
2294 uint32_t size)
2295{
2296 if (likely(sw_context->cmd_bounce_size >= size))
2297 return 0;
2298
2299 if (sw_context->cmd_bounce_size == 0)
2300 sw_context->cmd_bounce_size = VMWGFX_CMD_BOUNCE_INIT_SIZE;
2301
2302 while (sw_context->cmd_bounce_size < size) {
2303 sw_context->cmd_bounce_size =
2304 PAGE_ALIGN(sw_context->cmd_bounce_size +
2305 (sw_context->cmd_bounce_size >> 1));
2306 }
2307
2308 if (sw_context->cmd_bounce != NULL)
2309 vfree(sw_context->cmd_bounce);
2310
2311 sw_context->cmd_bounce = vmalloc(sw_context->cmd_bounce_size);
2312
2313 if (sw_context->cmd_bounce == NULL) {
2314 DRM_ERROR("Failed to allocate command bounce buffer.\n");
2315 sw_context->cmd_bounce_size = 0;
2316 return -ENOMEM;
2317 }
2318
2319 return 0;
2320}
2321
ae2a1040
TH
2322/**
2323 * vmw_execbuf_fence_commands - create and submit a command stream fence
2324 *
2325 * Creates a fence object and submits a command stream marker.
2326 * If this fails for some reason, We sync the fifo and return NULL.
2327 * It is then safe to fence buffers with a NULL pointer.
6070e9fa
JB
2328 *
2329 * If @p_handle is not NULL @file_priv must also not be NULL. Creates
2330 * a userspace handle if @p_handle is not NULL, otherwise not.
ae2a1040
TH
2331 */
2332
2333int vmw_execbuf_fence_commands(struct drm_file *file_priv,
2334 struct vmw_private *dev_priv,
2335 struct vmw_fence_obj **p_fence,
2336 uint32_t *p_handle)
2337{
2338 uint32_t sequence;
2339 int ret;
2340 bool synced = false;
2341
6070e9fa
JB
2342 /* p_handle implies file_priv. */
2343 BUG_ON(p_handle != NULL && file_priv == NULL);
ae2a1040
TH
2344
2345 ret = vmw_fifo_send_fence(dev_priv, &sequence);
2346 if (unlikely(ret != 0)) {
2347 DRM_ERROR("Fence submission error. Syncing.\n");
2348 synced = true;
2349 }
2350
2351 if (p_handle != NULL)
2352 ret = vmw_user_fence_create(file_priv, dev_priv->fman,
c060a4e1 2353 sequence, p_fence, p_handle);
ae2a1040 2354 else
c060a4e1 2355 ret = vmw_fence_create(dev_priv->fman, sequence, p_fence);
ae2a1040
TH
2356
2357 if (unlikely(ret != 0 && !synced)) {
2358 (void) vmw_fallback_wait(dev_priv, false, false,
2359 sequence, false,
2360 VMW_FENCE_WAIT_TIMEOUT);
2361 *p_fence = NULL;
2362 }
2363
2364 return 0;
2365}
2366
8bf445ce
TH
2367/**
2368 * vmw_execbuf_copy_fence_user - copy fence object information to
2369 * user-space.
2370 *
2371 * @dev_priv: Pointer to a vmw_private struct.
2372 * @vmw_fp: Pointer to the struct vmw_fpriv representing the calling file.
2373 * @ret: Return value from fence object creation.
2374 * @user_fence_rep: User space address of a struct drm_vmw_fence_rep to
2375 * which the information should be copied.
2376 * @fence: Pointer to the fenc object.
2377 * @fence_handle: User-space fence handle.
2378 *
2379 * This function copies fence information to user-space. If copying fails,
2380 * The user-space struct drm_vmw_fence_rep::error member is hopefully
2381 * left untouched, and if it's preloaded with an -EFAULT by user-space,
2382 * the error will hopefully be detected.
2383 * Also if copying fails, user-space will be unable to signal the fence
2384 * object so we wait for it immediately, and then unreference the
2385 * user-space reference.
2386 */
57c5ee79 2387void
8bf445ce
TH
2388vmw_execbuf_copy_fence_user(struct vmw_private *dev_priv,
2389 struct vmw_fpriv *vmw_fp,
2390 int ret,
2391 struct drm_vmw_fence_rep __user *user_fence_rep,
2392 struct vmw_fence_obj *fence,
2393 uint32_t fence_handle)
2394{
2395 struct drm_vmw_fence_rep fence_rep;
2396
2397 if (user_fence_rep == NULL)
2398 return;
2399
80d9b24a
DC
2400 memset(&fence_rep, 0, sizeof(fence_rep));
2401
8bf445ce
TH
2402 fence_rep.error = ret;
2403 if (ret == 0) {
2404 BUG_ON(fence == NULL);
2405
2406 fence_rep.handle = fence_handle;
2298e804 2407 fence_rep.seqno = fence->base.seqno;
8bf445ce
TH
2408 vmw_update_seqno(dev_priv, &dev_priv->fifo);
2409 fence_rep.passed_seqno = dev_priv->last_read_seqno;
2410 }
2411
2412 /*
2413 * copy_to_user errors will be detected by user space not
2414 * seeing fence_rep::error filled in. Typically
2415 * user-space would have pre-set that member to -EFAULT.
2416 */
2417 ret = copy_to_user(user_fence_rep, &fence_rep,
2418 sizeof(fence_rep));
2419
2420 /*
2421 * User-space lost the fence object. We need to sync
2422 * and unreference the handle.
2423 */
2424 if (unlikely(ret != 0) && (fence_rep.error == 0)) {
2425 ttm_ref_object_base_unref(vmw_fp->tfile,
2426 fence_handle, TTM_REF_USAGE);
2427 DRM_ERROR("Fence copy error. Syncing.\n");
c060a4e1 2428 (void) vmw_fence_obj_wait(fence, false, false,
8bf445ce
TH
2429 VMW_FENCE_WAIT_TIMEOUT);
2430 }
2431}
2432
3eab3d9e
TH
2433/**
2434 * vmw_execbuf_submit_fifo - Patch a command batch and submit it using
2435 * the fifo.
2436 *
2437 * @dev_priv: Pointer to a device private structure.
2438 * @kernel_commands: Pointer to the unpatched command batch.
2439 * @command_size: Size of the unpatched command batch.
2440 * @sw_context: Structure holding the relocation lists.
2441 *
2442 * Side effects: If this function returns 0, then the command batch
2443 * pointed to by @kernel_commands will have been modified.
2444 */
2445static int vmw_execbuf_submit_fifo(struct vmw_private *dev_priv,
2446 void *kernel_commands,
2447 u32 command_size,
2448 struct vmw_sw_context *sw_context)
2449{
2450 void *cmd = vmw_fifo_reserve(dev_priv, command_size);
2451
2452 if (!cmd) {
2453 DRM_ERROR("Failed reserving fifo space for commands.\n");
2454 return -ENOMEM;
2455 }
18e4a466 2456
3eab3d9e
TH
2457 vmw_apply_relocations(sw_context);
2458 memcpy(cmd, kernel_commands, command_size);
2459 vmw_resource_relocations_apply(cmd, &sw_context->res_relocations);
2460 vmw_resource_relocations_free(&sw_context->res_relocations);
2461 vmw_fifo_commit(dev_priv, command_size);
2462
2463 return 0;
2464}
2465
2466/**
2467 * vmw_execbuf_submit_cmdbuf - Patch a command batch and submit it using
2468 * the command buffer manager.
2469 *
2470 * @dev_priv: Pointer to a device private structure.
2471 * @header: Opaque handle to the command buffer allocation.
2472 * @command_size: Size of the unpatched command batch.
2473 * @sw_context: Structure holding the relocation lists.
2474 *
2475 * Side effects: If this function returns 0, then the command buffer
2476 * represented by @header will have been modified.
2477 */
2478static int vmw_execbuf_submit_cmdbuf(struct vmw_private *dev_priv,
2479 struct vmw_cmdbuf_header *header,
2480 u32 command_size,
2481 struct vmw_sw_context *sw_context)
2482{
2483 void *cmd = vmw_cmdbuf_reserve(dev_priv->cman, command_size,
2484 SVGA3D_INVALID_ID, false, header);
2485
2486 vmw_apply_relocations(sw_context);
2487 vmw_resource_relocations_apply(cmd, &sw_context->res_relocations);
2488 vmw_resource_relocations_free(&sw_context->res_relocations);
2489 vmw_cmdbuf_commit(dev_priv->cman, command_size, header, false);
2490
2491 return 0;
2492}
2493
2494/**
2495 * vmw_execbuf_cmdbuf - Prepare, if possible, a user-space command batch for
2496 * submission using a command buffer.
2497 *
2498 * @dev_priv: Pointer to a device private structure.
2499 * @user_commands: User-space pointer to the commands to be submitted.
2500 * @command_size: Size of the unpatched command batch.
2501 * @header: Out parameter returning the opaque pointer to the command buffer.
2502 *
2503 * This function checks whether we can use the command buffer manager for
2504 * submission and if so, creates a command buffer of suitable size and
2505 * copies the user data into that buffer.
2506 *
2507 * On successful return, the function returns a pointer to the data in the
2508 * command buffer and *@header is set to non-NULL.
2509 * If command buffers could not be used, the function will return the value
2510 * of @kernel_commands on function call. That value may be NULL. In that case,
2511 * the value of *@header will be set to NULL.
2512 * If an error is encountered, the function will return a pointer error value.
2513 * If the function is interrupted by a signal while sleeping, it will return
2514 * -ERESTARTSYS casted to a pointer error value.
2515 */
2516void *vmw_execbuf_cmdbuf(struct vmw_private *dev_priv,
2517 void __user *user_commands,
2518 void *kernel_commands,
2519 u32 command_size,
2520 struct vmw_cmdbuf_header **header)
2521{
2522 size_t cmdbuf_size;
2523 int ret;
2524
2525 *header = NULL;
2526 if (!dev_priv->cman || kernel_commands)
2527 return kernel_commands;
2528
2529 if (command_size > SVGA_CB_MAX_SIZE) {
2530 DRM_ERROR("Command buffer is too large.\n");
2531 return ERR_PTR(-EINVAL);
2532 }
2533
2534 /* If possible, add a little space for fencing. */
2535 cmdbuf_size = command_size + 512;
2536 cmdbuf_size = min_t(size_t, cmdbuf_size, SVGA_CB_MAX_SIZE);
2537 kernel_commands = vmw_cmdbuf_alloc(dev_priv->cman, cmdbuf_size,
2538 true, header);
2539 if (IS_ERR(kernel_commands))
2540 return kernel_commands;
2541
2542 ret = copy_from_user(kernel_commands, user_commands,
2543 command_size);
2544 if (ret) {
2545 DRM_ERROR("Failed copying commands.\n");
2546 vmw_cmdbuf_header_free(*header);
2547 *header = NULL;
2548 return ERR_PTR(-EFAULT);
2549 }
2550
2551 return kernel_commands;
2552}
18e4a466 2553
922ade0d
TH
2554int vmw_execbuf_process(struct drm_file *file_priv,
2555 struct vmw_private *dev_priv,
2556 void __user *user_commands,
2557 void *kernel_commands,
2558 uint32_t command_size,
2559 uint64_t throttle_us,
c9146cd9 2560 uint32_t quirks,
bb1bd2f4
JB
2561 struct drm_vmw_fence_rep __user *user_fence_rep,
2562 struct vmw_fence_obj **out_fence)
fb1d9738 2563{
fb1d9738 2564 struct vmw_sw_context *sw_context = &dev_priv->ctx;
bb1bd2f4 2565 struct vmw_fence_obj *fence = NULL;
c0951b79
TH
2566 struct vmw_resource *error_resource;
2567 struct list_head resource_list;
3eab3d9e 2568 struct vmw_cmdbuf_header *header;
ecff665f 2569 struct ww_acquire_ctx ticket;
ae2a1040 2570 uint32_t handle;
922ade0d 2571 int ret;
fb1d9738 2572
3eab3d9e
TH
2573 if (throttle_us) {
2574 ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue,
2575 throttle_us);
2576
2577 if (ret)
2578 return ret;
2579 }
2580
2581 kernel_commands = vmw_execbuf_cmdbuf(dev_priv, user_commands,
2582 kernel_commands, command_size,
2583 &header);
2584 if (IS_ERR(kernel_commands))
2585 return PTR_ERR(kernel_commands);
2586
922ade0d 2587 ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
3eab3d9e
TH
2588 if (ret) {
2589 ret = -ERESTARTSYS;
2590 goto out_free_header;
2591 }
fb1d9738 2592
3eab3d9e 2593 sw_context->kernel = false;
922ade0d 2594 if (kernel_commands == NULL) {
922ade0d
TH
2595 ret = vmw_resize_cmd_bounce(sw_context, command_size);
2596 if (unlikely(ret != 0))
2597 goto out_unlock;
fb1d9738 2598
fb1d9738 2599
922ade0d
TH
2600 ret = copy_from_user(sw_context->cmd_bounce,
2601 user_commands, command_size);
2602
2603 if (unlikely(ret != 0)) {
2604 ret = -EFAULT;
2605 DRM_ERROR("Failed copying commands.\n");
2606 goto out_unlock;
2607 }
2608 kernel_commands = sw_context->cmd_bounce;
3eab3d9e 2609 } else if (!header)
922ade0d 2610 sw_context->kernel = true;
fb1d9738 2611
d5bde956 2612 sw_context->fp = vmw_fpriv(file_priv);
fb1d9738
JB
2613 sw_context->cur_reloc = 0;
2614 sw_context->cur_val_buf = 0;
c9146cd9 2615 sw_context->quirks = quirks;
f18c8840 2616 INIT_LIST_HEAD(&sw_context->resource_list);
e2fa3a76 2617 sw_context->cur_query_bo = dev_priv->pinned_bo;
c0951b79
TH
2618 sw_context->last_query_ctx = NULL;
2619 sw_context->needs_post_query_barrier = false;
2620 memset(sw_context->res_cache, 0, sizeof(sw_context->res_cache));
fb1d9738 2621 INIT_LIST_HEAD(&sw_context->validate_nodes);
c0951b79
TH
2622 INIT_LIST_HEAD(&sw_context->res_relocations);
2623 if (!sw_context->res_ht_initialized) {
2624 ret = drm_ht_create(&sw_context->res_ht, VMW_RES_HT_ORDER);
2625 if (unlikely(ret != 0))
2626 goto out_unlock;
2627 sw_context->res_ht_initialized = true;
2628 }
18e4a466 2629 INIT_LIST_HEAD(&sw_context->staged_cmd_res);
c0951b79 2630 INIT_LIST_HEAD(&resource_list);
922ade0d
TH
2631 ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands,
2632 command_size);
fb1d9738 2633 if (unlikely(ret != 0))
cf5e3413 2634 goto out_err_nores;
be38ab6e 2635
c0951b79
TH
2636 ret = vmw_resources_reserve(sw_context);
2637 if (unlikely(ret != 0))
cf5e3413 2638 goto out_err_nores;
c0951b79 2639
aa35071c
CK
2640 ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes,
2641 true, NULL);
fb1d9738
JB
2642 if (unlikely(ret != 0))
2643 goto out_err;
2644
2645 ret = vmw_validate_buffers(dev_priv, sw_context);
2646 if (unlikely(ret != 0))
2647 goto out_err;
2648
c0951b79
TH
2649 ret = vmw_resources_validate(sw_context);
2650 if (unlikely(ret != 0))
2651 goto out_err;
1925d456 2652
173fb7d4
TH
2653 ret = mutex_lock_interruptible(&dev_priv->binding_mutex);
2654 if (unlikely(ret != 0)) {
2655 ret = -ERESTARTSYS;
2656 goto out_err;
2657 }
2658
30f82d81
TH
2659 if (dev_priv->has_mob) {
2660 ret = vmw_rebind_contexts(sw_context);
2661 if (unlikely(ret != 0))
b2ad9881 2662 goto out_unlock_binding;
30f82d81
TH
2663 }
2664
3eab3d9e
TH
2665 if (!header) {
2666 ret = vmw_execbuf_submit_fifo(dev_priv, kernel_commands,
2667 command_size, sw_context);
2668 } else {
2669 ret = vmw_execbuf_submit_cmdbuf(dev_priv, header, command_size,
2670 sw_context);
2671 header = NULL;
1925d456 2672 }
3eab3d9e
TH
2673 if (ret)
2674 goto out_unlock_binding;
fb1d9738 2675
e2fa3a76 2676 vmw_query_bo_switch_commit(dev_priv, sw_context);
ae2a1040
TH
2677 ret = vmw_execbuf_fence_commands(file_priv, dev_priv,
2678 &fence,
2679 (user_fence_rep) ? &handle : NULL);
fb1d9738
JB
2680 /*
2681 * This error is harmless, because if fence submission fails,
ae2a1040
TH
2682 * vmw_fifo_send_fence will sync. The error will be propagated to
2683 * user-space in @fence_rep
fb1d9738
JB
2684 */
2685
2686 if (ret != 0)
2687 DRM_ERROR("Fence submission error. Syncing.\n");
2688
c0951b79 2689 vmw_resource_list_unreserve(&sw_context->resource_list, false);
173fb7d4
TH
2690 mutex_unlock(&dev_priv->binding_mutex);
2691
ecff665f 2692 ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes,
ae2a1040 2693 (void *) fence);
fb1d9738 2694
c0951b79
TH
2695 if (unlikely(dev_priv->pinned_bo != NULL &&
2696 !dev_priv->query_cid_valid))
2697 __vmw_execbuf_release_pinned_bo(dev_priv, fence);
2698
ae2a1040 2699 vmw_clear_validations(sw_context);
8bf445ce
TH
2700 vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret,
2701 user_fence_rep, fence, handle);
fb1d9738 2702
bb1bd2f4
JB
2703 /* Don't unreference when handing fence out */
2704 if (unlikely(out_fence != NULL)) {
2705 *out_fence = fence;
2706 fence = NULL;
2707 } else if (likely(fence != NULL)) {
ae2a1040 2708 vmw_fence_obj_unreference(&fence);
bb1bd2f4 2709 }
fb1d9738 2710
c0951b79 2711 list_splice_init(&sw_context->resource_list, &resource_list);
18e4a466 2712 vmw_cmdbuf_res_commit(&sw_context->staged_cmd_res);
922ade0d 2713 mutex_unlock(&dev_priv->cmdbuf_mutex);
c0951b79
TH
2714
2715 /*
2716 * Unreference resources outside of the cmdbuf_mutex to
2717 * avoid deadlocks in resource destruction paths.
2718 */
2719 vmw_resource_list_unreference(&resource_list);
2720
fb1d9738 2721 return 0;
922ade0d 2722
173fb7d4
TH
2723out_unlock_binding:
2724 mutex_unlock(&dev_priv->binding_mutex);
fb1d9738 2725out_err:
ecff665f 2726 ttm_eu_backoff_reservation(&ticket, &sw_context->validate_nodes);
cf5e3413 2727out_err_nores:
c0951b79 2728 vmw_resource_list_unreserve(&sw_context->resource_list, true);
cf5e3413
TH
2729 vmw_resource_relocations_free(&sw_context->res_relocations);
2730 vmw_free_relocations(sw_context);
fb1d9738 2731 vmw_clear_validations(sw_context);
c0951b79
TH
2732 if (unlikely(dev_priv->pinned_bo != NULL &&
2733 !dev_priv->query_cid_valid))
2734 __vmw_execbuf_release_pinned_bo(dev_priv, NULL);
fb1d9738 2735out_unlock:
c0951b79
TH
2736 list_splice_init(&sw_context->resource_list, &resource_list);
2737 error_resource = sw_context->error_resource;
2738 sw_context->error_resource = NULL;
18e4a466 2739 vmw_cmdbuf_res_revert(&sw_context->staged_cmd_res);
fb1d9738 2740 mutex_unlock(&dev_priv->cmdbuf_mutex);
c0951b79
TH
2741
2742 /*
2743 * Unreference resources outside of the cmdbuf_mutex to
2744 * avoid deadlocks in resource destruction paths.
2745 */
2746 vmw_resource_list_unreference(&resource_list);
2747 if (unlikely(error_resource != NULL))
2748 vmw_resource_unreference(&error_resource);
3eab3d9e
TH
2749out_free_header:
2750 if (header)
2751 vmw_cmdbuf_header_free(header);
c0951b79 2752
922ade0d
TH
2753 return ret;
2754}
2755
e2fa3a76
TH
2756/**
2757 * vmw_execbuf_unpin_panic - Idle the fifo and unpin the query buffer.
2758 *
2759 * @dev_priv: The device private structure.
2760 *
2761 * This function is called to idle the fifo and unpin the query buffer
2762 * if the normal way to do this hits an error, which should typically be
2763 * extremely rare.
2764 */
2765static void vmw_execbuf_unpin_panic(struct vmw_private *dev_priv)
2766{
2767 DRM_ERROR("Can't unpin query buffer. Trying to recover.\n");
2768
2769 (void) vmw_fallback_wait(dev_priv, false, true, 0, false, 10*HZ);
2770 vmw_bo_pin(dev_priv->pinned_bo, false);
2771 vmw_bo_pin(dev_priv->dummy_query_bo, false);
2772 dev_priv->dummy_query_bo_pinned = false;
2773}
2774
2775
2776/**
c0951b79 2777 * __vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned
e2fa3a76
TH
2778 * query bo.
2779 *
2780 * @dev_priv: The device private structure.
c0951b79
TH
2781 * @fence: If non-NULL should point to a struct vmw_fence_obj issued
2782 * _after_ a query barrier that flushes all queries touching the current
2783 * buffer pointed to by @dev_priv->pinned_bo
e2fa3a76
TH
2784 *
2785 * This function should be used to unpin the pinned query bo, or
2786 * as a query barrier when we need to make sure that all queries have
2787 * finished before the next fifo command. (For example on hardware
2788 * context destructions where the hardware may otherwise leak unfinished
2789 * queries).
2790 *
2791 * This function does not return any failure codes, but make attempts
2792 * to do safe unpinning in case of errors.
2793 *
2794 * The function will synchronize on the previous query barrier, and will
2795 * thus not finish until that barrier has executed.
c0951b79
TH
2796 *
2797 * the @dev_priv->cmdbuf_mutex needs to be held by the current thread
2798 * before calling this function.
e2fa3a76 2799 */
c0951b79
TH
2800void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv,
2801 struct vmw_fence_obj *fence)
e2fa3a76
TH
2802{
2803 int ret = 0;
2804 struct list_head validate_list;
2805 struct ttm_validate_buffer pinned_val, query_val;
c0951b79 2806 struct vmw_fence_obj *lfence = NULL;
ecff665f 2807 struct ww_acquire_ctx ticket;
e2fa3a76
TH
2808
2809 if (dev_priv->pinned_bo == NULL)
2810 goto out_unlock;
2811
e2fa3a76
TH
2812 INIT_LIST_HEAD(&validate_list);
2813
e2fa3a76 2814 pinned_val.bo = ttm_bo_reference(dev_priv->pinned_bo);
ae9c0af2 2815 pinned_val.shared = false;
e2fa3a76
TH
2816 list_add_tail(&pinned_val.head, &validate_list);
2817
e2fa3a76 2818 query_val.bo = ttm_bo_reference(dev_priv->dummy_query_bo);
ae9c0af2 2819 query_val.shared = false;
e2fa3a76
TH
2820 list_add_tail(&query_val.head, &validate_list);
2821
aa35071c
CK
2822 ret = ttm_eu_reserve_buffers(&ticket, &validate_list,
2823 false, NULL);
e2fa3a76
TH
2824 if (unlikely(ret != 0)) {
2825 vmw_execbuf_unpin_panic(dev_priv);
2826 goto out_no_reserve;
2827 }
2828
c0951b79
TH
2829 if (dev_priv->query_cid_valid) {
2830 BUG_ON(fence != NULL);
2831 ret = vmw_fifo_emit_dummy_query(dev_priv, dev_priv->query_cid);
2832 if (unlikely(ret != 0)) {
2833 vmw_execbuf_unpin_panic(dev_priv);
2834 goto out_no_emit;
2835 }
2836 dev_priv->query_cid_valid = false;
e2fa3a76
TH
2837 }
2838
2839 vmw_bo_pin(dev_priv->pinned_bo, false);
2840 vmw_bo_pin(dev_priv->dummy_query_bo, false);
2841 dev_priv->dummy_query_bo_pinned = false;
2842
c0951b79
TH
2843 if (fence == NULL) {
2844 (void) vmw_execbuf_fence_commands(NULL, dev_priv, &lfence,
2845 NULL);
2846 fence = lfence;
2847 }
ecff665f 2848 ttm_eu_fence_buffer_objects(&ticket, &validate_list, (void *) fence);
c0951b79
TH
2849 if (lfence != NULL)
2850 vmw_fence_obj_unreference(&lfence);
e2fa3a76
TH
2851
2852 ttm_bo_unref(&query_val.bo);
2853 ttm_bo_unref(&pinned_val.bo);
2854 ttm_bo_unref(&dev_priv->pinned_bo);
2855
2856out_unlock:
e2fa3a76
TH
2857 return;
2858
2859out_no_emit:
ecff665f 2860 ttm_eu_backoff_reservation(&ticket, &validate_list);
e2fa3a76
TH
2861out_no_reserve:
2862 ttm_bo_unref(&query_val.bo);
2863 ttm_bo_unref(&pinned_val.bo);
2864 ttm_bo_unref(&dev_priv->pinned_bo);
c0951b79
TH
2865}
2866
2867/**
2868 * vmw_execbuf_release_pinned_bo - Flush queries and unpin the pinned
2869 * query bo.
2870 *
2871 * @dev_priv: The device private structure.
2872 *
2873 * This function should be used to unpin the pinned query bo, or
2874 * as a query barrier when we need to make sure that all queries have
2875 * finished before the next fifo command. (For example on hardware
2876 * context destructions where the hardware may otherwise leak unfinished
2877 * queries).
2878 *
2879 * This function does not return any failure codes, but make attempts
2880 * to do safe unpinning in case of errors.
2881 *
2882 * The function will synchronize on the previous query barrier, and will
2883 * thus not finish until that barrier has executed.
2884 */
2885void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv)
2886{
2887 mutex_lock(&dev_priv->cmdbuf_mutex);
2888 if (dev_priv->query_cid_valid)
2889 __vmw_execbuf_release_pinned_bo(dev_priv, NULL);
e2fa3a76
TH
2890 mutex_unlock(&dev_priv->cmdbuf_mutex);
2891}
2892
922ade0d
TH
2893
2894int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
2895 struct drm_file *file_priv)
2896{
2897 struct vmw_private *dev_priv = vmw_priv(dev);
2898 struct drm_vmw_execbuf_arg *arg = (struct drm_vmw_execbuf_arg *)data;
922ade0d
TH
2899 int ret;
2900
2901 /*
2902 * This will allow us to extend the ioctl argument while
2903 * maintaining backwards compatibility:
2904 * We take different code paths depending on the value of
2905 * arg->version.
2906 */
2907
2908 if (unlikely(arg->version != DRM_VMW_EXECBUF_VERSION)) {
2909 DRM_ERROR("Incorrect execbuf version.\n");
2910 DRM_ERROR("You're running outdated experimental "
2911 "vmwgfx user-space drivers.");
2912 return -EINVAL;
2913 }
2914
294adf7d 2915 ret = ttm_read_lock(&dev_priv->reservation_sem, true);
922ade0d
TH
2916 if (unlikely(ret != 0))
2917 return ret;
2918
2919 ret = vmw_execbuf_process(file_priv, dev_priv,
2920 (void __user *)(unsigned long)arg->commands,
2921 NULL, arg->command_size, arg->throttle_us,
c9146cd9 2922 0,
bb1bd2f4
JB
2923 (void __user *)(unsigned long)arg->fence_rep,
2924 NULL);
5151adb3 2925 ttm_read_unlock(&dev_priv->reservation_sem);
922ade0d 2926 if (unlikely(ret != 0))
5151adb3 2927 return ret;
922ade0d
TH
2928
2929 vmw_kms_cursor_post_execbuf(dev_priv);
2930
5151adb3 2931 return 0;
fb1d9738 2932}