projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
vmwgfx: Allow reference and unreference of NULL fence objects.
[linux-2.6-block.git] / drivers / gpu / drm / vmwgfx / vmwgfx_execbuf.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_drv.h"
29#include "vmwgfx_reg.h"
30#include "ttm/ttm_bo_api.h"
31#include "ttm/ttm_placement.h"
32
33static int vmw_cmd_invalid(struct vmw_private *dev_priv,
34 struct vmw_sw_context *sw_context,
35 SVGA3dCmdHeader *header)
36{
37 return capable(CAP_SYS_ADMIN) ? : -EINVAL;
38}
39
40static int vmw_cmd_ok(struct vmw_private *dev_priv,
41 struct vmw_sw_context *sw_context,
42 SVGA3dCmdHeader *header)
43{
44 return 0;
45}
46
be38ab6e
TH		 47
48static int vmw_resource_to_validate_list(struct vmw_sw_context *sw_context,
49 struct vmw_resource **p_res)
50{
51 int ret = 0;
52 struct vmw_resource *res = *p_res;
53
54 if (!res->on_validate_list) {
55 if (sw_context->num_ref_resources >= VMWGFX_MAX_VALIDATIONS) {
56 DRM_ERROR("Too many resources referenced in "
57 "command stream.\n");
58 ret = -ENOMEM;
59 goto out;
60 }
61 sw_context->resources[sw_context->num_ref_resources++] = res;
62 res->on_validate_list = true;
63 return 0;
64 }
65
66out:
67 vmw_resource_unreference(p_res);
68 return ret;
69}
70
fb1d9738
JB		 71static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
72 struct vmw_sw_context *sw_context,
73 SVGA3dCmdHeader *header)
74{
be38ab6e
TH		 75 struct vmw_resource *ctx;
76
fb1d9738
JB		 77 struct vmw_cid_cmd {
78 SVGA3dCmdHeader header;
79 __le32 cid;
80 } *cmd;
81 int ret;
82
83 cmd = container_of(header, struct vmw_cid_cmd, header);
84 if (likely(sw_context->cid_valid && cmd->cid == sw_context->last_cid))
85 return 0;
86
be38ab6e
TH		 87 ret = vmw_context_check(dev_priv, sw_context->tfile, cmd->cid,
88 &ctx);
fb1d9738
JB		 89 if (unlikely(ret != 0)) {
90 DRM_ERROR("Could not find or use context %u\n",
91 (unsigned) cmd->cid);
92 return ret;
93 }
94
95 sw_context->last_cid = cmd->cid;
96 sw_context->cid_valid = true;
be38ab6e 97 return vmw_resource_to_validate_list(sw_context, &ctx);
fb1d9738
JB		 98}
99
100static int vmw_cmd_sid_check(struct vmw_private *dev_priv,
101 struct vmw_sw_context *sw_context,
7a73ba74 102 uint32_t *sid)
fb1d9738 103{
be38ab6e
TH		 104 struct vmw_surface *srf;
105 int ret;
106 struct vmw_resource *res;
107
7a73ba74
TH		 108 if (*sid == SVGA3D_INVALID_ID)
109 return 0;
110
be38ab6e
TH		 111 if (likely((sw_context->sid_valid &&
112 *sid == sw_context->last_sid))) {
7a73ba74 113 *sid = sw_context->sid_translation;
be38ab6e
TH		 114 return 0;
115 }
7a73ba74 116
be38ab6e
TH		 117 ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
118 *sid, &srf);
119 if (unlikely(ret != 0)) {
120 DRM_ERROR("Could ot find or use surface 0x%08x "
121 "address 0x%08lx\n",
122 (unsigned int) *sid,
123 (unsigned long) sid);
124 return ret;
125 }
126
127 sw_context->last_sid = *sid;
128 sw_context->sid_valid = true;
129 sw_context->sid_translation = srf->res.id;
130 *sid = sw_context->sid_translation;
131
132 res = &srf->res;
133 return vmw_resource_to_validate_list(sw_context, &res);
fb1d9738
JB		 134}
135
136
137static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,
138 struct vmw_sw_context *sw_context,
139 SVGA3dCmdHeader *header)
140{
141 struct vmw_sid_cmd {
142 SVGA3dCmdHeader header;
143 SVGA3dCmdSetRenderTarget body;
144 } *cmd;
145 int ret;
146
147 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
148 if (unlikely(ret != 0))
149 return ret;
150
151 cmd = container_of(header, struct vmw_sid_cmd, header);
7a73ba74
TH		 152 ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.target.sid);
153 return ret;
fb1d9738
JB		 154}
155
156static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
157 struct vmw_sw_context *sw_context,
158 SVGA3dCmdHeader *header)
159{
160 struct vmw_sid_cmd {
161 SVGA3dCmdHeader header;
162 SVGA3dCmdSurfaceCopy body;
163 } *cmd;
164 int ret;
165
166 cmd = container_of(header, struct vmw_sid_cmd, header);
7a73ba74 167 ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
fb1d9738
JB		 168 if (unlikely(ret != 0))
169 return ret;
7a73ba74 170 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
fb1d9738
JB		 171}
172
173static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
174 struct vmw_sw_context *sw_context,
175 SVGA3dCmdHeader *header)
176{
177 struct vmw_sid_cmd {
178 SVGA3dCmdHeader header;
179 SVGA3dCmdSurfaceStretchBlt body;
180 } *cmd;
181 int ret;
182
183 cmd = container_of(header, struct vmw_sid_cmd, header);
7a73ba74 184 ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
fb1d9738
JB		 185 if (unlikely(ret != 0))
186 return ret;
7a73ba74 187 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
fb1d9738
JB		 188}
189
190static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
191 struct vmw_sw_context *sw_context,
192 SVGA3dCmdHeader *header)
193{
194 struct vmw_sid_cmd {
195 SVGA3dCmdHeader header;
196 SVGA3dCmdBlitSurfaceToScreen body;
197 } *cmd;
198
199 cmd = container_of(header, struct vmw_sid_cmd, header);
0cff60c6
JB		 200
201 if (unlikely(!sw_context->kernel)) {
202 DRM_ERROR("Kernel only SVGA3d command: %u.\n", cmd->header.id);
203 return -EPERM;
204 }
205
7a73ba74 206 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.srcImage.sid);
fb1d9738
JB		 207}
208
209static int vmw_cmd_present_check(struct vmw_private *dev_priv,
210 struct vmw_sw_context *sw_context,
211 SVGA3dCmdHeader *header)
212{
213 struct vmw_sid_cmd {
214 SVGA3dCmdHeader header;
215 SVGA3dCmdPresent body;
216 } *cmd;
217
218 cmd = container_of(header, struct vmw_sid_cmd, header);
0cff60c6
JB		 219
220 if (unlikely(!sw_context->kernel)) {
221 DRM_ERROR("Kernel only SVGA3d command: %u.\n", cmd->header.id);
222 return -EPERM;
223 }
224
7a73ba74 225 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid);
fb1d9738
JB		 226}
227
4e4ddd47
TH		 228static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,
229 struct vmw_sw_context *sw_context,
230 SVGAGuestPtr *ptr,
231 struct vmw_dma_buffer **vmw_bo_p)
fb1d9738 232{
fb1d9738
JB		 233 struct vmw_dma_buffer *vmw_bo = NULL;
234 struct ttm_buffer_object *bo;
4e4ddd47 235 uint32_t handle = ptr->gmrId;
fb1d9738 236 struct vmw_relocation *reloc;
fb1d9738
JB		 237 uint32_t cur_validate_node;
238 struct ttm_validate_buffer *val_buf;
4e4ddd47 239 int ret;
fb1d9738 240
fb1d9738
JB		 241 ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo);
242 if (unlikely(ret != 0)) {
243 DRM_ERROR("Could not find or use GMR region.\n");
244 return -EINVAL;
245 }
246 bo = &vmw_bo->base;
247
248 if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
4e4ddd47 249 DRM_ERROR("Max number relocations per submission"
fb1d9738
JB		 250 " exceeded\n");
251 ret = -EINVAL;
252 goto out_no_reloc;
253 }
254
255 reloc = &sw_context->relocs[sw_context->cur_reloc++];
4e4ddd47 256 reloc->location = ptr;
fb1d9738
JB		 257
258 cur_validate_node = vmw_dmabuf_validate_node(bo, sw_context->cur_val_buf);
be38ab6e 259 if (unlikely(cur_validate_node >= VMWGFX_MAX_VALIDATIONS)) {
fb1d9738
JB		 260 DRM_ERROR("Max number of DMA buffers per submission"
261 " exceeded.\n");
262 ret = -EINVAL;
263 goto out_no_reloc;
264 }
265
266 reloc->index = cur_validate_node;
267 if (unlikely(cur_validate_node == sw_context->cur_val_buf)) {
268 val_buf = &sw_context->val_bufs[cur_validate_node];
269 val_buf->bo = ttm_bo_reference(bo);
dfadbbdb 270 val_buf->usage = TTM_USAGE_READWRITE;
ae2a1040 271 val_buf->new_sync_obj_arg = (void *) DRM_VMW_FENCE_FLAG_EXEC;
fb1d9738
JB		 272 list_add_tail(&val_buf->head, &sw_context->validate_nodes);
273 ++sw_context->cur_val_buf;
274 }
4e4ddd47
TH		 275 *vmw_bo_p = vmw_bo;
276 return 0;
277
278out_no_reloc:
279 vmw_dmabuf_unreference(&vmw_bo);
280 vmw_bo_p = NULL;
281 return ret;
282}
283
284static int vmw_cmd_end_query(struct vmw_private *dev_priv,
285 struct vmw_sw_context *sw_context,
286 SVGA3dCmdHeader *header)
287{
288 struct vmw_dma_buffer *vmw_bo;
289 struct vmw_query_cmd {
290 SVGA3dCmdHeader header;
291 SVGA3dCmdEndQuery q;
292 } *cmd;
293 int ret;
294
295 cmd = container_of(header, struct vmw_query_cmd, header);
296 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
297 if (unlikely(ret != 0))
298 return ret;
299
300 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
301 &cmd->q.guestResult,
302 &vmw_bo);
303 if (unlikely(ret != 0))
304 return ret;
305
306 vmw_dmabuf_unreference(&vmw_bo);
307 return 0;
308}
fb1d9738 309
4e4ddd47
TH		 310static int vmw_cmd_wait_query(struct vmw_private *dev_priv,
311 struct vmw_sw_context *sw_context,
312 SVGA3dCmdHeader *header)
313{
314 struct vmw_dma_buffer *vmw_bo;
315 struct vmw_query_cmd {
316 SVGA3dCmdHeader header;
317 SVGA3dCmdWaitForQuery q;
318 } *cmd;
319 int ret;
320
321 cmd = container_of(header, struct vmw_query_cmd, header);
322 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
323 if (unlikely(ret != 0))
324 return ret;
325
326 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
327 &cmd->q.guestResult,
328 &vmw_bo);
329 if (unlikely(ret != 0))
330 return ret;
331
332 vmw_dmabuf_unreference(&vmw_bo);
333 return 0;
334}
335
4e4ddd47
TH		 336static int vmw_cmd_dma(struct vmw_private *dev_priv,
337 struct vmw_sw_context *sw_context,
338 SVGA3dCmdHeader *header)
339{
340 struct vmw_dma_buffer *vmw_bo = NULL;
341 struct ttm_buffer_object *bo;
342 struct vmw_surface *srf = NULL;
343 struct vmw_dma_cmd {
344 SVGA3dCmdHeader header;
345 SVGA3dCmdSurfaceDMA dma;
346 } *cmd;
347 int ret;
be38ab6e 348 struct vmw_resource *res;
4e4ddd47
TH		 349
350 cmd = container_of(header, struct vmw_dma_cmd, header);
351 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
352 &cmd->dma.guest.ptr,
353 &vmw_bo);
354 if (unlikely(ret != 0))
355 return ret;
356
357 bo = &vmw_bo->base;
7a73ba74
TH		 358 ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
359 cmd->dma.host.sid, &srf);
fb1d9738
JB		 360 if (ret) {
361 DRM_ERROR("could not find surface\n");
362 goto out_no_reloc;
363 }
364
be38ab6e 365 /*
7a73ba74
TH		 366 * Patch command stream with device SID.
367 */
7a73ba74 368 cmd->dma.host.sid = srf->res.id;
fb1d9738 369 vmw_kms_cursor_snoop(srf, sw_context->tfile, bo, header);
be38ab6e
TH		 370
371 vmw_dmabuf_unreference(&vmw_bo);
372
373 res = &srf->res;
374 return vmw_resource_to_validate_list(sw_context, &res);
fb1d9738
JB		 375
376out_no_reloc:
377 vmw_dmabuf_unreference(&vmw_bo);
378 return ret;
379}
380
7a73ba74
TH		 381static int vmw_cmd_draw(struct vmw_private *dev_priv,
382 struct vmw_sw_context *sw_context,
383 SVGA3dCmdHeader *header)
384{
385 struct vmw_draw_cmd {
386 SVGA3dCmdHeader header;
387 SVGA3dCmdDrawPrimitives body;
388 } *cmd;
389 SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)(
390 (unsigned long)header + sizeof(*cmd));
391 SVGA3dPrimitiveRange *range;
392 uint32_t i;
393 uint32_t maxnum;
394 int ret;
395
396 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
397 if (unlikely(ret != 0))
398 return ret;
399
400 cmd = container_of(header, struct vmw_draw_cmd, header);
401 maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl);
402
403 if (unlikely(cmd->body.numVertexDecls > maxnum)) {
404 DRM_ERROR("Illegal number of vertex declarations.\n");
405 return -EINVAL;
406 }
407
408 for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) {
409 ret = vmw_cmd_sid_check(dev_priv, sw_context,
410 &decl->array.surfaceId);
411 if (unlikely(ret != 0))
412 return ret;
413 }
414
415 maxnum = (header->size - sizeof(cmd->body) -
416 cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range);
417 if (unlikely(cmd->body.numRanges > maxnum)) {
418 DRM_ERROR("Illegal number of index ranges.\n");
419 return -EINVAL;
420 }
421
422 range = (SVGA3dPrimitiveRange *) decl;
423 for (i = 0; i < cmd->body.numRanges; ++i, ++range) {
424 ret = vmw_cmd_sid_check(dev_priv, sw_context,
425 &range->indexArray.surfaceId);
426 if (unlikely(ret != 0))
427 return ret;
428 }
429 return 0;
430}
431
432
433static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
434 struct vmw_sw_context *sw_context,
435 SVGA3dCmdHeader *header)
436{
437 struct vmw_tex_state_cmd {
438 SVGA3dCmdHeader header;
439 SVGA3dCmdSetTextureState state;
440 };
441
442 SVGA3dTextureState *last_state = (SVGA3dTextureState *)
443 ((unsigned long) header + header->size + sizeof(header));
444 SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
445 ((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
446 int ret;
447
448 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
449 if (unlikely(ret != 0))
450 return ret;
451
452 for (; cur_state < last_state; ++cur_state) {
453 if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
454 continue;
455
456 ret = vmw_cmd_sid_check(dev_priv, sw_context,
457 &cur_state->value);
458 if (unlikely(ret != 0))
459 return ret;
460 }
461
462 return 0;
463}
464
4084fb89
JB		 465static int vmw_cmd_check_define_gmrfb(struct vmw_private *dev_priv,
466 struct vmw_sw_context *sw_context,
467 void *buf)
468{
469 struct vmw_dma_buffer *vmw_bo;
470 int ret;
471
472 struct {
473 uint32_t header;
474 SVGAFifoCmdDefineGMRFB body;
475 } *cmd = buf;
476
477 ret = vmw_translate_guest_ptr(dev_priv, sw_context,
478 &cmd->body.ptr,
479 &vmw_bo);
480 if (unlikely(ret != 0))
481 return ret;
482
483 vmw_dmabuf_unreference(&vmw_bo);
484
485 return ret;
486}
487
488static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
489 struct vmw_sw_context *sw_context,
490 void *buf, uint32_t *size)
491{
492 uint32_t size_remaining = *size;
4084fb89
JB		 493 uint32_t cmd_id;
494
495 cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
496 switch (cmd_id) {
497 case SVGA_CMD_UPDATE:
498 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdUpdate);
4084fb89
JB		 499 break;
500 case SVGA_CMD_DEFINE_GMRFB:
501 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdDefineGMRFB);
502 break;
503 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
504 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
505 break;
506 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
507 *size = sizeof(uint32_t) + sizeof(SVGAFifoCmdBlitGMRFBToScreen);
508 break;
509 default:
510 DRM_ERROR("Unsupported SVGA command: %u.\n", cmd_id);
511 return -EINVAL;
512 }
513
514 if (*size > size_remaining) {
515 DRM_ERROR("Invalid SVGA command (size mismatch):"
516 " %u.\n", cmd_id);
517 return -EINVAL;
518 }
519
0cff60c6 520 if (unlikely(!sw_context->kernel)) {
4084fb89
JB		 521 DRM_ERROR("Kernel only SVGA command: %u.\n", cmd_id);
522 return -EPERM;
523 }
524
525 if (cmd_id == SVGA_CMD_DEFINE_GMRFB)
526 return vmw_cmd_check_define_gmrfb(dev_priv, sw_context, buf);
527
528 return 0;
529}
fb1d9738
JB		 530
531typedef int (*vmw_cmd_func) (struct vmw_private *,
532 struct vmw_sw_context *,
533 SVGA3dCmdHeader *);
534
535#define VMW_CMD_DEF(cmd, func) \
536 [cmd - SVGA_3D_CMD_BASE] = func
537
538static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
539 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid),
540 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid),
541 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_COPY, &vmw_cmd_surface_copy_check),
542 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_STRETCHBLT, &vmw_cmd_stretch_blt_check),
543 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DMA, &vmw_cmd_dma),
544 VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DEFINE, &vmw_cmd_invalid),
545 VMW_CMD_DEF(SVGA_3D_CMD_CONTEXT_DESTROY, &vmw_cmd_invalid),
546 VMW_CMD_DEF(SVGA_3D_CMD_SETTRANSFORM, &vmw_cmd_cid_check),
547 VMW_CMD_DEF(SVGA_3D_CMD_SETZRANGE, &vmw_cmd_cid_check),
548 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check),
549 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET,
550 &vmw_cmd_set_render_target_check),
7a73ba74 551 VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state),
fb1d9738
JB		 552 VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check),
553 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check),
554 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check),
555 VMW_CMD_DEF(SVGA_3D_CMD_SETVIEWPORT, &vmw_cmd_cid_check),
556 VMW_CMD_DEF(SVGA_3D_CMD_SETCLIPPLANE, &vmw_cmd_cid_check),
557 VMW_CMD_DEF(SVGA_3D_CMD_CLEAR, &vmw_cmd_cid_check),
558 VMW_CMD_DEF(SVGA_3D_CMD_PRESENT, &vmw_cmd_present_check),
559 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DEFINE, &vmw_cmd_cid_check),
560 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_cid_check),
561 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_cid_check),
562 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_cid_check),
7a73ba74 563 VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw),
fb1d9738
JB		 564 VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check),
565 VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check),
4e4ddd47
TH		 566 VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query),
567 VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query),
fb1d9738
JB		 568 VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok),
569 VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN,
570 &vmw_cmd_blt_surf_screen_check)
571};
572
573static int vmw_cmd_check(struct vmw_private *dev_priv,
574 struct vmw_sw_context *sw_context,
575 void *buf, uint32_t *size)
576{
577 uint32_t cmd_id;
7a73ba74 578 uint32_t size_remaining = *size;
fb1d9738
JB		 579 SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf;
580 int ret;
581
4084fb89
JB		 582 cmd_id = le32_to_cpu(((uint32_t *)buf)[0]);
583 /* Handle any none 3D commands */
584 if (unlikely(cmd_id < SVGA_CMD_MAX))
585 return vmw_cmd_check_not_3d(dev_priv, sw_context, buf, size);
586
fb1d9738
JB		 587
588 cmd_id = le32_to_cpu(header->id);
589 *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader);
590
591 cmd_id -= SVGA_3D_CMD_BASE;
7a73ba74
TH		 592 if (unlikely(*size > size_remaining))
593 goto out_err;
594
fb1d9738
JB		 595 if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE))
596 goto out_err;
597
598 ret = vmw_cmd_funcs[cmd_id](dev_priv, sw_context, header);
599 if (unlikely(ret != 0))
600 goto out_err;
601
602 return 0;
603out_err:
604 DRM_ERROR("Illegal / Invalid SVGA3D command: %d\n",
605 cmd_id + SVGA_3D_CMD_BASE);
606 return -EINVAL;
607}
608
609static int vmw_cmd_check_all(struct vmw_private *dev_priv,
610 struct vmw_sw_context *sw_context,
922ade0d 611 void *buf,
be38ab6e 612 uint32_t size)
fb1d9738
JB		 613{
614 int32_t cur_size = size;
615 int ret;
616
617 while (cur_size > 0) {
7a73ba74 618 size = cur_size;
fb1d9738
JB		 619 ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);
620 if (unlikely(ret != 0))
621 return ret;
622 buf = (void *)((unsigned long) buf + size);
623 cur_size -= size;
624 }
625
626 if (unlikely(cur_size != 0)) {
627 DRM_ERROR("Command verifier out of sync.\n");
628 return -EINVAL;
629 }
630
631 return 0;
632}
633
634static void vmw_free_relocations(struct vmw_sw_context *sw_context)
635{
636 sw_context->cur_reloc = 0;
637}
638
639static void vmw_apply_relocations(struct vmw_sw_context *sw_context)
640{
641 uint32_t i;
642 struct vmw_relocation *reloc;
643 struct ttm_validate_buffer *validate;
644 struct ttm_buffer_object *bo;
645
646 for (i = 0; i < sw_context->cur_reloc; ++i) {
647 reloc = &sw_context->relocs[i];
648 validate = &sw_context->val_bufs[reloc->index];
649 bo = validate->bo;
135cba0d
TH		 650 if (bo->mem.mem_type == TTM_PL_VRAM) {
651 reloc->location->offset += bo->offset;
652 reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
653 } else
654 reloc->location->gmrId = bo->mem.start;
fb1d9738
JB		 655 }
656 vmw_free_relocations(sw_context);
657}
658
659static void vmw_clear_validations(struct vmw_sw_context *sw_context)
660{
661 struct ttm_validate_buffer *entry, *next;
be38ab6e 662 uint32_t i = sw_context->num_ref_resources;
fb1d9738 663
be38ab6e
TH		 664 /*
665 * Drop references to DMA buffers held during command submission.
666 */
fb1d9738
JB		 667 list_for_each_entry_safe(entry, next, &sw_context->validate_nodes,
668 head) {
669 list_del(&entry->head);
670 vmw_dmabuf_validate_clear(entry->bo);
671 ttm_bo_unref(&entry->bo);
672 sw_context->cur_val_buf--;
673 }
674 BUG_ON(sw_context->cur_val_buf != 0);
be38ab6e
TH		 675
676 /*
677 * Drop references to resources held during command submission.
678 */
679 while (i-- > 0) {
680 sw_context->resources[i]->on_validate_list = false;
681 vmw_resource_unreference(&sw_context->resources[i]);
682 }
fb1d9738
JB		 683}
684
685static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
686 struct ttm_buffer_object *bo)
687{
688 int ret;
689
8ba5152a 690 /**
135cba0d
TH		 691 * Put BO in VRAM if there is space, otherwise as a GMR.
692 * If there is no space in VRAM and GMR ids are all used up,
693 * start evicting GMRs to make room. If the DMA buffer can't be
694 * used as a GMR, this will return -ENOMEM.
8ba5152a
TH		 695 */
696
135cba0d 697 ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, true, false, false);
3d3a5b32 698 if (likely(ret == 0 || ret == -ERESTARTSYS))
fb1d9738
JB		 699 return ret;
700
8ba5152a
TH		 701 /**
702 * If that failed, try VRAM again, this time evicting
703 * previous contents.
704 */
fb1d9738 705
135cba0d 706 DRM_INFO("Falling through to VRAM.\n");
9d87fa21 707 ret = ttm_bo_validate(bo, &vmw_vram_placement, true, false, false);
fb1d9738
JB		 708 return ret;
709}
710
711
712static int vmw_validate_buffers(struct vmw_private *dev_priv,
713 struct vmw_sw_context *sw_context)
714{
715 struct ttm_validate_buffer *entry;
716 int ret;
717
718 list_for_each_entry(entry, &sw_context->validate_nodes, head) {
719 ret = vmw_validate_single_buffer(dev_priv, entry->bo);
720 if (unlikely(ret != 0))
721 return ret;
722 }
723 return 0;
724}
725
be38ab6e
TH		 726static int vmw_resize_cmd_bounce(struct vmw_sw_context *sw_context,
727 uint32_t size)
728{
729 if (likely(sw_context->cmd_bounce_size >= size))
730 return 0;
731
732 if (sw_context->cmd_bounce_size == 0)
733 sw_context->cmd_bounce_size = VMWGFX_CMD_BOUNCE_INIT_SIZE;
734
735 while (sw_context->cmd_bounce_size < size) {
736 sw_context->cmd_bounce_size =
737 PAGE_ALIGN(sw_context->cmd_bounce_size +
738 (sw_context->cmd_bounce_size >> 1));
739 }
740
741 if (sw_context->cmd_bounce != NULL)
742 vfree(sw_context->cmd_bounce);
743
744 sw_context->cmd_bounce = vmalloc(sw_context->cmd_bounce_size);
745
746 if (sw_context->cmd_bounce == NULL) {
747 DRM_ERROR("Failed to allocate command bounce buffer.\n");
748 sw_context->cmd_bounce_size = 0;
749 return -ENOMEM;
750 }
751
752 return 0;
753}
754
ae2a1040
TH		 755/**
756 * vmw_execbuf_fence_commands - create and submit a command stream fence
757 *
758 * Creates a fence object and submits a command stream marker.
759 * If this fails for some reason, We sync the fifo and return NULL.
760 * It is then safe to fence buffers with a NULL pointer.
6070e9fa
JB		 761 *
762 * If @p_handle is not NULL @file_priv must also not be NULL. Creates
763 * a userspace handle if @p_handle is not NULL, otherwise not.
ae2a1040
TH		 764 */
765
766int vmw_execbuf_fence_commands(struct drm_file *file_priv,
767 struct vmw_private *dev_priv,
768 struct vmw_fence_obj **p_fence,
769 uint32_t *p_handle)
770{
771 uint32_t sequence;
772 int ret;
773 bool synced = false;
774
6070e9fa
JB		 775 /* p_handle implies file_priv. */
776 BUG_ON(p_handle != NULL && file_priv == NULL);
ae2a1040
TH		 777
778 ret = vmw_fifo_send_fence(dev_priv, &sequence);
779 if (unlikely(ret != 0)) {
780 DRM_ERROR("Fence submission error. Syncing.\n");
781 synced = true;
782 }
783
784 if (p_handle != NULL)
785 ret = vmw_user_fence_create(file_priv, dev_priv->fman,
786 sequence,
787 DRM_VMW_FENCE_FLAG_EXEC,
788 p_fence, p_handle);
789 else
790 ret = vmw_fence_create(dev_priv->fman, sequence,
791 DRM_VMW_FENCE_FLAG_EXEC,
792 p_fence);
793
794 if (unlikely(ret != 0 && !synced)) {
795 (void) vmw_fallback_wait(dev_priv, false, false,
796 sequence, false,
797 VMW_FENCE_WAIT_TIMEOUT);
798 *p_fence = NULL;
799 }
800
801 return 0;
802}
803
922ade0d
TH		 804int vmw_execbuf_process(struct drm_file *file_priv,
805 struct vmw_private *dev_priv,
806 void __user *user_commands,
807 void *kernel_commands,
808 uint32_t command_size,
809 uint64_t throttle_us,
810 struct drm_vmw_fence_rep __user *user_fence_rep)
fb1d9738 811{
fb1d9738 812 struct vmw_sw_context *sw_context = &dev_priv->ctx;
922ade0d 813 struct drm_vmw_fence_rep fence_rep;
ae2a1040
TH		 814 struct vmw_fence_obj *fence;
815 uint32_t handle;
922ade0d
TH		 816 void *cmd;
817 int ret;
fb1d9738 818
922ade0d 819 ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
fb1d9738 820 if (unlikely(ret != 0))
922ade0d 821 return -ERESTARTSYS;
fb1d9738 822
922ade0d
TH		 823 if (kernel_commands == NULL) {
824 sw_context->kernel = false;
fb1d9738 825
922ade0d
TH		 826 ret = vmw_resize_cmd_bounce(sw_context, command_size);
827 if (unlikely(ret != 0))
828 goto out_unlock;
fb1d9738 829
fb1d9738 830
922ade0d
TH		 831 ret = copy_from_user(sw_context->cmd_bounce,
832 user_commands, command_size);
833
834 if (unlikely(ret != 0)) {
835 ret = -EFAULT;
836 DRM_ERROR("Failed copying commands.\n");
837 goto out_unlock;
838 }
839 kernel_commands = sw_context->cmd_bounce;
840 } else
841 sw_context->kernel = true;
fb1d9738
JB		 842
843 sw_context->tfile = vmw_fpriv(file_priv)->tfile;
844 sw_context->cid_valid = false;
845 sw_context->sid_valid = false;
846 sw_context->cur_reloc = 0;
847 sw_context->cur_val_buf = 0;
be38ab6e 848 sw_context->num_ref_resources = 0;
fb1d9738
JB		 849
850 INIT_LIST_HEAD(&sw_context->validate_nodes);
851
922ade0d
TH		 852 ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands,
853 command_size);
fb1d9738
JB		 854 if (unlikely(ret != 0))
855 goto out_err;
be38ab6e 856
65705962 857 ret = ttm_eu_reserve_buffers(&sw_context->validate_nodes);
fb1d9738
JB		 858 if (unlikely(ret != 0))
859 goto out_err;
860
861 ret = vmw_validate_buffers(dev_priv, sw_context);
862 if (unlikely(ret != 0))
863 goto out_err;
864
865 vmw_apply_relocations(sw_context);
1925d456 866
922ade0d 867 if (throttle_us) {
6bcd8d3c 868 ret = vmw_wait_lag(dev_priv, &dev_priv->fifo.marker_queue,
922ade0d 869 throttle_us);
1925d456
TH		 870
871 if (unlikely(ret != 0))
be38ab6e
TH		 872 goto out_throttle;
873 }
874
922ade0d 875 cmd = vmw_fifo_reserve(dev_priv, command_size);
be38ab6e
TH		 876 if (unlikely(cmd == NULL)) {
877 DRM_ERROR("Failed reserving fifo space for commands.\n");
878 ret = -ENOMEM;
922ade0d 879 goto out_throttle;
1925d456
TH		 880 }
881
922ade0d
TH		 882 memcpy(cmd, kernel_commands, command_size);
883 vmw_fifo_commit(dev_priv, command_size);
fb1d9738 884
ae2a1040
TH		 885 ret = vmw_execbuf_fence_commands(file_priv, dev_priv,
886 &fence,
887 (user_fence_rep) ? &handle : NULL);
fb1d9738
JB		 888 /*
889 * This error is harmless, because if fence submission fails,
ae2a1040
TH		 890 * vmw_fifo_send_fence will sync. The error will be propagated to
891 * user-space in @fence_rep
fb1d9738
JB		 892 */
893
894 if (ret != 0)
895 DRM_ERROR("Fence submission error. Syncing.\n");
896
ae2a1040
TH		 897 ttm_eu_fence_buffer_objects(&sw_context->validate_nodes,
898 (void *) fence);
fb1d9738 899
ae2a1040 900 vmw_clear_validations(sw_context);
fb1d9738 901
ae2a1040
TH		 902 if (user_fence_rep) {
903 fence_rep.error = ret;
904 fence_rep.handle = handle;
905 fence_rep.seqno = fence->seqno;
906 vmw_update_seqno(dev_priv, &dev_priv->fifo);
907 fence_rep.passed_seqno = dev_priv->last_read_seqno;
908
909 /*
910 * copy_to_user errors will be detected by user space not
911 * seeing fence_rep::error filled in. Typically
912 * user-space would have pre-set that member to -EFAULT.
913 */
914 ret = copy_to_user(user_fence_rep, &fence_rep,
915 sizeof(fence_rep));
916
917 /*
918 * User-space lost the fence object. We need to sync
919 * and unreference the handle.
920 */
921 if (unlikely(ret != 0) && (fence_rep.error == 0)) {
922 BUG_ON(fence == NULL);
923
924 ttm_ref_object_base_unref(vmw_fpriv(file_priv)->tfile,
925 handle, TTM_REF_USAGE);
926 DRM_ERROR("Fence copy error. Syncing.\n");
927 (void) vmw_fence_obj_wait(fence,
928 fence->signal_mask,
929 false, false,
930 VMW_FENCE_WAIT_TIMEOUT);
931 }
932 }
fb1d9738 933
ae2a1040
TH		 934 if (likely(fence != NULL))
935 vmw_fence_obj_unreference(&fence);
fb1d9738 936
922ade0d 937 mutex_unlock(&dev_priv->cmdbuf_mutex);
fb1d9738 938 return 0;
922ade0d 939
fb1d9738
JB		 940out_err:
941 vmw_free_relocations(sw_context);
be38ab6e 942out_throttle:
fb1d9738
JB		 943 ttm_eu_backoff_reservation(&sw_context->validate_nodes);
944 vmw_clear_validations(sw_context);
fb1d9738
JB		 945out_unlock:
946 mutex_unlock(&dev_priv->cmdbuf_mutex);
922ade0d
TH		 947 return ret;
948}
949
950
951int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
952 struct drm_file *file_priv)
953{
954 struct vmw_private *dev_priv = vmw_priv(dev);
955 struct drm_vmw_execbuf_arg *arg = (struct drm_vmw_execbuf_arg *)data;
956 struct vmw_master *vmaster = vmw_master(file_priv->master);
957 int ret;
958
959 /*
960 * This will allow us to extend the ioctl argument while
961 * maintaining backwards compatibility:
962 * We take different code paths depending on the value of
963 * arg->version.
964 */
965
966 if (unlikely(arg->version != DRM_VMW_EXECBUF_VERSION)) {
967 DRM_ERROR("Incorrect execbuf version.\n");
968 DRM_ERROR("You're running outdated experimental "
969 "vmwgfx user-space drivers.");
970 return -EINVAL;
971 }
972
973 ret = ttm_read_lock(&vmaster->lock, true);
974 if (unlikely(ret != 0))
975 return ret;
976
977 ret = vmw_execbuf_process(file_priv, dev_priv,
978 (void __user *)(unsigned long)arg->commands,
979 NULL, arg->command_size, arg->throttle_us,
980 (void __user *)(unsigned long)arg->fence_rep);
981
982 if (unlikely(ret != 0))
983 goto out_unlock;
984
985 vmw_kms_cursor_post_execbuf(dev_priv);
986
987out_unlock:
fb1d9738
JB		 988 ttm_read_unlock(&vmaster->lock);
989 return ret;
990}
Linux 6.x block layer and io_uring tree(s)