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drm/radeon: halt engines before disabling MC (si)
[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c
CommitLineData
43b3cd99
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
0f0de06c
AD		 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
43b3cd99
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
43b3cd99
AD		 32#include "sid.h"
33#include "atom.h"
48c0c902 34#include "si_blit_shaders.h"
43b3cd99 35
0f0de06c
AD		 36#define SI_PFP_UCODE_SIZE 2144
37#define SI_PM4_UCODE_SIZE 2144
38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769
41
42MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53MODULE_FIRMWARE("radeon/VERDE_me.bin");
54MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
57
25a857fb
AD		 58extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59extern void r600_ih_ring_fini(struct radeon_device *rdev);
0a96d72b 60extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
c476dde2
AD		 61extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
ca7db22b 63extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
1c534671 64extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
014bb209 65extern bool evergreen_is_display_hung(struct radeon_device *rdev);
0a96d72b 66
1bd47d2e
AD		 67/* get temperature in millidegrees */
68int si_get_temp(struct radeon_device *rdev)
69{
70 u32 temp;
71 int actual_temp = 0;
72
73 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
74 CTF_TEMP_SHIFT;
75
76 if (temp & 0x200)
77 actual_temp = 255;
78 else
79 actual_temp = temp & 0x1ff;
80
81 actual_temp = (actual_temp * 1000);
82
83 return actual_temp;
84}
85
8b074dd6
AD		 86#define TAHITI_IO_MC_REGS_SIZE 36
87
88static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
89 {0x0000006f, 0x03044000},
90 {0x00000070, 0x0480c018},
91 {0x00000071, 0x00000040},
92 {0x00000072, 0x01000000},
93 {0x00000074, 0x000000ff},
94 {0x00000075, 0x00143400},
95 {0x00000076, 0x08ec0800},
96 {0x00000077, 0x040000cc},
97 {0x00000079, 0x00000000},
98 {0x0000007a, 0x21000409},
99 {0x0000007c, 0x00000000},
100 {0x0000007d, 0xe8000000},
101 {0x0000007e, 0x044408a8},
102 {0x0000007f, 0x00000003},
103 {0x00000080, 0x00000000},
104 {0x00000081, 0x01000000},
105 {0x00000082, 0x02000000},
106 {0x00000083, 0x00000000},
107 {0x00000084, 0xe3f3e4f4},
108 {0x00000085, 0x00052024},
109 {0x00000087, 0x00000000},
110 {0x00000088, 0x66036603},
111 {0x00000089, 0x01000000},
112 {0x0000008b, 0x1c0a0000},
113 {0x0000008c, 0xff010000},
114 {0x0000008e, 0xffffefff},
115 {0x0000008f, 0xfff3efff},
116 {0x00000090, 0xfff3efbf},
117 {0x00000094, 0x00101101},
118 {0x00000095, 0x00000fff},
119 {0x00000096, 0x00116fff},
120 {0x00000097, 0x60010000},
121 {0x00000098, 0x10010000},
122 {0x00000099, 0x00006000},
123 {0x0000009a, 0x00001000},
124 {0x0000009f, 0x00a77400}
125};
126
127static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
128 {0x0000006f, 0x03044000},
129 {0x00000070, 0x0480c018},
130 {0x00000071, 0x00000040},
131 {0x00000072, 0x01000000},
132 {0x00000074, 0x000000ff},
133 {0x00000075, 0x00143400},
134 {0x00000076, 0x08ec0800},
135 {0x00000077, 0x040000cc},
136 {0x00000079, 0x00000000},
137 {0x0000007a, 0x21000409},
138 {0x0000007c, 0x00000000},
139 {0x0000007d, 0xe8000000},
140 {0x0000007e, 0x044408a8},
141 {0x0000007f, 0x00000003},
142 {0x00000080, 0x00000000},
143 {0x00000081, 0x01000000},
144 {0x00000082, 0x02000000},
145 {0x00000083, 0x00000000},
146 {0x00000084, 0xe3f3e4f4},
147 {0x00000085, 0x00052024},
148 {0x00000087, 0x00000000},
149 {0x00000088, 0x66036603},
150 {0x00000089, 0x01000000},
151 {0x0000008b, 0x1c0a0000},
152 {0x0000008c, 0xff010000},
153 {0x0000008e, 0xffffefff},
154 {0x0000008f, 0xfff3efff},
155 {0x00000090, 0xfff3efbf},
156 {0x00000094, 0x00101101},
157 {0x00000095, 0x00000fff},
158 {0x00000096, 0x00116fff},
159 {0x00000097, 0x60010000},
160 {0x00000098, 0x10010000},
161 {0x00000099, 0x00006000},
162 {0x0000009a, 0x00001000},
163 {0x0000009f, 0x00a47400}
164};
165
166static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
167 {0x0000006f, 0x03044000},
168 {0x00000070, 0x0480c018},
169 {0x00000071, 0x00000040},
170 {0x00000072, 0x01000000},
171 {0x00000074, 0x000000ff},
172 {0x00000075, 0x00143400},
173 {0x00000076, 0x08ec0800},
174 {0x00000077, 0x040000cc},
175 {0x00000079, 0x00000000},
176 {0x0000007a, 0x21000409},
177 {0x0000007c, 0x00000000},
178 {0x0000007d, 0xe8000000},
179 {0x0000007e, 0x044408a8},
180 {0x0000007f, 0x00000003},
181 {0x00000080, 0x00000000},
182 {0x00000081, 0x01000000},
183 {0x00000082, 0x02000000},
184 {0x00000083, 0x00000000},
185 {0x00000084, 0xe3f3e4f4},
186 {0x00000085, 0x00052024},
187 {0x00000087, 0x00000000},
188 {0x00000088, 0x66036603},
189 {0x00000089, 0x01000000},
190 {0x0000008b, 0x1c0a0000},
191 {0x0000008c, 0xff010000},
192 {0x0000008e, 0xffffefff},
193 {0x0000008f, 0xfff3efff},
194 {0x00000090, 0xfff3efbf},
195 {0x00000094, 0x00101101},
196 {0x00000095, 0x00000fff},
197 {0x00000096, 0x00116fff},
198 {0x00000097, 0x60010000},
199 {0x00000098, 0x10010000},
200 {0x00000099, 0x00006000},
201 {0x0000009a, 0x00001000},
202 {0x0000009f, 0x00a37400}
203};
204
205/* ucode loading */
206static int si_mc_load_microcode(struct radeon_device *rdev)
207{
208 const __be32 *fw_data;
209 u32 running, blackout = 0;
210 u32 *io_mc_regs;
211 int i, ucode_size, regs_size;
212
213 if (!rdev->mc_fw)
214 return -EINVAL;
215
216 switch (rdev->family) {
217 case CHIP_TAHITI:
218 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
219 ucode_size = SI_MC_UCODE_SIZE;
220 regs_size = TAHITI_IO_MC_REGS_SIZE;
221 break;
222 case CHIP_PITCAIRN:
223 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
224 ucode_size = SI_MC_UCODE_SIZE;
225 regs_size = TAHITI_IO_MC_REGS_SIZE;
226 break;
227 case CHIP_VERDE:
228 default:
229 io_mc_regs = (u32 *)&verde_io_mc_regs;
230 ucode_size = SI_MC_UCODE_SIZE;
231 regs_size = TAHITI_IO_MC_REGS_SIZE;
232 break;
233 }
234
235 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
236
237 if (running == 0) {
238 if (running) {
239 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
240 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
241 }
242
243 /* reset the engine and set to writable */
244 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
245 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
246
247 /* load mc io regs */
248 for (i = 0; i < regs_size; i++) {
249 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
250 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
251 }
252 /* load the MC ucode */
253 fw_data = (const __be32 *)rdev->mc_fw->data;
254 for (i = 0; i < ucode_size; i++)
255 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
256
257 /* put the engine back into the active state */
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
259 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
260 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
261
262 /* wait for training to complete */
263 for (i = 0; i < rdev->usec_timeout; i++) {
264 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
265 break;
266 udelay(1);
267 }
268 for (i = 0; i < rdev->usec_timeout; i++) {
269 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
270 break;
271 udelay(1);
272 }
273
274 if (running)
275 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
276 }
277
278 return 0;
279}
280
0f0de06c
AD		 281static int si_init_microcode(struct radeon_device *rdev)
282{
283 struct platform_device *pdev;
284 const char *chip_name;
285 const char *rlc_chip_name;
286 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
287 char fw_name[30];
288 int err;
289
290 DRM_DEBUG("\n");
291
292 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
293 err = IS_ERR(pdev);
294 if (err) {
295 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
296 return -EINVAL;
297 }
298
299 switch (rdev->family) {
300 case CHIP_TAHITI:
301 chip_name = "TAHITI";
302 rlc_chip_name = "TAHITI";
303 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
304 me_req_size = SI_PM4_UCODE_SIZE * 4;
305 ce_req_size = SI_CE_UCODE_SIZE * 4;
306 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
307 mc_req_size = SI_MC_UCODE_SIZE * 4;
308 break;
309 case CHIP_PITCAIRN:
310 chip_name = "PITCAIRN";
311 rlc_chip_name = "PITCAIRN";
312 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
313 me_req_size = SI_PM4_UCODE_SIZE * 4;
314 ce_req_size = SI_CE_UCODE_SIZE * 4;
315 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
316 mc_req_size = SI_MC_UCODE_SIZE * 4;
317 break;
318 case CHIP_VERDE:
319 chip_name = "VERDE";
320 rlc_chip_name = "VERDE";
321 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
322 me_req_size = SI_PM4_UCODE_SIZE * 4;
323 ce_req_size = SI_CE_UCODE_SIZE * 4;
324 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
325 mc_req_size = SI_MC_UCODE_SIZE * 4;
326 break;
327 default: BUG();
328 }
329
330 DRM_INFO("Loading %s Microcode\n", chip_name);
331
332 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
333 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
334 if (err)
335 goto out;
336 if (rdev->pfp_fw->size != pfp_req_size) {
337 printk(KERN_ERR
338 "si_cp: Bogus length %zu in firmware \"%s\"\n",
339 rdev->pfp_fw->size, fw_name);
340 err = -EINVAL;
341 goto out;
342 }
343
344 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
345 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
346 if (err)
347 goto out;
348 if (rdev->me_fw->size != me_req_size) {
349 printk(KERN_ERR
350 "si_cp: Bogus length %zu in firmware \"%s\"\n",
351 rdev->me_fw->size, fw_name);
352 err = -EINVAL;
353 }
354
355 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
356 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
357 if (err)
358 goto out;
359 if (rdev->ce_fw->size != ce_req_size) {
360 printk(KERN_ERR
361 "si_cp: Bogus length %zu in firmware \"%s\"\n",
362 rdev->ce_fw->size, fw_name);
363 err = -EINVAL;
364 }
365
366 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
367 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
368 if (err)
369 goto out;
370 if (rdev->rlc_fw->size != rlc_req_size) {
371 printk(KERN_ERR
372 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
373 rdev->rlc_fw->size, fw_name);
374 err = -EINVAL;
375 }
376
377 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
378 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
379 if (err)
380 goto out;
381 if (rdev->mc_fw->size != mc_req_size) {
382 printk(KERN_ERR
383 "si_mc: Bogus length %zu in firmware \"%s\"\n",
384 rdev->mc_fw->size, fw_name);
385 err = -EINVAL;
386 }
387
388out:
389 platform_device_unregister(pdev);
390
391 if (err) {
392 if (err != -EINVAL)
393 printk(KERN_ERR
394 "si_cp: Failed to load firmware \"%s\"\n",
395 fw_name);
396 release_firmware(rdev->pfp_fw);
397 rdev->pfp_fw = NULL;
398 release_firmware(rdev->me_fw);
399 rdev->me_fw = NULL;
400 release_firmware(rdev->ce_fw);
401 rdev->ce_fw = NULL;
402 release_firmware(rdev->rlc_fw);
403 rdev->rlc_fw = NULL;
404 release_firmware(rdev->mc_fw);
405 rdev->mc_fw = NULL;
406 }
407 return err;
408}
409
43b3cd99
AD		 410/* watermark setup */
411static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
412 struct radeon_crtc *radeon_crtc,
413 struct drm_display_mode *mode,
414 struct drm_display_mode *other_mode)
415{
416 u32 tmp;
417 /*
418 * Line Buffer Setup
419 * There are 3 line buffers, each one shared by 2 display controllers.
420 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
421 * the display controllers. The paritioning is done via one of four
422 * preset allocations specified in bits 21:20:
423 * 0 - half lb
424 * 2 - whole lb, other crtc must be disabled
425 */
426 /* this can get tricky if we have two large displays on a paired group
427 * of crtcs. Ideally for multiple large displays we'd assign them to
428 * non-linked crtcs for maximum line buffer allocation.
429 */
430 if (radeon_crtc->base.enabled && mode) {
431 if (other_mode)
432 tmp = 0; /* 1/2 */
433 else
434 tmp = 2; /* whole */
435 } else
436 tmp = 0;
437
438 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
439 DC_LB_MEMORY_CONFIG(tmp));
440
441 if (radeon_crtc->base.enabled && mode) {
442 switch (tmp) {
443 case 0:
444 default:
445 return 4096 * 2;
446 case 2:
447 return 8192 * 2;
448 }
449 }
450
451 /* controller not enabled, so no lb used */
452 return 0;
453}
454
ca7db22b 455static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
43b3cd99
AD		 456{
457 u32 tmp = RREG32(MC_SHARED_CHMAP);
458
459 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
460 case 0:
461 default:
462 return 1;
463 case 1:
464 return 2;
465 case 2:
466 return 4;
467 case 3:
468 return 8;
469 case 4:
470 return 3;
471 case 5:
472 return 6;
473 case 6:
474 return 10;
475 case 7:
476 return 12;
477 case 8:
478 return 16;
479 }
480}
481
482struct dce6_wm_params {
483 u32 dram_channels; /* number of dram channels */
484 u32 yclk; /* bandwidth per dram data pin in kHz */
485 u32 sclk; /* engine clock in kHz */
486 u32 disp_clk; /* display clock in kHz */
487 u32 src_width; /* viewport width */
488 u32 active_time; /* active display time in ns */
489 u32 blank_time; /* blank time in ns */
490 bool interlaced; /* mode is interlaced */
491 fixed20_12 vsc; /* vertical scale ratio */
492 u32 num_heads; /* number of active crtcs */
493 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
494 u32 lb_size; /* line buffer allocated to pipe */
495 u32 vtaps; /* vertical scaler taps */
496};
497
498static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
499{
500 /* Calculate raw DRAM Bandwidth */
501 fixed20_12 dram_efficiency; /* 0.7 */
502 fixed20_12 yclk, dram_channels, bandwidth;
503 fixed20_12 a;
504
505 a.full = dfixed_const(1000);
506 yclk.full = dfixed_const(wm->yclk);
507 yclk.full = dfixed_div(yclk, a);
508 dram_channels.full = dfixed_const(wm->dram_channels * 4);
509 a.full = dfixed_const(10);
510 dram_efficiency.full = dfixed_const(7);
511 dram_efficiency.full = dfixed_div(dram_efficiency, a);
512 bandwidth.full = dfixed_mul(dram_channels, yclk);
513 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
514
515 return dfixed_trunc(bandwidth);
516}
517
518static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
519{
520 /* Calculate DRAM Bandwidth and the part allocated to display. */
521 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
522 fixed20_12 yclk, dram_channels, bandwidth;
523 fixed20_12 a;
524
525 a.full = dfixed_const(1000);
526 yclk.full = dfixed_const(wm->yclk);
527 yclk.full = dfixed_div(yclk, a);
528 dram_channels.full = dfixed_const(wm->dram_channels * 4);
529 a.full = dfixed_const(10);
530 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
531 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
532 bandwidth.full = dfixed_mul(dram_channels, yclk);
533 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
534
535 return dfixed_trunc(bandwidth);
536}
537
538static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
539{
540 /* Calculate the display Data return Bandwidth */
541 fixed20_12 return_efficiency; /* 0.8 */
542 fixed20_12 sclk, bandwidth;
543 fixed20_12 a;
544
545 a.full = dfixed_const(1000);
546 sclk.full = dfixed_const(wm->sclk);
547 sclk.full = dfixed_div(sclk, a);
548 a.full = dfixed_const(10);
549 return_efficiency.full = dfixed_const(8);
550 return_efficiency.full = dfixed_div(return_efficiency, a);
551 a.full = dfixed_const(32);
552 bandwidth.full = dfixed_mul(a, sclk);
553 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
554
555 return dfixed_trunc(bandwidth);
556}
557
558static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
559{
560 return 32;
561}
562
563static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
564{
565 /* Calculate the DMIF Request Bandwidth */
566 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
567 fixed20_12 disp_clk, sclk, bandwidth;
568 fixed20_12 a, b1, b2;
569 u32 min_bandwidth;
570
571 a.full = dfixed_const(1000);
572 disp_clk.full = dfixed_const(wm->disp_clk);
573 disp_clk.full = dfixed_div(disp_clk, a);
574 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
575 b1.full = dfixed_mul(a, disp_clk);
576
577 a.full = dfixed_const(1000);
578 sclk.full = dfixed_const(wm->sclk);
579 sclk.full = dfixed_div(sclk, a);
580 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
581 b2.full = dfixed_mul(a, sclk);
582
583 a.full = dfixed_const(10);
584 disp_clk_request_efficiency.full = dfixed_const(8);
585 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
586
587 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
588
589 a.full = dfixed_const(min_bandwidth);
590 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
591
592 return dfixed_trunc(bandwidth);
593}
594
595static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
596{
597 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
598 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
599 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
600 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
601
602 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
603}
604
605static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
606{
607 /* Calculate the display mode Average Bandwidth
608 * DisplayMode should contain the source and destination dimensions,
609 * timing, etc.
610 */
611 fixed20_12 bpp;
612 fixed20_12 line_time;
613 fixed20_12 src_width;
614 fixed20_12 bandwidth;
615 fixed20_12 a;
616
617 a.full = dfixed_const(1000);
618 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
619 line_time.full = dfixed_div(line_time, a);
620 bpp.full = dfixed_const(wm->bytes_per_pixel);
621 src_width.full = dfixed_const(wm->src_width);
622 bandwidth.full = dfixed_mul(src_width, bpp);
623 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
624 bandwidth.full = dfixed_div(bandwidth, line_time);
625
626 return dfixed_trunc(bandwidth);
627}
628
629static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
630{
631 /* First calcualte the latency in ns */
632 u32 mc_latency = 2000; /* 2000 ns. */
633 u32 available_bandwidth = dce6_available_bandwidth(wm);
634 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
635 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
636 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
637 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
638 (wm->num_heads * cursor_line_pair_return_time);
639 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
640 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
641 u32 tmp, dmif_size = 12288;
642 fixed20_12 a, b, c;
643
644 if (wm->num_heads == 0)
645 return 0;
646
647 a.full = dfixed_const(2);
648 b.full = dfixed_const(1);
649 if ((wm->vsc.full > a.full) ||
650 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
651 (wm->vtaps >= 5) ||
652 ((wm->vsc.full >= a.full) && wm->interlaced))
653 max_src_lines_per_dst_line = 4;
654 else
655 max_src_lines_per_dst_line = 2;
656
657 a.full = dfixed_const(available_bandwidth);
658 b.full = dfixed_const(wm->num_heads);
659 a.full = dfixed_div(a, b);
660
661 b.full = dfixed_const(mc_latency + 512);
662 c.full = dfixed_const(wm->disp_clk);
663 b.full = dfixed_div(b, c);
664
665 c.full = dfixed_const(dmif_size);
666 b.full = dfixed_div(c, b);
667
668 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
669
670 b.full = dfixed_const(1000);
671 c.full = dfixed_const(wm->disp_clk);
672 b.full = dfixed_div(c, b);
673 c.full = dfixed_const(wm->bytes_per_pixel);
674 b.full = dfixed_mul(b, c);
675
676 lb_fill_bw = min(tmp, dfixed_trunc(b));
677
678 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
679 b.full = dfixed_const(1000);
680 c.full = dfixed_const(lb_fill_bw);
681 b.full = dfixed_div(c, b);
682 a.full = dfixed_div(a, b);
683 line_fill_time = dfixed_trunc(a);
684
685 if (line_fill_time < wm->active_time)
686 return latency;
687 else
688 return latency + (line_fill_time - wm->active_time);
689
690}
691
692static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
693{
694 if (dce6_average_bandwidth(wm) <=
695 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
696 return true;
697 else
698 return false;
699};
700
701static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
702{
703 if (dce6_average_bandwidth(wm) <=
704 (dce6_available_bandwidth(wm) / wm->num_heads))
705 return true;
706 else
707 return false;
708};
709
710static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
711{
712 u32 lb_partitions = wm->lb_size / wm->src_width;
713 u32 line_time = wm->active_time + wm->blank_time;
714 u32 latency_tolerant_lines;
715 u32 latency_hiding;
716 fixed20_12 a;
717
718 a.full = dfixed_const(1);
719 if (wm->vsc.full > a.full)
720 latency_tolerant_lines = 1;
721 else {
722 if (lb_partitions <= (wm->vtaps + 1))
723 latency_tolerant_lines = 1;
724 else
725 latency_tolerant_lines = 2;
726 }
727
728 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
729
730 if (dce6_latency_watermark(wm) <= latency_hiding)
731 return true;
732 else
733 return false;
734}
735
736static void dce6_program_watermarks(struct radeon_device *rdev,
737 struct radeon_crtc *radeon_crtc,
738 u32 lb_size, u32 num_heads)
739{
740 struct drm_display_mode *mode = &radeon_crtc->base.mode;
741 struct dce6_wm_params wm;
742 u32 pixel_period;
743 u32 line_time = 0;
744 u32 latency_watermark_a = 0, latency_watermark_b = 0;
745 u32 priority_a_mark = 0, priority_b_mark = 0;
746 u32 priority_a_cnt = PRIORITY_OFF;
747 u32 priority_b_cnt = PRIORITY_OFF;
748 u32 tmp, arb_control3;
749 fixed20_12 a, b, c;
750
751 if (radeon_crtc->base.enabled && num_heads && mode) {
752 pixel_period = 1000000 / (u32)mode->clock;
753 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
754 priority_a_cnt = 0;
755 priority_b_cnt = 0;
756
757 wm.yclk = rdev->pm.current_mclk * 10;
758 wm.sclk = rdev->pm.current_sclk * 10;
759 wm.disp_clk = mode->clock;
760 wm.src_width = mode->crtc_hdisplay;
761 wm.active_time = mode->crtc_hdisplay * pixel_period;
762 wm.blank_time = line_time - wm.active_time;
763 wm.interlaced = false;
764 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
765 wm.interlaced = true;
766 wm.vsc = radeon_crtc->vsc;
767 wm.vtaps = 1;
768 if (radeon_crtc->rmx_type != RMX_OFF)
769 wm.vtaps = 2;
770 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
771 wm.lb_size = lb_size;
ca7db22b
AD		 772 if (rdev->family == CHIP_ARUBA)
773 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
774 else
775 wm.dram_channels = si_get_number_of_dram_channels(rdev);
43b3cd99
AD		 776 wm.num_heads = num_heads;
777
778 /* set for high clocks */
779 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
780 /* set for low clocks */
781 /* wm.yclk = low clk; wm.sclk = low clk */
782 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
783
784 /* possibly force display priority to high */
785 /* should really do this at mode validation time... */
786 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
787 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
788 !dce6_check_latency_hiding(&wm) ||
789 (rdev->disp_priority == 2)) {
790 DRM_DEBUG_KMS("force priority to high\n");
791 priority_a_cnt |= PRIORITY_ALWAYS_ON;
792 priority_b_cnt |= PRIORITY_ALWAYS_ON;
793 }
794
795 a.full = dfixed_const(1000);
796 b.full = dfixed_const(mode->clock);
797 b.full = dfixed_div(b, a);
798 c.full = dfixed_const(latency_watermark_a);
799 c.full = dfixed_mul(c, b);
800 c.full = dfixed_mul(c, radeon_crtc->hsc);
801 c.full = dfixed_div(c, a);
802 a.full = dfixed_const(16);
803 c.full = dfixed_div(c, a);
804 priority_a_mark = dfixed_trunc(c);
805 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
806
807 a.full = dfixed_const(1000);
808 b.full = dfixed_const(mode->clock);
809 b.full = dfixed_div(b, a);
810 c.full = dfixed_const(latency_watermark_b);
811 c.full = dfixed_mul(c, b);
812 c.full = dfixed_mul(c, radeon_crtc->hsc);
813 c.full = dfixed_div(c, a);
814 a.full = dfixed_const(16);
815 c.full = dfixed_div(c, a);
816 priority_b_mark = dfixed_trunc(c);
817 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
818 }
819
820 /* select wm A */
821 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
822 tmp = arb_control3;
823 tmp &= ~LATENCY_WATERMARK_MASK(3);
824 tmp |= LATENCY_WATERMARK_MASK(1);
825 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
826 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
827 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
828 LATENCY_HIGH_WATERMARK(line_time)));
829 /* select wm B */
830 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
831 tmp &= ~LATENCY_WATERMARK_MASK(3);
832 tmp |= LATENCY_WATERMARK_MASK(2);
833 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
834 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
835 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
836 LATENCY_HIGH_WATERMARK(line_time)));
837 /* restore original selection */
838 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
839
840 /* write the priority marks */
841 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
842 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
843
844}
845
846void dce6_bandwidth_update(struct radeon_device *rdev)
847{
848 struct drm_display_mode *mode0 = NULL;
849 struct drm_display_mode *mode1 = NULL;
850 u32 num_heads = 0, lb_size;
851 int i;
852
853 radeon_update_display_priority(rdev);
854
855 for (i = 0; i < rdev->num_crtc; i++) {
856 if (rdev->mode_info.crtcs[i]->base.enabled)
857 num_heads++;
858 }
859 for (i = 0; i < rdev->num_crtc; i += 2) {
860 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
861 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
862 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
863 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
864 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
865 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
866 }
867}
868
0a96d72b
AD		 869/*
870 * Core functions
871 */
0a96d72b
AD		 872static void si_tiling_mode_table_init(struct radeon_device *rdev)
873{
874 const u32 num_tile_mode_states = 32;
875 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
876
877 switch (rdev->config.si.mem_row_size_in_kb) {
878 case 1:
879 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
880 break;
881 case 2:
882 default:
883 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
884 break;
885 case 4:
886 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
887 break;
888 }
889
890 if ((rdev->family == CHIP_TAHITI) ||
891 (rdev->family == CHIP_PITCAIRN)) {
892 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
893 switch (reg_offset) {
894 case 0: /* non-AA compressed depth or any compressed stencil */
895 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
896 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
897 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
898 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
899 NUM_BANKS(ADDR_SURF_16_BANK) |
900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
903 break;
904 case 1: /* 2xAA/4xAA compressed depth only */
905 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
906 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
907 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
909 NUM_BANKS(ADDR_SURF_16_BANK) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
913 break;
914 case 2: /* 8xAA compressed depth only */
915 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
917 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
918 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
919 NUM_BANKS(ADDR_SURF_16_BANK) |
920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
923 break;
924 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
925 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
927 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
929 NUM_BANKS(ADDR_SURF_16_BANK) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
933 break;
934 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
935 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
936 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
937 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
938 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
939 NUM_BANKS(ADDR_SURF_16_BANK) |
940 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
941 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
942 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
943 break;
944 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
945 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
947 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
948 TILE_SPLIT(split_equal_to_row_size) |
949 NUM_BANKS(ADDR_SURF_16_BANK) |
950 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
953 break;
954 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
957 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
958 TILE_SPLIT(split_equal_to_row_size) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
961 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
962 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
963 break;
964 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
965 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
967 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
968 TILE_SPLIT(split_equal_to_row_size) |
969 NUM_BANKS(ADDR_SURF_16_BANK) |
970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
973 break;
974 case 8: /* 1D and 1D Array Surfaces */
975 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
976 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
977 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
979 NUM_BANKS(ADDR_SURF_16_BANK) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
983 break;
984 case 9: /* Displayable maps. */
985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
986 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
987 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
989 NUM_BANKS(ADDR_SURF_16_BANK) |
990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
993 break;
994 case 10: /* Display 8bpp. */
995 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
996 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
997 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
998 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
999 NUM_BANKS(ADDR_SURF_16_BANK) |
1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1003 break;
1004 case 11: /* Display 16bpp. */
1005 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1006 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1008 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1009 NUM_BANKS(ADDR_SURF_16_BANK) |
1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1013 break;
1014 case 12: /* Display 32bpp. */
1015 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1016 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1017 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1019 NUM_BANKS(ADDR_SURF_16_BANK) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1023 break;
1024 case 13: /* Thin. */
1025 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1026 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1027 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1029 NUM_BANKS(ADDR_SURF_16_BANK) |
1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1033 break;
1034 case 14: /* Thin 8 bpp. */
1035 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1036 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1037 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1039 NUM_BANKS(ADDR_SURF_16_BANK) |
1040 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1043 break;
1044 case 15: /* Thin 16 bpp. */
1045 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1047 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1049 NUM_BANKS(ADDR_SURF_16_BANK) |
1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1053 break;
1054 case 16: /* Thin 32 bpp. */
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1057 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1059 NUM_BANKS(ADDR_SURF_16_BANK) |
1060 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1063 break;
1064 case 17: /* Thin 64 bpp. */
1065 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1067 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1068 TILE_SPLIT(split_equal_to_row_size) |
1069 NUM_BANKS(ADDR_SURF_16_BANK) |
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1073 break;
1074 case 21: /* 8 bpp PRT. */
1075 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1076 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1079 NUM_BANKS(ADDR_SURF_16_BANK) |
1080 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1081 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1082 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1083 break;
1084 case 22: /* 16 bpp PRT */
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1089 NUM_BANKS(ADDR_SURF_16_BANK) |
1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1093 break;
1094 case 23: /* 32 bpp PRT */
1095 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 NUM_BANKS(ADDR_SURF_16_BANK) |
1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1103 break;
1104 case 24: /* 64 bpp PRT */
1105 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1109 NUM_BANKS(ADDR_SURF_16_BANK) |
1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1113 break;
1114 case 25: /* 128 bpp PRT */
1115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1119 NUM_BANKS(ADDR_SURF_8_BANK) |
1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1123 break;
1124 default:
1125 gb_tile_moden = 0;
1126 break;
1127 }
1128 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1129 }
1130 } else if (rdev->family == CHIP_VERDE) {
1131 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1132 switch (reg_offset) {
1133 case 0: /* non-AA compressed depth or any compressed stencil */
1134 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1135 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1136 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1138 NUM_BANKS(ADDR_SURF_16_BANK) |
1139 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1141 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1142 break;
1143 case 1: /* 2xAA/4xAA compressed depth only */
1144 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1145 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1146 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1147 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1148 NUM_BANKS(ADDR_SURF_16_BANK) |
1149 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1152 break;
1153 case 2: /* 8xAA compressed depth only */
1154 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1155 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1156 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1158 NUM_BANKS(ADDR_SURF_16_BANK) |
1159 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1162 break;
1163 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1164 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1165 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1166 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1167 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1168 NUM_BANKS(ADDR_SURF_16_BANK) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1172 break;
1173 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1174 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1175 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1176 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1177 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1178 NUM_BANKS(ADDR_SURF_16_BANK) |
1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1182 break;
1183 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1184 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1185 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1186 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1187 TILE_SPLIT(split_equal_to_row_size) |
1188 NUM_BANKS(ADDR_SURF_16_BANK) |
1189 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1192 break;
1193 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1194 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1196 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1197 TILE_SPLIT(split_equal_to_row_size) |
1198 NUM_BANKS(ADDR_SURF_16_BANK) |
1199 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1202 break;
1203 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1204 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1206 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1207 TILE_SPLIT(split_equal_to_row_size) |
1208 NUM_BANKS(ADDR_SURF_16_BANK) |
1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1212 break;
1213 case 8: /* 1D and 1D Array Surfaces */
1214 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1215 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1216 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1218 NUM_BANKS(ADDR_SURF_16_BANK) |
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1222 break;
1223 case 9: /* Displayable maps. */
1224 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1228 NUM_BANKS(ADDR_SURF_16_BANK) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1232 break;
1233 case 10: /* Display 8bpp. */
1234 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1238 NUM_BANKS(ADDR_SURF_16_BANK) |
1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1242 break;
1243 case 11: /* Display 16bpp. */
1244 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1248 NUM_BANKS(ADDR_SURF_16_BANK) |
1249 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1252 break;
1253 case 12: /* Display 32bpp. */
1254 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1255 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1258 NUM_BANKS(ADDR_SURF_16_BANK) |
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1262 break;
1263 case 13: /* Thin. */
1264 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1265 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1268 NUM_BANKS(ADDR_SURF_16_BANK) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1272 break;
1273 case 14: /* Thin 8 bpp. */
1274 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1275 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1278 NUM_BANKS(ADDR_SURF_16_BANK) |
1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1282 break;
1283 case 15: /* Thin 16 bpp. */
1284 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1285 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1286 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1288 NUM_BANKS(ADDR_SURF_16_BANK) |
1289 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1292 break;
1293 case 16: /* Thin 32 bpp. */
1294 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1295 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1296 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1297 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1298 NUM_BANKS(ADDR_SURF_16_BANK) |
1299 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1300 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1301 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1302 break;
1303 case 17: /* Thin 64 bpp. */
1304 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1305 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1306 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1307 TILE_SPLIT(split_equal_to_row_size) |
1308 NUM_BANKS(ADDR_SURF_16_BANK) |
1309 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1310 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1311 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1312 break;
1313 case 21: /* 8 bpp PRT. */
1314 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1315 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1316 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1318 NUM_BANKS(ADDR_SURF_16_BANK) |
1319 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1322 break;
1323 case 22: /* 16 bpp PRT */
1324 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1326 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1327 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1328 NUM_BANKS(ADDR_SURF_16_BANK) |
1329 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1330 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1331 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1332 break;
1333 case 23: /* 32 bpp PRT */
1334 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1335 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1336 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1337 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1338 NUM_BANKS(ADDR_SURF_16_BANK) |
1339 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1342 break;
1343 case 24: /* 64 bpp PRT */
1344 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1347 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1348 NUM_BANKS(ADDR_SURF_16_BANK) |
1349 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1352 break;
1353 case 25: /* 128 bpp PRT */
1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1356 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1357 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1358 NUM_BANKS(ADDR_SURF_8_BANK) |
1359 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1362 break;
1363 default:
1364 gb_tile_moden = 0;
1365 break;
1366 }
1367 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1368 }
1369 } else
1370 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1371}
1372
1a8ca750
AD		 1373static void si_select_se_sh(struct radeon_device *rdev,
1374 u32 se_num, u32 sh_num)
1375{
1376 u32 data = INSTANCE_BROADCAST_WRITES;
1377
1378 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1379 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1380 else if (se_num == 0xffffffff)
1381 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1382 else if (sh_num == 0xffffffff)
1383 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1384 else
1385 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1386 WREG32(GRBM_GFX_INDEX, data);
1387}
1388
1389static u32 si_create_bitmask(u32 bit_width)
1390{
1391 u32 i, mask = 0;
1392
1393 for (i = 0; i < bit_width; i++) {
1394 mask <<= 1;
1395 mask |= 1;
1396 }
1397 return mask;
1398}
1399
1400static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1401{
1402 u32 data, mask;
1403
1404 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1405 if (data & 1)
1406 data &= INACTIVE_CUS_MASK;
1407 else
1408 data = 0;
1409 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1410
1411 data >>= INACTIVE_CUS_SHIFT;
1412
1413 mask = si_create_bitmask(cu_per_sh);
1414
1415 return ~data & mask;
1416}
1417
1418static void si_setup_spi(struct radeon_device *rdev,
1419 u32 se_num, u32 sh_per_se,
1420 u32 cu_per_sh)
1421{
1422 int i, j, k;
1423 u32 data, mask, active_cu;
1424
1425 for (i = 0; i < se_num; i++) {
1426 for (j = 0; j < sh_per_se; j++) {
1427 si_select_se_sh(rdev, i, j);
1428 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1429 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1430
1431 mask = 1;
1432 for (k = 0; k < 16; k++) {
1433 mask <<= k;
1434 if (active_cu & mask) {
1435 data &= ~mask;
1436 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1437 break;
1438 }
1439 }
1440 }
1441 }
1442 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1443}
1444
1445static u32 si_get_rb_disabled(struct radeon_device *rdev,
1446 u32 max_rb_num, u32 se_num,
1447 u32 sh_per_se)
1448{
1449 u32 data, mask;
1450
1451 data = RREG32(CC_RB_BACKEND_DISABLE);
1452 if (data & 1)
1453 data &= BACKEND_DISABLE_MASK;
1454 else
1455 data = 0;
1456 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1457
1458 data >>= BACKEND_DISABLE_SHIFT;
1459
1460 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1461
1462 return data & mask;
1463}
1464
1465static void si_setup_rb(struct radeon_device *rdev,
1466 u32 se_num, u32 sh_per_se,
1467 u32 max_rb_num)
1468{
1469 int i, j;
1470 u32 data, mask;
1471 u32 disabled_rbs = 0;
1472 u32 enabled_rbs = 0;
1473
1474 for (i = 0; i < se_num; i++) {
1475 for (j = 0; j < sh_per_se; j++) {
1476 si_select_se_sh(rdev, i, j);
1477 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1478 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1479 }
1480 }
1481 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1482
1483 mask = 1;
1484 for (i = 0; i < max_rb_num; i++) {
1485 if (!(disabled_rbs & mask))
1486 enabled_rbs |= mask;
1487 mask <<= 1;
1488 }
1489
1490 for (i = 0; i < se_num; i++) {
1491 si_select_se_sh(rdev, i, 0xffffffff);
1492 data = 0;
1493 for (j = 0; j < sh_per_se; j++) {
1494 switch (enabled_rbs & 3) {
1495 case 1:
1496 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1497 break;
1498 case 2:
1499 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1500 break;
1501 case 3:
1502 default:
1503 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1504 break;
1505 }
1506 enabled_rbs >>= 2;
1507 }
1508 WREG32(PA_SC_RASTER_CONFIG, data);
1509 }
1510 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1511}
1512
0a96d72b
AD		 1513static void si_gpu_init(struct radeon_device *rdev)
1514{
0a96d72b
AD		 1515 u32 gb_addr_config = 0;
1516 u32 mc_shared_chmap, mc_arb_ramcfg;
0a96d72b 1517 u32 sx_debug_1;
0a96d72b
AD		 1518 u32 hdp_host_path_cntl;
1519 u32 tmp;
1520 int i, j;
1521
1522 switch (rdev->family) {
1523 case CHIP_TAHITI:
1524 rdev->config.si.max_shader_engines = 2;
0a96d72b 1525 rdev->config.si.max_tile_pipes = 12;
1a8ca750
AD		 1526 rdev->config.si.max_cu_per_sh = 8;
1527 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1528 rdev->config.si.max_backends_per_se = 4;
1529 rdev->config.si.max_texture_channel_caches = 12;
1530 rdev->config.si.max_gprs = 256;
1531 rdev->config.si.max_gs_threads = 32;
1532 rdev->config.si.max_hw_contexts = 8;
1533
1534 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1535 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1536 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1537 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1538 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1539 break;
1540 case CHIP_PITCAIRN:
1541 rdev->config.si.max_shader_engines = 2;
0a96d72b 1542 rdev->config.si.max_tile_pipes = 8;
1a8ca750
AD		 1543 rdev->config.si.max_cu_per_sh = 5;
1544 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1545 rdev->config.si.max_backends_per_se = 4;
1546 rdev->config.si.max_texture_channel_caches = 8;
1547 rdev->config.si.max_gprs = 256;
1548 rdev->config.si.max_gs_threads = 32;
1549 rdev->config.si.max_hw_contexts = 8;
1550
1551 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1552 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1553 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1554 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1555 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1556 break;
1557 case CHIP_VERDE:
1558 default:
1559 rdev->config.si.max_shader_engines = 1;
0a96d72b 1560 rdev->config.si.max_tile_pipes = 4;
1a8ca750
AD		 1561 rdev->config.si.max_cu_per_sh = 2;
1562 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1563 rdev->config.si.max_backends_per_se = 4;
1564 rdev->config.si.max_texture_channel_caches = 4;
1565 rdev->config.si.max_gprs = 256;
1566 rdev->config.si.max_gs_threads = 32;
1567 rdev->config.si.max_hw_contexts = 8;
1568
1569 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1570 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1571 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1572 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1573 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1574 break;
1575 }
1576
1577 /* Initialize HDP */
1578 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1579 WREG32((0x2c14 + j), 0x00000000);
1580 WREG32((0x2c18 + j), 0x00000000);
1581 WREG32((0x2c1c + j), 0x00000000);
1582 WREG32((0x2c20 + j), 0x00000000);
1583 WREG32((0x2c24 + j), 0x00000000);
1584 }
1585
1586 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1587
1588 evergreen_fix_pci_max_read_req_size(rdev);
1589
1590 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1591
1592 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1593 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1594
0a96d72b 1595 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
0a96d72b
AD		 1596 rdev->config.si.mem_max_burst_length_bytes = 256;
1597 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1598 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1599 if (rdev->config.si.mem_row_size_in_kb > 4)
1600 rdev->config.si.mem_row_size_in_kb = 4;
1601 /* XXX use MC settings? */
1602 rdev->config.si.shader_engine_tile_size = 32;
1603 rdev->config.si.num_gpus = 1;
1604 rdev->config.si.multi_gpu_tile_size = 64;
1605
1a8ca750
AD		 1606 /* fix up row size */
1607 gb_addr_config &= ~ROW_SIZE_MASK;
0a96d72b
AD		 1608 switch (rdev->config.si.mem_row_size_in_kb) {
1609 case 1:
1610 default:
1611 gb_addr_config |= ROW_SIZE(0);
1612 break;
1613 case 2:
1614 gb_addr_config |= ROW_SIZE(1);
1615 break;
1616 case 4:
1617 gb_addr_config |= ROW_SIZE(2);
1618 break;
1619 }
1620
0a96d72b
AD		 1621 /* setup tiling info dword. gb_addr_config is not adequate since it does
1622 * not have bank info, so create a custom tiling dword.
1623 * bits 3:0 num_pipes
1624 * bits 7:4 num_banks
1625 * bits 11:8 group_size
1626 * bits 15:12 row_size
1627 */
1628 rdev->config.si.tile_config = 0;
1629 switch (rdev->config.si.num_tile_pipes) {
1630 case 1:
1631 rdev->config.si.tile_config |= (0 << 0);
1632 break;
1633 case 2:
1634 rdev->config.si.tile_config |= (1 << 0);
1635 break;
1636 case 4:
1637 rdev->config.si.tile_config |= (2 << 0);
1638 break;
1639 case 8:
1640 default:
1641 /* XXX what about 12? */
1642 rdev->config.si.tile_config |= (3 << 0);
1643 break;
dca571a6
CK		 1644 }
1645 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1646 case 0: /* four banks */
1a8ca750 1647 rdev->config.si.tile_config |= 0 << 4;
dca571a6
CK		 1648 break;
1649 case 1: /* eight banks */
1650 rdev->config.si.tile_config |= 1 << 4;
1651 break;
1652 case 2: /* sixteen banks */
1653 default:
1654 rdev->config.si.tile_config |= 2 << 4;
1655 break;
1656 }
0a96d72b
AD		 1657 rdev->config.si.tile_config |=
1658 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1659 rdev->config.si.tile_config |=
1660 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1661
0a96d72b
AD		 1662 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1663 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1664 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
8c5fd7ef
AD		 1665 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1666 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
0a96d72b 1667
1a8ca750 1668 si_tiling_mode_table_init(rdev);
0a96d72b 1669
1a8ca750
AD		 1670 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1671 rdev->config.si.max_sh_per_se,
1672 rdev->config.si.max_backends_per_se);
0a96d72b 1673
1a8ca750
AD		 1674 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1675 rdev->config.si.max_sh_per_se,
1676 rdev->config.si.max_cu_per_sh);
0a96d72b 1677
0a96d72b
AD		 1678
1679 /* set HW defaults for 3D engine */
1680 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1681 ROQ_IB2_START(0x2b)));
1682 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1683
1684 sx_debug_1 = RREG32(SX_DEBUG_1);
1685 WREG32(SX_DEBUG_1, sx_debug_1);
1686
1687 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1688
1689 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1690 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1691 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1692 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1693
1694 WREG32(VGT_NUM_INSTANCES, 1);
1695
1696 WREG32(CP_PERFMON_CNTL, 0);
1697
1698 WREG32(SQ_CONFIG, 0);
1699
1700 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1701 FORCE_EOV_MAX_REZ_CNT(255)));
1702
1703 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1704 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1705
1706 WREG32(VGT_GS_VERTEX_REUSE, 16);
1707 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1708
1709 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1710 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1711 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1712 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1713 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1714 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1715 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1716 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1717
1718 tmp = RREG32(HDP_MISC_CNTL);
1719 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1720 WREG32(HDP_MISC_CNTL, tmp);
1721
1722 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1723 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1724
1725 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1726
1727 udelay(50);
1728}
c476dde2 1729
2ece2e8b
AD		 1730/*
1731 * GPU scratch registers helpers function.
1732 */
1733static void si_scratch_init(struct radeon_device *rdev)
1734{
1735 int i;
1736
1737 rdev->scratch.num_reg = 7;
1738 rdev->scratch.reg_base = SCRATCH_REG0;
1739 for (i = 0; i < rdev->scratch.num_reg; i++) {
1740 rdev->scratch.free[i] = true;
1741 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1742 }
1743}
1744
1745void si_fence_ring_emit(struct radeon_device *rdev,
1746 struct radeon_fence *fence)
1747{
1748 struct radeon_ring *ring = &rdev->ring[fence->ring];
1749 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1750
1751 /* flush read cache over gart */
1752 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1753 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1754 radeon_ring_write(ring, 0);
1755 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1756 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1757 PACKET3_TC_ACTION_ENA |
1758 PACKET3_SH_KCACHE_ACTION_ENA |
1759 PACKET3_SH_ICACHE_ACTION_ENA);
1760 radeon_ring_write(ring, 0xFFFFFFFF);
1761 radeon_ring_write(ring, 0);
1762 radeon_ring_write(ring, 10); /* poll interval */
1763 /* EVENT_WRITE_EOP - flush caches, send int */
1764 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1765 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1766 radeon_ring_write(ring, addr & 0xffffffff);
1767 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1768 radeon_ring_write(ring, fence->seq);
1769 radeon_ring_write(ring, 0);
1770}
1771
1772/*
1773 * IB stuff
1774 */
1775void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1776{
876dc9f3 1777 struct radeon_ring *ring = &rdev->ring[ib->ring];
2ece2e8b
AD		 1778 u32 header;
1779
a85a7da4
AD		 1780 if (ib->is_const_ib) {
1781 /* set switch buffer packet before const IB */
1782 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1783 radeon_ring_write(ring, 0);
45df6803 1784
2ece2e8b 1785 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
a85a7da4 1786 } else {
89d35807 1787 u32 next_rptr;
a85a7da4 1788 if (ring->rptr_save_reg) {
89d35807 1789 next_rptr = ring->wptr + 3 + 4 + 8;
a85a7da4
AD		 1790 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 radeon_ring_write(ring, ((ring->rptr_save_reg -
1792 PACKET3_SET_CONFIG_REG_START) >> 2));
1793 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1794 } else if (rdev->wb.enabled) {
1795 next_rptr = ring->wptr + 5 + 4 + 8;
1796 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1797 radeon_ring_write(ring, (1 << 8));
1798 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1799 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1800 radeon_ring_write(ring, next_rptr);
a85a7da4
AD		 1801 }
1802
2ece2e8b 1803 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
a85a7da4 1804 }
2ece2e8b
AD		 1805
1806 radeon_ring_write(ring, header);
1807 radeon_ring_write(ring,
1808#ifdef __BIG_ENDIAN
1809 (2 << 0) |
1810#endif
1811 (ib->gpu_addr & 0xFFFFFFFC));
1812 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4bf3dd92
CK		 1813 radeon_ring_write(ring, ib->length_dw |
1814 (ib->vm ? (ib->vm->id << 24) : 0));
2ece2e8b 1815
a85a7da4
AD		 1816 if (!ib->is_const_ib) {
1817 /* flush read cache over gart for this vmid */
1818 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1819 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 1820 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
a85a7da4
AD		 1821 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1822 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1823 PACKET3_TC_ACTION_ENA |
1824 PACKET3_SH_KCACHE_ACTION_ENA |
1825 PACKET3_SH_ICACHE_ACTION_ENA);
1826 radeon_ring_write(ring, 0xFFFFFFFF);
1827 radeon_ring_write(ring, 0);
1828 radeon_ring_write(ring, 10); /* poll interval */
1829 }
2ece2e8b
AD		 1830}
1831
48c0c902
AD		 1832/*
1833 * CP.
1834 */
1835static void si_cp_enable(struct radeon_device *rdev, bool enable)
1836{
1837 if (enable)
1838 WREG32(CP_ME_CNTL, 0);
1839 else {
1840 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1841 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1842 WREG32(SCRATCH_UMSK, 0);
8c5fd7ef
AD		 1843 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1844 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1845 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
48c0c902
AD		 1846 }
1847 udelay(50);
1848}
1849
1850static int si_cp_load_microcode(struct radeon_device *rdev)
1851{
1852 const __be32 *fw_data;
1853 int i;
1854
1855 if (!rdev->me_fw || !rdev->pfp_fw)
1856 return -EINVAL;
1857
1858 si_cp_enable(rdev, false);
1859
1860 /* PFP */
1861 fw_data = (const __be32 *)rdev->pfp_fw->data;
1862 WREG32(CP_PFP_UCODE_ADDR, 0);
1863 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1864 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1865 WREG32(CP_PFP_UCODE_ADDR, 0);
1866
1867 /* CE */
1868 fw_data = (const __be32 *)rdev->ce_fw->data;
1869 WREG32(CP_CE_UCODE_ADDR, 0);
1870 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1871 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1872 WREG32(CP_CE_UCODE_ADDR, 0);
1873
1874 /* ME */
1875 fw_data = (const __be32 *)rdev->me_fw->data;
1876 WREG32(CP_ME_RAM_WADDR, 0);
1877 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1878 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1879 WREG32(CP_ME_RAM_WADDR, 0);
1880
1881 WREG32(CP_PFP_UCODE_ADDR, 0);
1882 WREG32(CP_CE_UCODE_ADDR, 0);
1883 WREG32(CP_ME_RAM_WADDR, 0);
1884 WREG32(CP_ME_RAM_RADDR, 0);
1885 return 0;
1886}
1887
1888static int si_cp_start(struct radeon_device *rdev)
1889{
1890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1891 int r, i;
1892
1893 r = radeon_ring_lock(rdev, ring, 7 + 4);
1894 if (r) {
1895 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1896 return r;
1897 }
1898 /* init the CP */
1899 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1900 radeon_ring_write(ring, 0x1);
1901 radeon_ring_write(ring, 0x0);
1902 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1903 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1904 radeon_ring_write(ring, 0);
1905 radeon_ring_write(ring, 0);
1906
1907 /* init the CE partitions */
1908 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1909 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1910 radeon_ring_write(ring, 0xc000);
1911 radeon_ring_write(ring, 0xe000);
1912 radeon_ring_unlock_commit(rdev, ring);
1913
1914 si_cp_enable(rdev, true);
1915
1916 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1917 if (r) {
1918 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1919 return r;
1920 }
1921
1922 /* setup clear context state */
1923 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1924 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1925
1926 for (i = 0; i < si_default_size; i++)
1927 radeon_ring_write(ring, si_default_state[i]);
1928
1929 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1930 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1931
1932 /* set clear context state */
1933 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1934 radeon_ring_write(ring, 0);
1935
1936 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1937 radeon_ring_write(ring, 0x00000316);
1938 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1939 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1940
1941 radeon_ring_unlock_commit(rdev, ring);
1942
1943 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1944 ring = &rdev->ring[i];
1945 r = radeon_ring_lock(rdev, ring, 2);
1946
1947 /* clear the compute context state */
1948 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
1949 radeon_ring_write(ring, 0);
1950
1951 radeon_ring_unlock_commit(rdev, ring);
1952 }
1953
1954 return 0;
1955}
1956
1957static void si_cp_fini(struct radeon_device *rdev)
1958{
45df6803 1959 struct radeon_ring *ring;
48c0c902 1960 si_cp_enable(rdev, false);
45df6803
CK		 1961
1962 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1963 radeon_ring_fini(rdev, ring);
1964 radeon_scratch_free(rdev, ring->rptr_save_reg);
1965
1966 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1967 radeon_ring_fini(rdev, ring);
1968 radeon_scratch_free(rdev, ring->rptr_save_reg);
1969
1970 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1971 radeon_ring_fini(rdev, ring);
1972 radeon_scratch_free(rdev, ring->rptr_save_reg);
48c0c902
AD		 1973}
1974
1975static int si_cp_resume(struct radeon_device *rdev)
1976{
1977 struct radeon_ring *ring;
1978 u32 tmp;
1979 u32 rb_bufsz;
1980 int r;
1981
1982 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1983 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1984 SOFT_RESET_PA |
1985 SOFT_RESET_VGT |
1986 SOFT_RESET_SPI |
1987 SOFT_RESET_SX));
1988 RREG32(GRBM_SOFT_RESET);
1989 mdelay(15);
1990 WREG32(GRBM_SOFT_RESET, 0);
1991 RREG32(GRBM_SOFT_RESET);
1992
1993 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1994 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1995
1996 /* Set the write pointer delay */
1997 WREG32(CP_RB_WPTR_DELAY, 0);
1998
1999 WREG32(CP_DEBUG, 0);
2000 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2001
2002 /* ring 0 - compute and gfx */
2003 /* Set ring buffer size */
2004 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2005 rb_bufsz = drm_order(ring->ring_size / 8);
2006 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2007#ifdef __BIG_ENDIAN
2008 tmp |= BUF_SWAP_32BIT;
2009#endif
2010 WREG32(CP_RB0_CNTL, tmp);
2011
2012 /* Initialize the ring buffer's read and write pointers */
2013 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2014 ring->wptr = 0;
2015 WREG32(CP_RB0_WPTR, ring->wptr);
2016
48fc7f7e 2017 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2018 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2019 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2020
2021 if (rdev->wb.enabled)
2022 WREG32(SCRATCH_UMSK, 0xff);
2023 else {
2024 tmp |= RB_NO_UPDATE;
2025 WREG32(SCRATCH_UMSK, 0);
2026 }
2027
2028 mdelay(1);
2029 WREG32(CP_RB0_CNTL, tmp);
2030
2031 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2032
2033 ring->rptr = RREG32(CP_RB0_RPTR);
2034
2035 /* ring1 - compute only */
2036 /* Set ring buffer size */
2037 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2038 rb_bufsz = drm_order(ring->ring_size / 8);
2039 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2040#ifdef __BIG_ENDIAN
2041 tmp |= BUF_SWAP_32BIT;
2042#endif
2043 WREG32(CP_RB1_CNTL, tmp);
2044
2045 /* Initialize the ring buffer's read and write pointers */
2046 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2047 ring->wptr = 0;
2048 WREG32(CP_RB1_WPTR, ring->wptr);
2049
48fc7f7e 2050 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2051 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2052 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2053
2054 mdelay(1);
2055 WREG32(CP_RB1_CNTL, tmp);
2056
2057 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2058
2059 ring->rptr = RREG32(CP_RB1_RPTR);
2060
2061 /* ring2 - compute only */
2062 /* Set ring buffer size */
2063 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2064 rb_bufsz = drm_order(ring->ring_size / 8);
2065 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2066#ifdef __BIG_ENDIAN
2067 tmp |= BUF_SWAP_32BIT;
2068#endif
2069 WREG32(CP_RB2_CNTL, tmp);
2070
2071 /* Initialize the ring buffer's read and write pointers */
2072 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2073 ring->wptr = 0;
2074 WREG32(CP_RB2_WPTR, ring->wptr);
2075
48fc7f7e 2076 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2077 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2078 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2079
2080 mdelay(1);
2081 WREG32(CP_RB2_CNTL, tmp);
2082
2083 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2084
2085 ring->rptr = RREG32(CP_RB2_RPTR);
2086
2087 /* start the rings */
2088 si_cp_start(rdev);
2089 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2090 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2091 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2092 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2093 if (r) {
2094 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2095 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2096 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2097 return r;
2098 }
2099 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2100 if (r) {
2101 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2102 }
2103 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2104 if (r) {
2105 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2106 }
2107
2108 return 0;
2109}
2110
c476dde2
AD		 2111bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2112{
2113 u32 srbm_status;
2114 u32 grbm_status, grbm_status2;
2115 u32 grbm_status_se0, grbm_status_se1;
c476dde2
AD		 2116
2117 srbm_status = RREG32(SRBM_STATUS);
2118 grbm_status = RREG32(GRBM_STATUS);
2119 grbm_status2 = RREG32(GRBM_STATUS2);
2120 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2121 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2122 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2123 radeon_ring_lockup_update(ring);
c476dde2
AD		 2124 return false;
2125 }
2126 /* force CP activities */
7b9ef16b 2127 radeon_ring_force_activity(rdev, ring);
069211e5 2128 return radeon_ring_test_lockup(rdev, ring);
c476dde2
AD		 2129}
2130
014bb209 2131static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
06bc6df0 2132{
014bb209 2133 u32 reset_mask = 0;
1c534671 2134 u32 tmp;
06bc6df0 2135
014bb209
AD		 2136 /* GRBM_STATUS */
2137 tmp = RREG32(GRBM_STATUS);
2138 if (tmp & (PA_BUSY | SC_BUSY |
2139 BCI_BUSY | SX_BUSY |
2140 TA_BUSY | VGT_BUSY |
2141 DB_BUSY | CB_BUSY |
2142 GDS_BUSY | SPI_BUSY |
2143 IA_BUSY | IA_BUSY_NO_DMA))
2144 reset_mask |= RADEON_RESET_GFX;
2145
2146 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2147 CP_BUSY | CP_COHERENCY_BUSY))
2148 reset_mask |= RADEON_RESET_CP;
2149
2150 if (tmp & GRBM_EE_BUSY)
2151 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2152
2153 /* GRBM_STATUS2 */
2154 tmp = RREG32(GRBM_STATUS2);
2155 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2156 reset_mask |= RADEON_RESET_RLC;
2157
2158 /* DMA_STATUS_REG 0 */
2159 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2160 if (!(tmp & DMA_IDLE))
2161 reset_mask |= RADEON_RESET_DMA;
2162
2163 /* DMA_STATUS_REG 1 */
2164 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2165 if (!(tmp & DMA_IDLE))
2166 reset_mask |= RADEON_RESET_DMA1;
2167
2168 /* SRBM_STATUS2 */
2169 tmp = RREG32(SRBM_STATUS2);
2170 if (tmp & DMA_BUSY)
2171 reset_mask |= RADEON_RESET_DMA;
2172
2173 if (tmp & DMA1_BUSY)
2174 reset_mask |= RADEON_RESET_DMA1;
2175
2176 /* SRBM_STATUS */
2177 tmp = RREG32(SRBM_STATUS);
2178
2179 if (tmp & IH_BUSY)
2180 reset_mask |= RADEON_RESET_IH;
2181
2182 if (tmp & SEM_BUSY)
2183 reset_mask |= RADEON_RESET_SEM;
2184
2185 if (tmp & GRBM_RQ_PENDING)
2186 reset_mask |= RADEON_RESET_GRBM;
2187
2188 if (tmp & VMC_BUSY)
2189 reset_mask |= RADEON_RESET_VMC;
19fc42ed 2190
014bb209
AD		 2191 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2192 MCC_BUSY | MCD_BUSY))
2193 reset_mask |= RADEON_RESET_MC;
2194
2195 if (evergreen_is_display_hung(rdev))
2196 reset_mask |= RADEON_RESET_DISPLAY;
2197
2198 /* VM_L2_STATUS */
2199 tmp = RREG32(VM_L2_STATUS);
2200 if (tmp & L2_BUSY)
2201 reset_mask |= RADEON_RESET_VMC;
2202
2203 return reset_mask;
2204}
2205
2206static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2207{
2208 struct evergreen_mc_save save;
2209 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2210 u32 tmp;
19fc42ed 2211
06bc6df0 2212 if (reset_mask == 0)
014bb209 2213 return;
06bc6df0
AD		 2214
2215 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2216
1c534671 2217 evergreen_print_gpu_status_regs(rdev);
06bc6df0
AD		 2218 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2219 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2220 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2221 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2222
1c534671
AD		 2223 /* Disable CP parsing/prefetching */
2224 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2225
2226 if (reset_mask & RADEON_RESET_DMA) {
2227 /* dma0 */
2228 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2229 tmp &= ~DMA_RB_ENABLE;
2230 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
014bb209
AD		 2231 }
2232 if (reset_mask & RADEON_RESET_DMA1) {
1c534671
AD		 2233 /* dma1 */
2234 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2235 tmp &= ~DMA_RB_ENABLE;
2236 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2237 }
2238
f770d78a
AD		 2239 udelay(50);
2240
2241 evergreen_mc_stop(rdev, &save);
2242 if (evergreen_mc_wait_for_idle(rdev)) {
2243 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2244 }
2245
1c534671
AD		 2246 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2247 grbm_soft_reset = SOFT_RESET_CB |
2248 SOFT_RESET_DB |
2249 SOFT_RESET_GDS |
2250 SOFT_RESET_PA |
2251 SOFT_RESET_SC |
2252 SOFT_RESET_BCI |
2253 SOFT_RESET_SPI |
2254 SOFT_RESET_SX |
2255 SOFT_RESET_TC |
2256 SOFT_RESET_TA |
2257 SOFT_RESET_VGT |
2258 SOFT_RESET_IA;
2259 }
2260
2261 if (reset_mask & RADEON_RESET_CP) {
2262 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2263
2264 srbm_soft_reset |= SOFT_RESET_GRBM;
2265 }
06bc6df0
AD		 2266
2267 if (reset_mask & RADEON_RESET_DMA)
014bb209
AD		 2268 srbm_soft_reset |= SOFT_RESET_DMA;
2269
2270 if (reset_mask & RADEON_RESET_DMA1)
2271 srbm_soft_reset |= SOFT_RESET_DMA1;
2272
2273 if (reset_mask & RADEON_RESET_DISPLAY)
2274 srbm_soft_reset |= SOFT_RESET_DC;
2275
2276 if (reset_mask & RADEON_RESET_RLC)
2277 grbm_soft_reset |= SOFT_RESET_RLC;
2278
2279 if (reset_mask & RADEON_RESET_SEM)
2280 srbm_soft_reset |= SOFT_RESET_SEM;
2281
2282 if (reset_mask & RADEON_RESET_IH)
2283 srbm_soft_reset |= SOFT_RESET_IH;
2284
2285 if (reset_mask & RADEON_RESET_GRBM)
2286 srbm_soft_reset |= SOFT_RESET_GRBM;
2287
2288 if (reset_mask & RADEON_RESET_VMC)
2289 srbm_soft_reset |= SOFT_RESET_VMC;
2290
2291 if (reset_mask & RADEON_RESET_MC)
2292 srbm_soft_reset |= SOFT_RESET_MC;
1c534671
AD		 2293
2294 if (grbm_soft_reset) {
2295 tmp = RREG32(GRBM_SOFT_RESET);
2296 tmp |= grbm_soft_reset;
2297 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2298 WREG32(GRBM_SOFT_RESET, tmp);
2299 tmp = RREG32(GRBM_SOFT_RESET);
2300
2301 udelay(50);
2302
2303 tmp &= ~grbm_soft_reset;
2304 WREG32(GRBM_SOFT_RESET, tmp);
2305 tmp = RREG32(GRBM_SOFT_RESET);
2306 }
2307
2308 if (srbm_soft_reset) {
2309 tmp = RREG32(SRBM_SOFT_RESET);
2310 tmp |= srbm_soft_reset;
2311 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2312 WREG32(SRBM_SOFT_RESET, tmp);
2313 tmp = RREG32(SRBM_SOFT_RESET);
2314
2315 udelay(50);
2316
2317 tmp &= ~srbm_soft_reset;
2318 WREG32(SRBM_SOFT_RESET, tmp);
2319 tmp = RREG32(SRBM_SOFT_RESET);
2320 }
06bc6df0
AD		 2321
2322 /* Wait a little for things to settle down */
2323 udelay(50);
2324
c476dde2 2325 evergreen_mc_resume(rdev, &save);
1c534671
AD		 2326 udelay(50);
2327
1c534671 2328 evergreen_print_gpu_status_regs(rdev);
c476dde2
AD		 2329}
2330
2331int si_asic_reset(struct radeon_device *rdev)
2332{
014bb209
AD		 2333 u32 reset_mask;
2334
2335 reset_mask = si_gpu_check_soft_reset(rdev);
2336
2337 if (reset_mask)
2338 r600_set_bios_scratch_engine_hung(rdev, true);
2339
2340 si_gpu_soft_reset(rdev, reset_mask);
2341
2342 reset_mask = si_gpu_check_soft_reset(rdev);
2343
2344 if (!reset_mask)
2345 r600_set_bios_scratch_engine_hung(rdev, false);
2346
2347 return 0;
c476dde2
AD		 2348}
2349
d2800ee5
AD		 2350/* MC */
2351static void si_mc_program(struct radeon_device *rdev)
2352{
2353 struct evergreen_mc_save save;
2354 u32 tmp;
2355 int i, j;
2356
2357 /* Initialize HDP */
2358 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2359 WREG32((0x2c14 + j), 0x00000000);
2360 WREG32((0x2c18 + j), 0x00000000);
2361 WREG32((0x2c1c + j), 0x00000000);
2362 WREG32((0x2c20 + j), 0x00000000);
2363 WREG32((0x2c24 + j), 0x00000000);
2364 }
2365 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2366
2367 evergreen_mc_stop(rdev, &save);
2368 if (radeon_mc_wait_for_idle(rdev)) {
2369 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2370 }
2371 /* Lockout access through VGA aperture*/
2372 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2373 /* Update configuration */
2374 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2375 rdev->mc.vram_start >> 12);
2376 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2377 rdev->mc.vram_end >> 12);
2378 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2379 rdev->vram_scratch.gpu_addr >> 12);
2380 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2381 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2382 WREG32(MC_VM_FB_LOCATION, tmp);
2383 /* XXX double check these! */
2384 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2385 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2386 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2387 WREG32(MC_VM_AGP_BASE, 0);
2388 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2389 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2390 if (radeon_mc_wait_for_idle(rdev)) {
2391 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2392 }
2393 evergreen_mc_resume(rdev, &save);
2394 /* we need to own VRAM, so turn off the VGA renderer here
2395 * to stop it overwriting our objects */
2396 rv515_vga_render_disable(rdev);
2397}
2398
2399/* SI MC address space is 40 bits */
2400static void si_vram_location(struct radeon_device *rdev,
2401 struct radeon_mc *mc, u64 base)
2402{
2403 mc->vram_start = base;
2404 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2405 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2406 mc->real_vram_size = mc->aper_size;
2407 mc->mc_vram_size = mc->aper_size;
2408 }
2409 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2410 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2411 mc->mc_vram_size >> 20, mc->vram_start,
2412 mc->vram_end, mc->real_vram_size >> 20);
2413}
2414
2415static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2416{
2417 u64 size_af, size_bf;
2418
2419 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2420 size_bf = mc->vram_start & ~mc->gtt_base_align;
2421 if (size_bf > size_af) {
2422 if (mc->gtt_size > size_bf) {
2423 dev_warn(rdev->dev, "limiting GTT\n");
2424 mc->gtt_size = size_bf;
2425 }
2426 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2427 } else {
2428 if (mc->gtt_size > size_af) {
2429 dev_warn(rdev->dev, "limiting GTT\n");
2430 mc->gtt_size = size_af;
2431 }
2432 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2433 }
2434 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2435 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2436 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2437}
2438
2439static void si_vram_gtt_location(struct radeon_device *rdev,
2440 struct radeon_mc *mc)
2441{
2442 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2443 /* leave room for at least 1024M GTT */
2444 dev_warn(rdev->dev, "limiting VRAM\n");
2445 mc->real_vram_size = 0xFFC0000000ULL;
2446 mc->mc_vram_size = 0xFFC0000000ULL;
2447 }
2448 si_vram_location(rdev, &rdev->mc, 0);
2449 rdev->mc.gtt_base_align = 0;
2450 si_gtt_location(rdev, mc);
2451}
2452
2453static int si_mc_init(struct radeon_device *rdev)
2454{
2455 u32 tmp;
2456 int chansize, numchan;
2457
2458 /* Get VRAM informations */
2459 rdev->mc.vram_is_ddr = true;
2460 tmp = RREG32(MC_ARB_RAMCFG);
2461 if (tmp & CHANSIZE_OVERRIDE) {
2462 chansize = 16;
2463 } else if (tmp & CHANSIZE_MASK) {
2464 chansize = 64;
2465 } else {
2466 chansize = 32;
2467 }
2468 tmp = RREG32(MC_SHARED_CHMAP);
2469 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2470 case 0:
2471 default:
2472 numchan = 1;
2473 break;
2474 case 1:
2475 numchan = 2;
2476 break;
2477 case 2:
2478 numchan = 4;
2479 break;
2480 case 3:
2481 numchan = 8;
2482 break;
2483 case 4:
2484 numchan = 3;
2485 break;
2486 case 5:
2487 numchan = 6;
2488 break;
2489 case 6:
2490 numchan = 10;
2491 break;
2492 case 7:
2493 numchan = 12;
2494 break;
2495 case 8:
2496 numchan = 16;
2497 break;
2498 }
2499 rdev->mc.vram_width = numchan * chansize;
2500 /* Could aper size report 0 ? */
2501 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2502 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2503 /* size in MB on si */
2504 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2505 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2506 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2507 si_vram_gtt_location(rdev, &rdev->mc);
2508 radeon_update_bandwidth_info(rdev);
2509
2510 return 0;
2511}
2512
2513/*
2514 * GART
2515 */
2516void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2517{
2518 /* flush hdp cache */
2519 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2520
2521 /* bits 0-15 are the VM contexts0-15 */
2522 WREG32(VM_INVALIDATE_REQUEST, 1);
2523}
2524
1109ca09 2525static int si_pcie_gart_enable(struct radeon_device *rdev)
d2800ee5
AD		 2526{
2527 int r, i;
2528
2529 if (rdev->gart.robj == NULL) {
2530 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2531 return -EINVAL;
2532 }
2533 r = radeon_gart_table_vram_pin(rdev);
2534 if (r)
2535 return r;
2536 radeon_gart_restore(rdev);
2537 /* Setup TLB control */
2538 WREG32(MC_VM_MX_L1_TLB_CNTL,
2539 (0xA << 7) |
2540 ENABLE_L1_TLB |
2541 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2542 ENABLE_ADVANCED_DRIVER_MODEL |
2543 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2544 /* Setup L2 cache */
2545 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2546 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2547 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2548 EFFECTIVE_L2_QUEUE_SIZE(7) |
2549 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2550 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2551 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2552 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2553 /* setup context0 */
2554 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2555 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2556 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2557 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2558 (u32)(rdev->dummy_page.addr >> 12));
2559 WREG32(VM_CONTEXT0_CNTL2, 0);
2560 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2561 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2562
2563 WREG32(0x15D4, 0);
2564 WREG32(0x15D8, 0);
2565 WREG32(0x15DC, 0);
2566
2567 /* empty context1-15 */
d2800ee5
AD		 2568 /* set vm size, must be a multiple of 4 */
2569 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
c21b328e 2570 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
23d4f1f2
AD		 2571 /* Assign the pt base to something valid for now; the pts used for
2572 * the VMs are determined by the application and setup and assigned
2573 * on the fly in the vm part of radeon_gart.c
2574 */
d2800ee5
AD		 2575 for (i = 1; i < 16; i++) {
2576 if (i < 8)
2577 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2578 rdev->gart.table_addr >> 12);
2579 else
2580 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2581 rdev->gart.table_addr >> 12);
2582 }
2583
2584 /* enable context1-15 */
2585 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2586 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 2587 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 2588 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 2589 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2590 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2591 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2592 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2593 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2594 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2595 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2596 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2597 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2598 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2599 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2600 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
d2800ee5
AD		 2601
2602 si_pcie_gart_tlb_flush(rdev);
2603 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2604 (unsigned)(rdev->mc.gtt_size >> 20),
2605 (unsigned long long)rdev->gart.table_addr);
2606 rdev->gart.ready = true;
2607 return 0;
2608}
2609
1109ca09 2610static void si_pcie_gart_disable(struct radeon_device *rdev)
d2800ee5
AD		 2611{
2612 /* Disable all tables */
2613 WREG32(VM_CONTEXT0_CNTL, 0);
2614 WREG32(VM_CONTEXT1_CNTL, 0);
2615 /* Setup TLB control */
2616 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2617 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2618 /* Setup L2 cache */
2619 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2620 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2621 EFFECTIVE_L2_QUEUE_SIZE(7) |
2622 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2623 WREG32(VM_L2_CNTL2, 0);
2624 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2625 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2626 radeon_gart_table_vram_unpin(rdev);
2627}
2628
1109ca09 2629static void si_pcie_gart_fini(struct radeon_device *rdev)
d2800ee5
AD		 2630{
2631 si_pcie_gart_disable(rdev);
2632 radeon_gart_table_vram_free(rdev);
2633 radeon_gart_fini(rdev);
2634}
2635
498dd8b3
AD		 2636/* vm parser */
2637static bool si_vm_reg_valid(u32 reg)
2638{
2639 /* context regs are fine */
2640 if (reg >= 0x28000)
2641 return true;
2642
2643 /* check config regs */
2644 switch (reg) {
2645 case GRBM_GFX_INDEX:
f418b88a 2646 case CP_STRMOUT_CNTL:
498dd8b3
AD		 2647 case VGT_VTX_VECT_EJECT_REG:
2648 case VGT_CACHE_INVALIDATION:
2649 case VGT_ESGS_RING_SIZE:
2650 case VGT_GSVS_RING_SIZE:
2651 case VGT_GS_VERTEX_REUSE:
2652 case VGT_PRIMITIVE_TYPE:
2653 case VGT_INDEX_TYPE:
2654 case VGT_NUM_INDICES:
2655 case VGT_NUM_INSTANCES:
2656 case VGT_TF_RING_SIZE:
2657 case VGT_HS_OFFCHIP_PARAM:
2658 case VGT_TF_MEMORY_BASE:
2659 case PA_CL_ENHANCE:
2660 case PA_SU_LINE_STIPPLE_VALUE:
2661 case PA_SC_LINE_STIPPLE_STATE:
2662 case PA_SC_ENHANCE:
2663 case SQC_CACHES:
2664 case SPI_STATIC_THREAD_MGMT_1:
2665 case SPI_STATIC_THREAD_MGMT_2:
2666 case SPI_STATIC_THREAD_MGMT_3:
2667 case SPI_PS_MAX_WAVE_ID:
2668 case SPI_CONFIG_CNTL:
2669 case SPI_CONFIG_CNTL_1:
2670 case TA_CNTL_AUX:
2671 return true;
2672 default:
2673 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2674 return false;
2675 }
2676}
2677
2678static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2679 u32 *ib, struct radeon_cs_packet *pkt)
2680{
2681 switch (pkt->opcode) {
2682 case PACKET3_NOP:
2683 case PACKET3_SET_BASE:
2684 case PACKET3_SET_CE_DE_COUNTERS:
2685 case PACKET3_LOAD_CONST_RAM:
2686 case PACKET3_WRITE_CONST_RAM:
2687 case PACKET3_WRITE_CONST_RAM_OFFSET:
2688 case PACKET3_DUMP_CONST_RAM:
2689 case PACKET3_INCREMENT_CE_COUNTER:
2690 case PACKET3_WAIT_ON_DE_COUNTER:
2691 case PACKET3_CE_WRITE:
2692 break;
2693 default:
2694 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2695 return -EINVAL;
2696 }
2697 return 0;
2698}
2699
2700static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2701 u32 *ib, struct radeon_cs_packet *pkt)
2702{
2703 u32 idx = pkt->idx + 1;
2704 u32 idx_value = ib[idx];
2705 u32 start_reg, end_reg, reg, i;
5aa709be 2706 u32 command, info;
498dd8b3
AD		 2707
2708 switch (pkt->opcode) {
2709 case PACKET3_NOP:
2710 case PACKET3_SET_BASE:
2711 case PACKET3_CLEAR_STATE:
2712 case PACKET3_INDEX_BUFFER_SIZE:
2713 case PACKET3_DISPATCH_DIRECT:
2714 case PACKET3_DISPATCH_INDIRECT:
2715 case PACKET3_ALLOC_GDS:
2716 case PACKET3_WRITE_GDS_RAM:
2717 case PACKET3_ATOMIC_GDS:
2718 case PACKET3_ATOMIC:
2719 case PACKET3_OCCLUSION_QUERY:
2720 case PACKET3_SET_PREDICATION:
2721 case PACKET3_COND_EXEC:
2722 case PACKET3_PRED_EXEC:
2723 case PACKET3_DRAW_INDIRECT:
2724 case PACKET3_DRAW_INDEX_INDIRECT:
2725 case PACKET3_INDEX_BASE:
2726 case PACKET3_DRAW_INDEX_2:
2727 case PACKET3_CONTEXT_CONTROL:
2728 case PACKET3_INDEX_TYPE:
2729 case PACKET3_DRAW_INDIRECT_MULTI:
2730 case PACKET3_DRAW_INDEX_AUTO:
2731 case PACKET3_DRAW_INDEX_IMMD:
2732 case PACKET3_NUM_INSTANCES:
2733 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2734 case PACKET3_STRMOUT_BUFFER_UPDATE:
2735 case PACKET3_DRAW_INDEX_OFFSET_2:
2736 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2737 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2738 case PACKET3_MPEG_INDEX:
2739 case PACKET3_WAIT_REG_MEM:
2740 case PACKET3_MEM_WRITE:
2741 case PACKET3_PFP_SYNC_ME:
2742 case PACKET3_SURFACE_SYNC:
2743 case PACKET3_EVENT_WRITE:
2744 case PACKET3_EVENT_WRITE_EOP:
2745 case PACKET3_EVENT_WRITE_EOS:
2746 case PACKET3_SET_CONTEXT_REG:
2747 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2748 case PACKET3_SET_SH_REG:
2749 case PACKET3_SET_SH_REG_OFFSET:
2750 case PACKET3_INCREMENT_DE_COUNTER:
2751 case PACKET3_WAIT_ON_CE_COUNTER:
2752 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2753 case PACKET3_ME_WRITE:
2754 break;
2755 case PACKET3_COPY_DATA:
2756 if ((idx_value & 0xf00) == 0) {
2757 reg = ib[idx + 3] * 4;
2758 if (!si_vm_reg_valid(reg))
2759 return -EINVAL;
2760 }
2761 break;
2762 case PACKET3_WRITE_DATA:
2763 if ((idx_value & 0xf00) == 0) {
2764 start_reg = ib[idx + 1] * 4;
2765 if (idx_value & 0x10000) {
2766 if (!si_vm_reg_valid(start_reg))
2767 return -EINVAL;
2768 } else {
2769 for (i = 0; i < (pkt->count - 2); i++) {
2770 reg = start_reg + (4 * i);
2771 if (!si_vm_reg_valid(reg))
2772 return -EINVAL;
2773 }
2774 }
2775 }
2776 break;
2777 case PACKET3_COND_WRITE:
2778 if (idx_value & 0x100) {
2779 reg = ib[idx + 5] * 4;
2780 if (!si_vm_reg_valid(reg))
2781 return -EINVAL;
2782 }
2783 break;
2784 case PACKET3_COPY_DW:
2785 if (idx_value & 0x2) {
2786 reg = ib[idx + 3] * 4;
2787 if (!si_vm_reg_valid(reg))
2788 return -EINVAL;
2789 }
2790 break;
2791 case PACKET3_SET_CONFIG_REG:
2792 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2793 end_reg = 4 * pkt->count + start_reg - 4;
2794 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2795 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2796 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2797 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2798 return -EINVAL;
2799 }
2800 for (i = 0; i < pkt->count; i++) {
2801 reg = start_reg + (4 * i);
2802 if (!si_vm_reg_valid(reg))
2803 return -EINVAL;
2804 }
2805 break;
5aa709be
AD		 2806 case PACKET3_CP_DMA:
2807 command = ib[idx + 4];
2808 info = ib[idx + 1];
2809 if (command & PACKET3_CP_DMA_CMD_SAS) {
2810 /* src address space is register */
2811 if (((info & 0x60000000) >> 29) == 0) {
2812 start_reg = idx_value << 2;
2813 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2814 reg = start_reg;
2815 if (!si_vm_reg_valid(reg)) {
2816 DRM_ERROR("CP DMA Bad SRC register\n");
2817 return -EINVAL;
2818 }
2819 } else {
2820 for (i = 0; i < (command & 0x1fffff); i++) {
2821 reg = start_reg + (4 * i);
2822 if (!si_vm_reg_valid(reg)) {
2823 DRM_ERROR("CP DMA Bad SRC register\n");
2824 return -EINVAL;
2825 }
2826 }
2827 }
2828 }
2829 }
2830 if (command & PACKET3_CP_DMA_CMD_DAS) {
2831 /* dst address space is register */
2832 if (((info & 0x00300000) >> 20) == 0) {
2833 start_reg = ib[idx + 2];
2834 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2835 reg = start_reg;
2836 if (!si_vm_reg_valid(reg)) {
2837 DRM_ERROR("CP DMA Bad DST register\n");
2838 return -EINVAL;
2839 }
2840 } else {
2841 for (i = 0; i < (command & 0x1fffff); i++) {
2842 reg = start_reg + (4 * i);
2843 if (!si_vm_reg_valid(reg)) {
2844 DRM_ERROR("CP DMA Bad DST register\n");
2845 return -EINVAL;
2846 }
2847 }
2848 }
2849 }
2850 }
2851 break;
498dd8b3
AD		 2852 default:
2853 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2854 return -EINVAL;
2855 }
2856 return 0;
2857}
2858
2859static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2860 u32 *ib, struct radeon_cs_packet *pkt)
2861{
2862 u32 idx = pkt->idx + 1;
2863 u32 idx_value = ib[idx];
2864 u32 start_reg, reg, i;
2865
2866 switch (pkt->opcode) {
2867 case PACKET3_NOP:
2868 case PACKET3_SET_BASE:
2869 case PACKET3_CLEAR_STATE:
2870 case PACKET3_DISPATCH_DIRECT:
2871 case PACKET3_DISPATCH_INDIRECT:
2872 case PACKET3_ALLOC_GDS:
2873 case PACKET3_WRITE_GDS_RAM:
2874 case PACKET3_ATOMIC_GDS:
2875 case PACKET3_ATOMIC:
2876 case PACKET3_OCCLUSION_QUERY:
2877 case PACKET3_SET_PREDICATION:
2878 case PACKET3_COND_EXEC:
2879 case PACKET3_PRED_EXEC:
2880 case PACKET3_CONTEXT_CONTROL:
2881 case PACKET3_STRMOUT_BUFFER_UPDATE:
2882 case PACKET3_WAIT_REG_MEM:
2883 case PACKET3_MEM_WRITE:
2884 case PACKET3_PFP_SYNC_ME:
2885 case PACKET3_SURFACE_SYNC:
2886 case PACKET3_EVENT_WRITE:
2887 case PACKET3_EVENT_WRITE_EOP:
2888 case PACKET3_EVENT_WRITE_EOS:
2889 case PACKET3_SET_CONTEXT_REG:
2890 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2891 case PACKET3_SET_SH_REG:
2892 case PACKET3_SET_SH_REG_OFFSET:
2893 case PACKET3_INCREMENT_DE_COUNTER:
2894 case PACKET3_WAIT_ON_CE_COUNTER:
2895 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2896 case PACKET3_ME_WRITE:
2897 break;
2898 case PACKET3_COPY_DATA:
2899 if ((idx_value & 0xf00) == 0) {
2900 reg = ib[idx + 3] * 4;
2901 if (!si_vm_reg_valid(reg))
2902 return -EINVAL;
2903 }
2904 break;
2905 case PACKET3_WRITE_DATA:
2906 if ((idx_value & 0xf00) == 0) {
2907 start_reg = ib[idx + 1] * 4;
2908 if (idx_value & 0x10000) {
2909 if (!si_vm_reg_valid(start_reg))
2910 return -EINVAL;
2911 } else {
2912 for (i = 0; i < (pkt->count - 2); i++) {
2913 reg = start_reg + (4 * i);
2914 if (!si_vm_reg_valid(reg))
2915 return -EINVAL;
2916 }
2917 }
2918 }
2919 break;
2920 case PACKET3_COND_WRITE:
2921 if (idx_value & 0x100) {
2922 reg = ib[idx + 5] * 4;
2923 if (!si_vm_reg_valid(reg))
2924 return -EINVAL;
2925 }
2926 break;
2927 case PACKET3_COPY_DW:
2928 if (idx_value & 0x2) {
2929 reg = ib[idx + 3] * 4;
2930 if (!si_vm_reg_valid(reg))
2931 return -EINVAL;
2932 }
2933 break;
2934 default:
2935 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2936 return -EINVAL;
2937 }
2938 return 0;
2939}
2940
2941int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2942{
2943 int ret = 0;
2944 u32 idx = 0;
2945 struct radeon_cs_packet pkt;
2946
2947 do {
2948 pkt.idx = idx;
4e872ae2
IH		 2949 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
2950 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
498dd8b3
AD		 2951 pkt.one_reg_wr = 0;
2952 switch (pkt.type) {
4e872ae2 2953 case RADEON_PACKET_TYPE0:
498dd8b3
AD		 2954 dev_err(rdev->dev, "Packet0 not allowed!\n");
2955 ret = -EINVAL;
2956 break;
4e872ae2 2957 case RADEON_PACKET_TYPE2:
498dd8b3
AD		 2958 idx += 1;
2959 break;
4e872ae2
IH		 2960 case RADEON_PACKET_TYPE3:
2961 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
498dd8b3
AD		 2962 if (ib->is_const_ib)
2963 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2964 else {
876dc9f3 2965 switch (ib->ring) {
498dd8b3
AD		 2966 case RADEON_RING_TYPE_GFX_INDEX:
2967 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2968 break;
2969 case CAYMAN_RING_TYPE_CP1_INDEX:
2970 case CAYMAN_RING_TYPE_CP2_INDEX:
2971 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2972 break;
2973 default:
876dc9f3 2974 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
498dd8b3
AD		 2975 ret = -EINVAL;
2976 break;
2977 }
2978 }
2979 idx += pkt.count + 2;
2980 break;
2981 default:
2982 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2983 ret = -EINVAL;
2984 break;
2985 }
2986 if (ret)
2987 break;
2988 } while (idx < ib->length_dw);
2989
2990 return ret;
2991}
2992
d2800ee5
AD		 2993/*
2994 * vm
2995 */
2996int si_vm_init(struct radeon_device *rdev)
2997{
2998 /* number of VMs */
2999 rdev->vm_manager.nvm = 16;
3000 /* base offset of vram pages */
3001 rdev->vm_manager.vram_base_offset = 0;
3002
3003 return 0;
3004}
3005
3006void si_vm_fini(struct radeon_device *rdev)
3007{
3008}
3009
82ffd92b
AD		 3010/**
3011 * si_vm_set_page - update the page tables using the CP
3012 *
3013 * @rdev: radeon_device pointer
3014 * @pe: addr of the page entry
3015 * @addr: dst addr to write into pe
3016 * @count: number of page entries to update
3017 * @incr: increase next addr by incr bytes
3018 * @flags: access flags
3019 *
3020 * Update the page tables using the CP (cayman-si).
3021 */
3022void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
3023 uint64_t addr, unsigned count,
3024 uint32_t incr, uint32_t flags)
d2800ee5 3025{
82ffd92b
AD		 3026 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
3027 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
deab48f1
AD		 3028 uint64_t value;
3029 unsigned ndw;
3030
3031 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
3032 while (count) {
3033 ndw = 2 + count * 2;
3034 if (ndw > 0x3FFE)
3035 ndw = 0x3FFE;
3036
3037 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
3038 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3039 WRITE_DATA_DST_SEL(1)));
3040 radeon_ring_write(ring, pe);
3041 radeon_ring_write(ring, upper_32_bits(pe));
3042 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3043 if (flags & RADEON_VM_PAGE_SYSTEM) {
3044 value = radeon_vm_map_gart(rdev, addr);
3045 value &= 0xFFFFFFFFFFFFF000ULL;
3046 } else if (flags & RADEON_VM_PAGE_VALID) {
3047 value = addr;
3048 } else {
3049 value = 0;
3050 }
3051 addr += incr;
3052 value |= r600_flags;
3053 radeon_ring_write(ring, value);
3054 radeon_ring_write(ring, upper_32_bits(value));
3055 }
3056 }
3057 } else {
3058 /* DMA */
3059 if (flags & RADEON_VM_PAGE_SYSTEM) {
3060 while (count) {
3061 ndw = count * 2;
3062 if (ndw > 0xFFFFE)
3063 ndw = 0xFFFFE;
3064
3065 /* for non-physically contiguous pages (system) */
3066 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw));
3067 radeon_ring_write(ring, pe);
3068 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
3069 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3070 if (flags & RADEON_VM_PAGE_SYSTEM) {
3071 value = radeon_vm_map_gart(rdev, addr);
3072 value &= 0xFFFFFFFFFFFFF000ULL;
3073 } else if (flags & RADEON_VM_PAGE_VALID) {
3074 value = addr;
3075 } else {
3076 value = 0;
3077 }
3078 addr += incr;
3079 value |= r600_flags;
3080 radeon_ring_write(ring, value);
3081 radeon_ring_write(ring, upper_32_bits(value));
3082 }
3083 }
3084 } else {
3085 while (count) {
3086 ndw = count * 2;
3087 if (ndw > 0xFFFFE)
3088 ndw = 0xFFFFE;
3089
3090 if (flags & RADEON_VM_PAGE_VALID)
3091 value = addr;
3092 else
3093 value = 0;
3094 /* for physically contiguous pages (vram) */
3095 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw));
3096 radeon_ring_write(ring, pe); /* dst addr */
3097 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
3098 radeon_ring_write(ring, r600_flags); /* mask */
3099 radeon_ring_write(ring, 0);
3100 radeon_ring_write(ring, value); /* value */
3101 radeon_ring_write(ring, upper_32_bits(value));
3102 radeon_ring_write(ring, incr); /* increment size */
3103 radeon_ring_write(ring, 0);
3104 pe += ndw * 4;
3105 addr += (ndw / 2) * incr;
3106 count -= ndw / 2;
3107 }
d7025d89 3108 }
82ffd92b 3109 }
d2800ee5
AD		 3110}
3111
498522b4 3112void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
d2800ee5 3113{
498522b4 3114 struct radeon_ring *ring = &rdev->ring[ridx];
d2800ee5 3115
ee60e29f 3116 if (vm == NULL)
d2800ee5
AD		 3117 return;
3118
76c44f2c
AD		 3119 /* write new base address */
3120 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3121 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3122 WRITE_DATA_DST_SEL(0)));
3123
ee60e29f 3124 if (vm->id < 8) {
76c44f2c
AD		 3125 radeon_ring_write(ring,
3126 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
ee60e29f 3127 } else {
76c44f2c
AD		 3128 radeon_ring_write(ring,
3129 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
ee60e29f 3130 }
76c44f2c 3131 radeon_ring_write(ring, 0);
fa87e62d 3132 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 3133
d2800ee5 3134 /* flush hdp cache */
76c44f2c
AD		 3135 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3136 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3137 WRITE_DATA_DST_SEL(0)));
3138 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3139 radeon_ring_write(ring, 0);
ee60e29f
CK		 3140 radeon_ring_write(ring, 0x1);
3141
d2800ee5 3142 /* bits 0-15 are the VM contexts0-15 */
76c44f2c
AD		 3143 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3144 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3145 WRITE_DATA_DST_SEL(0)));
3146 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3147 radeon_ring_write(ring, 0);
498522b4 3148 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 3149
3150 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3151 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3152 radeon_ring_write(ring, 0x0);
d2800ee5
AD		 3153}
3154
8c5fd7ef
AD		 3155void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3156{
3157 struct radeon_ring *ring = &rdev->ring[ridx];
3158
3159 if (vm == NULL)
3160 return;
3161
3162 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3163 if (vm->id < 8) {
3164 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3165 } else {
3166 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3167 }
3168 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3169
3170 /* flush hdp cache */
3171 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3172 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3173 radeon_ring_write(ring, 1);
3174
3175 /* bits 0-7 are the VM contexts0-7 */
3176 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3177 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3178 radeon_ring_write(ring, 1 << vm->id);
3179}
3180
347e7592
AD		 3181/*
3182 * RLC
3183 */
c420c745 3184void si_rlc_fini(struct radeon_device *rdev)
347e7592
AD		 3185{
3186 int r;
3187
3188 /* save restore block */
3189 if (rdev->rlc.save_restore_obj) {
3190 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3191 if (unlikely(r != 0))
3192 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3193 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3194 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3195
3196 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3197 rdev->rlc.save_restore_obj = NULL;
3198 }
3199
3200 /* clear state block */
3201 if (rdev->rlc.clear_state_obj) {
3202 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3203 if (unlikely(r != 0))
3204 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3205 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3206 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3207
3208 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3209 rdev->rlc.clear_state_obj = NULL;
3210 }
3211}
3212
c420c745 3213int si_rlc_init(struct radeon_device *rdev)
347e7592
AD		 3214{
3215 int r;
3216
3217 /* save restore block */
3218 if (rdev->rlc.save_restore_obj == NULL) {
3219 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3220 RADEON_GEM_DOMAIN_VRAM, NULL,
3221 &rdev->rlc.save_restore_obj);
347e7592
AD		 3222 if (r) {
3223 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3224 return r;
3225 }
3226 }
3227
3228 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3229 if (unlikely(r != 0)) {
3230 si_rlc_fini(rdev);
3231 return r;
3232 }
3233 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3234 &rdev->rlc.save_restore_gpu_addr);
5273db70 3235 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
347e7592 3236 if (r) {
347e7592
AD		 3237 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3238 si_rlc_fini(rdev);
3239 return r;
3240 }
3241
3242 /* clear state block */
3243 if (rdev->rlc.clear_state_obj == NULL) {
3244 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3245 RADEON_GEM_DOMAIN_VRAM, NULL,
3246 &rdev->rlc.clear_state_obj);
347e7592
AD		 3247 if (r) {
3248 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3249 si_rlc_fini(rdev);
3250 return r;
3251 }
3252 }
3253 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3254 if (unlikely(r != 0)) {
3255 si_rlc_fini(rdev);
3256 return r;
3257 }
3258 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3259 &rdev->rlc.clear_state_gpu_addr);
5273db70 3260 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
347e7592 3261 if (r) {
347e7592
AD		 3262 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3263 si_rlc_fini(rdev);
3264 return r;
3265 }
3266
3267 return 0;
3268}
3269
3270static void si_rlc_stop(struct radeon_device *rdev)
3271{
3272 WREG32(RLC_CNTL, 0);
3273}
3274
3275static void si_rlc_start(struct radeon_device *rdev)
3276{
3277 WREG32(RLC_CNTL, RLC_ENABLE);
3278}
3279
3280static int si_rlc_resume(struct radeon_device *rdev)
3281{
3282 u32 i;
3283 const __be32 *fw_data;
3284
3285 if (!rdev->rlc_fw)
3286 return -EINVAL;
3287
3288 si_rlc_stop(rdev);
3289
3290 WREG32(RLC_RL_BASE, 0);
3291 WREG32(RLC_RL_SIZE, 0);
3292 WREG32(RLC_LB_CNTL, 0);
3293 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3294 WREG32(RLC_LB_CNTR_INIT, 0);
3295
3296 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3297 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3298
3299 WREG32(RLC_MC_CNTL, 0);
3300 WREG32(RLC_UCODE_CNTL, 0);
3301
3302 fw_data = (const __be32 *)rdev->rlc_fw->data;
3303 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3304 WREG32(RLC_UCODE_ADDR, i);
3305 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3306 }
3307 WREG32(RLC_UCODE_ADDR, 0);
3308
3309 si_rlc_start(rdev);
3310
3311 return 0;
3312}
3313
25a857fb
AD		 3314static void si_enable_interrupts(struct radeon_device *rdev)
3315{
3316 u32 ih_cntl = RREG32(IH_CNTL);
3317 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3318
3319 ih_cntl |= ENABLE_INTR;
3320 ih_rb_cntl |= IH_RB_ENABLE;
3321 WREG32(IH_CNTL, ih_cntl);
3322 WREG32(IH_RB_CNTL, ih_rb_cntl);
3323 rdev->ih.enabled = true;
3324}
3325
3326static void si_disable_interrupts(struct radeon_device *rdev)
3327{
3328 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3329 u32 ih_cntl = RREG32(IH_CNTL);
3330
3331 ih_rb_cntl &= ~IH_RB_ENABLE;
3332 ih_cntl &= ~ENABLE_INTR;
3333 WREG32(IH_RB_CNTL, ih_rb_cntl);
3334 WREG32(IH_CNTL, ih_cntl);
3335 /* set rptr, wptr to 0 */
3336 WREG32(IH_RB_RPTR, 0);
3337 WREG32(IH_RB_WPTR, 0);
3338 rdev->ih.enabled = false;
25a857fb
AD		 3339 rdev->ih.rptr = 0;
3340}
3341
3342static void si_disable_interrupt_state(struct radeon_device *rdev)
3343{
3344 u32 tmp;
3345
3346 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3347 WREG32(CP_INT_CNTL_RING1, 0);
3348 WREG32(CP_INT_CNTL_RING2, 0);
8c5fd7ef
AD		 3349 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3350 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3351 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3352 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
25a857fb
AD		 3353 WREG32(GRBM_INT_CNTL, 0);
3354 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3355 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3356 if (rdev->num_crtc >= 4) {
3357 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3358 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3359 }
3360 if (rdev->num_crtc >= 6) {
3361 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3362 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3363 }
3364
3365 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3366 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3367 if (rdev->num_crtc >= 4) {
3368 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3369 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3370 }
3371 if (rdev->num_crtc >= 6) {
3372 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3373 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3374 }
3375
3376 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3377
3378 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3379 WREG32(DC_HPD1_INT_CONTROL, tmp);
3380 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3381 WREG32(DC_HPD2_INT_CONTROL, tmp);
3382 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3383 WREG32(DC_HPD3_INT_CONTROL, tmp);
3384 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3385 WREG32(DC_HPD4_INT_CONTROL, tmp);
3386 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3387 WREG32(DC_HPD5_INT_CONTROL, tmp);
3388 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3389 WREG32(DC_HPD6_INT_CONTROL, tmp);
3390
3391}
3392
3393static int si_irq_init(struct radeon_device *rdev)
3394{
3395 int ret = 0;
3396 int rb_bufsz;
3397 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3398
3399 /* allocate ring */
3400 ret = r600_ih_ring_alloc(rdev);
3401 if (ret)
3402 return ret;
3403
3404 /* disable irqs */
3405 si_disable_interrupts(rdev);
3406
3407 /* init rlc */
3408 ret = si_rlc_resume(rdev);
3409 if (ret) {
3410 r600_ih_ring_fini(rdev);
3411 return ret;
3412 }
3413
3414 /* setup interrupt control */
3415 /* set dummy read address to ring address */
3416 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3417 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3418 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3419 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3420 */
3421 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3422 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3423 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3424 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3425
3426 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3427 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3428
3429 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3430 IH_WPTR_OVERFLOW_CLEAR |
3431 (rb_bufsz << 1));
3432
3433 if (rdev->wb.enabled)
3434 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3435
3436 /* set the writeback address whether it's enabled or not */
3437 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3438 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3439
3440 WREG32(IH_RB_CNTL, ih_rb_cntl);
3441
3442 /* set rptr, wptr to 0 */
3443 WREG32(IH_RB_RPTR, 0);
3444 WREG32(IH_RB_WPTR, 0);
3445
3446 /* Default settings for IH_CNTL (disabled at first) */
3447 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3448 /* RPTR_REARM only works if msi's are enabled */
3449 if (rdev->msi_enabled)
3450 ih_cntl |= RPTR_REARM;
3451 WREG32(IH_CNTL, ih_cntl);
3452
3453 /* force the active interrupt state to all disabled */
3454 si_disable_interrupt_state(rdev);
3455
2099810f
DA		 3456 pci_set_master(rdev->pdev);
3457
25a857fb
AD		 3458 /* enable irqs */
3459 si_enable_interrupts(rdev);
3460
3461 return ret;
3462}
3463
3464int si_irq_set(struct radeon_device *rdev)
3465{
3466 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3467 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3468 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3469 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3470 u32 grbm_int_cntl = 0;
3471 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
8c5fd7ef 3472 u32 dma_cntl, dma_cntl1;
25a857fb
AD		 3473
3474 if (!rdev->irq.installed) {
3475 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3476 return -EINVAL;
3477 }
3478 /* don't enable anything if the ih is disabled */
3479 if (!rdev->ih.enabled) {
3480 si_disable_interrupts(rdev);
3481 /* force the active interrupt state to all disabled */
3482 si_disable_interrupt_state(rdev);
3483 return 0;
3484 }
3485
3486 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3487 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3488 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3489 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3490 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3491 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3492
8c5fd7ef
AD		 3493 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3494 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3495
25a857fb 3496 /* enable CP interrupts on all rings */
736fc37f 3497 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
25a857fb
AD		 3498 DRM_DEBUG("si_irq_set: sw int gfx\n");
3499 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3500 }
736fc37f 3501 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
25a857fb
AD		 3502 DRM_DEBUG("si_irq_set: sw int cp1\n");
3503 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3504 }
736fc37f 3505 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
25a857fb
AD		 3506 DRM_DEBUG("si_irq_set: sw int cp2\n");
3507 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3508 }
8c5fd7ef
AD		 3509 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3510 DRM_DEBUG("si_irq_set: sw int dma\n");
3511 dma_cntl |= TRAP_ENABLE;
3512 }
3513
3514 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3515 DRM_DEBUG("si_irq_set: sw int dma1\n");
3516 dma_cntl1 |= TRAP_ENABLE;
3517 }
25a857fb 3518 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3519 atomic_read(&rdev->irq.pflip[0])) {
25a857fb
AD		 3520 DRM_DEBUG("si_irq_set: vblank 0\n");
3521 crtc1 |= VBLANK_INT_MASK;
3522 }
3523 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3524 atomic_read(&rdev->irq.pflip[1])) {
25a857fb
AD		 3525 DRM_DEBUG("si_irq_set: vblank 1\n");
3526 crtc2 |= VBLANK_INT_MASK;
3527 }
3528 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3529 atomic_read(&rdev->irq.pflip[2])) {
25a857fb
AD		 3530 DRM_DEBUG("si_irq_set: vblank 2\n");
3531 crtc3 |= VBLANK_INT_MASK;
3532 }
3533 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3534 atomic_read(&rdev->irq.pflip[3])) {
25a857fb
AD		 3535 DRM_DEBUG("si_irq_set: vblank 3\n");
3536 crtc4 |= VBLANK_INT_MASK;
3537 }
3538 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3539 atomic_read(&rdev->irq.pflip[4])) {
25a857fb
AD		 3540 DRM_DEBUG("si_irq_set: vblank 4\n");
3541 crtc5 |= VBLANK_INT_MASK;
3542 }
3543 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3544 atomic_read(&rdev->irq.pflip[5])) {
25a857fb
AD		 3545 DRM_DEBUG("si_irq_set: vblank 5\n");
3546 crtc6 |= VBLANK_INT_MASK;
3547 }
3548 if (rdev->irq.hpd[0]) {
3549 DRM_DEBUG("si_irq_set: hpd 1\n");
3550 hpd1 |= DC_HPDx_INT_EN;
3551 }
3552 if (rdev->irq.hpd[1]) {
3553 DRM_DEBUG("si_irq_set: hpd 2\n");
3554 hpd2 |= DC_HPDx_INT_EN;
3555 }
3556 if (rdev->irq.hpd[2]) {
3557 DRM_DEBUG("si_irq_set: hpd 3\n");
3558 hpd3 |= DC_HPDx_INT_EN;
3559 }
3560 if (rdev->irq.hpd[3]) {
3561 DRM_DEBUG("si_irq_set: hpd 4\n");
3562 hpd4 |= DC_HPDx_INT_EN;
3563 }
3564 if (rdev->irq.hpd[4]) {
3565 DRM_DEBUG("si_irq_set: hpd 5\n");
3566 hpd5 |= DC_HPDx_INT_EN;
3567 }
3568 if (rdev->irq.hpd[5]) {
3569 DRM_DEBUG("si_irq_set: hpd 6\n");
3570 hpd6 |= DC_HPDx_INT_EN;
3571 }
25a857fb
AD		 3572
3573 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3574 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3575 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3576
8c5fd7ef
AD		 3577 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3578 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3579
25a857fb
AD		 3580 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3581
3582 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3583 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3584 if (rdev->num_crtc >= 4) {
3585 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3586 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3587 }
3588 if (rdev->num_crtc >= 6) {
3589 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3590 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3591 }
3592
3593 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3595 if (rdev->num_crtc >= 4) {
3596 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3597 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3598 }
3599 if (rdev->num_crtc >= 6) {
3600 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3601 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3602 }
3603
3604 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3605 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3606 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3607 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3608 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3609 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3610
3611 return 0;
3612}
3613
3614static inline void si_irq_ack(struct radeon_device *rdev)
3615{
3616 u32 tmp;
3617
3618 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3619 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3620 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3621 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3622 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3623 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3624 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3625 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3626 if (rdev->num_crtc >= 4) {
3627 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3628 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3629 }
3630 if (rdev->num_crtc >= 6) {
3631 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3632 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3633 }
3634
3635 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3636 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3637 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3638 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3639 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3640 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3641 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3642 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3643 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3644 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3645 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3646 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3647
3648 if (rdev->num_crtc >= 4) {
3649 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3650 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3651 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3652 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3653 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3654 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3655 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3656 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3657 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3658 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3659 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3660 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3661 }
3662
3663 if (rdev->num_crtc >= 6) {
3664 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3665 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3666 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3667 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3668 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3669 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3670 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3671 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3672 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3673 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3674 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3675 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3676 }
3677
3678 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3679 tmp = RREG32(DC_HPD1_INT_CONTROL);
3680 tmp |= DC_HPDx_INT_ACK;
3681 WREG32(DC_HPD1_INT_CONTROL, tmp);
3682 }
3683 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3684 tmp = RREG32(DC_HPD2_INT_CONTROL);
3685 tmp |= DC_HPDx_INT_ACK;
3686 WREG32(DC_HPD2_INT_CONTROL, tmp);
3687 }
3688 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3689 tmp = RREG32(DC_HPD3_INT_CONTROL);
3690 tmp |= DC_HPDx_INT_ACK;
3691 WREG32(DC_HPD3_INT_CONTROL, tmp);
3692 }
3693 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3694 tmp = RREG32(DC_HPD4_INT_CONTROL);
3695 tmp |= DC_HPDx_INT_ACK;
3696 WREG32(DC_HPD4_INT_CONTROL, tmp);
3697 }
3698 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3699 tmp = RREG32(DC_HPD5_INT_CONTROL);
3700 tmp |= DC_HPDx_INT_ACK;
3701 WREG32(DC_HPD5_INT_CONTROL, tmp);
3702 }
3703 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3704 tmp = RREG32(DC_HPD5_INT_CONTROL);
3705 tmp |= DC_HPDx_INT_ACK;
3706 WREG32(DC_HPD6_INT_CONTROL, tmp);
3707 }
3708}
3709
3710static void si_irq_disable(struct radeon_device *rdev)
3711{
3712 si_disable_interrupts(rdev);
3713 /* Wait and acknowledge irq */
3714 mdelay(1);
3715 si_irq_ack(rdev);
3716 si_disable_interrupt_state(rdev);
3717}
3718
3719static void si_irq_suspend(struct radeon_device *rdev)
3720{
3721 si_irq_disable(rdev);
3722 si_rlc_stop(rdev);
3723}
3724
9b136d51
AD		 3725static void si_irq_fini(struct radeon_device *rdev)
3726{
3727 si_irq_suspend(rdev);
3728 r600_ih_ring_fini(rdev);
3729}
3730
25a857fb
AD		 3731static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3732{
3733 u32 wptr, tmp;
3734
3735 if (rdev->wb.enabled)
3736 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3737 else
3738 wptr = RREG32(IH_RB_WPTR);
3739
3740 if (wptr & RB_OVERFLOW) {
3741 /* When a ring buffer overflow happen start parsing interrupt
3742 * from the last not overwritten vector (wptr + 16). Hopefully
3743 * this should allow us to catchup.
3744 */
3745 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3746 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3747 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3748 tmp = RREG32(IH_RB_CNTL);
3749 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3750 WREG32(IH_RB_CNTL, tmp);
3751 }
3752 return (wptr & rdev->ih.ptr_mask);
3753}
3754
3755/* SI IV Ring
3756 * Each IV ring entry is 128 bits:
3757 * [7:0] - interrupt source id
3758 * [31:8] - reserved
3759 * [59:32] - interrupt source data
3760 * [63:60] - reserved
3761 * [71:64] - RINGID
3762 * [79:72] - VMID
3763 * [127:80] - reserved
3764 */
3765int si_irq_process(struct radeon_device *rdev)
3766{
3767 u32 wptr;
3768 u32 rptr;
3769 u32 src_id, src_data, ring_id;
3770 u32 ring_index;
25a857fb
AD		 3771 bool queue_hotplug = false;
3772
3773 if (!rdev->ih.enabled || rdev->shutdown)
3774 return IRQ_NONE;
3775
3776 wptr = si_get_ih_wptr(rdev);
c20dc369
CK		 3777
3778restart_ih:
3779 /* is somebody else already processing irqs? */
3780 if (atomic_xchg(&rdev->ih.lock, 1))
3781 return IRQ_NONE;
3782
25a857fb
AD		 3783 rptr = rdev->ih.rptr;
3784 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3785
25a857fb
AD		 3786 /* Order reading of wptr vs. reading of IH ring data */
3787 rmb();
3788
3789 /* display interrupts */
3790 si_irq_ack(rdev);
3791
25a857fb
AD		 3792 while (rptr != wptr) {
3793 /* wptr/rptr are in bytes! */
3794 ring_index = rptr / 4;
3795 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3796 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3797 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3798
3799 switch (src_id) {
3800 case 1: /* D1 vblank/vline */
3801 switch (src_data) {
3802 case 0: /* D1 vblank */
3803 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3804 if (rdev->irq.crtc_vblank_int[0]) {
3805 drm_handle_vblank(rdev->ddev, 0);
3806 rdev->pm.vblank_sync = true;
3807 wake_up(&rdev->irq.vblank_queue);
3808 }
736fc37f 3809 if (atomic_read(&rdev->irq.pflip[0]))
25a857fb
AD		 3810 radeon_crtc_handle_flip(rdev, 0);
3811 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3812 DRM_DEBUG("IH: D1 vblank\n");
3813 }
3814 break;
3815 case 1: /* D1 vline */
3816 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3817 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3818 DRM_DEBUG("IH: D1 vline\n");
3819 }
3820 break;
3821 default:
3822 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3823 break;
3824 }
3825 break;
3826 case 2: /* D2 vblank/vline */
3827 switch (src_data) {
3828 case 0: /* D2 vblank */
3829 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3830 if (rdev->irq.crtc_vblank_int[1]) {
3831 drm_handle_vblank(rdev->ddev, 1);
3832 rdev->pm.vblank_sync = true;
3833 wake_up(&rdev->irq.vblank_queue);
3834 }
736fc37f 3835 if (atomic_read(&rdev->irq.pflip[1]))
25a857fb
AD		 3836 radeon_crtc_handle_flip(rdev, 1);
3837 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3838 DRM_DEBUG("IH: D2 vblank\n");
3839 }
3840 break;
3841 case 1: /* D2 vline */
3842 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3843 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3844 DRM_DEBUG("IH: D2 vline\n");
3845 }
3846 break;
3847 default:
3848 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3849 break;
3850 }
3851 break;
3852 case 3: /* D3 vblank/vline */
3853 switch (src_data) {
3854 case 0: /* D3 vblank */
3855 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3856 if (rdev->irq.crtc_vblank_int[2]) {
3857 drm_handle_vblank(rdev->ddev, 2);
3858 rdev->pm.vblank_sync = true;
3859 wake_up(&rdev->irq.vblank_queue);
3860 }
736fc37f 3861 if (atomic_read(&rdev->irq.pflip[2]))
25a857fb
AD		 3862 radeon_crtc_handle_flip(rdev, 2);
3863 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3864 DRM_DEBUG("IH: D3 vblank\n");
3865 }
3866 break;
3867 case 1: /* D3 vline */
3868 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3869 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3870 DRM_DEBUG("IH: D3 vline\n");
3871 }
3872 break;
3873 default:
3874 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3875 break;
3876 }
3877 break;
3878 case 4: /* D4 vblank/vline */
3879 switch (src_data) {
3880 case 0: /* D4 vblank */
3881 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3882 if (rdev->irq.crtc_vblank_int[3]) {
3883 drm_handle_vblank(rdev->ddev, 3);
3884 rdev->pm.vblank_sync = true;
3885 wake_up(&rdev->irq.vblank_queue);
3886 }
736fc37f 3887 if (atomic_read(&rdev->irq.pflip[3]))
25a857fb
AD		 3888 radeon_crtc_handle_flip(rdev, 3);
3889 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3890 DRM_DEBUG("IH: D4 vblank\n");
3891 }
3892 break;
3893 case 1: /* D4 vline */
3894 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3895 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3896 DRM_DEBUG("IH: D4 vline\n");
3897 }
3898 break;
3899 default:
3900 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3901 break;
3902 }
3903 break;
3904 case 5: /* D5 vblank/vline */
3905 switch (src_data) {
3906 case 0: /* D5 vblank */
3907 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3908 if (rdev->irq.crtc_vblank_int[4]) {
3909 drm_handle_vblank(rdev->ddev, 4);
3910 rdev->pm.vblank_sync = true;
3911 wake_up(&rdev->irq.vblank_queue);
3912 }
736fc37f 3913 if (atomic_read(&rdev->irq.pflip[4]))
25a857fb
AD		 3914 radeon_crtc_handle_flip(rdev, 4);
3915 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3916 DRM_DEBUG("IH: D5 vblank\n");
3917 }
3918 break;
3919 case 1: /* D5 vline */
3920 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3921 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3922 DRM_DEBUG("IH: D5 vline\n");
3923 }
3924 break;
3925 default:
3926 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3927 break;
3928 }
3929 break;
3930 case 6: /* D6 vblank/vline */
3931 switch (src_data) {
3932 case 0: /* D6 vblank */
3933 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3934 if (rdev->irq.crtc_vblank_int[5]) {
3935 drm_handle_vblank(rdev->ddev, 5);
3936 rdev->pm.vblank_sync = true;
3937 wake_up(&rdev->irq.vblank_queue);
3938 }
736fc37f 3939 if (atomic_read(&rdev->irq.pflip[5]))
25a857fb
AD		 3940 radeon_crtc_handle_flip(rdev, 5);
3941 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3942 DRM_DEBUG("IH: D6 vblank\n");
3943 }
3944 break;
3945 case 1: /* D6 vline */
3946 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3947 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3948 DRM_DEBUG("IH: D6 vline\n");
3949 }
3950 break;
3951 default:
3952 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3953 break;
3954 }
3955 break;
3956 case 42: /* HPD hotplug */
3957 switch (src_data) {
3958 case 0:
3959 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3960 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3961 queue_hotplug = true;
3962 DRM_DEBUG("IH: HPD1\n");
3963 }
3964 break;
3965 case 1:
3966 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3967 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3968 queue_hotplug = true;
3969 DRM_DEBUG("IH: HPD2\n");
3970 }
3971 break;
3972 case 2:
3973 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3974 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3975 queue_hotplug = true;
3976 DRM_DEBUG("IH: HPD3\n");
3977 }
3978 break;
3979 case 3:
3980 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3981 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3982 queue_hotplug = true;
3983 DRM_DEBUG("IH: HPD4\n");
3984 }
3985 break;
3986 case 4:
3987 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3988 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3989 queue_hotplug = true;
3990 DRM_DEBUG("IH: HPD5\n");
3991 }
3992 break;
3993 case 5:
3994 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3995 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3996 queue_hotplug = true;
3997 DRM_DEBUG("IH: HPD6\n");
3998 }
3999 break;
4000 default:
4001 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4002 break;
4003 }
4004 break;
ae133a11
CK		 4005 case 146:
4006 case 147:
4007 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4008 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4009 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4010 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4011 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4012 /* reset addr and status */
4013 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4014 break;
25a857fb
AD		 4015 case 176: /* RINGID0 CP_INT */
4016 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4017 break;
4018 case 177: /* RINGID1 CP_INT */
4019 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4020 break;
4021 case 178: /* RINGID2 CP_INT */
4022 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4023 break;
4024 case 181: /* CP EOP event */
4025 DRM_DEBUG("IH: CP EOP\n");
4026 switch (ring_id) {
4027 case 0:
4028 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4029 break;
4030 case 1:
4031 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4032 break;
4033 case 2:
4034 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4035 break;
4036 }
4037 break;
8c5fd7ef
AD		 4038 case 224: /* DMA trap event */
4039 DRM_DEBUG("IH: DMA trap\n");
4040 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4041 break;
25a857fb
AD		 4042 case 233: /* GUI IDLE */
4043 DRM_DEBUG("IH: GUI idle\n");
25a857fb 4044 break;
8c5fd7ef
AD		 4045 case 244: /* DMA trap event */
4046 DRM_DEBUG("IH: DMA1 trap\n");
4047 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4048 break;
25a857fb
AD		 4049 default:
4050 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4051 break;
4052 }
4053
4054 /* wptr/rptr are in bytes! */
4055 rptr += 16;
4056 rptr &= rdev->ih.ptr_mask;
4057 }
25a857fb
AD		 4058 if (queue_hotplug)
4059 schedule_work(&rdev->hotplug_work);
4060 rdev->ih.rptr = rptr;
4061 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4062 atomic_set(&rdev->ih.lock, 0);
4063
4064 /* make sure wptr hasn't changed while processing */
4065 wptr = si_get_ih_wptr(rdev);
4066 if (wptr != rptr)
4067 goto restart_ih;
4068
25a857fb
AD		 4069 return IRQ_HANDLED;
4070}
4071
8c5fd7ef
AD		 4072/**
4073 * si_copy_dma - copy pages using the DMA engine
4074 *
4075 * @rdev: radeon_device pointer
4076 * @src_offset: src GPU address
4077 * @dst_offset: dst GPU address
4078 * @num_gpu_pages: number of GPU pages to xfer
4079 * @fence: radeon fence object
4080 *
4081 * Copy GPU paging using the DMA engine (SI).
4082 * Used by the radeon ttm implementation to move pages if
4083 * registered as the asic copy callback.
4084 */
4085int si_copy_dma(struct radeon_device *rdev,
4086 uint64_t src_offset, uint64_t dst_offset,
4087 unsigned num_gpu_pages,
4088 struct radeon_fence **fence)
4089{
4090 struct radeon_semaphore *sem = NULL;
4091 int ring_index = rdev->asic->copy.dma_ring_index;
4092 struct radeon_ring *ring = &rdev->ring[ring_index];
4093 u32 size_in_bytes, cur_size_in_bytes;
4094 int i, num_loops;
4095 int r = 0;
4096
4097 r = radeon_semaphore_create(rdev, &sem);
4098 if (r) {
4099 DRM_ERROR("radeon: moving bo (%d).\n", r);
4100 return r;
4101 }
4102
4103 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4104 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4105 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4106 if (r) {
4107 DRM_ERROR("radeon: moving bo (%d).\n", r);
4108 radeon_semaphore_free(rdev, &sem, NULL);
4109 return r;
4110 }
4111
4112 if (radeon_fence_need_sync(*fence, ring->idx)) {
4113 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4114 ring->idx);
4115 radeon_fence_note_sync(*fence, ring->idx);
4116 } else {
4117 radeon_semaphore_free(rdev, &sem, NULL);
4118 }
4119
4120 for (i = 0; i < num_loops; i++) {
4121 cur_size_in_bytes = size_in_bytes;
4122 if (cur_size_in_bytes > 0xFFFFF)
4123 cur_size_in_bytes = 0xFFFFF;
4124 size_in_bytes -= cur_size_in_bytes;
4125 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4126 radeon_ring_write(ring, dst_offset & 0xffffffff);
4127 radeon_ring_write(ring, src_offset & 0xffffffff);
4128 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4129 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4130 src_offset += cur_size_in_bytes;
4131 dst_offset += cur_size_in_bytes;
4132 }
4133
4134 r = radeon_fence_emit(rdev, fence, ring->idx);
4135 if (r) {
4136 radeon_ring_unlock_undo(rdev, ring);
4137 return r;
4138 }
4139
4140 radeon_ring_unlock_commit(rdev, ring);
4141 radeon_semaphore_free(rdev, &sem, *fence);
4142
4143 return r;
4144}
4145
9b136d51
AD		 4146/*
4147 * startup/shutdown callbacks
4148 */
4149static int si_startup(struct radeon_device *rdev)
4150{
4151 struct radeon_ring *ring;
4152 int r;
4153
4154 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4155 !rdev->rlc_fw || !rdev->mc_fw) {
4156 r = si_init_microcode(rdev);
4157 if (r) {
4158 DRM_ERROR("Failed to load firmware!\n");
4159 return r;
4160 }
4161 }
4162
4163 r = si_mc_load_microcode(rdev);
4164 if (r) {
4165 DRM_ERROR("Failed to load MC firmware!\n");
4166 return r;
4167 }
4168
4169 r = r600_vram_scratch_init(rdev);
4170 if (r)
4171 return r;
4172
4173 si_mc_program(rdev);
4174 r = si_pcie_gart_enable(rdev);
4175 if (r)
4176 return r;
4177 si_gpu_init(rdev);
4178
4179#if 0
4180 r = evergreen_blit_init(rdev);
4181 if (r) {
4182 r600_blit_fini(rdev);
4183 rdev->asic->copy = NULL;
4184 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4185 }
4186#endif
4187 /* allocate rlc buffers */
4188 r = si_rlc_init(rdev);
4189 if (r) {
4190 DRM_ERROR("Failed to init rlc BOs!\n");
4191 return r;
4192 }
4193
4194 /* allocate wb buffer */
4195 r = radeon_wb_init(rdev);
4196 if (r)
4197 return r;
4198
4199 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4200 if (r) {
4201 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4202 return r;
4203 }
4204
4205 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4206 if (r) {
4207 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4208 return r;
4209 }
4210
4211 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4212 if (r) {
4213 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4214 return r;
4215 }
4216
8c5fd7ef
AD		 4217 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4218 if (r) {
4219 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4220 return r;
4221 }
4222
4223 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4224 if (r) {
4225 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4226 return r;
4227 }
4228
9b136d51
AD		 4229 /* Enable IRQ */
4230 r = si_irq_init(rdev);
4231 if (r) {
4232 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4233 radeon_irq_kms_fini(rdev);
4234 return r;
4235 }
4236 si_irq_set(rdev);
4237
4238 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4239 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4240 CP_RB0_RPTR, CP_RB0_WPTR,
4241 0, 0xfffff, RADEON_CP_PACKET2);
4242 if (r)
4243 return r;
4244
4245 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4246 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4247 CP_RB1_RPTR, CP_RB1_WPTR,
4248 0, 0xfffff, RADEON_CP_PACKET2);
4249 if (r)
4250 return r;
4251
4252 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4253 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4254 CP_RB2_RPTR, CP_RB2_WPTR,
4255 0, 0xfffff, RADEON_CP_PACKET2);
4256 if (r)
4257 return r;
4258
8c5fd7ef
AD		 4259 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4260 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4261 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4262 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4263 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4264 if (r)
4265 return r;
4266
4267 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4268 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4269 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4270 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4271 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4272 if (r)
4273 return r;
4274
9b136d51
AD		 4275 r = si_cp_load_microcode(rdev);
4276 if (r)
4277 return r;
4278 r = si_cp_resume(rdev);
4279 if (r)
4280 return r;
4281
8c5fd7ef
AD		 4282 r = cayman_dma_resume(rdev);
4283 if (r)
4284 return r;
4285
2898c348
CK		 4286 r = radeon_ib_pool_init(rdev);
4287 if (r) {
4288 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
9b136d51 4289 return r;
2898c348 4290 }
9b136d51 4291
c6105f24
CK		 4292 r = radeon_vm_manager_init(rdev);
4293 if (r) {
4294 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
9b136d51 4295 return r;
c6105f24 4296 }
9b136d51
AD		 4297
4298 return 0;
4299}
4300
4301int si_resume(struct radeon_device *rdev)
4302{
4303 int r;
4304
4305 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4306 * posting will perform necessary task to bring back GPU into good
4307 * shape.
4308 */
4309 /* post card */
4310 atom_asic_init(rdev->mode_info.atom_context);
4311
4312 rdev->accel_working = true;
4313 r = si_startup(rdev);
4314 if (r) {
4315 DRM_ERROR("si startup failed on resume\n");
4316 rdev->accel_working = false;
4317 return r;
4318 }
4319
4320 return r;
4321
4322}
4323
4324int si_suspend(struct radeon_device *rdev)
4325{
9b136d51 4326 si_cp_enable(rdev, false);
8c5fd7ef 4327 cayman_dma_stop(rdev);
9b136d51
AD		 4328 si_irq_suspend(rdev);
4329 radeon_wb_disable(rdev);
4330 si_pcie_gart_disable(rdev);
4331 return 0;
4332}
4333
4334/* Plan is to move initialization in that function and use
4335 * helper function so that radeon_device_init pretty much
4336 * do nothing more than calling asic specific function. This
4337 * should also allow to remove a bunch of callback function
4338 * like vram_info.
4339 */
4340int si_init(struct radeon_device *rdev)
4341{
4342 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4343 int r;
4344
9b136d51
AD		 4345 /* Read BIOS */
4346 if (!radeon_get_bios(rdev)) {
4347 if (ASIC_IS_AVIVO(rdev))
4348 return -EINVAL;
4349 }
4350 /* Must be an ATOMBIOS */
4351 if (!rdev->is_atom_bios) {
4352 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4353 return -EINVAL;
4354 }
4355 r = radeon_atombios_init(rdev);
4356 if (r)
4357 return r;
4358
4359 /* Post card if necessary */
4360 if (!radeon_card_posted(rdev)) {
4361 if (!rdev->bios) {
4362 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4363 return -EINVAL;
4364 }
4365 DRM_INFO("GPU not posted. posting now...\n");
4366 atom_asic_init(rdev->mode_info.atom_context);
4367 }
4368 /* Initialize scratch registers */
4369 si_scratch_init(rdev);
4370 /* Initialize surface registers */
4371 radeon_surface_init(rdev);
4372 /* Initialize clocks */
4373 radeon_get_clock_info(rdev->ddev);
4374
4375 /* Fence driver */
4376 r = radeon_fence_driver_init(rdev);
4377 if (r)
4378 return r;
4379
4380 /* initialize memory controller */
4381 r = si_mc_init(rdev);
4382 if (r)
4383 return r;
4384 /* Memory manager */
4385 r = radeon_bo_init(rdev);
4386 if (r)
4387 return r;
4388
4389 r = radeon_irq_kms_init(rdev);
4390 if (r)
4391 return r;
4392
4393 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4394 ring->ring_obj = NULL;
4395 r600_ring_init(rdev, ring, 1024 * 1024);
4396
4397 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4398 ring->ring_obj = NULL;
4399 r600_ring_init(rdev, ring, 1024 * 1024);
4400
4401 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4402 ring->ring_obj = NULL;
4403 r600_ring_init(rdev, ring, 1024 * 1024);
4404
8c5fd7ef
AD		 4405 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4406 ring->ring_obj = NULL;
4407 r600_ring_init(rdev, ring, 64 * 1024);
4408
4409 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4410 ring->ring_obj = NULL;
4411 r600_ring_init(rdev, ring, 64 * 1024);
4412
9b136d51
AD		 4413 rdev->ih.ring_obj = NULL;
4414 r600_ih_ring_init(rdev, 64 * 1024);
4415
4416 r = r600_pcie_gart_init(rdev);
4417 if (r)
4418 return r;
4419
9b136d51 4420 rdev->accel_working = true;
9b136d51
AD		 4421 r = si_startup(rdev);
4422 if (r) {
4423 dev_err(rdev->dev, "disabling GPU acceleration\n");
4424 si_cp_fini(rdev);
8c5fd7ef 4425 cayman_dma_fini(rdev);
9b136d51
AD		 4426 si_irq_fini(rdev);
4427 si_rlc_fini(rdev);
4428 radeon_wb_fini(rdev);
2898c348 4429 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4430 radeon_vm_manager_fini(rdev);
4431 radeon_irq_kms_fini(rdev);
4432 si_pcie_gart_fini(rdev);
4433 rdev->accel_working = false;
4434 }
4435
4436 /* Don't start up if the MC ucode is missing.
4437 * The default clocks and voltages before the MC ucode
4438 * is loaded are not suffient for advanced operations.
4439 */
4440 if (!rdev->mc_fw) {
4441 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4442 return -EINVAL;
4443 }
4444
4445 return 0;
4446}
4447
4448void si_fini(struct radeon_device *rdev)
4449{
4450#if 0
4451 r600_blit_fini(rdev);
4452#endif
4453 si_cp_fini(rdev);
8c5fd7ef 4454 cayman_dma_fini(rdev);
9b136d51
AD		 4455 si_irq_fini(rdev);
4456 si_rlc_fini(rdev);
4457 radeon_wb_fini(rdev);
4458 radeon_vm_manager_fini(rdev);
2898c348 4459 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4460 radeon_irq_kms_fini(rdev);
4461 si_pcie_gart_fini(rdev);
4462 r600_vram_scratch_fini(rdev);
4463 radeon_gem_fini(rdev);
9b136d51
AD		 4464 radeon_fence_driver_fini(rdev);
4465 radeon_bo_fini(rdev);
4466 radeon_atombios_fini(rdev);
4467 kfree(rdev->bios);
4468 rdev->bios = NULL;
4469}
4470
6759a0a7
MO		 4471/**
4472 * si_get_gpu_clock - return GPU clock counter snapshot
4473 *
4474 * @rdev: radeon_device pointer
4475 *
4476 * Fetches a GPU clock counter snapshot (SI).
4477 * Returns the 64 bit clock counter snapshot.
4478 */
4479uint64_t si_get_gpu_clock(struct radeon_device *rdev)
4480{
4481 uint64_t clock;
4482
4483 mutex_lock(&rdev->gpu_clock_mutex);
4484 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4485 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4486 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4487 mutex_unlock(&rdev->gpu_clock_mutex);
4488 return clock;
4489}
Linux 6.x block layer and io_uring tree(s)