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drm/radeon: add set_uvd_clocks callback for evergreen
[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c
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43b3cd99
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
0f0de06c
AD		 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
43b3cd99
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
43b3cd99
AD		 32#include "sid.h"
33#include "atom.h"
48c0c902 34#include "si_blit_shaders.h"
43b3cd99 35
0f0de06c
AD		 36#define SI_PFP_UCODE_SIZE 2144
37#define SI_PM4_UCODE_SIZE 2144
38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769
bcc7f5d2 41#define OLAND_MC_UCODE_SIZE 7863
0f0de06c
AD		 42
43MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
44MODULE_FIRMWARE("radeon/TAHITI_me.bin");
45MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
46MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
47MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
52MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
53MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
54MODULE_FIRMWARE("radeon/VERDE_me.bin");
55MODULE_FIRMWARE("radeon/VERDE_ce.bin");
56MODULE_FIRMWARE("radeon/VERDE_mc.bin");
57MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
bcc7f5d2
AD		 58MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
59MODULE_FIRMWARE("radeon/OLAND_me.bin");
60MODULE_FIRMWARE("radeon/OLAND_ce.bin");
61MODULE_FIRMWARE("radeon/OLAND_mc.bin");
62MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
0f0de06c 63
25a857fb
AD		 64extern int r600_ih_ring_alloc(struct radeon_device *rdev);
65extern void r600_ih_ring_fini(struct radeon_device *rdev);
0a96d72b 66extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
c476dde2
AD		 67extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
68extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
ca7db22b 69extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
1c534671 70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
014bb209 71extern bool evergreen_is_display_hung(struct radeon_device *rdev);
0a96d72b 72
454d2e2a
AD		 73#define PCIE_BUS_CLK 10000
74#define TCLK (PCIE_BUS_CLK / 10)
75
76/**
77 * si_get_xclk - get the xclk
78 *
79 * @rdev: radeon_device pointer
80 *
81 * Returns the reference clock used by the gfx engine
82 * (SI).
83 */
84u32 si_get_xclk(struct radeon_device *rdev)
85{
86 u32 reference_clock = rdev->clock.spll.reference_freq;
87 u32 tmp;
88
89 tmp = RREG32(CG_CLKPIN_CNTL_2);
90 if (tmp & MUX_TCLK_TO_XCLK)
91 return TCLK;
92
93 tmp = RREG32(CG_CLKPIN_CNTL);
94 if (tmp & XTALIN_DIVIDE)
95 return reference_clock / 4;
96
97 return reference_clock;
98}
99
1bd47d2e
AD		 100/* get temperature in millidegrees */
101int si_get_temp(struct radeon_device *rdev)
102{
103 u32 temp;
104 int actual_temp = 0;
105
106 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
107 CTF_TEMP_SHIFT;
108
109 if (temp & 0x200)
110 actual_temp = 255;
111 else
112 actual_temp = temp & 0x1ff;
113
114 actual_temp = (actual_temp * 1000);
115
116 return actual_temp;
117}
118
8b074dd6
AD		 119#define TAHITI_IO_MC_REGS_SIZE 36
120
121static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
122 {0x0000006f, 0x03044000},
123 {0x00000070, 0x0480c018},
124 {0x00000071, 0x00000040},
125 {0x00000072, 0x01000000},
126 {0x00000074, 0x000000ff},
127 {0x00000075, 0x00143400},
128 {0x00000076, 0x08ec0800},
129 {0x00000077, 0x040000cc},
130 {0x00000079, 0x00000000},
131 {0x0000007a, 0x21000409},
132 {0x0000007c, 0x00000000},
133 {0x0000007d, 0xe8000000},
134 {0x0000007e, 0x044408a8},
135 {0x0000007f, 0x00000003},
136 {0x00000080, 0x00000000},
137 {0x00000081, 0x01000000},
138 {0x00000082, 0x02000000},
139 {0x00000083, 0x00000000},
140 {0x00000084, 0xe3f3e4f4},
141 {0x00000085, 0x00052024},
142 {0x00000087, 0x00000000},
143 {0x00000088, 0x66036603},
144 {0x00000089, 0x01000000},
145 {0x0000008b, 0x1c0a0000},
146 {0x0000008c, 0xff010000},
147 {0x0000008e, 0xffffefff},
148 {0x0000008f, 0xfff3efff},
149 {0x00000090, 0xfff3efbf},
150 {0x00000094, 0x00101101},
151 {0x00000095, 0x00000fff},
152 {0x00000096, 0x00116fff},
153 {0x00000097, 0x60010000},
154 {0x00000098, 0x10010000},
155 {0x00000099, 0x00006000},
156 {0x0000009a, 0x00001000},
157 {0x0000009f, 0x00a77400}
158};
159
160static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
161 {0x0000006f, 0x03044000},
162 {0x00000070, 0x0480c018},
163 {0x00000071, 0x00000040},
164 {0x00000072, 0x01000000},
165 {0x00000074, 0x000000ff},
166 {0x00000075, 0x00143400},
167 {0x00000076, 0x08ec0800},
168 {0x00000077, 0x040000cc},
169 {0x00000079, 0x00000000},
170 {0x0000007a, 0x21000409},
171 {0x0000007c, 0x00000000},
172 {0x0000007d, 0xe8000000},
173 {0x0000007e, 0x044408a8},
174 {0x0000007f, 0x00000003},
175 {0x00000080, 0x00000000},
176 {0x00000081, 0x01000000},
177 {0x00000082, 0x02000000},
178 {0x00000083, 0x00000000},
179 {0x00000084, 0xe3f3e4f4},
180 {0x00000085, 0x00052024},
181 {0x00000087, 0x00000000},
182 {0x00000088, 0x66036603},
183 {0x00000089, 0x01000000},
184 {0x0000008b, 0x1c0a0000},
185 {0x0000008c, 0xff010000},
186 {0x0000008e, 0xffffefff},
187 {0x0000008f, 0xfff3efff},
188 {0x00000090, 0xfff3efbf},
189 {0x00000094, 0x00101101},
190 {0x00000095, 0x00000fff},
191 {0x00000096, 0x00116fff},
192 {0x00000097, 0x60010000},
193 {0x00000098, 0x10010000},
194 {0x00000099, 0x00006000},
195 {0x0000009a, 0x00001000},
196 {0x0000009f, 0x00a47400}
197};
198
199static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
200 {0x0000006f, 0x03044000},
201 {0x00000070, 0x0480c018},
202 {0x00000071, 0x00000040},
203 {0x00000072, 0x01000000},
204 {0x00000074, 0x000000ff},
205 {0x00000075, 0x00143400},
206 {0x00000076, 0x08ec0800},
207 {0x00000077, 0x040000cc},
208 {0x00000079, 0x00000000},
209 {0x0000007a, 0x21000409},
210 {0x0000007c, 0x00000000},
211 {0x0000007d, 0xe8000000},
212 {0x0000007e, 0x044408a8},
213 {0x0000007f, 0x00000003},
214 {0x00000080, 0x00000000},
215 {0x00000081, 0x01000000},
216 {0x00000082, 0x02000000},
217 {0x00000083, 0x00000000},
218 {0x00000084, 0xe3f3e4f4},
219 {0x00000085, 0x00052024},
220 {0x00000087, 0x00000000},
221 {0x00000088, 0x66036603},
222 {0x00000089, 0x01000000},
223 {0x0000008b, 0x1c0a0000},
224 {0x0000008c, 0xff010000},
225 {0x0000008e, 0xffffefff},
226 {0x0000008f, 0xfff3efff},
227 {0x00000090, 0xfff3efbf},
228 {0x00000094, 0x00101101},
229 {0x00000095, 0x00000fff},
230 {0x00000096, 0x00116fff},
231 {0x00000097, 0x60010000},
232 {0x00000098, 0x10010000},
233 {0x00000099, 0x00006000},
234 {0x0000009a, 0x00001000},
235 {0x0000009f, 0x00a37400}
236};
237
bcc7f5d2
AD		 238static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
239 {0x0000006f, 0x03044000},
240 {0x00000070, 0x0480c018},
241 {0x00000071, 0x00000040},
242 {0x00000072, 0x01000000},
243 {0x00000074, 0x000000ff},
244 {0x00000075, 0x00143400},
245 {0x00000076, 0x08ec0800},
246 {0x00000077, 0x040000cc},
247 {0x00000079, 0x00000000},
248 {0x0000007a, 0x21000409},
249 {0x0000007c, 0x00000000},
250 {0x0000007d, 0xe8000000},
251 {0x0000007e, 0x044408a8},
252 {0x0000007f, 0x00000003},
253 {0x00000080, 0x00000000},
254 {0x00000081, 0x01000000},
255 {0x00000082, 0x02000000},
256 {0x00000083, 0x00000000},
257 {0x00000084, 0xe3f3e4f4},
258 {0x00000085, 0x00052024},
259 {0x00000087, 0x00000000},
260 {0x00000088, 0x66036603},
261 {0x00000089, 0x01000000},
262 {0x0000008b, 0x1c0a0000},
263 {0x0000008c, 0xff010000},
264 {0x0000008e, 0xffffefff},
265 {0x0000008f, 0xfff3efff},
266 {0x00000090, 0xfff3efbf},
267 {0x00000094, 0x00101101},
268 {0x00000095, 0x00000fff},
269 {0x00000096, 0x00116fff},
270 {0x00000097, 0x60010000},
271 {0x00000098, 0x10010000},
272 {0x00000099, 0x00006000},
273 {0x0000009a, 0x00001000},
274 {0x0000009f, 0x00a17730}
275};
276
8b074dd6
AD		 277/* ucode loading */
278static int si_mc_load_microcode(struct radeon_device *rdev)
279{
280 const __be32 *fw_data;
281 u32 running, blackout = 0;
282 u32 *io_mc_regs;
283 int i, ucode_size, regs_size;
284
285 if (!rdev->mc_fw)
286 return -EINVAL;
287
288 switch (rdev->family) {
289 case CHIP_TAHITI:
290 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
291 ucode_size = SI_MC_UCODE_SIZE;
292 regs_size = TAHITI_IO_MC_REGS_SIZE;
293 break;
294 case CHIP_PITCAIRN:
295 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
296 ucode_size = SI_MC_UCODE_SIZE;
297 regs_size = TAHITI_IO_MC_REGS_SIZE;
298 break;
299 case CHIP_VERDE:
300 default:
301 io_mc_regs = (u32 *)&verde_io_mc_regs;
302 ucode_size = SI_MC_UCODE_SIZE;
303 regs_size = TAHITI_IO_MC_REGS_SIZE;
304 break;
bcc7f5d2
AD		 305 case CHIP_OLAND:
306 io_mc_regs = (u32 *)&oland_io_mc_regs;
307 ucode_size = OLAND_MC_UCODE_SIZE;
308 regs_size = TAHITI_IO_MC_REGS_SIZE;
309 break;
8b074dd6
AD		 310 }
311
312 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
313
314 if (running == 0) {
315 if (running) {
316 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
317 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
318 }
319
320 /* reset the engine and set to writable */
321 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
322 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
323
324 /* load mc io regs */
325 for (i = 0; i < regs_size; i++) {
326 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
327 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
328 }
329 /* load the MC ucode */
330 fw_data = (const __be32 *)rdev->mc_fw->data;
331 for (i = 0; i < ucode_size; i++)
332 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
333
334 /* put the engine back into the active state */
335 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
336 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
337 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
338
339 /* wait for training to complete */
340 for (i = 0; i < rdev->usec_timeout; i++) {
341 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
342 break;
343 udelay(1);
344 }
345 for (i = 0; i < rdev->usec_timeout; i++) {
346 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
347 break;
348 udelay(1);
349 }
350
351 if (running)
352 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
353 }
354
355 return 0;
356}
357
0f0de06c
AD		 358static int si_init_microcode(struct radeon_device *rdev)
359{
360 struct platform_device *pdev;
361 const char *chip_name;
362 const char *rlc_chip_name;
363 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
364 char fw_name[30];
365 int err;
366
367 DRM_DEBUG("\n");
368
369 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
370 err = IS_ERR(pdev);
371 if (err) {
372 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
373 return -EINVAL;
374 }
375
376 switch (rdev->family) {
377 case CHIP_TAHITI:
378 chip_name = "TAHITI";
379 rlc_chip_name = "TAHITI";
380 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
381 me_req_size = SI_PM4_UCODE_SIZE * 4;
382 ce_req_size = SI_CE_UCODE_SIZE * 4;
383 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
384 mc_req_size = SI_MC_UCODE_SIZE * 4;
385 break;
386 case CHIP_PITCAIRN:
387 chip_name = "PITCAIRN";
388 rlc_chip_name = "PITCAIRN";
389 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
390 me_req_size = SI_PM4_UCODE_SIZE * 4;
391 ce_req_size = SI_CE_UCODE_SIZE * 4;
392 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
393 mc_req_size = SI_MC_UCODE_SIZE * 4;
394 break;
395 case CHIP_VERDE:
396 chip_name = "VERDE";
397 rlc_chip_name = "VERDE";
398 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
399 me_req_size = SI_PM4_UCODE_SIZE * 4;
400 ce_req_size = SI_CE_UCODE_SIZE * 4;
401 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
402 mc_req_size = SI_MC_UCODE_SIZE * 4;
403 break;
bcc7f5d2
AD		 404 case CHIP_OLAND:
405 chip_name = "OLAND";
406 rlc_chip_name = "OLAND";
407 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
408 me_req_size = SI_PM4_UCODE_SIZE * 4;
409 ce_req_size = SI_CE_UCODE_SIZE * 4;
410 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
411 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
412 break;
0f0de06c
AD		 413 default: BUG();
414 }
415
416 DRM_INFO("Loading %s Microcode\n", chip_name);
417
418 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
419 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
420 if (err)
421 goto out;
422 if (rdev->pfp_fw->size != pfp_req_size) {
423 printk(KERN_ERR
424 "si_cp: Bogus length %zu in firmware \"%s\"\n",
425 rdev->pfp_fw->size, fw_name);
426 err = -EINVAL;
427 goto out;
428 }
429
430 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
431 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
432 if (err)
433 goto out;
434 if (rdev->me_fw->size != me_req_size) {
435 printk(KERN_ERR
436 "si_cp: Bogus length %zu in firmware \"%s\"\n",
437 rdev->me_fw->size, fw_name);
438 err = -EINVAL;
439 }
440
441 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
442 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
443 if (err)
444 goto out;
445 if (rdev->ce_fw->size != ce_req_size) {
446 printk(KERN_ERR
447 "si_cp: Bogus length %zu in firmware \"%s\"\n",
448 rdev->ce_fw->size, fw_name);
449 err = -EINVAL;
450 }
451
452 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
453 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
454 if (err)
455 goto out;
456 if (rdev->rlc_fw->size != rlc_req_size) {
457 printk(KERN_ERR
458 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
459 rdev->rlc_fw->size, fw_name);
460 err = -EINVAL;
461 }
462
463 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
464 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
465 if (err)
466 goto out;
467 if (rdev->mc_fw->size != mc_req_size) {
468 printk(KERN_ERR
469 "si_mc: Bogus length %zu in firmware \"%s\"\n",
470 rdev->mc_fw->size, fw_name);
471 err = -EINVAL;
472 }
473
474out:
475 platform_device_unregister(pdev);
476
477 if (err) {
478 if (err != -EINVAL)
479 printk(KERN_ERR
480 "si_cp: Failed to load firmware \"%s\"\n",
481 fw_name);
482 release_firmware(rdev->pfp_fw);
483 rdev->pfp_fw = NULL;
484 release_firmware(rdev->me_fw);
485 rdev->me_fw = NULL;
486 release_firmware(rdev->ce_fw);
487 rdev->ce_fw = NULL;
488 release_firmware(rdev->rlc_fw);
489 rdev->rlc_fw = NULL;
490 release_firmware(rdev->mc_fw);
491 rdev->mc_fw = NULL;
492 }
493 return err;
494}
495
43b3cd99
AD		 496/* watermark setup */
497static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
498 struct radeon_crtc *radeon_crtc,
499 struct drm_display_mode *mode,
500 struct drm_display_mode *other_mode)
501{
502 u32 tmp;
503 /*
504 * Line Buffer Setup
505 * There are 3 line buffers, each one shared by 2 display controllers.
506 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
507 * the display controllers. The paritioning is done via one of four
508 * preset allocations specified in bits 21:20:
509 * 0 - half lb
510 * 2 - whole lb, other crtc must be disabled
511 */
512 /* this can get tricky if we have two large displays on a paired group
513 * of crtcs. Ideally for multiple large displays we'd assign them to
514 * non-linked crtcs for maximum line buffer allocation.
515 */
516 if (radeon_crtc->base.enabled && mode) {
517 if (other_mode)
518 tmp = 0; /* 1/2 */
519 else
520 tmp = 2; /* whole */
521 } else
522 tmp = 0;
523
524 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
525 DC_LB_MEMORY_CONFIG(tmp));
526
527 if (radeon_crtc->base.enabled && mode) {
528 switch (tmp) {
529 case 0:
530 default:
531 return 4096 * 2;
532 case 2:
533 return 8192 * 2;
534 }
535 }
536
537 /* controller not enabled, so no lb used */
538 return 0;
539}
540
ca7db22b 541static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
43b3cd99
AD		 542{
543 u32 tmp = RREG32(MC_SHARED_CHMAP);
544
545 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
546 case 0:
547 default:
548 return 1;
549 case 1:
550 return 2;
551 case 2:
552 return 4;
553 case 3:
554 return 8;
555 case 4:
556 return 3;
557 case 5:
558 return 6;
559 case 6:
560 return 10;
561 case 7:
562 return 12;
563 case 8:
564 return 16;
565 }
566}
567
568struct dce6_wm_params {
569 u32 dram_channels; /* number of dram channels */
570 u32 yclk; /* bandwidth per dram data pin in kHz */
571 u32 sclk; /* engine clock in kHz */
572 u32 disp_clk; /* display clock in kHz */
573 u32 src_width; /* viewport width */
574 u32 active_time; /* active display time in ns */
575 u32 blank_time; /* blank time in ns */
576 bool interlaced; /* mode is interlaced */
577 fixed20_12 vsc; /* vertical scale ratio */
578 u32 num_heads; /* number of active crtcs */
579 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
580 u32 lb_size; /* line buffer allocated to pipe */
581 u32 vtaps; /* vertical scaler taps */
582};
583
584static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
585{
586 /* Calculate raw DRAM Bandwidth */
587 fixed20_12 dram_efficiency; /* 0.7 */
588 fixed20_12 yclk, dram_channels, bandwidth;
589 fixed20_12 a;
590
591 a.full = dfixed_const(1000);
592 yclk.full = dfixed_const(wm->yclk);
593 yclk.full = dfixed_div(yclk, a);
594 dram_channels.full = dfixed_const(wm->dram_channels * 4);
595 a.full = dfixed_const(10);
596 dram_efficiency.full = dfixed_const(7);
597 dram_efficiency.full = dfixed_div(dram_efficiency, a);
598 bandwidth.full = dfixed_mul(dram_channels, yclk);
599 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
600
601 return dfixed_trunc(bandwidth);
602}
603
604static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
605{
606 /* Calculate DRAM Bandwidth and the part allocated to display. */
607 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
608 fixed20_12 yclk, dram_channels, bandwidth;
609 fixed20_12 a;
610
611 a.full = dfixed_const(1000);
612 yclk.full = dfixed_const(wm->yclk);
613 yclk.full = dfixed_div(yclk, a);
614 dram_channels.full = dfixed_const(wm->dram_channels * 4);
615 a.full = dfixed_const(10);
616 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
617 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
618 bandwidth.full = dfixed_mul(dram_channels, yclk);
619 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
620
621 return dfixed_trunc(bandwidth);
622}
623
624static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
625{
626 /* Calculate the display Data return Bandwidth */
627 fixed20_12 return_efficiency; /* 0.8 */
628 fixed20_12 sclk, bandwidth;
629 fixed20_12 a;
630
631 a.full = dfixed_const(1000);
632 sclk.full = dfixed_const(wm->sclk);
633 sclk.full = dfixed_div(sclk, a);
634 a.full = dfixed_const(10);
635 return_efficiency.full = dfixed_const(8);
636 return_efficiency.full = dfixed_div(return_efficiency, a);
637 a.full = dfixed_const(32);
638 bandwidth.full = dfixed_mul(a, sclk);
639 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
640
641 return dfixed_trunc(bandwidth);
642}
643
644static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
645{
646 return 32;
647}
648
649static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
650{
651 /* Calculate the DMIF Request Bandwidth */
652 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
653 fixed20_12 disp_clk, sclk, bandwidth;
654 fixed20_12 a, b1, b2;
655 u32 min_bandwidth;
656
657 a.full = dfixed_const(1000);
658 disp_clk.full = dfixed_const(wm->disp_clk);
659 disp_clk.full = dfixed_div(disp_clk, a);
660 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
661 b1.full = dfixed_mul(a, disp_clk);
662
663 a.full = dfixed_const(1000);
664 sclk.full = dfixed_const(wm->sclk);
665 sclk.full = dfixed_div(sclk, a);
666 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
667 b2.full = dfixed_mul(a, sclk);
668
669 a.full = dfixed_const(10);
670 disp_clk_request_efficiency.full = dfixed_const(8);
671 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
672
673 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
674
675 a.full = dfixed_const(min_bandwidth);
676 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
677
678 return dfixed_trunc(bandwidth);
679}
680
681static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
682{
683 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
684 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
685 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
686 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
687
688 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
689}
690
691static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
692{
693 /* Calculate the display mode Average Bandwidth
694 * DisplayMode should contain the source and destination dimensions,
695 * timing, etc.
696 */
697 fixed20_12 bpp;
698 fixed20_12 line_time;
699 fixed20_12 src_width;
700 fixed20_12 bandwidth;
701 fixed20_12 a;
702
703 a.full = dfixed_const(1000);
704 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
705 line_time.full = dfixed_div(line_time, a);
706 bpp.full = dfixed_const(wm->bytes_per_pixel);
707 src_width.full = dfixed_const(wm->src_width);
708 bandwidth.full = dfixed_mul(src_width, bpp);
709 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
710 bandwidth.full = dfixed_div(bandwidth, line_time);
711
712 return dfixed_trunc(bandwidth);
713}
714
715static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
716{
717 /* First calcualte the latency in ns */
718 u32 mc_latency = 2000; /* 2000 ns. */
719 u32 available_bandwidth = dce6_available_bandwidth(wm);
720 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
721 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
722 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
723 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
724 (wm->num_heads * cursor_line_pair_return_time);
725 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
726 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
727 u32 tmp, dmif_size = 12288;
728 fixed20_12 a, b, c;
729
730 if (wm->num_heads == 0)
731 return 0;
732
733 a.full = dfixed_const(2);
734 b.full = dfixed_const(1);
735 if ((wm->vsc.full > a.full) ||
736 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
737 (wm->vtaps >= 5) ||
738 ((wm->vsc.full >= a.full) && wm->interlaced))
739 max_src_lines_per_dst_line = 4;
740 else
741 max_src_lines_per_dst_line = 2;
742
743 a.full = dfixed_const(available_bandwidth);
744 b.full = dfixed_const(wm->num_heads);
745 a.full = dfixed_div(a, b);
746
747 b.full = dfixed_const(mc_latency + 512);
748 c.full = dfixed_const(wm->disp_clk);
749 b.full = dfixed_div(b, c);
750
751 c.full = dfixed_const(dmif_size);
752 b.full = dfixed_div(c, b);
753
754 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
755
756 b.full = dfixed_const(1000);
757 c.full = dfixed_const(wm->disp_clk);
758 b.full = dfixed_div(c, b);
759 c.full = dfixed_const(wm->bytes_per_pixel);
760 b.full = dfixed_mul(b, c);
761
762 lb_fill_bw = min(tmp, dfixed_trunc(b));
763
764 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
765 b.full = dfixed_const(1000);
766 c.full = dfixed_const(lb_fill_bw);
767 b.full = dfixed_div(c, b);
768 a.full = dfixed_div(a, b);
769 line_fill_time = dfixed_trunc(a);
770
771 if (line_fill_time < wm->active_time)
772 return latency;
773 else
774 return latency + (line_fill_time - wm->active_time);
775
776}
777
778static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
779{
780 if (dce6_average_bandwidth(wm) <=
781 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
782 return true;
783 else
784 return false;
785};
786
787static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
788{
789 if (dce6_average_bandwidth(wm) <=
790 (dce6_available_bandwidth(wm) / wm->num_heads))
791 return true;
792 else
793 return false;
794};
795
796static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
797{
798 u32 lb_partitions = wm->lb_size / wm->src_width;
799 u32 line_time = wm->active_time + wm->blank_time;
800 u32 latency_tolerant_lines;
801 u32 latency_hiding;
802 fixed20_12 a;
803
804 a.full = dfixed_const(1);
805 if (wm->vsc.full > a.full)
806 latency_tolerant_lines = 1;
807 else {
808 if (lb_partitions <= (wm->vtaps + 1))
809 latency_tolerant_lines = 1;
810 else
811 latency_tolerant_lines = 2;
812 }
813
814 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
815
816 if (dce6_latency_watermark(wm) <= latency_hiding)
817 return true;
818 else
819 return false;
820}
821
822static void dce6_program_watermarks(struct radeon_device *rdev,
823 struct radeon_crtc *radeon_crtc,
824 u32 lb_size, u32 num_heads)
825{
826 struct drm_display_mode *mode = &radeon_crtc->base.mode;
827 struct dce6_wm_params wm;
828 u32 pixel_period;
829 u32 line_time = 0;
830 u32 latency_watermark_a = 0, latency_watermark_b = 0;
831 u32 priority_a_mark = 0, priority_b_mark = 0;
832 u32 priority_a_cnt = PRIORITY_OFF;
833 u32 priority_b_cnt = PRIORITY_OFF;
834 u32 tmp, arb_control3;
835 fixed20_12 a, b, c;
836
837 if (radeon_crtc->base.enabled && num_heads && mode) {
838 pixel_period = 1000000 / (u32)mode->clock;
839 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
840 priority_a_cnt = 0;
841 priority_b_cnt = 0;
842
843 wm.yclk = rdev->pm.current_mclk * 10;
844 wm.sclk = rdev->pm.current_sclk * 10;
845 wm.disp_clk = mode->clock;
846 wm.src_width = mode->crtc_hdisplay;
847 wm.active_time = mode->crtc_hdisplay * pixel_period;
848 wm.blank_time = line_time - wm.active_time;
849 wm.interlaced = false;
850 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
851 wm.interlaced = true;
852 wm.vsc = radeon_crtc->vsc;
853 wm.vtaps = 1;
854 if (radeon_crtc->rmx_type != RMX_OFF)
855 wm.vtaps = 2;
856 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
857 wm.lb_size = lb_size;
ca7db22b
AD		 858 if (rdev->family == CHIP_ARUBA)
859 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
860 else
861 wm.dram_channels = si_get_number_of_dram_channels(rdev);
43b3cd99
AD		 862 wm.num_heads = num_heads;
863
864 /* set for high clocks */
865 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
866 /* set for low clocks */
867 /* wm.yclk = low clk; wm.sclk = low clk */
868 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
869
870 /* possibly force display priority to high */
871 /* should really do this at mode validation time... */
872 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
873 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
874 !dce6_check_latency_hiding(&wm) ||
875 (rdev->disp_priority == 2)) {
876 DRM_DEBUG_KMS("force priority to high\n");
877 priority_a_cnt |= PRIORITY_ALWAYS_ON;
878 priority_b_cnt |= PRIORITY_ALWAYS_ON;
879 }
880
881 a.full = dfixed_const(1000);
882 b.full = dfixed_const(mode->clock);
883 b.full = dfixed_div(b, a);
884 c.full = dfixed_const(latency_watermark_a);
885 c.full = dfixed_mul(c, b);
886 c.full = dfixed_mul(c, radeon_crtc->hsc);
887 c.full = dfixed_div(c, a);
888 a.full = dfixed_const(16);
889 c.full = dfixed_div(c, a);
890 priority_a_mark = dfixed_trunc(c);
891 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
892
893 a.full = dfixed_const(1000);
894 b.full = dfixed_const(mode->clock);
895 b.full = dfixed_div(b, a);
896 c.full = dfixed_const(latency_watermark_b);
897 c.full = dfixed_mul(c, b);
898 c.full = dfixed_mul(c, radeon_crtc->hsc);
899 c.full = dfixed_div(c, a);
900 a.full = dfixed_const(16);
901 c.full = dfixed_div(c, a);
902 priority_b_mark = dfixed_trunc(c);
903 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
904 }
905
906 /* select wm A */
907 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
908 tmp = arb_control3;
909 tmp &= ~LATENCY_WATERMARK_MASK(3);
910 tmp |= LATENCY_WATERMARK_MASK(1);
911 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
912 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
913 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
914 LATENCY_HIGH_WATERMARK(line_time)));
915 /* select wm B */
916 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
917 tmp &= ~LATENCY_WATERMARK_MASK(3);
918 tmp |= LATENCY_WATERMARK_MASK(2);
919 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
920 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
921 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
922 LATENCY_HIGH_WATERMARK(line_time)));
923 /* restore original selection */
924 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
925
926 /* write the priority marks */
927 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
928 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
929
930}
931
932void dce6_bandwidth_update(struct radeon_device *rdev)
933{
934 struct drm_display_mode *mode0 = NULL;
935 struct drm_display_mode *mode1 = NULL;
936 u32 num_heads = 0, lb_size;
937 int i;
938
939 radeon_update_display_priority(rdev);
940
941 for (i = 0; i < rdev->num_crtc; i++) {
942 if (rdev->mode_info.crtcs[i]->base.enabled)
943 num_heads++;
944 }
945 for (i = 0; i < rdev->num_crtc; i += 2) {
946 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
947 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
948 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
949 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
950 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
951 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
952 }
953}
954
0a96d72b
AD		 955/*
956 * Core functions
957 */
0a96d72b
AD		 958static void si_tiling_mode_table_init(struct radeon_device *rdev)
959{
960 const u32 num_tile_mode_states = 32;
961 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
962
963 switch (rdev->config.si.mem_row_size_in_kb) {
964 case 1:
965 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
966 break;
967 case 2:
968 default:
969 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
970 break;
971 case 4:
972 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
973 break;
974 }
975
976 if ((rdev->family == CHIP_TAHITI) ||
977 (rdev->family == CHIP_PITCAIRN)) {
978 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
979 switch (reg_offset) {
980 case 0: /* non-AA compressed depth or any compressed stencil */
981 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
982 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
983 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
984 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
985 NUM_BANKS(ADDR_SURF_16_BANK) |
986 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
987 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
988 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
989 break;
990 case 1: /* 2xAA/4xAA compressed depth only */
991 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
992 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
993 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
994 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
995 NUM_BANKS(ADDR_SURF_16_BANK) |
996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
999 break;
1000 case 2: /* 8xAA compressed depth only */
1001 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1003 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1005 NUM_BANKS(ADDR_SURF_16_BANK) |
1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1009 break;
1010 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1011 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1012 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1013 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1014 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1015 NUM_BANKS(ADDR_SURF_16_BANK) |
1016 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1017 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1018 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1019 break;
1020 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1021 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1022 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1023 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1025 NUM_BANKS(ADDR_SURF_16_BANK) |
1026 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1027 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1028 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1029 break;
1030 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1031 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1033 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1034 TILE_SPLIT(split_equal_to_row_size) |
1035 NUM_BANKS(ADDR_SURF_16_BANK) |
1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1039 break;
1040 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1041 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1043 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1044 TILE_SPLIT(split_equal_to_row_size) |
1045 NUM_BANKS(ADDR_SURF_16_BANK) |
1046 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1049 break;
1050 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1051 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1052 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1054 TILE_SPLIT(split_equal_to_row_size) |
1055 NUM_BANKS(ADDR_SURF_16_BANK) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1059 break;
1060 case 8: /* 1D and 1D Array Surfaces */
1061 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1062 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1063 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1065 NUM_BANKS(ADDR_SURF_16_BANK) |
1066 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1069 break;
1070 case 9: /* Displayable maps. */
1071 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1072 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1074 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1075 NUM_BANKS(ADDR_SURF_16_BANK) |
1076 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1077 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1078 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1079 break;
1080 case 10: /* Display 8bpp. */
1081 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1082 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1084 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1085 NUM_BANKS(ADDR_SURF_16_BANK) |
1086 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1089 break;
1090 case 11: /* Display 16bpp. */
1091 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1092 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1095 NUM_BANKS(ADDR_SURF_16_BANK) |
1096 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1097 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1098 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1099 break;
1100 case 12: /* Display 32bpp. */
1101 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1102 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1105 NUM_BANKS(ADDR_SURF_16_BANK) |
1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1109 break;
1110 case 13: /* Thin. */
1111 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1112 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1113 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1115 NUM_BANKS(ADDR_SURF_16_BANK) |
1116 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1117 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1118 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1119 break;
1120 case 14: /* Thin 8 bpp. */
1121 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1122 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1125 NUM_BANKS(ADDR_SURF_16_BANK) |
1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1129 break;
1130 case 15: /* Thin 16 bpp. */
1131 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1135 NUM_BANKS(ADDR_SURF_16_BANK) |
1136 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1139 break;
1140 case 16: /* Thin 32 bpp. */
1141 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1142 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1145 NUM_BANKS(ADDR_SURF_16_BANK) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1149 break;
1150 case 17: /* Thin 64 bpp. */
1151 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1154 TILE_SPLIT(split_equal_to_row_size) |
1155 NUM_BANKS(ADDR_SURF_16_BANK) |
1156 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1159 break;
1160 case 21: /* 8 bpp PRT. */
1161 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1162 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1164 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1165 NUM_BANKS(ADDR_SURF_16_BANK) |
1166 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1169 break;
1170 case 22: /* 16 bpp PRT */
1171 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1172 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1173 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1174 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1175 NUM_BANKS(ADDR_SURF_16_BANK) |
1176 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1179 break;
1180 case 23: /* 32 bpp PRT */
1181 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1182 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1183 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1184 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1185 NUM_BANKS(ADDR_SURF_16_BANK) |
1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1189 break;
1190 case 24: /* 64 bpp PRT */
1191 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1192 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1195 NUM_BANKS(ADDR_SURF_16_BANK) |
1196 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1199 break;
1200 case 25: /* 128 bpp PRT */
1201 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1205 NUM_BANKS(ADDR_SURF_8_BANK) |
1206 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1209 break;
1210 default:
1211 gb_tile_moden = 0;
1212 break;
1213 }
1214 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1215 }
d0ae7fcc
AD		 1216 } else if ((rdev->family == CHIP_VERDE) ||
1217 (rdev->family == CHIP_OLAND)) {
0a96d72b
AD		 1218 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1219 switch (reg_offset) {
1220 case 0: /* non-AA compressed depth or any compressed stencil */
1221 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1222 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1223 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1224 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1225 NUM_BANKS(ADDR_SURF_16_BANK) |
1226 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1227 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1228 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1229 break;
1230 case 1: /* 2xAA/4xAA compressed depth only */
1231 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1233 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1235 NUM_BANKS(ADDR_SURF_16_BANK) |
1236 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1239 break;
1240 case 2: /* 8xAA compressed depth only */
1241 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1245 NUM_BANKS(ADDR_SURF_16_BANK) |
1246 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1249 break;
1250 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1251 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1252 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1253 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1254 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1255 NUM_BANKS(ADDR_SURF_16_BANK) |
1256 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1258 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1259 break;
1260 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1261 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1262 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1263 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1264 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1265 NUM_BANKS(ADDR_SURF_16_BANK) |
1266 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1269 break;
1270 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1271 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1273 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1274 TILE_SPLIT(split_equal_to_row_size) |
1275 NUM_BANKS(ADDR_SURF_16_BANK) |
1276 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1277 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1278 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1279 break;
1280 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1281 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1282 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1283 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1284 TILE_SPLIT(split_equal_to_row_size) |
1285 NUM_BANKS(ADDR_SURF_16_BANK) |
1286 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1289 break;
1290 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1291 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1292 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1293 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1294 TILE_SPLIT(split_equal_to_row_size) |
1295 NUM_BANKS(ADDR_SURF_16_BANK) |
1296 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1297 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1298 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1299 break;
1300 case 8: /* 1D and 1D Array Surfaces */
1301 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1302 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1303 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1304 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1305 NUM_BANKS(ADDR_SURF_16_BANK) |
1306 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1307 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1308 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1309 break;
1310 case 9: /* Displayable maps. */
1311 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1312 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1313 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1314 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1315 NUM_BANKS(ADDR_SURF_16_BANK) |
1316 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1317 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1318 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1319 break;
1320 case 10: /* Display 8bpp. */
1321 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1322 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1323 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1325 NUM_BANKS(ADDR_SURF_16_BANK) |
1326 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1327 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1328 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1329 break;
1330 case 11: /* Display 16bpp. */
1331 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1332 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1333 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1334 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1335 NUM_BANKS(ADDR_SURF_16_BANK) |
1336 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1337 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1338 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1339 break;
1340 case 12: /* Display 32bpp. */
1341 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1342 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1343 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1345 NUM_BANKS(ADDR_SURF_16_BANK) |
1346 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1349 break;
1350 case 13: /* Thin. */
1351 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1352 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1353 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1354 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1355 NUM_BANKS(ADDR_SURF_16_BANK) |
1356 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1357 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1358 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1359 break;
1360 case 14: /* Thin 8 bpp. */
1361 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1362 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1363 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1364 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1365 NUM_BANKS(ADDR_SURF_16_BANK) |
1366 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1369 break;
1370 case 15: /* Thin 16 bpp. */
1371 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1372 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1373 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1375 NUM_BANKS(ADDR_SURF_16_BANK) |
1376 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1377 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1378 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1379 break;
1380 case 16: /* Thin 32 bpp. */
1381 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1382 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1383 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1385 NUM_BANKS(ADDR_SURF_16_BANK) |
1386 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1389 break;
1390 case 17: /* Thin 64 bpp. */
1391 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1392 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1393 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1394 TILE_SPLIT(split_equal_to_row_size) |
1395 NUM_BANKS(ADDR_SURF_16_BANK) |
1396 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1397 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1398 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1399 break;
1400 case 21: /* 8 bpp PRT. */
1401 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1402 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1403 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1405 NUM_BANKS(ADDR_SURF_16_BANK) |
1406 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1407 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1408 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1409 break;
1410 case 22: /* 16 bpp PRT */
1411 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1412 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1413 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1414 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1415 NUM_BANKS(ADDR_SURF_16_BANK) |
1416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1419 break;
1420 case 23: /* 32 bpp PRT */
1421 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1422 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1423 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1425 NUM_BANKS(ADDR_SURF_16_BANK) |
1426 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1429 break;
1430 case 24: /* 64 bpp PRT */
1431 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1432 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1433 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1435 NUM_BANKS(ADDR_SURF_16_BANK) |
1436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1439 break;
1440 case 25: /* 128 bpp PRT */
1441 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1442 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1443 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1444 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1445 NUM_BANKS(ADDR_SURF_8_BANK) |
1446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1449 break;
1450 default:
1451 gb_tile_moden = 0;
1452 break;
1453 }
1454 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1455 }
1456 } else
1457 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1458}
1459
1a8ca750
AD		 1460static void si_select_se_sh(struct radeon_device *rdev,
1461 u32 se_num, u32 sh_num)
1462{
1463 u32 data = INSTANCE_BROADCAST_WRITES;
1464
1465 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1466 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1467 else if (se_num == 0xffffffff)
1468 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1469 else if (sh_num == 0xffffffff)
1470 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1471 else
1472 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1473 WREG32(GRBM_GFX_INDEX, data);
1474}
1475
1476static u32 si_create_bitmask(u32 bit_width)
1477{
1478 u32 i, mask = 0;
1479
1480 for (i = 0; i < bit_width; i++) {
1481 mask <<= 1;
1482 mask |= 1;
1483 }
1484 return mask;
1485}
1486
1487static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1488{
1489 u32 data, mask;
1490
1491 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1492 if (data & 1)
1493 data &= INACTIVE_CUS_MASK;
1494 else
1495 data = 0;
1496 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1497
1498 data >>= INACTIVE_CUS_SHIFT;
1499
1500 mask = si_create_bitmask(cu_per_sh);
1501
1502 return ~data & mask;
1503}
1504
1505static void si_setup_spi(struct radeon_device *rdev,
1506 u32 se_num, u32 sh_per_se,
1507 u32 cu_per_sh)
1508{
1509 int i, j, k;
1510 u32 data, mask, active_cu;
1511
1512 for (i = 0; i < se_num; i++) {
1513 for (j = 0; j < sh_per_se; j++) {
1514 si_select_se_sh(rdev, i, j);
1515 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1516 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1517
1518 mask = 1;
1519 for (k = 0; k < 16; k++) {
1520 mask <<= k;
1521 if (active_cu & mask) {
1522 data &= ~mask;
1523 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1524 break;
1525 }
1526 }
1527 }
1528 }
1529 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1530}
1531
1532static u32 si_get_rb_disabled(struct radeon_device *rdev,
1533 u32 max_rb_num, u32 se_num,
1534 u32 sh_per_se)
1535{
1536 u32 data, mask;
1537
1538 data = RREG32(CC_RB_BACKEND_DISABLE);
1539 if (data & 1)
1540 data &= BACKEND_DISABLE_MASK;
1541 else
1542 data = 0;
1543 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1544
1545 data >>= BACKEND_DISABLE_SHIFT;
1546
1547 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1548
1549 return data & mask;
1550}
1551
1552static void si_setup_rb(struct radeon_device *rdev,
1553 u32 se_num, u32 sh_per_se,
1554 u32 max_rb_num)
1555{
1556 int i, j;
1557 u32 data, mask;
1558 u32 disabled_rbs = 0;
1559 u32 enabled_rbs = 0;
1560
1561 for (i = 0; i < se_num; i++) {
1562 for (j = 0; j < sh_per_se; j++) {
1563 si_select_se_sh(rdev, i, j);
1564 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1565 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1566 }
1567 }
1568 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1569
1570 mask = 1;
1571 for (i = 0; i < max_rb_num; i++) {
1572 if (!(disabled_rbs & mask))
1573 enabled_rbs |= mask;
1574 mask <<= 1;
1575 }
1576
1577 for (i = 0; i < se_num; i++) {
1578 si_select_se_sh(rdev, i, 0xffffffff);
1579 data = 0;
1580 for (j = 0; j < sh_per_se; j++) {
1581 switch (enabled_rbs & 3) {
1582 case 1:
1583 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1584 break;
1585 case 2:
1586 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1587 break;
1588 case 3:
1589 default:
1590 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1591 break;
1592 }
1593 enabled_rbs >>= 2;
1594 }
1595 WREG32(PA_SC_RASTER_CONFIG, data);
1596 }
1597 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1598}
1599
0a96d72b
AD		 1600static void si_gpu_init(struct radeon_device *rdev)
1601{
0a96d72b
AD		 1602 u32 gb_addr_config = 0;
1603 u32 mc_shared_chmap, mc_arb_ramcfg;
0a96d72b 1604 u32 sx_debug_1;
0a96d72b
AD		 1605 u32 hdp_host_path_cntl;
1606 u32 tmp;
1607 int i, j;
1608
1609 switch (rdev->family) {
1610 case CHIP_TAHITI:
1611 rdev->config.si.max_shader_engines = 2;
0a96d72b 1612 rdev->config.si.max_tile_pipes = 12;
1a8ca750
AD		 1613 rdev->config.si.max_cu_per_sh = 8;
1614 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1615 rdev->config.si.max_backends_per_se = 4;
1616 rdev->config.si.max_texture_channel_caches = 12;
1617 rdev->config.si.max_gprs = 256;
1618 rdev->config.si.max_gs_threads = 32;
1619 rdev->config.si.max_hw_contexts = 8;
1620
1621 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1622 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1623 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1624 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1625 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1626 break;
1627 case CHIP_PITCAIRN:
1628 rdev->config.si.max_shader_engines = 2;
0a96d72b 1629 rdev->config.si.max_tile_pipes = 8;
1a8ca750
AD		 1630 rdev->config.si.max_cu_per_sh = 5;
1631 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1632 rdev->config.si.max_backends_per_se = 4;
1633 rdev->config.si.max_texture_channel_caches = 8;
1634 rdev->config.si.max_gprs = 256;
1635 rdev->config.si.max_gs_threads = 32;
1636 rdev->config.si.max_hw_contexts = 8;
1637
1638 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1639 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1640 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1641 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1642 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1643 break;
1644 case CHIP_VERDE:
1645 default:
1646 rdev->config.si.max_shader_engines = 1;
0a96d72b 1647 rdev->config.si.max_tile_pipes = 4;
1a8ca750
AD		 1648 rdev->config.si.max_cu_per_sh = 2;
1649 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1650 rdev->config.si.max_backends_per_se = 4;
1651 rdev->config.si.max_texture_channel_caches = 4;
1652 rdev->config.si.max_gprs = 256;
1653 rdev->config.si.max_gs_threads = 32;
1654 rdev->config.si.max_hw_contexts = 8;
1655
d0ae7fcc
AD		 1656 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1657 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1658 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1659 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1660 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1661 break;
1662 case CHIP_OLAND:
1663 rdev->config.si.max_shader_engines = 1;
1664 rdev->config.si.max_tile_pipes = 4;
1665 rdev->config.si.max_cu_per_sh = 6;
1666 rdev->config.si.max_sh_per_se = 1;
1667 rdev->config.si.max_backends_per_se = 2;
1668 rdev->config.si.max_texture_channel_caches = 4;
1669 rdev->config.si.max_gprs = 256;
1670 rdev->config.si.max_gs_threads = 16;
1671 rdev->config.si.max_hw_contexts = 8;
1672
0a96d72b
AD		 1673 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1674 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1675 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1676 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1677 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1678 break;
1679 }
1680
1681 /* Initialize HDP */
1682 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1683 WREG32((0x2c14 + j), 0x00000000);
1684 WREG32((0x2c18 + j), 0x00000000);
1685 WREG32((0x2c1c + j), 0x00000000);
1686 WREG32((0x2c20 + j), 0x00000000);
1687 WREG32((0x2c24 + j), 0x00000000);
1688 }
1689
1690 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1691
1692 evergreen_fix_pci_max_read_req_size(rdev);
1693
1694 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1695
1696 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1697 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1698
0a96d72b 1699 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
0a96d72b
AD		 1700 rdev->config.si.mem_max_burst_length_bytes = 256;
1701 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1702 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1703 if (rdev->config.si.mem_row_size_in_kb > 4)
1704 rdev->config.si.mem_row_size_in_kb = 4;
1705 /* XXX use MC settings? */
1706 rdev->config.si.shader_engine_tile_size = 32;
1707 rdev->config.si.num_gpus = 1;
1708 rdev->config.si.multi_gpu_tile_size = 64;
1709
1a8ca750
AD		 1710 /* fix up row size */
1711 gb_addr_config &= ~ROW_SIZE_MASK;
0a96d72b
AD		 1712 switch (rdev->config.si.mem_row_size_in_kb) {
1713 case 1:
1714 default:
1715 gb_addr_config |= ROW_SIZE(0);
1716 break;
1717 case 2:
1718 gb_addr_config |= ROW_SIZE(1);
1719 break;
1720 case 4:
1721 gb_addr_config |= ROW_SIZE(2);
1722 break;
1723 }
1724
0a96d72b
AD		 1725 /* setup tiling info dword. gb_addr_config is not adequate since it does
1726 * not have bank info, so create a custom tiling dword.
1727 * bits 3:0 num_pipes
1728 * bits 7:4 num_banks
1729 * bits 11:8 group_size
1730 * bits 15:12 row_size
1731 */
1732 rdev->config.si.tile_config = 0;
1733 switch (rdev->config.si.num_tile_pipes) {
1734 case 1:
1735 rdev->config.si.tile_config |= (0 << 0);
1736 break;
1737 case 2:
1738 rdev->config.si.tile_config |= (1 << 0);
1739 break;
1740 case 4:
1741 rdev->config.si.tile_config |= (2 << 0);
1742 break;
1743 case 8:
1744 default:
1745 /* XXX what about 12? */
1746 rdev->config.si.tile_config |= (3 << 0);
1747 break;
dca571a6
CK		 1748 }
1749 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1750 case 0: /* four banks */
1a8ca750 1751 rdev->config.si.tile_config |= 0 << 4;
dca571a6
CK		 1752 break;
1753 case 1: /* eight banks */
1754 rdev->config.si.tile_config |= 1 << 4;
1755 break;
1756 case 2: /* sixteen banks */
1757 default:
1758 rdev->config.si.tile_config |= 2 << 4;
1759 break;
1760 }
0a96d72b
AD		 1761 rdev->config.si.tile_config |=
1762 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1763 rdev->config.si.tile_config |=
1764 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1765
0a96d72b
AD		 1766 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1767 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
7c1c7c18 1768 WREG32(DMIF_ADDR_CALC, gb_addr_config);
0a96d72b 1769 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
8c5fd7ef
AD		 1770 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1771 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
0a96d72b 1772
1a8ca750 1773 si_tiling_mode_table_init(rdev);
0a96d72b 1774
1a8ca750
AD		 1775 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1776 rdev->config.si.max_sh_per_se,
1777 rdev->config.si.max_backends_per_se);
0a96d72b 1778
1a8ca750
AD		 1779 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1780 rdev->config.si.max_sh_per_se,
1781 rdev->config.si.max_cu_per_sh);
0a96d72b 1782
0a96d72b
AD		 1783
1784 /* set HW defaults for 3D engine */
1785 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1786 ROQ_IB2_START(0x2b)));
1787 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1788
1789 sx_debug_1 = RREG32(SX_DEBUG_1);
1790 WREG32(SX_DEBUG_1, sx_debug_1);
1791
1792 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1793
1794 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1795 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1796 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1797 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1798
1799 WREG32(VGT_NUM_INSTANCES, 1);
1800
1801 WREG32(CP_PERFMON_CNTL, 0);
1802
1803 WREG32(SQ_CONFIG, 0);
1804
1805 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1806 FORCE_EOV_MAX_REZ_CNT(255)));
1807
1808 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1809 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1810
1811 WREG32(VGT_GS_VERTEX_REUSE, 16);
1812 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1813
1814 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1815 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1816 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1817 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1818 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1819 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1820 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1821 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1822
1823 tmp = RREG32(HDP_MISC_CNTL);
1824 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1825 WREG32(HDP_MISC_CNTL, tmp);
1826
1827 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1828 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1829
1830 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1831
1832 udelay(50);
1833}
c476dde2 1834
2ece2e8b
AD		 1835/*
1836 * GPU scratch registers helpers function.
1837 */
1838static void si_scratch_init(struct radeon_device *rdev)
1839{
1840 int i;
1841
1842 rdev->scratch.num_reg = 7;
1843 rdev->scratch.reg_base = SCRATCH_REG0;
1844 for (i = 0; i < rdev->scratch.num_reg; i++) {
1845 rdev->scratch.free[i] = true;
1846 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1847 }
1848}
1849
1850void si_fence_ring_emit(struct radeon_device *rdev,
1851 struct radeon_fence *fence)
1852{
1853 struct radeon_ring *ring = &rdev->ring[fence->ring];
1854 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1855
1856 /* flush read cache over gart */
1857 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1858 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1859 radeon_ring_write(ring, 0);
1860 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1861 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1862 PACKET3_TC_ACTION_ENA |
1863 PACKET3_SH_KCACHE_ACTION_ENA |
1864 PACKET3_SH_ICACHE_ACTION_ENA);
1865 radeon_ring_write(ring, 0xFFFFFFFF);
1866 radeon_ring_write(ring, 0);
1867 radeon_ring_write(ring, 10); /* poll interval */
1868 /* EVENT_WRITE_EOP - flush caches, send int */
1869 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1870 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1871 radeon_ring_write(ring, addr & 0xffffffff);
1872 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1873 radeon_ring_write(ring, fence->seq);
1874 radeon_ring_write(ring, 0);
1875}
1876
1877/*
1878 * IB stuff
1879 */
1880void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1881{
876dc9f3 1882 struct radeon_ring *ring = &rdev->ring[ib->ring];
2ece2e8b
AD		 1883 u32 header;
1884
a85a7da4
AD		 1885 if (ib->is_const_ib) {
1886 /* set switch buffer packet before const IB */
1887 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1888 radeon_ring_write(ring, 0);
45df6803 1889
2ece2e8b 1890 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
a85a7da4 1891 } else {
89d35807 1892 u32 next_rptr;
a85a7da4 1893 if (ring->rptr_save_reg) {
89d35807 1894 next_rptr = ring->wptr + 3 + 4 + 8;
a85a7da4
AD		 1895 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1896 radeon_ring_write(ring, ((ring->rptr_save_reg -
1897 PACKET3_SET_CONFIG_REG_START) >> 2));
1898 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1899 } else if (rdev->wb.enabled) {
1900 next_rptr = ring->wptr + 5 + 4 + 8;
1901 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1902 radeon_ring_write(ring, (1 << 8));
1903 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1904 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1905 radeon_ring_write(ring, next_rptr);
a85a7da4
AD		 1906 }
1907
2ece2e8b 1908 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
a85a7da4 1909 }
2ece2e8b
AD		 1910
1911 radeon_ring_write(ring, header);
1912 radeon_ring_write(ring,
1913#ifdef __BIG_ENDIAN
1914 (2 << 0) |
1915#endif
1916 (ib->gpu_addr & 0xFFFFFFFC));
1917 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4bf3dd92
CK		 1918 radeon_ring_write(ring, ib->length_dw |
1919 (ib->vm ? (ib->vm->id << 24) : 0));
2ece2e8b 1920
a85a7da4
AD		 1921 if (!ib->is_const_ib) {
1922 /* flush read cache over gart for this vmid */
1923 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1924 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 1925 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
a85a7da4
AD		 1926 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1927 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1928 PACKET3_TC_ACTION_ENA |
1929 PACKET3_SH_KCACHE_ACTION_ENA |
1930 PACKET3_SH_ICACHE_ACTION_ENA);
1931 radeon_ring_write(ring, 0xFFFFFFFF);
1932 radeon_ring_write(ring, 0);
1933 radeon_ring_write(ring, 10); /* poll interval */
1934 }
2ece2e8b
AD		 1935}
1936
48c0c902
AD		 1937/*
1938 * CP.
1939 */
1940static void si_cp_enable(struct radeon_device *rdev, bool enable)
1941{
1942 if (enable)
1943 WREG32(CP_ME_CNTL, 0);
1944 else {
1945 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1946 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1947 WREG32(SCRATCH_UMSK, 0);
8c5fd7ef
AD		 1948 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1949 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1950 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
48c0c902
AD		 1951 }
1952 udelay(50);
1953}
1954
1955static int si_cp_load_microcode(struct radeon_device *rdev)
1956{
1957 const __be32 *fw_data;
1958 int i;
1959
1960 if (!rdev->me_fw || !rdev->pfp_fw)
1961 return -EINVAL;
1962
1963 si_cp_enable(rdev, false);
1964
1965 /* PFP */
1966 fw_data = (const __be32 *)rdev->pfp_fw->data;
1967 WREG32(CP_PFP_UCODE_ADDR, 0);
1968 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1969 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1970 WREG32(CP_PFP_UCODE_ADDR, 0);
1971
1972 /* CE */
1973 fw_data = (const __be32 *)rdev->ce_fw->data;
1974 WREG32(CP_CE_UCODE_ADDR, 0);
1975 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1976 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1977 WREG32(CP_CE_UCODE_ADDR, 0);
1978
1979 /* ME */
1980 fw_data = (const __be32 *)rdev->me_fw->data;
1981 WREG32(CP_ME_RAM_WADDR, 0);
1982 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1983 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1984 WREG32(CP_ME_RAM_WADDR, 0);
1985
1986 WREG32(CP_PFP_UCODE_ADDR, 0);
1987 WREG32(CP_CE_UCODE_ADDR, 0);
1988 WREG32(CP_ME_RAM_WADDR, 0);
1989 WREG32(CP_ME_RAM_RADDR, 0);
1990 return 0;
1991}
1992
1993static int si_cp_start(struct radeon_device *rdev)
1994{
1995 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1996 int r, i;
1997
1998 r = radeon_ring_lock(rdev, ring, 7 + 4);
1999 if (r) {
2000 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2001 return r;
2002 }
2003 /* init the CP */
2004 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2005 radeon_ring_write(ring, 0x1);
2006 radeon_ring_write(ring, 0x0);
2007 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
2008 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2009 radeon_ring_write(ring, 0);
2010 radeon_ring_write(ring, 0);
2011
2012 /* init the CE partitions */
2013 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2014 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2015 radeon_ring_write(ring, 0xc000);
2016 radeon_ring_write(ring, 0xe000);
2017 radeon_ring_unlock_commit(rdev, ring);
2018
2019 si_cp_enable(rdev, true);
2020
2021 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
2022 if (r) {
2023 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2024 return r;
2025 }
2026
2027 /* setup clear context state */
2028 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2029 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2030
2031 for (i = 0; i < si_default_size; i++)
2032 radeon_ring_write(ring, si_default_state[i]);
2033
2034 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2035 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2036
2037 /* set clear context state */
2038 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2039 radeon_ring_write(ring, 0);
2040
2041 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2042 radeon_ring_write(ring, 0x00000316);
2043 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2044 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2045
2046 radeon_ring_unlock_commit(rdev, ring);
2047
2048 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
2049 ring = &rdev->ring[i];
2050 r = radeon_ring_lock(rdev, ring, 2);
2051
2052 /* clear the compute context state */
2053 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2054 radeon_ring_write(ring, 0);
2055
2056 radeon_ring_unlock_commit(rdev, ring);
2057 }
2058
2059 return 0;
2060}
2061
2062static void si_cp_fini(struct radeon_device *rdev)
2063{
45df6803 2064 struct radeon_ring *ring;
48c0c902 2065 si_cp_enable(rdev, false);
45df6803
CK		 2066
2067 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2068 radeon_ring_fini(rdev, ring);
2069 radeon_scratch_free(rdev, ring->rptr_save_reg);
2070
2071 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2072 radeon_ring_fini(rdev, ring);
2073 radeon_scratch_free(rdev, ring->rptr_save_reg);
2074
2075 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2076 radeon_ring_fini(rdev, ring);
2077 radeon_scratch_free(rdev, ring->rptr_save_reg);
48c0c902
AD		 2078}
2079
2080static int si_cp_resume(struct radeon_device *rdev)
2081{
2082 struct radeon_ring *ring;
2083 u32 tmp;
2084 u32 rb_bufsz;
2085 int r;
2086
2087 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2088 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2089 SOFT_RESET_PA |
2090 SOFT_RESET_VGT |
2091 SOFT_RESET_SPI |
2092 SOFT_RESET_SX));
2093 RREG32(GRBM_SOFT_RESET);
2094 mdelay(15);
2095 WREG32(GRBM_SOFT_RESET, 0);
2096 RREG32(GRBM_SOFT_RESET);
2097
2098 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2099 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2100
2101 /* Set the write pointer delay */
2102 WREG32(CP_RB_WPTR_DELAY, 0);
2103
2104 WREG32(CP_DEBUG, 0);
2105 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2106
2107 /* ring 0 - compute and gfx */
2108 /* Set ring buffer size */
2109 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2110 rb_bufsz = drm_order(ring->ring_size / 8);
2111 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2112#ifdef __BIG_ENDIAN
2113 tmp |= BUF_SWAP_32BIT;
2114#endif
2115 WREG32(CP_RB0_CNTL, tmp);
2116
2117 /* Initialize the ring buffer's read and write pointers */
2118 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2119 ring->wptr = 0;
2120 WREG32(CP_RB0_WPTR, ring->wptr);
2121
48fc7f7e 2122 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2123 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2124 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2125
2126 if (rdev->wb.enabled)
2127 WREG32(SCRATCH_UMSK, 0xff);
2128 else {
2129 tmp |= RB_NO_UPDATE;
2130 WREG32(SCRATCH_UMSK, 0);
2131 }
2132
2133 mdelay(1);
2134 WREG32(CP_RB0_CNTL, tmp);
2135
2136 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2137
2138 ring->rptr = RREG32(CP_RB0_RPTR);
2139
2140 /* ring1 - compute only */
2141 /* Set ring buffer size */
2142 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2143 rb_bufsz = drm_order(ring->ring_size / 8);
2144 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2145#ifdef __BIG_ENDIAN
2146 tmp |= BUF_SWAP_32BIT;
2147#endif
2148 WREG32(CP_RB1_CNTL, tmp);
2149
2150 /* Initialize the ring buffer's read and write pointers */
2151 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2152 ring->wptr = 0;
2153 WREG32(CP_RB1_WPTR, ring->wptr);
2154
48fc7f7e 2155 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2156 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2157 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2158
2159 mdelay(1);
2160 WREG32(CP_RB1_CNTL, tmp);
2161
2162 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2163
2164 ring->rptr = RREG32(CP_RB1_RPTR);
2165
2166 /* ring2 - compute only */
2167 /* Set ring buffer size */
2168 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2169 rb_bufsz = drm_order(ring->ring_size / 8);
2170 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2171#ifdef __BIG_ENDIAN
2172 tmp |= BUF_SWAP_32BIT;
2173#endif
2174 WREG32(CP_RB2_CNTL, tmp);
2175
2176 /* Initialize the ring buffer's read and write pointers */
2177 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2178 ring->wptr = 0;
2179 WREG32(CP_RB2_WPTR, ring->wptr);
2180
48fc7f7e 2181 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2182 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2183 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2184
2185 mdelay(1);
2186 WREG32(CP_RB2_CNTL, tmp);
2187
2188 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2189
2190 ring->rptr = RREG32(CP_RB2_RPTR);
2191
2192 /* start the rings */
2193 si_cp_start(rdev);
2194 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2195 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2196 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2197 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2198 if (r) {
2199 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2200 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2201 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2202 return r;
2203 }
2204 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2205 if (r) {
2206 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2207 }
2208 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2209 if (r) {
2210 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2211 }
2212
2213 return 0;
2214}
2215
014bb209 2216static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
06bc6df0 2217{
014bb209 2218 u32 reset_mask = 0;
1c534671 2219 u32 tmp;
06bc6df0 2220
014bb209
AD		 2221 /* GRBM_STATUS */
2222 tmp = RREG32(GRBM_STATUS);
2223 if (tmp & (PA_BUSY | SC_BUSY |
2224 BCI_BUSY | SX_BUSY |
2225 TA_BUSY | VGT_BUSY |
2226 DB_BUSY | CB_BUSY |
2227 GDS_BUSY | SPI_BUSY |
2228 IA_BUSY | IA_BUSY_NO_DMA))
2229 reset_mask |= RADEON_RESET_GFX;
2230
2231 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2232 CP_BUSY | CP_COHERENCY_BUSY))
2233 reset_mask |= RADEON_RESET_CP;
2234
2235 if (tmp & GRBM_EE_BUSY)
2236 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2237
2238 /* GRBM_STATUS2 */
2239 tmp = RREG32(GRBM_STATUS2);
2240 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2241 reset_mask |= RADEON_RESET_RLC;
2242
2243 /* DMA_STATUS_REG 0 */
2244 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2245 if (!(tmp & DMA_IDLE))
2246 reset_mask |= RADEON_RESET_DMA;
2247
2248 /* DMA_STATUS_REG 1 */
2249 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2250 if (!(tmp & DMA_IDLE))
2251 reset_mask |= RADEON_RESET_DMA1;
2252
2253 /* SRBM_STATUS2 */
2254 tmp = RREG32(SRBM_STATUS2);
2255 if (tmp & DMA_BUSY)
2256 reset_mask |= RADEON_RESET_DMA;
2257
2258 if (tmp & DMA1_BUSY)
2259 reset_mask |= RADEON_RESET_DMA1;
2260
2261 /* SRBM_STATUS */
2262 tmp = RREG32(SRBM_STATUS);
2263
2264 if (tmp & IH_BUSY)
2265 reset_mask |= RADEON_RESET_IH;
2266
2267 if (tmp & SEM_BUSY)
2268 reset_mask |= RADEON_RESET_SEM;
2269
2270 if (tmp & GRBM_RQ_PENDING)
2271 reset_mask |= RADEON_RESET_GRBM;
2272
2273 if (tmp & VMC_BUSY)
2274 reset_mask |= RADEON_RESET_VMC;
19fc42ed 2275
014bb209
AD		 2276 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2277 MCC_BUSY | MCD_BUSY))
2278 reset_mask |= RADEON_RESET_MC;
2279
2280 if (evergreen_is_display_hung(rdev))
2281 reset_mask |= RADEON_RESET_DISPLAY;
2282
2283 /* VM_L2_STATUS */
2284 tmp = RREG32(VM_L2_STATUS);
2285 if (tmp & L2_BUSY)
2286 reset_mask |= RADEON_RESET_VMC;
2287
d808fc88
AD		 2288 /* Skip MC reset as it's mostly likely not hung, just busy */
2289 if (reset_mask & RADEON_RESET_MC) {
2290 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
2291 reset_mask &= ~RADEON_RESET_MC;
2292 }
2293
014bb209
AD		 2294 return reset_mask;
2295}
2296
2297static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2298{
2299 struct evergreen_mc_save save;
2300 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2301 u32 tmp;
19fc42ed 2302
06bc6df0 2303 if (reset_mask == 0)
014bb209 2304 return;
06bc6df0
AD		 2305
2306 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2307
1c534671 2308 evergreen_print_gpu_status_regs(rdev);
06bc6df0
AD		 2309 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2310 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2311 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2312 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2313
1c534671
AD		 2314 /* Disable CP parsing/prefetching */
2315 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2316
2317 if (reset_mask & RADEON_RESET_DMA) {
2318 /* dma0 */
2319 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2320 tmp &= ~DMA_RB_ENABLE;
2321 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
014bb209
AD		 2322 }
2323 if (reset_mask & RADEON_RESET_DMA1) {
1c534671
AD		 2324 /* dma1 */
2325 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2326 tmp &= ~DMA_RB_ENABLE;
2327 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2328 }
2329
f770d78a
AD		 2330 udelay(50);
2331
2332 evergreen_mc_stop(rdev, &save);
2333 if (evergreen_mc_wait_for_idle(rdev)) {
2334 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2335 }
2336
1c534671
AD		 2337 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2338 grbm_soft_reset = SOFT_RESET_CB |
2339 SOFT_RESET_DB |
2340 SOFT_RESET_GDS |
2341 SOFT_RESET_PA |
2342 SOFT_RESET_SC |
2343 SOFT_RESET_BCI |
2344 SOFT_RESET_SPI |
2345 SOFT_RESET_SX |
2346 SOFT_RESET_TC |
2347 SOFT_RESET_TA |
2348 SOFT_RESET_VGT |
2349 SOFT_RESET_IA;
2350 }
2351
2352 if (reset_mask & RADEON_RESET_CP) {
2353 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2354
2355 srbm_soft_reset |= SOFT_RESET_GRBM;
2356 }
06bc6df0
AD		 2357
2358 if (reset_mask & RADEON_RESET_DMA)
014bb209
AD		 2359 srbm_soft_reset |= SOFT_RESET_DMA;
2360
2361 if (reset_mask & RADEON_RESET_DMA1)
2362 srbm_soft_reset |= SOFT_RESET_DMA1;
2363
2364 if (reset_mask & RADEON_RESET_DISPLAY)
2365 srbm_soft_reset |= SOFT_RESET_DC;
2366
2367 if (reset_mask & RADEON_RESET_RLC)
2368 grbm_soft_reset |= SOFT_RESET_RLC;
2369
2370 if (reset_mask & RADEON_RESET_SEM)
2371 srbm_soft_reset |= SOFT_RESET_SEM;
2372
2373 if (reset_mask & RADEON_RESET_IH)
2374 srbm_soft_reset |= SOFT_RESET_IH;
2375
2376 if (reset_mask & RADEON_RESET_GRBM)
2377 srbm_soft_reset |= SOFT_RESET_GRBM;
2378
2379 if (reset_mask & RADEON_RESET_VMC)
2380 srbm_soft_reset |= SOFT_RESET_VMC;
2381
2382 if (reset_mask & RADEON_RESET_MC)
2383 srbm_soft_reset |= SOFT_RESET_MC;
1c534671
AD		 2384
2385 if (grbm_soft_reset) {
2386 tmp = RREG32(GRBM_SOFT_RESET);
2387 tmp |= grbm_soft_reset;
2388 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2389 WREG32(GRBM_SOFT_RESET, tmp);
2390 tmp = RREG32(GRBM_SOFT_RESET);
2391
2392 udelay(50);
2393
2394 tmp &= ~grbm_soft_reset;
2395 WREG32(GRBM_SOFT_RESET, tmp);
2396 tmp = RREG32(GRBM_SOFT_RESET);
2397 }
2398
2399 if (srbm_soft_reset) {
2400 tmp = RREG32(SRBM_SOFT_RESET);
2401 tmp |= srbm_soft_reset;
2402 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2403 WREG32(SRBM_SOFT_RESET, tmp);
2404 tmp = RREG32(SRBM_SOFT_RESET);
2405
2406 udelay(50);
2407
2408 tmp &= ~srbm_soft_reset;
2409 WREG32(SRBM_SOFT_RESET, tmp);
2410 tmp = RREG32(SRBM_SOFT_RESET);
2411 }
06bc6df0
AD		 2412
2413 /* Wait a little for things to settle down */
2414 udelay(50);
2415
c476dde2 2416 evergreen_mc_resume(rdev, &save);
1c534671
AD		 2417 udelay(50);
2418
1c534671 2419 evergreen_print_gpu_status_regs(rdev);
c476dde2
AD		 2420}
2421
2422int si_asic_reset(struct radeon_device *rdev)
2423{
014bb209
AD		 2424 u32 reset_mask;
2425
2426 reset_mask = si_gpu_check_soft_reset(rdev);
2427
2428 if (reset_mask)
2429 r600_set_bios_scratch_engine_hung(rdev, true);
2430
2431 si_gpu_soft_reset(rdev, reset_mask);
2432
2433 reset_mask = si_gpu_check_soft_reset(rdev);
2434
2435 if (!reset_mask)
2436 r600_set_bios_scratch_engine_hung(rdev, false);
2437
2438 return 0;
c476dde2
AD		 2439}
2440
123bc183
AD		 2441/**
2442 * si_gfx_is_lockup - Check if the GFX engine is locked up
2443 *
2444 * @rdev: radeon_device pointer
2445 * @ring: radeon_ring structure holding ring information
2446 *
2447 * Check if the GFX engine is locked up.
2448 * Returns true if the engine appears to be locked up, false if not.
2449 */
2450bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2451{
2452 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2453
2454 if (!(reset_mask & (RADEON_RESET_GFX |
2455 RADEON_RESET_COMPUTE |
2456 RADEON_RESET_CP))) {
2457 radeon_ring_lockup_update(ring);
2458 return false;
2459 }
2460 /* force CP activities */
2461 radeon_ring_force_activity(rdev, ring);
2462 return radeon_ring_test_lockup(rdev, ring);
2463}
2464
2465/**
2466 * si_dma_is_lockup - Check if the DMA engine is locked up
2467 *
2468 * @rdev: radeon_device pointer
2469 * @ring: radeon_ring structure holding ring information
2470 *
2471 * Check if the async DMA engine is locked up.
2472 * Returns true if the engine appears to be locked up, false if not.
2473 */
2474bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2475{
2476 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2477 u32 mask;
2478
2479 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2480 mask = RADEON_RESET_DMA;
2481 else
2482 mask = RADEON_RESET_DMA1;
2483
2484 if (!(reset_mask & mask)) {
2485 radeon_ring_lockup_update(ring);
2486 return false;
2487 }
2488 /* force ring activities */
2489 radeon_ring_force_activity(rdev, ring);
2490 return radeon_ring_test_lockup(rdev, ring);
2491}
2492
d2800ee5
AD		 2493/* MC */
2494static void si_mc_program(struct radeon_device *rdev)
2495{
2496 struct evergreen_mc_save save;
2497 u32 tmp;
2498 int i, j;
2499
2500 /* Initialize HDP */
2501 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2502 WREG32((0x2c14 + j), 0x00000000);
2503 WREG32((0x2c18 + j), 0x00000000);
2504 WREG32((0x2c1c + j), 0x00000000);
2505 WREG32((0x2c20 + j), 0x00000000);
2506 WREG32((0x2c24 + j), 0x00000000);
2507 }
2508 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2509
2510 evergreen_mc_stop(rdev, &save);
2511 if (radeon_mc_wait_for_idle(rdev)) {
2512 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2513 }
2514 /* Lockout access through VGA aperture*/
2515 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2516 /* Update configuration */
2517 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2518 rdev->mc.vram_start >> 12);
2519 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2520 rdev->mc.vram_end >> 12);
2521 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2522 rdev->vram_scratch.gpu_addr >> 12);
2523 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2524 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2525 WREG32(MC_VM_FB_LOCATION, tmp);
2526 /* XXX double check these! */
2527 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2528 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2529 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2530 WREG32(MC_VM_AGP_BASE, 0);
2531 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2532 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2533 if (radeon_mc_wait_for_idle(rdev)) {
2534 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2535 }
2536 evergreen_mc_resume(rdev, &save);
2537 /* we need to own VRAM, so turn off the VGA renderer here
2538 * to stop it overwriting our objects */
2539 rv515_vga_render_disable(rdev);
2540}
2541
d2800ee5
AD		 2542static void si_vram_gtt_location(struct radeon_device *rdev,
2543 struct radeon_mc *mc)
2544{
2545 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2546 /* leave room for at least 1024M GTT */
2547 dev_warn(rdev->dev, "limiting VRAM\n");
2548 mc->real_vram_size = 0xFFC0000000ULL;
2549 mc->mc_vram_size = 0xFFC0000000ULL;
2550 }
9ed8b1f9 2551 radeon_vram_location(rdev, &rdev->mc, 0);
d2800ee5 2552 rdev->mc.gtt_base_align = 0;
9ed8b1f9 2553 radeon_gtt_location(rdev, mc);
d2800ee5
AD		 2554}
2555
2556static int si_mc_init(struct radeon_device *rdev)
2557{
2558 u32 tmp;
2559 int chansize, numchan;
2560
2561 /* Get VRAM informations */
2562 rdev->mc.vram_is_ddr = true;
2563 tmp = RREG32(MC_ARB_RAMCFG);
2564 if (tmp & CHANSIZE_OVERRIDE) {
2565 chansize = 16;
2566 } else if (tmp & CHANSIZE_MASK) {
2567 chansize = 64;
2568 } else {
2569 chansize = 32;
2570 }
2571 tmp = RREG32(MC_SHARED_CHMAP);
2572 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2573 case 0:
2574 default:
2575 numchan = 1;
2576 break;
2577 case 1:
2578 numchan = 2;
2579 break;
2580 case 2:
2581 numchan = 4;
2582 break;
2583 case 3:
2584 numchan = 8;
2585 break;
2586 case 4:
2587 numchan = 3;
2588 break;
2589 case 5:
2590 numchan = 6;
2591 break;
2592 case 6:
2593 numchan = 10;
2594 break;
2595 case 7:
2596 numchan = 12;
2597 break;
2598 case 8:
2599 numchan = 16;
2600 break;
2601 }
2602 rdev->mc.vram_width = numchan * chansize;
2603 /* Could aper size report 0 ? */
2604 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2605 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2606 /* size in MB on si */
2607 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2608 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2609 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2610 si_vram_gtt_location(rdev, &rdev->mc);
2611 radeon_update_bandwidth_info(rdev);
2612
2613 return 0;
2614}
2615
2616/*
2617 * GART
2618 */
2619void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2620{
2621 /* flush hdp cache */
2622 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2623
2624 /* bits 0-15 are the VM contexts0-15 */
2625 WREG32(VM_INVALIDATE_REQUEST, 1);
2626}
2627
1109ca09 2628static int si_pcie_gart_enable(struct radeon_device *rdev)
d2800ee5
AD		 2629{
2630 int r, i;
2631
2632 if (rdev->gart.robj == NULL) {
2633 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2634 return -EINVAL;
2635 }
2636 r = radeon_gart_table_vram_pin(rdev);
2637 if (r)
2638 return r;
2639 radeon_gart_restore(rdev);
2640 /* Setup TLB control */
2641 WREG32(MC_VM_MX_L1_TLB_CNTL,
2642 (0xA << 7) |
2643 ENABLE_L1_TLB |
2644 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2645 ENABLE_ADVANCED_DRIVER_MODEL |
2646 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2647 /* Setup L2 cache */
2648 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2649 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2650 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2651 EFFECTIVE_L2_QUEUE_SIZE(7) |
2652 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2653 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2654 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2655 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2656 /* setup context0 */
2657 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2658 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2659 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2660 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2661 (u32)(rdev->dummy_page.addr >> 12));
2662 WREG32(VM_CONTEXT0_CNTL2, 0);
2663 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2664 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2665
2666 WREG32(0x15D4, 0);
2667 WREG32(0x15D8, 0);
2668 WREG32(0x15DC, 0);
2669
2670 /* empty context1-15 */
d2800ee5
AD		 2671 /* set vm size, must be a multiple of 4 */
2672 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
c21b328e 2673 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
23d4f1f2
AD		 2674 /* Assign the pt base to something valid for now; the pts used for
2675 * the VMs are determined by the application and setup and assigned
2676 * on the fly in the vm part of radeon_gart.c
2677 */
d2800ee5
AD		 2678 for (i = 1; i < 16; i++) {
2679 if (i < 8)
2680 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2681 rdev->gart.table_addr >> 12);
2682 else
2683 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2684 rdev->gart.table_addr >> 12);
2685 }
2686
2687 /* enable context1-15 */
2688 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2689 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 2690 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 2691 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 2692 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2693 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2694 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2695 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2696 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2697 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2698 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2699 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2700 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2701 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2702 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2703 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
d2800ee5
AD		 2704
2705 si_pcie_gart_tlb_flush(rdev);
2706 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2707 (unsigned)(rdev->mc.gtt_size >> 20),
2708 (unsigned long long)rdev->gart.table_addr);
2709 rdev->gart.ready = true;
2710 return 0;
2711}
2712
1109ca09 2713static void si_pcie_gart_disable(struct radeon_device *rdev)
d2800ee5
AD		 2714{
2715 /* Disable all tables */
2716 WREG32(VM_CONTEXT0_CNTL, 0);
2717 WREG32(VM_CONTEXT1_CNTL, 0);
2718 /* Setup TLB control */
2719 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2720 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2721 /* Setup L2 cache */
2722 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2723 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2724 EFFECTIVE_L2_QUEUE_SIZE(7) |
2725 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2726 WREG32(VM_L2_CNTL2, 0);
2727 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2728 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2729 radeon_gart_table_vram_unpin(rdev);
2730}
2731
1109ca09 2732static void si_pcie_gart_fini(struct radeon_device *rdev)
d2800ee5
AD		 2733{
2734 si_pcie_gart_disable(rdev);
2735 radeon_gart_table_vram_free(rdev);
2736 radeon_gart_fini(rdev);
2737}
2738
498dd8b3
AD		 2739/* vm parser */
2740static bool si_vm_reg_valid(u32 reg)
2741{
2742 /* context regs are fine */
2743 if (reg >= 0x28000)
2744 return true;
2745
2746 /* check config regs */
2747 switch (reg) {
2748 case GRBM_GFX_INDEX:
f418b88a 2749 case CP_STRMOUT_CNTL:
498dd8b3
AD		 2750 case VGT_VTX_VECT_EJECT_REG:
2751 case VGT_CACHE_INVALIDATION:
2752 case VGT_ESGS_RING_SIZE:
2753 case VGT_GSVS_RING_SIZE:
2754 case VGT_GS_VERTEX_REUSE:
2755 case VGT_PRIMITIVE_TYPE:
2756 case VGT_INDEX_TYPE:
2757 case VGT_NUM_INDICES:
2758 case VGT_NUM_INSTANCES:
2759 case VGT_TF_RING_SIZE:
2760 case VGT_HS_OFFCHIP_PARAM:
2761 case VGT_TF_MEMORY_BASE:
2762 case PA_CL_ENHANCE:
2763 case PA_SU_LINE_STIPPLE_VALUE:
2764 case PA_SC_LINE_STIPPLE_STATE:
2765 case PA_SC_ENHANCE:
2766 case SQC_CACHES:
2767 case SPI_STATIC_THREAD_MGMT_1:
2768 case SPI_STATIC_THREAD_MGMT_2:
2769 case SPI_STATIC_THREAD_MGMT_3:
2770 case SPI_PS_MAX_WAVE_ID:
2771 case SPI_CONFIG_CNTL:
2772 case SPI_CONFIG_CNTL_1:
2773 case TA_CNTL_AUX:
2774 return true;
2775 default:
2776 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2777 return false;
2778 }
2779}
2780
2781static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2782 u32 *ib, struct radeon_cs_packet *pkt)
2783{
2784 switch (pkt->opcode) {
2785 case PACKET3_NOP:
2786 case PACKET3_SET_BASE:
2787 case PACKET3_SET_CE_DE_COUNTERS:
2788 case PACKET3_LOAD_CONST_RAM:
2789 case PACKET3_WRITE_CONST_RAM:
2790 case PACKET3_WRITE_CONST_RAM_OFFSET:
2791 case PACKET3_DUMP_CONST_RAM:
2792 case PACKET3_INCREMENT_CE_COUNTER:
2793 case PACKET3_WAIT_ON_DE_COUNTER:
2794 case PACKET3_CE_WRITE:
2795 break;
2796 default:
2797 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2798 return -EINVAL;
2799 }
2800 return 0;
2801}
2802
2803static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2804 u32 *ib, struct radeon_cs_packet *pkt)
2805{
2806 u32 idx = pkt->idx + 1;
2807 u32 idx_value = ib[idx];
2808 u32 start_reg, end_reg, reg, i;
5aa709be 2809 u32 command, info;
498dd8b3
AD		 2810
2811 switch (pkt->opcode) {
2812 case PACKET3_NOP:
2813 case PACKET3_SET_BASE:
2814 case PACKET3_CLEAR_STATE:
2815 case PACKET3_INDEX_BUFFER_SIZE:
2816 case PACKET3_DISPATCH_DIRECT:
2817 case PACKET3_DISPATCH_INDIRECT:
2818 case PACKET3_ALLOC_GDS:
2819 case PACKET3_WRITE_GDS_RAM:
2820 case PACKET3_ATOMIC_GDS:
2821 case PACKET3_ATOMIC:
2822 case PACKET3_OCCLUSION_QUERY:
2823 case PACKET3_SET_PREDICATION:
2824 case PACKET3_COND_EXEC:
2825 case PACKET3_PRED_EXEC:
2826 case PACKET3_DRAW_INDIRECT:
2827 case PACKET3_DRAW_INDEX_INDIRECT:
2828 case PACKET3_INDEX_BASE:
2829 case PACKET3_DRAW_INDEX_2:
2830 case PACKET3_CONTEXT_CONTROL:
2831 case PACKET3_INDEX_TYPE:
2832 case PACKET3_DRAW_INDIRECT_MULTI:
2833 case PACKET3_DRAW_INDEX_AUTO:
2834 case PACKET3_DRAW_INDEX_IMMD:
2835 case PACKET3_NUM_INSTANCES:
2836 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2837 case PACKET3_STRMOUT_BUFFER_UPDATE:
2838 case PACKET3_DRAW_INDEX_OFFSET_2:
2839 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2840 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2841 case PACKET3_MPEG_INDEX:
2842 case PACKET3_WAIT_REG_MEM:
2843 case PACKET3_MEM_WRITE:
2844 case PACKET3_PFP_SYNC_ME:
2845 case PACKET3_SURFACE_SYNC:
2846 case PACKET3_EVENT_WRITE:
2847 case PACKET3_EVENT_WRITE_EOP:
2848 case PACKET3_EVENT_WRITE_EOS:
2849 case PACKET3_SET_CONTEXT_REG:
2850 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2851 case PACKET3_SET_SH_REG:
2852 case PACKET3_SET_SH_REG_OFFSET:
2853 case PACKET3_INCREMENT_DE_COUNTER:
2854 case PACKET3_WAIT_ON_CE_COUNTER:
2855 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2856 case PACKET3_ME_WRITE:
2857 break;
2858 case PACKET3_COPY_DATA:
2859 if ((idx_value & 0xf00) == 0) {
2860 reg = ib[idx + 3] * 4;
2861 if (!si_vm_reg_valid(reg))
2862 return -EINVAL;
2863 }
2864 break;
2865 case PACKET3_WRITE_DATA:
2866 if ((idx_value & 0xf00) == 0) {
2867 start_reg = ib[idx + 1] * 4;
2868 if (idx_value & 0x10000) {
2869 if (!si_vm_reg_valid(start_reg))
2870 return -EINVAL;
2871 } else {
2872 for (i = 0; i < (pkt->count - 2); i++) {
2873 reg = start_reg + (4 * i);
2874 if (!si_vm_reg_valid(reg))
2875 return -EINVAL;
2876 }
2877 }
2878 }
2879 break;
2880 case PACKET3_COND_WRITE:
2881 if (idx_value & 0x100) {
2882 reg = ib[idx + 5] * 4;
2883 if (!si_vm_reg_valid(reg))
2884 return -EINVAL;
2885 }
2886 break;
2887 case PACKET3_COPY_DW:
2888 if (idx_value & 0x2) {
2889 reg = ib[idx + 3] * 4;
2890 if (!si_vm_reg_valid(reg))
2891 return -EINVAL;
2892 }
2893 break;
2894 case PACKET3_SET_CONFIG_REG:
2895 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2896 end_reg = 4 * pkt->count + start_reg - 4;
2897 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2898 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2899 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2900 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2901 return -EINVAL;
2902 }
2903 for (i = 0; i < pkt->count; i++) {
2904 reg = start_reg + (4 * i);
2905 if (!si_vm_reg_valid(reg))
2906 return -EINVAL;
2907 }
2908 break;
5aa709be
AD		 2909 case PACKET3_CP_DMA:
2910 command = ib[idx + 4];
2911 info = ib[idx + 1];
2912 if (command & PACKET3_CP_DMA_CMD_SAS) {
2913 /* src address space is register */
2914 if (((info & 0x60000000) >> 29) == 0) {
2915 start_reg = idx_value << 2;
2916 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2917 reg = start_reg;
2918 if (!si_vm_reg_valid(reg)) {
2919 DRM_ERROR("CP DMA Bad SRC register\n");
2920 return -EINVAL;
2921 }
2922 } else {
2923 for (i = 0; i < (command & 0x1fffff); i++) {
2924 reg = start_reg + (4 * i);
2925 if (!si_vm_reg_valid(reg)) {
2926 DRM_ERROR("CP DMA Bad SRC register\n");
2927 return -EINVAL;
2928 }
2929 }
2930 }
2931 }
2932 }
2933 if (command & PACKET3_CP_DMA_CMD_DAS) {
2934 /* dst address space is register */
2935 if (((info & 0x00300000) >> 20) == 0) {
2936 start_reg = ib[idx + 2];
2937 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2938 reg = start_reg;
2939 if (!si_vm_reg_valid(reg)) {
2940 DRM_ERROR("CP DMA Bad DST register\n");
2941 return -EINVAL;
2942 }
2943 } else {
2944 for (i = 0; i < (command & 0x1fffff); i++) {
2945 reg = start_reg + (4 * i);
2946 if (!si_vm_reg_valid(reg)) {
2947 DRM_ERROR("CP DMA Bad DST register\n");
2948 return -EINVAL;
2949 }
2950 }
2951 }
2952 }
2953 }
2954 break;
498dd8b3
AD		 2955 default:
2956 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2957 return -EINVAL;
2958 }
2959 return 0;
2960}
2961
2962static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2963 u32 *ib, struct radeon_cs_packet *pkt)
2964{
2965 u32 idx = pkt->idx + 1;
2966 u32 idx_value = ib[idx];
2967 u32 start_reg, reg, i;
2968
2969 switch (pkt->opcode) {
2970 case PACKET3_NOP:
2971 case PACKET3_SET_BASE:
2972 case PACKET3_CLEAR_STATE:
2973 case PACKET3_DISPATCH_DIRECT:
2974 case PACKET3_DISPATCH_INDIRECT:
2975 case PACKET3_ALLOC_GDS:
2976 case PACKET3_WRITE_GDS_RAM:
2977 case PACKET3_ATOMIC_GDS:
2978 case PACKET3_ATOMIC:
2979 case PACKET3_OCCLUSION_QUERY:
2980 case PACKET3_SET_PREDICATION:
2981 case PACKET3_COND_EXEC:
2982 case PACKET3_PRED_EXEC:
2983 case PACKET3_CONTEXT_CONTROL:
2984 case PACKET3_STRMOUT_BUFFER_UPDATE:
2985 case PACKET3_WAIT_REG_MEM:
2986 case PACKET3_MEM_WRITE:
2987 case PACKET3_PFP_SYNC_ME:
2988 case PACKET3_SURFACE_SYNC:
2989 case PACKET3_EVENT_WRITE:
2990 case PACKET3_EVENT_WRITE_EOP:
2991 case PACKET3_EVENT_WRITE_EOS:
2992 case PACKET3_SET_CONTEXT_REG:
2993 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2994 case PACKET3_SET_SH_REG:
2995 case PACKET3_SET_SH_REG_OFFSET:
2996 case PACKET3_INCREMENT_DE_COUNTER:
2997 case PACKET3_WAIT_ON_CE_COUNTER:
2998 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2999 case PACKET3_ME_WRITE:
3000 break;
3001 case PACKET3_COPY_DATA:
3002 if ((idx_value & 0xf00) == 0) {
3003 reg = ib[idx + 3] * 4;
3004 if (!si_vm_reg_valid(reg))
3005 return -EINVAL;
3006 }
3007 break;
3008 case PACKET3_WRITE_DATA:
3009 if ((idx_value & 0xf00) == 0) {
3010 start_reg = ib[idx + 1] * 4;
3011 if (idx_value & 0x10000) {
3012 if (!si_vm_reg_valid(start_reg))
3013 return -EINVAL;
3014 } else {
3015 for (i = 0; i < (pkt->count - 2); i++) {
3016 reg = start_reg + (4 * i);
3017 if (!si_vm_reg_valid(reg))
3018 return -EINVAL;
3019 }
3020 }
3021 }
3022 break;
3023 case PACKET3_COND_WRITE:
3024 if (idx_value & 0x100) {
3025 reg = ib[idx + 5] * 4;
3026 if (!si_vm_reg_valid(reg))
3027 return -EINVAL;
3028 }
3029 break;
3030 case PACKET3_COPY_DW:
3031 if (idx_value & 0x2) {
3032 reg = ib[idx + 3] * 4;
3033 if (!si_vm_reg_valid(reg))
3034 return -EINVAL;
3035 }
3036 break;
3037 default:
3038 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
3039 return -EINVAL;
3040 }
3041 return 0;
3042}
3043
3044int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3045{
3046 int ret = 0;
3047 u32 idx = 0;
3048 struct radeon_cs_packet pkt;
3049
3050 do {
3051 pkt.idx = idx;
4e872ae2
IH		 3052 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
3053 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
498dd8b3
AD		 3054 pkt.one_reg_wr = 0;
3055 switch (pkt.type) {
4e872ae2 3056 case RADEON_PACKET_TYPE0:
498dd8b3
AD		 3057 dev_err(rdev->dev, "Packet0 not allowed!\n");
3058 ret = -EINVAL;
3059 break;
4e872ae2 3060 case RADEON_PACKET_TYPE2:
498dd8b3
AD		 3061 idx += 1;
3062 break;
4e872ae2
IH		 3063 case RADEON_PACKET_TYPE3:
3064 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
498dd8b3
AD		 3065 if (ib->is_const_ib)
3066 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
3067 else {
876dc9f3 3068 switch (ib->ring) {
498dd8b3
AD		 3069 case RADEON_RING_TYPE_GFX_INDEX:
3070 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
3071 break;
3072 case CAYMAN_RING_TYPE_CP1_INDEX:
3073 case CAYMAN_RING_TYPE_CP2_INDEX:
3074 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
3075 break;
3076 default:
876dc9f3 3077 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
498dd8b3
AD		 3078 ret = -EINVAL;
3079 break;
3080 }
3081 }
3082 idx += pkt.count + 2;
3083 break;
3084 default:
3085 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3086 ret = -EINVAL;
3087 break;
3088 }
3089 if (ret)
3090 break;
3091 } while (idx < ib->length_dw);
3092
3093 return ret;
3094}
3095
d2800ee5
AD		 3096/*
3097 * vm
3098 */
3099int si_vm_init(struct radeon_device *rdev)
3100{
3101 /* number of VMs */
3102 rdev->vm_manager.nvm = 16;
3103 /* base offset of vram pages */
3104 rdev->vm_manager.vram_base_offset = 0;
3105
3106 return 0;
3107}
3108
3109void si_vm_fini(struct radeon_device *rdev)
3110{
3111}
3112
82ffd92b
AD		 3113/**
3114 * si_vm_set_page - update the page tables using the CP
3115 *
3116 * @rdev: radeon_device pointer
43f1214a 3117 * @ib: indirect buffer to fill with commands
82ffd92b
AD		 3118 * @pe: addr of the page entry
3119 * @addr: dst addr to write into pe
3120 * @count: number of page entries to update
3121 * @incr: increase next addr by incr bytes
3122 * @flags: access flags
3123 *
43f1214a 3124 * Update the page tables using the CP (SI).
82ffd92b 3125 */
43f1214a
AD		 3126void si_vm_set_page(struct radeon_device *rdev,
3127 struct radeon_ib *ib,
3128 uint64_t pe,
82ffd92b
AD		 3129 uint64_t addr, unsigned count,
3130 uint32_t incr, uint32_t flags)
d2800ee5 3131{
82ffd92b 3132 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
deab48f1
AD		 3133 uint64_t value;
3134 unsigned ndw;
3135
3136 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
3137 while (count) {
3138 ndw = 2 + count * 2;
3139 if (ndw > 0x3FFE)
3140 ndw = 0x3FFE;
3141
43f1214a
AD		 3142 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
3143 ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
3144 WRITE_DATA_DST_SEL(1));
3145 ib->ptr[ib->length_dw++] = pe;
3146 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
deab48f1
AD		 3147 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3148 if (flags & RADEON_VM_PAGE_SYSTEM) {
3149 value = radeon_vm_map_gart(rdev, addr);
3150 value &= 0xFFFFFFFFFFFFF000ULL;
3151 } else if (flags & RADEON_VM_PAGE_VALID) {
3152 value = addr;
3153 } else {
3154 value = 0;
3155 }
3156 addr += incr;
3157 value |= r600_flags;
43f1214a
AD		 3158 ib->ptr[ib->length_dw++] = value;
3159 ib->ptr[ib->length_dw++] = upper_32_bits(value);
deab48f1
AD		 3160 }
3161 }
3162 } else {
3163 /* DMA */
3164 if (flags & RADEON_VM_PAGE_SYSTEM) {
3165 while (count) {
3166 ndw = count * 2;
3167 if (ndw > 0xFFFFE)
3168 ndw = 0xFFFFE;
3169
3170 /* for non-physically contiguous pages (system) */
43f1214a
AD		 3171 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
3172 ib->ptr[ib->length_dw++] = pe;
3173 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
deab48f1
AD		 3174 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3175 if (flags & RADEON_VM_PAGE_SYSTEM) {
3176 value = radeon_vm_map_gart(rdev, addr);
3177 value &= 0xFFFFFFFFFFFFF000ULL;
3178 } else if (flags & RADEON_VM_PAGE_VALID) {
3179 value = addr;
3180 } else {
3181 value = 0;
3182 }
3183 addr += incr;
3184 value |= r600_flags;
43f1214a
AD		 3185 ib->ptr[ib->length_dw++] = value;
3186 ib->ptr[ib->length_dw++] = upper_32_bits(value);
deab48f1
AD		 3187 }
3188 }
3189 } else {
3190 while (count) {
3191 ndw = count * 2;
3192 if (ndw > 0xFFFFE)
3193 ndw = 0xFFFFE;
3194
3195 if (flags & RADEON_VM_PAGE_VALID)
3196 value = addr;
3197 else
3198 value = 0;
3199 /* for physically contiguous pages (vram) */
43f1214a
AD		 3200 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
3201 ib->ptr[ib->length_dw++] = pe; /* dst addr */
3202 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3203 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
3204 ib->ptr[ib->length_dw++] = 0;
3205 ib->ptr[ib->length_dw++] = value; /* value */
3206 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3207 ib->ptr[ib->length_dw++] = incr; /* increment size */
3208 ib->ptr[ib->length_dw++] = 0;
deab48f1
AD		 3209 pe += ndw * 4;
3210 addr += (ndw / 2) * incr;
3211 count -= ndw / 2;
3212 }
d7025d89 3213 }
43f1214a
AD		 3214 while (ib->length_dw & 0x7)
3215 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);
82ffd92b 3216 }
d2800ee5
AD		 3217}
3218
498522b4 3219void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
d2800ee5 3220{
498522b4 3221 struct radeon_ring *ring = &rdev->ring[ridx];
d2800ee5 3222
ee60e29f 3223 if (vm == NULL)
d2800ee5
AD		 3224 return;
3225
76c44f2c
AD		 3226 /* write new base address */
3227 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3228 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3229 WRITE_DATA_DST_SEL(0)));
3230
ee60e29f 3231 if (vm->id < 8) {
76c44f2c
AD		 3232 radeon_ring_write(ring,
3233 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
ee60e29f 3234 } else {
76c44f2c
AD		 3235 radeon_ring_write(ring,
3236 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
ee60e29f 3237 }
76c44f2c 3238 radeon_ring_write(ring, 0);
fa87e62d 3239 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 3240
d2800ee5 3241 /* flush hdp cache */
76c44f2c
AD		 3242 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3243 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3244 WRITE_DATA_DST_SEL(0)));
3245 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3246 radeon_ring_write(ring, 0);
ee60e29f
CK		 3247 radeon_ring_write(ring, 0x1);
3248
d2800ee5 3249 /* bits 0-15 are the VM contexts0-15 */
76c44f2c
AD		 3250 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3251 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3252 WRITE_DATA_DST_SEL(0)));
3253 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3254 radeon_ring_write(ring, 0);
498522b4 3255 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 3256
3257 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3258 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3259 radeon_ring_write(ring, 0x0);
d2800ee5
AD		 3260}
3261
8c5fd7ef
AD		 3262void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3263{
3264 struct radeon_ring *ring = &rdev->ring[ridx];
3265
3266 if (vm == NULL)
3267 return;
3268
3269 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3270 if (vm->id < 8) {
3271 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3272 } else {
3273 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3274 }
3275 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3276
3277 /* flush hdp cache */
3278 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3279 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3280 radeon_ring_write(ring, 1);
3281
3282 /* bits 0-7 are the VM contexts0-7 */
3283 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3284 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3285 radeon_ring_write(ring, 1 << vm->id);
3286}
3287
347e7592
AD		 3288/*
3289 * RLC
3290 */
c420c745 3291void si_rlc_fini(struct radeon_device *rdev)
347e7592
AD		 3292{
3293 int r;
3294
3295 /* save restore block */
3296 if (rdev->rlc.save_restore_obj) {
3297 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3298 if (unlikely(r != 0))
3299 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3300 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3301 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3302
3303 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3304 rdev->rlc.save_restore_obj = NULL;
3305 }
3306
3307 /* clear state block */
3308 if (rdev->rlc.clear_state_obj) {
3309 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3310 if (unlikely(r != 0))
3311 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3312 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3313 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3314
3315 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3316 rdev->rlc.clear_state_obj = NULL;
3317 }
3318}
3319
c420c745 3320int si_rlc_init(struct radeon_device *rdev)
347e7592
AD		 3321{
3322 int r;
3323
3324 /* save restore block */
3325 if (rdev->rlc.save_restore_obj == NULL) {
3326 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3327 RADEON_GEM_DOMAIN_VRAM, NULL,
3328 &rdev->rlc.save_restore_obj);
347e7592
AD		 3329 if (r) {
3330 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3331 return r;
3332 }
3333 }
3334
3335 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3336 if (unlikely(r != 0)) {
3337 si_rlc_fini(rdev);
3338 return r;
3339 }
3340 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3341 &rdev->rlc.save_restore_gpu_addr);
5273db70 3342 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
347e7592 3343 if (r) {
347e7592
AD		 3344 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3345 si_rlc_fini(rdev);
3346 return r;
3347 }
3348
3349 /* clear state block */
3350 if (rdev->rlc.clear_state_obj == NULL) {
3351 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3352 RADEON_GEM_DOMAIN_VRAM, NULL,
3353 &rdev->rlc.clear_state_obj);
347e7592
AD		 3354 if (r) {
3355 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3356 si_rlc_fini(rdev);
3357 return r;
3358 }
3359 }
3360 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3361 if (unlikely(r != 0)) {
3362 si_rlc_fini(rdev);
3363 return r;
3364 }
3365 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3366 &rdev->rlc.clear_state_gpu_addr);
5273db70 3367 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
347e7592 3368 if (r) {
347e7592
AD		 3369 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3370 si_rlc_fini(rdev);
3371 return r;
3372 }
3373
3374 return 0;
3375}
3376
3377static void si_rlc_stop(struct radeon_device *rdev)
3378{
3379 WREG32(RLC_CNTL, 0);
3380}
3381
3382static void si_rlc_start(struct radeon_device *rdev)
3383{
3384 WREG32(RLC_CNTL, RLC_ENABLE);
3385}
3386
3387static int si_rlc_resume(struct radeon_device *rdev)
3388{
3389 u32 i;
3390 const __be32 *fw_data;
3391
3392 if (!rdev->rlc_fw)
3393 return -EINVAL;
3394
3395 si_rlc_stop(rdev);
3396
3397 WREG32(RLC_RL_BASE, 0);
3398 WREG32(RLC_RL_SIZE, 0);
3399 WREG32(RLC_LB_CNTL, 0);
3400 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3401 WREG32(RLC_LB_CNTR_INIT, 0);
3402
3403 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3404 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3405
3406 WREG32(RLC_MC_CNTL, 0);
3407 WREG32(RLC_UCODE_CNTL, 0);
3408
3409 fw_data = (const __be32 *)rdev->rlc_fw->data;
3410 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3411 WREG32(RLC_UCODE_ADDR, i);
3412 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3413 }
3414 WREG32(RLC_UCODE_ADDR, 0);
3415
3416 si_rlc_start(rdev);
3417
3418 return 0;
3419}
3420
25a857fb
AD		 3421static void si_enable_interrupts(struct radeon_device *rdev)
3422{
3423 u32 ih_cntl = RREG32(IH_CNTL);
3424 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3425
3426 ih_cntl |= ENABLE_INTR;
3427 ih_rb_cntl |= IH_RB_ENABLE;
3428 WREG32(IH_CNTL, ih_cntl);
3429 WREG32(IH_RB_CNTL, ih_rb_cntl);
3430 rdev->ih.enabled = true;
3431}
3432
3433static void si_disable_interrupts(struct radeon_device *rdev)
3434{
3435 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3436 u32 ih_cntl = RREG32(IH_CNTL);
3437
3438 ih_rb_cntl &= ~IH_RB_ENABLE;
3439 ih_cntl &= ~ENABLE_INTR;
3440 WREG32(IH_RB_CNTL, ih_rb_cntl);
3441 WREG32(IH_CNTL, ih_cntl);
3442 /* set rptr, wptr to 0 */
3443 WREG32(IH_RB_RPTR, 0);
3444 WREG32(IH_RB_WPTR, 0);
3445 rdev->ih.enabled = false;
25a857fb
AD		 3446 rdev->ih.rptr = 0;
3447}
3448
3449static void si_disable_interrupt_state(struct radeon_device *rdev)
3450{
3451 u32 tmp;
3452
3453 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3454 WREG32(CP_INT_CNTL_RING1, 0);
3455 WREG32(CP_INT_CNTL_RING2, 0);
8c5fd7ef
AD		 3456 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3457 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3458 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3459 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
25a857fb
AD		 3460 WREG32(GRBM_INT_CNTL, 0);
3461 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3462 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3463 if (rdev->num_crtc >= 4) {
3464 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3465 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3466 }
3467 if (rdev->num_crtc >= 6) {
3468 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3469 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3470 }
3471
3472 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3473 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3474 if (rdev->num_crtc >= 4) {
3475 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3476 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3477 }
3478 if (rdev->num_crtc >= 6) {
3479 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3480 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3481 }
3482
3483 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3484
3485 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3486 WREG32(DC_HPD1_INT_CONTROL, tmp);
3487 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3488 WREG32(DC_HPD2_INT_CONTROL, tmp);
3489 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3490 WREG32(DC_HPD3_INT_CONTROL, tmp);
3491 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3492 WREG32(DC_HPD4_INT_CONTROL, tmp);
3493 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3494 WREG32(DC_HPD5_INT_CONTROL, tmp);
3495 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3496 WREG32(DC_HPD6_INT_CONTROL, tmp);
3497
3498}
3499
3500static int si_irq_init(struct radeon_device *rdev)
3501{
3502 int ret = 0;
3503 int rb_bufsz;
3504 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3505
3506 /* allocate ring */
3507 ret = r600_ih_ring_alloc(rdev);
3508 if (ret)
3509 return ret;
3510
3511 /* disable irqs */
3512 si_disable_interrupts(rdev);
3513
3514 /* init rlc */
3515 ret = si_rlc_resume(rdev);
3516 if (ret) {
3517 r600_ih_ring_fini(rdev);
3518 return ret;
3519 }
3520
3521 /* setup interrupt control */
3522 /* set dummy read address to ring address */
3523 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3524 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3525 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3526 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3527 */
3528 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3529 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3530 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3531 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3532
3533 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3534 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3535
3536 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3537 IH_WPTR_OVERFLOW_CLEAR |
3538 (rb_bufsz << 1));
3539
3540 if (rdev->wb.enabled)
3541 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3542
3543 /* set the writeback address whether it's enabled or not */
3544 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3545 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3546
3547 WREG32(IH_RB_CNTL, ih_rb_cntl);
3548
3549 /* set rptr, wptr to 0 */
3550 WREG32(IH_RB_RPTR, 0);
3551 WREG32(IH_RB_WPTR, 0);
3552
3553 /* Default settings for IH_CNTL (disabled at first) */
3554 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3555 /* RPTR_REARM only works if msi's are enabled */
3556 if (rdev->msi_enabled)
3557 ih_cntl |= RPTR_REARM;
3558 WREG32(IH_CNTL, ih_cntl);
3559
3560 /* force the active interrupt state to all disabled */
3561 si_disable_interrupt_state(rdev);
3562
2099810f
DA		 3563 pci_set_master(rdev->pdev);
3564
25a857fb
AD		 3565 /* enable irqs */
3566 si_enable_interrupts(rdev);
3567
3568 return ret;
3569}
3570
3571int si_irq_set(struct radeon_device *rdev)
3572{
3573 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3574 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3575 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3576 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3577 u32 grbm_int_cntl = 0;
3578 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
8c5fd7ef 3579 u32 dma_cntl, dma_cntl1;
25a857fb
AD		 3580
3581 if (!rdev->irq.installed) {
3582 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3583 return -EINVAL;
3584 }
3585 /* don't enable anything if the ih is disabled */
3586 if (!rdev->ih.enabled) {
3587 si_disable_interrupts(rdev);
3588 /* force the active interrupt state to all disabled */
3589 si_disable_interrupt_state(rdev);
3590 return 0;
3591 }
3592
3593 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3594 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3595 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3596 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3597 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3598 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3599
8c5fd7ef
AD		 3600 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3601 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3602
25a857fb 3603 /* enable CP interrupts on all rings */
736fc37f 3604 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
25a857fb
AD		 3605 DRM_DEBUG("si_irq_set: sw int gfx\n");
3606 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3607 }
736fc37f 3608 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
25a857fb
AD		 3609 DRM_DEBUG("si_irq_set: sw int cp1\n");
3610 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3611 }
736fc37f 3612 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
25a857fb
AD		 3613 DRM_DEBUG("si_irq_set: sw int cp2\n");
3614 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3615 }
8c5fd7ef
AD		 3616 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3617 DRM_DEBUG("si_irq_set: sw int dma\n");
3618 dma_cntl |= TRAP_ENABLE;
3619 }
3620
3621 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3622 DRM_DEBUG("si_irq_set: sw int dma1\n");
3623 dma_cntl1 |= TRAP_ENABLE;
3624 }
25a857fb 3625 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3626 atomic_read(&rdev->irq.pflip[0])) {
25a857fb
AD		 3627 DRM_DEBUG("si_irq_set: vblank 0\n");
3628 crtc1 |= VBLANK_INT_MASK;
3629 }
3630 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3631 atomic_read(&rdev->irq.pflip[1])) {
25a857fb
AD		 3632 DRM_DEBUG("si_irq_set: vblank 1\n");
3633 crtc2 |= VBLANK_INT_MASK;
3634 }
3635 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3636 atomic_read(&rdev->irq.pflip[2])) {
25a857fb
AD		 3637 DRM_DEBUG("si_irq_set: vblank 2\n");
3638 crtc3 |= VBLANK_INT_MASK;
3639 }
3640 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3641 atomic_read(&rdev->irq.pflip[3])) {
25a857fb
AD		 3642 DRM_DEBUG("si_irq_set: vblank 3\n");
3643 crtc4 |= VBLANK_INT_MASK;
3644 }
3645 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3646 atomic_read(&rdev->irq.pflip[4])) {
25a857fb
AD		 3647 DRM_DEBUG("si_irq_set: vblank 4\n");
3648 crtc5 |= VBLANK_INT_MASK;
3649 }
3650 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3651 atomic_read(&rdev->irq.pflip[5])) {
25a857fb
AD		 3652 DRM_DEBUG("si_irq_set: vblank 5\n");
3653 crtc6 |= VBLANK_INT_MASK;
3654 }
3655 if (rdev->irq.hpd[0]) {
3656 DRM_DEBUG("si_irq_set: hpd 1\n");
3657 hpd1 |= DC_HPDx_INT_EN;
3658 }
3659 if (rdev->irq.hpd[1]) {
3660 DRM_DEBUG("si_irq_set: hpd 2\n");
3661 hpd2 |= DC_HPDx_INT_EN;
3662 }
3663 if (rdev->irq.hpd[2]) {
3664 DRM_DEBUG("si_irq_set: hpd 3\n");
3665 hpd3 |= DC_HPDx_INT_EN;
3666 }
3667 if (rdev->irq.hpd[3]) {
3668 DRM_DEBUG("si_irq_set: hpd 4\n");
3669 hpd4 |= DC_HPDx_INT_EN;
3670 }
3671 if (rdev->irq.hpd[4]) {
3672 DRM_DEBUG("si_irq_set: hpd 5\n");
3673 hpd5 |= DC_HPDx_INT_EN;
3674 }
3675 if (rdev->irq.hpd[5]) {
3676 DRM_DEBUG("si_irq_set: hpd 6\n");
3677 hpd6 |= DC_HPDx_INT_EN;
3678 }
25a857fb
AD		 3679
3680 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3681 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3682 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3683
8c5fd7ef
AD		 3684 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3685 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3686
25a857fb
AD		 3687 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3688
3689 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3690 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3691 if (rdev->num_crtc >= 4) {
3692 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3693 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3694 }
3695 if (rdev->num_crtc >= 6) {
3696 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3697 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3698 }
3699
3700 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3701 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3702 if (rdev->num_crtc >= 4) {
3703 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3704 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3705 }
3706 if (rdev->num_crtc >= 6) {
3707 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3708 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3709 }
3710
3711 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3712 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3713 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3714 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3715 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3716 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3717
3718 return 0;
3719}
3720
3721static inline void si_irq_ack(struct radeon_device *rdev)
3722{
3723 u32 tmp;
3724
3725 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3726 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3727 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3728 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3729 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3730 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3731 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3732 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3733 if (rdev->num_crtc >= 4) {
3734 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3735 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3736 }
3737 if (rdev->num_crtc >= 6) {
3738 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3739 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3740 }
3741
3742 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3743 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3744 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3745 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3746 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3747 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3748 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3749 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3750 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3751 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3752 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3753 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3754
3755 if (rdev->num_crtc >= 4) {
3756 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3757 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3758 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3759 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3760 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3761 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3762 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3763 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3764 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3765 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3766 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3767 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3768 }
3769
3770 if (rdev->num_crtc >= 6) {
3771 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3772 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3773 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3774 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3775 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3776 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3777 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3778 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3779 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3780 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3781 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3782 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3783 }
3784
3785 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3786 tmp = RREG32(DC_HPD1_INT_CONTROL);
3787 tmp |= DC_HPDx_INT_ACK;
3788 WREG32(DC_HPD1_INT_CONTROL, tmp);
3789 }
3790 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3791 tmp = RREG32(DC_HPD2_INT_CONTROL);
3792 tmp |= DC_HPDx_INT_ACK;
3793 WREG32(DC_HPD2_INT_CONTROL, tmp);
3794 }
3795 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3796 tmp = RREG32(DC_HPD3_INT_CONTROL);
3797 tmp |= DC_HPDx_INT_ACK;
3798 WREG32(DC_HPD3_INT_CONTROL, tmp);
3799 }
3800 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3801 tmp = RREG32(DC_HPD4_INT_CONTROL);
3802 tmp |= DC_HPDx_INT_ACK;
3803 WREG32(DC_HPD4_INT_CONTROL, tmp);
3804 }
3805 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3806 tmp = RREG32(DC_HPD5_INT_CONTROL);
3807 tmp |= DC_HPDx_INT_ACK;
3808 WREG32(DC_HPD5_INT_CONTROL, tmp);
3809 }
3810 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3811 tmp = RREG32(DC_HPD5_INT_CONTROL);
3812 tmp |= DC_HPDx_INT_ACK;
3813 WREG32(DC_HPD6_INT_CONTROL, tmp);
3814 }
3815}
3816
3817static void si_irq_disable(struct radeon_device *rdev)
3818{
3819 si_disable_interrupts(rdev);
3820 /* Wait and acknowledge irq */
3821 mdelay(1);
3822 si_irq_ack(rdev);
3823 si_disable_interrupt_state(rdev);
3824}
3825
3826static void si_irq_suspend(struct radeon_device *rdev)
3827{
3828 si_irq_disable(rdev);
3829 si_rlc_stop(rdev);
3830}
3831
9b136d51
AD		 3832static void si_irq_fini(struct radeon_device *rdev)
3833{
3834 si_irq_suspend(rdev);
3835 r600_ih_ring_fini(rdev);
3836}
3837
25a857fb
AD		 3838static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3839{
3840 u32 wptr, tmp;
3841
3842 if (rdev->wb.enabled)
3843 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3844 else
3845 wptr = RREG32(IH_RB_WPTR);
3846
3847 if (wptr & RB_OVERFLOW) {
3848 /* When a ring buffer overflow happen start parsing interrupt
3849 * from the last not overwritten vector (wptr + 16). Hopefully
3850 * this should allow us to catchup.
3851 */
3852 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3853 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3854 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3855 tmp = RREG32(IH_RB_CNTL);
3856 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3857 WREG32(IH_RB_CNTL, tmp);
3858 }
3859 return (wptr & rdev->ih.ptr_mask);
3860}
3861
3862/* SI IV Ring
3863 * Each IV ring entry is 128 bits:
3864 * [7:0] - interrupt source id
3865 * [31:8] - reserved
3866 * [59:32] - interrupt source data
3867 * [63:60] - reserved
3868 * [71:64] - RINGID
3869 * [79:72] - VMID
3870 * [127:80] - reserved
3871 */
3872int si_irq_process(struct radeon_device *rdev)
3873{
3874 u32 wptr;
3875 u32 rptr;
3876 u32 src_id, src_data, ring_id;
3877 u32 ring_index;
25a857fb
AD		 3878 bool queue_hotplug = false;
3879
3880 if (!rdev->ih.enabled || rdev->shutdown)
3881 return IRQ_NONE;
3882
3883 wptr = si_get_ih_wptr(rdev);
c20dc369
CK		 3884
3885restart_ih:
3886 /* is somebody else already processing irqs? */
3887 if (atomic_xchg(&rdev->ih.lock, 1))
3888 return IRQ_NONE;
3889
25a857fb
AD		 3890 rptr = rdev->ih.rptr;
3891 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3892
25a857fb
AD		 3893 /* Order reading of wptr vs. reading of IH ring data */
3894 rmb();
3895
3896 /* display interrupts */
3897 si_irq_ack(rdev);
3898
25a857fb
AD		 3899 while (rptr != wptr) {
3900 /* wptr/rptr are in bytes! */
3901 ring_index = rptr / 4;
3902 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3903 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3904 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3905
3906 switch (src_id) {
3907 case 1: /* D1 vblank/vline */
3908 switch (src_data) {
3909 case 0: /* D1 vblank */
3910 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3911 if (rdev->irq.crtc_vblank_int[0]) {
3912 drm_handle_vblank(rdev->ddev, 0);
3913 rdev->pm.vblank_sync = true;
3914 wake_up(&rdev->irq.vblank_queue);
3915 }
736fc37f 3916 if (atomic_read(&rdev->irq.pflip[0]))
25a857fb
AD		 3917 radeon_crtc_handle_flip(rdev, 0);
3918 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3919 DRM_DEBUG("IH: D1 vblank\n");
3920 }
3921 break;
3922 case 1: /* D1 vline */
3923 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3924 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3925 DRM_DEBUG("IH: D1 vline\n");
3926 }
3927 break;
3928 default:
3929 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3930 break;
3931 }
3932 break;
3933 case 2: /* D2 vblank/vline */
3934 switch (src_data) {
3935 case 0: /* D2 vblank */
3936 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3937 if (rdev->irq.crtc_vblank_int[1]) {
3938 drm_handle_vblank(rdev->ddev, 1);
3939 rdev->pm.vblank_sync = true;
3940 wake_up(&rdev->irq.vblank_queue);
3941 }
736fc37f 3942 if (atomic_read(&rdev->irq.pflip[1]))
25a857fb
AD		 3943 radeon_crtc_handle_flip(rdev, 1);
3944 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3945 DRM_DEBUG("IH: D2 vblank\n");
3946 }
3947 break;
3948 case 1: /* D2 vline */
3949 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3950 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3951 DRM_DEBUG("IH: D2 vline\n");
3952 }
3953 break;
3954 default:
3955 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3956 break;
3957 }
3958 break;
3959 case 3: /* D3 vblank/vline */
3960 switch (src_data) {
3961 case 0: /* D3 vblank */
3962 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3963 if (rdev->irq.crtc_vblank_int[2]) {
3964 drm_handle_vblank(rdev->ddev, 2);
3965 rdev->pm.vblank_sync = true;
3966 wake_up(&rdev->irq.vblank_queue);
3967 }
736fc37f 3968 if (atomic_read(&rdev->irq.pflip[2]))
25a857fb
AD		 3969 radeon_crtc_handle_flip(rdev, 2);
3970 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3971 DRM_DEBUG("IH: D3 vblank\n");
3972 }
3973 break;
3974 case 1: /* D3 vline */
3975 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3976 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3977 DRM_DEBUG("IH: D3 vline\n");
3978 }
3979 break;
3980 default:
3981 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3982 break;
3983 }
3984 break;
3985 case 4: /* D4 vblank/vline */
3986 switch (src_data) {
3987 case 0: /* D4 vblank */
3988 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3989 if (rdev->irq.crtc_vblank_int[3]) {
3990 drm_handle_vblank(rdev->ddev, 3);
3991 rdev->pm.vblank_sync = true;
3992 wake_up(&rdev->irq.vblank_queue);
3993 }
736fc37f 3994 if (atomic_read(&rdev->irq.pflip[3]))
25a857fb
AD		 3995 radeon_crtc_handle_flip(rdev, 3);
3996 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3997 DRM_DEBUG("IH: D4 vblank\n");
3998 }
3999 break;
4000 case 1: /* D4 vline */
4001 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
4002 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
4003 DRM_DEBUG("IH: D4 vline\n");
4004 }
4005 break;
4006 default:
4007 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4008 break;
4009 }
4010 break;
4011 case 5: /* D5 vblank/vline */
4012 switch (src_data) {
4013 case 0: /* D5 vblank */
4014 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
4015 if (rdev->irq.crtc_vblank_int[4]) {
4016 drm_handle_vblank(rdev->ddev, 4);
4017 rdev->pm.vblank_sync = true;
4018 wake_up(&rdev->irq.vblank_queue);
4019 }
736fc37f 4020 if (atomic_read(&rdev->irq.pflip[4]))
25a857fb
AD		 4021 radeon_crtc_handle_flip(rdev, 4);
4022 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
4023 DRM_DEBUG("IH: D5 vblank\n");
4024 }
4025 break;
4026 case 1: /* D5 vline */
4027 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
4028 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
4029 DRM_DEBUG("IH: D5 vline\n");
4030 }
4031 break;
4032 default:
4033 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4034 break;
4035 }
4036 break;
4037 case 6: /* D6 vblank/vline */
4038 switch (src_data) {
4039 case 0: /* D6 vblank */
4040 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
4041 if (rdev->irq.crtc_vblank_int[5]) {
4042 drm_handle_vblank(rdev->ddev, 5);
4043 rdev->pm.vblank_sync = true;
4044 wake_up(&rdev->irq.vblank_queue);
4045 }
736fc37f 4046 if (atomic_read(&rdev->irq.pflip[5]))
25a857fb
AD		 4047 radeon_crtc_handle_flip(rdev, 5);
4048 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
4049 DRM_DEBUG("IH: D6 vblank\n");
4050 }
4051 break;
4052 case 1: /* D6 vline */
4053 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
4054 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
4055 DRM_DEBUG("IH: D6 vline\n");
4056 }
4057 break;
4058 default:
4059 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4060 break;
4061 }
4062 break;
4063 case 42: /* HPD hotplug */
4064 switch (src_data) {
4065 case 0:
4066 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
4067 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
4068 queue_hotplug = true;
4069 DRM_DEBUG("IH: HPD1\n");
4070 }
4071 break;
4072 case 1:
4073 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
4074 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
4075 queue_hotplug = true;
4076 DRM_DEBUG("IH: HPD2\n");
4077 }
4078 break;
4079 case 2:
4080 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
4081 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
4082 queue_hotplug = true;
4083 DRM_DEBUG("IH: HPD3\n");
4084 }
4085 break;
4086 case 3:
4087 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
4088 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
4089 queue_hotplug = true;
4090 DRM_DEBUG("IH: HPD4\n");
4091 }
4092 break;
4093 case 4:
4094 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
4095 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
4096 queue_hotplug = true;
4097 DRM_DEBUG("IH: HPD5\n");
4098 }
4099 break;
4100 case 5:
4101 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4102 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
4103 queue_hotplug = true;
4104 DRM_DEBUG("IH: HPD6\n");
4105 }
4106 break;
4107 default:
4108 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4109 break;
4110 }
4111 break;
ae133a11
CK		 4112 case 146:
4113 case 147:
4114 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4115 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4116 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4117 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4118 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4119 /* reset addr and status */
4120 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4121 break;
25a857fb
AD		 4122 case 176: /* RINGID0 CP_INT */
4123 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4124 break;
4125 case 177: /* RINGID1 CP_INT */
4126 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4127 break;
4128 case 178: /* RINGID2 CP_INT */
4129 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4130 break;
4131 case 181: /* CP EOP event */
4132 DRM_DEBUG("IH: CP EOP\n");
4133 switch (ring_id) {
4134 case 0:
4135 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4136 break;
4137 case 1:
4138 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4139 break;
4140 case 2:
4141 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4142 break;
4143 }
4144 break;
8c5fd7ef
AD		 4145 case 224: /* DMA trap event */
4146 DRM_DEBUG("IH: DMA trap\n");
4147 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4148 break;
25a857fb
AD		 4149 case 233: /* GUI IDLE */
4150 DRM_DEBUG("IH: GUI idle\n");
25a857fb 4151 break;
8c5fd7ef
AD		 4152 case 244: /* DMA trap event */
4153 DRM_DEBUG("IH: DMA1 trap\n");
4154 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4155 break;
25a857fb
AD		 4156 default:
4157 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4158 break;
4159 }
4160
4161 /* wptr/rptr are in bytes! */
4162 rptr += 16;
4163 rptr &= rdev->ih.ptr_mask;
4164 }
25a857fb
AD		 4165 if (queue_hotplug)
4166 schedule_work(&rdev->hotplug_work);
4167 rdev->ih.rptr = rptr;
4168 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4169 atomic_set(&rdev->ih.lock, 0);
4170
4171 /* make sure wptr hasn't changed while processing */
4172 wptr = si_get_ih_wptr(rdev);
4173 if (wptr != rptr)
4174 goto restart_ih;
4175
25a857fb
AD		 4176 return IRQ_HANDLED;
4177}
4178
8c5fd7ef
AD		 4179/**
4180 * si_copy_dma - copy pages using the DMA engine
4181 *
4182 * @rdev: radeon_device pointer
4183 * @src_offset: src GPU address
4184 * @dst_offset: dst GPU address
4185 * @num_gpu_pages: number of GPU pages to xfer
4186 * @fence: radeon fence object
4187 *
4188 * Copy GPU paging using the DMA engine (SI).
4189 * Used by the radeon ttm implementation to move pages if
4190 * registered as the asic copy callback.
4191 */
4192int si_copy_dma(struct radeon_device *rdev,
4193 uint64_t src_offset, uint64_t dst_offset,
4194 unsigned num_gpu_pages,
4195 struct radeon_fence **fence)
4196{
4197 struct radeon_semaphore *sem = NULL;
4198 int ring_index = rdev->asic->copy.dma_ring_index;
4199 struct radeon_ring *ring = &rdev->ring[ring_index];
4200 u32 size_in_bytes, cur_size_in_bytes;
4201 int i, num_loops;
4202 int r = 0;
4203
4204 r = radeon_semaphore_create(rdev, &sem);
4205 if (r) {
4206 DRM_ERROR("radeon: moving bo (%d).\n", r);
4207 return r;
4208 }
4209
4210 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4211 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4212 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4213 if (r) {
4214 DRM_ERROR("radeon: moving bo (%d).\n", r);
4215 radeon_semaphore_free(rdev, &sem, NULL);
4216 return r;
4217 }
4218
4219 if (radeon_fence_need_sync(*fence, ring->idx)) {
4220 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4221 ring->idx);
4222 radeon_fence_note_sync(*fence, ring->idx);
4223 } else {
4224 radeon_semaphore_free(rdev, &sem, NULL);
4225 }
4226
4227 for (i = 0; i < num_loops; i++) {
4228 cur_size_in_bytes = size_in_bytes;
4229 if (cur_size_in_bytes > 0xFFFFF)
4230 cur_size_in_bytes = 0xFFFFF;
4231 size_in_bytes -= cur_size_in_bytes;
4232 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4233 radeon_ring_write(ring, dst_offset & 0xffffffff);
4234 radeon_ring_write(ring, src_offset & 0xffffffff);
4235 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4236 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4237 src_offset += cur_size_in_bytes;
4238 dst_offset += cur_size_in_bytes;
4239 }
4240
4241 r = radeon_fence_emit(rdev, fence, ring->idx);
4242 if (r) {
4243 radeon_ring_unlock_undo(rdev, ring);
4244 return r;
4245 }
4246
4247 radeon_ring_unlock_commit(rdev, ring);
4248 radeon_semaphore_free(rdev, &sem, *fence);
4249
4250 return r;
4251}
4252
9b136d51
AD		 4253/*
4254 * startup/shutdown callbacks
4255 */
4256static int si_startup(struct radeon_device *rdev)
4257{
4258 struct radeon_ring *ring;
4259 int r;
4260
4261 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4262 !rdev->rlc_fw || !rdev->mc_fw) {
4263 r = si_init_microcode(rdev);
4264 if (r) {
4265 DRM_ERROR("Failed to load firmware!\n");
4266 return r;
4267 }
4268 }
4269
4270 r = si_mc_load_microcode(rdev);
4271 if (r) {
4272 DRM_ERROR("Failed to load MC firmware!\n");
4273 return r;
4274 }
4275
4276 r = r600_vram_scratch_init(rdev);
4277 if (r)
4278 return r;
4279
4280 si_mc_program(rdev);
4281 r = si_pcie_gart_enable(rdev);
4282 if (r)
4283 return r;
4284 si_gpu_init(rdev);
4285
4286#if 0
4287 r = evergreen_blit_init(rdev);
4288 if (r) {
4289 r600_blit_fini(rdev);
4290 rdev->asic->copy = NULL;
4291 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4292 }
4293#endif
4294 /* allocate rlc buffers */
4295 r = si_rlc_init(rdev);
4296 if (r) {
4297 DRM_ERROR("Failed to init rlc BOs!\n");
4298 return r;
4299 }
4300
4301 /* allocate wb buffer */
4302 r = radeon_wb_init(rdev);
4303 if (r)
4304 return r;
4305
4306 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4307 if (r) {
4308 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4309 return r;
4310 }
4311
4312 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4313 if (r) {
4314 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4315 return r;
4316 }
4317
4318 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4319 if (r) {
4320 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4321 return r;
4322 }
4323
8c5fd7ef
AD		 4324 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4325 if (r) {
4326 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4327 return r;
4328 }
4329
4330 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4331 if (r) {
4332 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4333 return r;
4334 }
4335
f2ba57b5
CK		 4336 r = rv770_uvd_resume(rdev);
4337 if (!r) {
4338 r = radeon_fence_driver_start_ring(rdev,
4339 R600_RING_TYPE_UVD_INDEX);
4340 if (r)
4341 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
4342 }
4343 if (r)
4344 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4345
9b136d51
AD		 4346 /* Enable IRQ */
4347 r = si_irq_init(rdev);
4348 if (r) {
4349 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4350 radeon_irq_kms_fini(rdev);
4351 return r;
4352 }
4353 si_irq_set(rdev);
4354
4355 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4356 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4357 CP_RB0_RPTR, CP_RB0_WPTR,
4358 0, 0xfffff, RADEON_CP_PACKET2);
4359 if (r)
4360 return r;
4361
4362 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4363 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4364 CP_RB1_RPTR, CP_RB1_WPTR,
4365 0, 0xfffff, RADEON_CP_PACKET2);
4366 if (r)
4367 return r;
4368
4369 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4370 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4371 CP_RB2_RPTR, CP_RB2_WPTR,
4372 0, 0xfffff, RADEON_CP_PACKET2);
4373 if (r)
4374 return r;
4375
8c5fd7ef
AD		 4376 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4377 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4378 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4379 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4380 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4381 if (r)
4382 return r;
4383
4384 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4385 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4386 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4387 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4388 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4389 if (r)
4390 return r;
4391
9b136d51
AD		 4392 r = si_cp_load_microcode(rdev);
4393 if (r)
4394 return r;
4395 r = si_cp_resume(rdev);
4396 if (r)
4397 return r;
4398
8c5fd7ef
AD		 4399 r = cayman_dma_resume(rdev);
4400 if (r)
4401 return r;
4402
f2ba57b5
CK		 4403 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4404 if (ring->ring_size) {
4405 r = radeon_ring_init(rdev, ring, ring->ring_size,
4406 R600_WB_UVD_RPTR_OFFSET,
4407 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
4408 0, 0xfffff, RADEON_CP_PACKET2);
4409 if (!r)
4410 r = r600_uvd_init(rdev);
4411 if (r)
4412 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
4413 }
4414
2898c348
CK		 4415 r = radeon_ib_pool_init(rdev);
4416 if (r) {
4417 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
9b136d51 4418 return r;
2898c348 4419 }
9b136d51 4420
c6105f24
CK		 4421 r = radeon_vm_manager_init(rdev);
4422 if (r) {
4423 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
9b136d51 4424 return r;
c6105f24 4425 }
9b136d51
AD		 4426
4427 return 0;
4428}
4429
4430int si_resume(struct radeon_device *rdev)
4431{
4432 int r;
4433
4434 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4435 * posting will perform necessary task to bring back GPU into good
4436 * shape.
4437 */
4438 /* post card */
4439 atom_asic_init(rdev->mode_info.atom_context);
4440
4441 rdev->accel_working = true;
4442 r = si_startup(rdev);
4443 if (r) {
4444 DRM_ERROR("si startup failed on resume\n");
4445 rdev->accel_working = false;
4446 return r;
4447 }
4448
4449 return r;
4450
4451}
4452
4453int si_suspend(struct radeon_device *rdev)
4454{
fa3daf9a 4455 radeon_vm_manager_fini(rdev);
9b136d51 4456 si_cp_enable(rdev, false);
8c5fd7ef 4457 cayman_dma_stop(rdev);
f2ba57b5
CK		 4458 r600_uvd_rbc_stop(rdev);
4459 radeon_uvd_suspend(rdev);
9b136d51
AD		 4460 si_irq_suspend(rdev);
4461 radeon_wb_disable(rdev);
4462 si_pcie_gart_disable(rdev);
4463 return 0;
4464}
4465
4466/* Plan is to move initialization in that function and use
4467 * helper function so that radeon_device_init pretty much
4468 * do nothing more than calling asic specific function. This
4469 * should also allow to remove a bunch of callback function
4470 * like vram_info.
4471 */
4472int si_init(struct radeon_device *rdev)
4473{
4474 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4475 int r;
4476
9b136d51
AD		 4477 /* Read BIOS */
4478 if (!radeon_get_bios(rdev)) {
4479 if (ASIC_IS_AVIVO(rdev))
4480 return -EINVAL;
4481 }
4482 /* Must be an ATOMBIOS */
4483 if (!rdev->is_atom_bios) {
4484 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4485 return -EINVAL;
4486 }
4487 r = radeon_atombios_init(rdev);
4488 if (r)
4489 return r;
4490
4491 /* Post card if necessary */
4492 if (!radeon_card_posted(rdev)) {
4493 if (!rdev->bios) {
4494 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4495 return -EINVAL;
4496 }
4497 DRM_INFO("GPU not posted. posting now...\n");
4498 atom_asic_init(rdev->mode_info.atom_context);
4499 }
4500 /* Initialize scratch registers */
4501 si_scratch_init(rdev);
4502 /* Initialize surface registers */
4503 radeon_surface_init(rdev);
4504 /* Initialize clocks */
4505 radeon_get_clock_info(rdev->ddev);
4506
4507 /* Fence driver */
4508 r = radeon_fence_driver_init(rdev);
4509 if (r)
4510 return r;
4511
4512 /* initialize memory controller */
4513 r = si_mc_init(rdev);
4514 if (r)
4515 return r;
4516 /* Memory manager */
4517 r = radeon_bo_init(rdev);
4518 if (r)
4519 return r;
4520
4521 r = radeon_irq_kms_init(rdev);
4522 if (r)
4523 return r;
4524
4525 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4526 ring->ring_obj = NULL;
4527 r600_ring_init(rdev, ring, 1024 * 1024);
4528
4529 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4530 ring->ring_obj = NULL;
4531 r600_ring_init(rdev, ring, 1024 * 1024);
4532
4533 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4534 ring->ring_obj = NULL;
4535 r600_ring_init(rdev, ring, 1024 * 1024);
4536
8c5fd7ef
AD		 4537 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4538 ring->ring_obj = NULL;
4539 r600_ring_init(rdev, ring, 64 * 1024);
4540
4541 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4542 ring->ring_obj = NULL;
4543 r600_ring_init(rdev, ring, 64 * 1024);
4544
f2ba57b5
CK		 4545 r = radeon_uvd_init(rdev);
4546 if (!r) {
4547 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4548 ring->ring_obj = NULL;
4549 r600_ring_init(rdev, ring, 4096);
4550 }
4551
9b136d51
AD		 4552 rdev->ih.ring_obj = NULL;
4553 r600_ih_ring_init(rdev, 64 * 1024);
4554
4555 r = r600_pcie_gart_init(rdev);
4556 if (r)
4557 return r;
4558
9b136d51 4559 rdev->accel_working = true;
9b136d51
AD		 4560 r = si_startup(rdev);
4561 if (r) {
4562 dev_err(rdev->dev, "disabling GPU acceleration\n");
4563 si_cp_fini(rdev);
8c5fd7ef 4564 cayman_dma_fini(rdev);
9b136d51
AD		 4565 si_irq_fini(rdev);
4566 si_rlc_fini(rdev);
4567 radeon_wb_fini(rdev);
2898c348 4568 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4569 radeon_vm_manager_fini(rdev);
4570 radeon_irq_kms_fini(rdev);
4571 si_pcie_gart_fini(rdev);
4572 rdev->accel_working = false;
4573 }
4574
4575 /* Don't start up if the MC ucode is missing.
4576 * The default clocks and voltages before the MC ucode
4577 * is loaded are not suffient for advanced operations.
4578 */
4579 if (!rdev->mc_fw) {
4580 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4581 return -EINVAL;
4582 }
4583
4584 return 0;
4585}
4586
4587void si_fini(struct radeon_device *rdev)
4588{
4589#if 0
4590 r600_blit_fini(rdev);
4591#endif
4592 si_cp_fini(rdev);
8c5fd7ef 4593 cayman_dma_fini(rdev);
9b136d51
AD		 4594 si_irq_fini(rdev);
4595 si_rlc_fini(rdev);
4596 radeon_wb_fini(rdev);
4597 radeon_vm_manager_fini(rdev);
2898c348 4598 radeon_ib_pool_fini(rdev);
9b136d51 4599 radeon_irq_kms_fini(rdev);
f2ba57b5 4600 radeon_uvd_fini(rdev);
9b136d51
AD		 4601 si_pcie_gart_fini(rdev);
4602 r600_vram_scratch_fini(rdev);
4603 radeon_gem_fini(rdev);
9b136d51
AD		 4604 radeon_fence_driver_fini(rdev);
4605 radeon_bo_fini(rdev);
4606 radeon_atombios_fini(rdev);
4607 kfree(rdev->bios);
4608 rdev->bios = NULL;
4609}
4610
6759a0a7 4611/**
d0418894 4612 * si_get_gpu_clock_counter - return GPU clock counter snapshot
6759a0a7
MO		 4613 *
4614 * @rdev: radeon_device pointer
4615 *
4616 * Fetches a GPU clock counter snapshot (SI).
4617 * Returns the 64 bit clock counter snapshot.
4618 */
d0418894 4619uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
6759a0a7
MO		 4620{
4621 uint64_t clock;
4622
4623 mutex_lock(&rdev->gpu_clock_mutex);
4624 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4625 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4626 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4627 mutex_unlock(&rdev->gpu_clock_mutex);
4628 return clock;
4629}
Linux 6.x block layer and io_uring tree(s)