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drm/radeon/cayman,TN: add support for golden register init (v2)
[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c
CommitLineData
43b3cd99
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
0f0de06c
AD		 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
43b3cd99
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
43b3cd99
AD		 32#include "sid.h"
33#include "atom.h"
48c0c902 34#include "si_blit_shaders.h"
43b3cd99 35
0f0de06c
AD		 36#define SI_PFP_UCODE_SIZE 2144
37#define SI_PM4_UCODE_SIZE 2144
38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769
bcc7f5d2 41#define OLAND_MC_UCODE_SIZE 7863
0f0de06c
AD		 42
43MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
44MODULE_FIRMWARE("radeon/TAHITI_me.bin");
45MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
46MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
47MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
52MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
53MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
54MODULE_FIRMWARE("radeon/VERDE_me.bin");
55MODULE_FIRMWARE("radeon/VERDE_ce.bin");
56MODULE_FIRMWARE("radeon/VERDE_mc.bin");
57MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
bcc7f5d2
AD		 58MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
59MODULE_FIRMWARE("radeon/OLAND_me.bin");
60MODULE_FIRMWARE("radeon/OLAND_ce.bin");
61MODULE_FIRMWARE("radeon/OLAND_mc.bin");
62MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
0f0de06c 63
25a857fb
AD		 64extern int r600_ih_ring_alloc(struct radeon_device *rdev);
65extern void r600_ih_ring_fini(struct radeon_device *rdev);
0a96d72b 66extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
c476dde2
AD		 67extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
68extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
ca7db22b 69extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
1c534671 70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
014bb209 71extern bool evergreen_is_display_hung(struct radeon_device *rdev);
0a96d72b 72
454d2e2a
AD		 73#define PCIE_BUS_CLK 10000
74#define TCLK (PCIE_BUS_CLK / 10)
75
76/**
77 * si_get_xclk - get the xclk
78 *
79 * @rdev: radeon_device pointer
80 *
81 * Returns the reference clock used by the gfx engine
82 * (SI).
83 */
84u32 si_get_xclk(struct radeon_device *rdev)
85{
86 u32 reference_clock = rdev->clock.spll.reference_freq;
87 u32 tmp;
88
89 tmp = RREG32(CG_CLKPIN_CNTL_2);
90 if (tmp & MUX_TCLK_TO_XCLK)
91 return TCLK;
92
93 tmp = RREG32(CG_CLKPIN_CNTL);
94 if (tmp & XTALIN_DIVIDE)
95 return reference_clock / 4;
96
97 return reference_clock;
98}
99
1bd47d2e
AD		 100/* get temperature in millidegrees */
101int si_get_temp(struct radeon_device *rdev)
102{
103 u32 temp;
104 int actual_temp = 0;
105
106 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
107 CTF_TEMP_SHIFT;
108
109 if (temp & 0x200)
110 actual_temp = 255;
111 else
112 actual_temp = temp & 0x1ff;
113
114 actual_temp = (actual_temp * 1000);
115
116 return actual_temp;
117}
118
8b074dd6
AD		 119#define TAHITI_IO_MC_REGS_SIZE 36
120
121static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
122 {0x0000006f, 0x03044000},
123 {0x00000070, 0x0480c018},
124 {0x00000071, 0x00000040},
125 {0x00000072, 0x01000000},
126 {0x00000074, 0x000000ff},
127 {0x00000075, 0x00143400},
128 {0x00000076, 0x08ec0800},
129 {0x00000077, 0x040000cc},
130 {0x00000079, 0x00000000},
131 {0x0000007a, 0x21000409},
132 {0x0000007c, 0x00000000},
133 {0x0000007d, 0xe8000000},
134 {0x0000007e, 0x044408a8},
135 {0x0000007f, 0x00000003},
136 {0x00000080, 0x00000000},
137 {0x00000081, 0x01000000},
138 {0x00000082, 0x02000000},
139 {0x00000083, 0x00000000},
140 {0x00000084, 0xe3f3e4f4},
141 {0x00000085, 0x00052024},
142 {0x00000087, 0x00000000},
143 {0x00000088, 0x66036603},
144 {0x00000089, 0x01000000},
145 {0x0000008b, 0x1c0a0000},
146 {0x0000008c, 0xff010000},
147 {0x0000008e, 0xffffefff},
148 {0x0000008f, 0xfff3efff},
149 {0x00000090, 0xfff3efbf},
150 {0x00000094, 0x00101101},
151 {0x00000095, 0x00000fff},
152 {0x00000096, 0x00116fff},
153 {0x00000097, 0x60010000},
154 {0x00000098, 0x10010000},
155 {0x00000099, 0x00006000},
156 {0x0000009a, 0x00001000},
157 {0x0000009f, 0x00a77400}
158};
159
160static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
161 {0x0000006f, 0x03044000},
162 {0x00000070, 0x0480c018},
163 {0x00000071, 0x00000040},
164 {0x00000072, 0x01000000},
165 {0x00000074, 0x000000ff},
166 {0x00000075, 0x00143400},
167 {0x00000076, 0x08ec0800},
168 {0x00000077, 0x040000cc},
169 {0x00000079, 0x00000000},
170 {0x0000007a, 0x21000409},
171 {0x0000007c, 0x00000000},
172 {0x0000007d, 0xe8000000},
173 {0x0000007e, 0x044408a8},
174 {0x0000007f, 0x00000003},
175 {0x00000080, 0x00000000},
176 {0x00000081, 0x01000000},
177 {0x00000082, 0x02000000},
178 {0x00000083, 0x00000000},
179 {0x00000084, 0xe3f3e4f4},
180 {0x00000085, 0x00052024},
181 {0x00000087, 0x00000000},
182 {0x00000088, 0x66036603},
183 {0x00000089, 0x01000000},
184 {0x0000008b, 0x1c0a0000},
185 {0x0000008c, 0xff010000},
186 {0x0000008e, 0xffffefff},
187 {0x0000008f, 0xfff3efff},
188 {0x00000090, 0xfff3efbf},
189 {0x00000094, 0x00101101},
190 {0x00000095, 0x00000fff},
191 {0x00000096, 0x00116fff},
192 {0x00000097, 0x60010000},
193 {0x00000098, 0x10010000},
194 {0x00000099, 0x00006000},
195 {0x0000009a, 0x00001000},
196 {0x0000009f, 0x00a47400}
197};
198
199static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
200 {0x0000006f, 0x03044000},
201 {0x00000070, 0x0480c018},
202 {0x00000071, 0x00000040},
203 {0x00000072, 0x01000000},
204 {0x00000074, 0x000000ff},
205 {0x00000075, 0x00143400},
206 {0x00000076, 0x08ec0800},
207 {0x00000077, 0x040000cc},
208 {0x00000079, 0x00000000},
209 {0x0000007a, 0x21000409},
210 {0x0000007c, 0x00000000},
211 {0x0000007d, 0xe8000000},
212 {0x0000007e, 0x044408a8},
213 {0x0000007f, 0x00000003},
214 {0x00000080, 0x00000000},
215 {0x00000081, 0x01000000},
216 {0x00000082, 0x02000000},
217 {0x00000083, 0x00000000},
218 {0x00000084, 0xe3f3e4f4},
219 {0x00000085, 0x00052024},
220 {0x00000087, 0x00000000},
221 {0x00000088, 0x66036603},
222 {0x00000089, 0x01000000},
223 {0x0000008b, 0x1c0a0000},
224 {0x0000008c, 0xff010000},
225 {0x0000008e, 0xffffefff},
226 {0x0000008f, 0xfff3efff},
227 {0x00000090, 0xfff3efbf},
228 {0x00000094, 0x00101101},
229 {0x00000095, 0x00000fff},
230 {0x00000096, 0x00116fff},
231 {0x00000097, 0x60010000},
232 {0x00000098, 0x10010000},
233 {0x00000099, 0x00006000},
234 {0x0000009a, 0x00001000},
235 {0x0000009f, 0x00a37400}
236};
237
bcc7f5d2
AD		 238static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
239 {0x0000006f, 0x03044000},
240 {0x00000070, 0x0480c018},
241 {0x00000071, 0x00000040},
242 {0x00000072, 0x01000000},
243 {0x00000074, 0x000000ff},
244 {0x00000075, 0x00143400},
245 {0x00000076, 0x08ec0800},
246 {0x00000077, 0x040000cc},
247 {0x00000079, 0x00000000},
248 {0x0000007a, 0x21000409},
249 {0x0000007c, 0x00000000},
250 {0x0000007d, 0xe8000000},
251 {0x0000007e, 0x044408a8},
252 {0x0000007f, 0x00000003},
253 {0x00000080, 0x00000000},
254 {0x00000081, 0x01000000},
255 {0x00000082, 0x02000000},
256 {0x00000083, 0x00000000},
257 {0x00000084, 0xe3f3e4f4},
258 {0x00000085, 0x00052024},
259 {0x00000087, 0x00000000},
260 {0x00000088, 0x66036603},
261 {0x00000089, 0x01000000},
262 {0x0000008b, 0x1c0a0000},
263 {0x0000008c, 0xff010000},
264 {0x0000008e, 0xffffefff},
265 {0x0000008f, 0xfff3efff},
266 {0x00000090, 0xfff3efbf},
267 {0x00000094, 0x00101101},
268 {0x00000095, 0x00000fff},
269 {0x00000096, 0x00116fff},
270 {0x00000097, 0x60010000},
271 {0x00000098, 0x10010000},
272 {0x00000099, 0x00006000},
273 {0x0000009a, 0x00001000},
274 {0x0000009f, 0x00a17730}
275};
276
8b074dd6
AD		 277/* ucode loading */
278static int si_mc_load_microcode(struct radeon_device *rdev)
279{
280 const __be32 *fw_data;
281 u32 running, blackout = 0;
282 u32 *io_mc_regs;
283 int i, ucode_size, regs_size;
284
285 if (!rdev->mc_fw)
286 return -EINVAL;
287
288 switch (rdev->family) {
289 case CHIP_TAHITI:
290 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
291 ucode_size = SI_MC_UCODE_SIZE;
292 regs_size = TAHITI_IO_MC_REGS_SIZE;
293 break;
294 case CHIP_PITCAIRN:
295 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
296 ucode_size = SI_MC_UCODE_SIZE;
297 regs_size = TAHITI_IO_MC_REGS_SIZE;
298 break;
299 case CHIP_VERDE:
300 default:
301 io_mc_regs = (u32 *)&verde_io_mc_regs;
302 ucode_size = SI_MC_UCODE_SIZE;
303 regs_size = TAHITI_IO_MC_REGS_SIZE;
304 break;
bcc7f5d2
AD		 305 case CHIP_OLAND:
306 io_mc_regs = (u32 *)&oland_io_mc_regs;
307 ucode_size = OLAND_MC_UCODE_SIZE;
308 regs_size = TAHITI_IO_MC_REGS_SIZE;
309 break;
8b074dd6
AD		 310 }
311
312 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
313
314 if (running == 0) {
315 if (running) {
316 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
317 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
318 }
319
320 /* reset the engine and set to writable */
321 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
322 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
323
324 /* load mc io regs */
325 for (i = 0; i < regs_size; i++) {
326 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
327 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
328 }
329 /* load the MC ucode */
330 fw_data = (const __be32 *)rdev->mc_fw->data;
331 for (i = 0; i < ucode_size; i++)
332 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
333
334 /* put the engine back into the active state */
335 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
336 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
337 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
338
339 /* wait for training to complete */
340 for (i = 0; i < rdev->usec_timeout; i++) {
341 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
342 break;
343 udelay(1);
344 }
345 for (i = 0; i < rdev->usec_timeout; i++) {
346 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
347 break;
348 udelay(1);
349 }
350
351 if (running)
352 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
353 }
354
355 return 0;
356}
357
0f0de06c
AD		 358static int si_init_microcode(struct radeon_device *rdev)
359{
360 struct platform_device *pdev;
361 const char *chip_name;
362 const char *rlc_chip_name;
363 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
364 char fw_name[30];
365 int err;
366
367 DRM_DEBUG("\n");
368
369 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
370 err = IS_ERR(pdev);
371 if (err) {
372 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
373 return -EINVAL;
374 }
375
376 switch (rdev->family) {
377 case CHIP_TAHITI:
378 chip_name = "TAHITI";
379 rlc_chip_name = "TAHITI";
380 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
381 me_req_size = SI_PM4_UCODE_SIZE * 4;
382 ce_req_size = SI_CE_UCODE_SIZE * 4;
383 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
384 mc_req_size = SI_MC_UCODE_SIZE * 4;
385 break;
386 case CHIP_PITCAIRN:
387 chip_name = "PITCAIRN";
388 rlc_chip_name = "PITCAIRN";
389 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
390 me_req_size = SI_PM4_UCODE_SIZE * 4;
391 ce_req_size = SI_CE_UCODE_SIZE * 4;
392 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
393 mc_req_size = SI_MC_UCODE_SIZE * 4;
394 break;
395 case CHIP_VERDE:
396 chip_name = "VERDE";
397 rlc_chip_name = "VERDE";
398 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
399 me_req_size = SI_PM4_UCODE_SIZE * 4;
400 ce_req_size = SI_CE_UCODE_SIZE * 4;
401 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
402 mc_req_size = SI_MC_UCODE_SIZE * 4;
403 break;
bcc7f5d2
AD		 404 case CHIP_OLAND:
405 chip_name = "OLAND";
406 rlc_chip_name = "OLAND";
407 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
408 me_req_size = SI_PM4_UCODE_SIZE * 4;
409 ce_req_size = SI_CE_UCODE_SIZE * 4;
410 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
411 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
412 break;
0f0de06c
AD		 413 default: BUG();
414 }
415
416 DRM_INFO("Loading %s Microcode\n", chip_name);
417
418 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
419 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
420 if (err)
421 goto out;
422 if (rdev->pfp_fw->size != pfp_req_size) {
423 printk(KERN_ERR
424 "si_cp: Bogus length %zu in firmware \"%s\"\n",
425 rdev->pfp_fw->size, fw_name);
426 err = -EINVAL;
427 goto out;
428 }
429
430 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
431 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
432 if (err)
433 goto out;
434 if (rdev->me_fw->size != me_req_size) {
435 printk(KERN_ERR
436 "si_cp: Bogus length %zu in firmware \"%s\"\n",
437 rdev->me_fw->size, fw_name);
438 err = -EINVAL;
439 }
440
441 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
442 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
443 if (err)
444 goto out;
445 if (rdev->ce_fw->size != ce_req_size) {
446 printk(KERN_ERR
447 "si_cp: Bogus length %zu in firmware \"%s\"\n",
448 rdev->ce_fw->size, fw_name);
449 err = -EINVAL;
450 }
451
452 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
453 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
454 if (err)
455 goto out;
456 if (rdev->rlc_fw->size != rlc_req_size) {
457 printk(KERN_ERR
458 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
459 rdev->rlc_fw->size, fw_name);
460 err = -EINVAL;
461 }
462
463 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
464 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
465 if (err)
466 goto out;
467 if (rdev->mc_fw->size != mc_req_size) {
468 printk(KERN_ERR
469 "si_mc: Bogus length %zu in firmware \"%s\"\n",
470 rdev->mc_fw->size, fw_name);
471 err = -EINVAL;
472 }
473
474out:
475 platform_device_unregister(pdev);
476
477 if (err) {
478 if (err != -EINVAL)
479 printk(KERN_ERR
480 "si_cp: Failed to load firmware \"%s\"\n",
481 fw_name);
482 release_firmware(rdev->pfp_fw);
483 rdev->pfp_fw = NULL;
484 release_firmware(rdev->me_fw);
485 rdev->me_fw = NULL;
486 release_firmware(rdev->ce_fw);
487 rdev->ce_fw = NULL;
488 release_firmware(rdev->rlc_fw);
489 rdev->rlc_fw = NULL;
490 release_firmware(rdev->mc_fw);
491 rdev->mc_fw = NULL;
492 }
493 return err;
494}
495
43b3cd99
AD		 496/* watermark setup */
497static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
498 struct radeon_crtc *radeon_crtc,
499 struct drm_display_mode *mode,
500 struct drm_display_mode *other_mode)
501{
502 u32 tmp;
503 /*
504 * Line Buffer Setup
505 * There are 3 line buffers, each one shared by 2 display controllers.
506 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
507 * the display controllers. The paritioning is done via one of four
508 * preset allocations specified in bits 21:20:
509 * 0 - half lb
510 * 2 - whole lb, other crtc must be disabled
511 */
512 /* this can get tricky if we have two large displays on a paired group
513 * of crtcs. Ideally for multiple large displays we'd assign them to
514 * non-linked crtcs for maximum line buffer allocation.
515 */
516 if (radeon_crtc->base.enabled && mode) {
517 if (other_mode)
518 tmp = 0; /* 1/2 */
519 else
520 tmp = 2; /* whole */
521 } else
522 tmp = 0;
523
524 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
525 DC_LB_MEMORY_CONFIG(tmp));
526
527 if (radeon_crtc->base.enabled && mode) {
528 switch (tmp) {
529 case 0:
530 default:
531 return 4096 * 2;
532 case 2:
533 return 8192 * 2;
534 }
535 }
536
537 /* controller not enabled, so no lb used */
538 return 0;
539}
540
ca7db22b 541static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
43b3cd99
AD		 542{
543 u32 tmp = RREG32(MC_SHARED_CHMAP);
544
545 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
546 case 0:
547 default:
548 return 1;
549 case 1:
550 return 2;
551 case 2:
552 return 4;
553 case 3:
554 return 8;
555 case 4:
556 return 3;
557 case 5:
558 return 6;
559 case 6:
560 return 10;
561 case 7:
562 return 12;
563 case 8:
564 return 16;
565 }
566}
567
568struct dce6_wm_params {
569 u32 dram_channels; /* number of dram channels */
570 u32 yclk; /* bandwidth per dram data pin in kHz */
571 u32 sclk; /* engine clock in kHz */
572 u32 disp_clk; /* display clock in kHz */
573 u32 src_width; /* viewport width */
574 u32 active_time; /* active display time in ns */
575 u32 blank_time; /* blank time in ns */
576 bool interlaced; /* mode is interlaced */
577 fixed20_12 vsc; /* vertical scale ratio */
578 u32 num_heads; /* number of active crtcs */
579 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
580 u32 lb_size; /* line buffer allocated to pipe */
581 u32 vtaps; /* vertical scaler taps */
582};
583
584static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
585{
586 /* Calculate raw DRAM Bandwidth */
587 fixed20_12 dram_efficiency; /* 0.7 */
588 fixed20_12 yclk, dram_channels, bandwidth;
589 fixed20_12 a;
590
591 a.full = dfixed_const(1000);
592 yclk.full = dfixed_const(wm->yclk);
593 yclk.full = dfixed_div(yclk, a);
594 dram_channels.full = dfixed_const(wm->dram_channels * 4);
595 a.full = dfixed_const(10);
596 dram_efficiency.full = dfixed_const(7);
597 dram_efficiency.full = dfixed_div(dram_efficiency, a);
598 bandwidth.full = dfixed_mul(dram_channels, yclk);
599 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
600
601 return dfixed_trunc(bandwidth);
602}
603
604static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
605{
606 /* Calculate DRAM Bandwidth and the part allocated to display. */
607 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
608 fixed20_12 yclk, dram_channels, bandwidth;
609 fixed20_12 a;
610
611 a.full = dfixed_const(1000);
612 yclk.full = dfixed_const(wm->yclk);
613 yclk.full = dfixed_div(yclk, a);
614 dram_channels.full = dfixed_const(wm->dram_channels * 4);
615 a.full = dfixed_const(10);
616 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
617 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
618 bandwidth.full = dfixed_mul(dram_channels, yclk);
619 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
620
621 return dfixed_trunc(bandwidth);
622}
623
624static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
625{
626 /* Calculate the display Data return Bandwidth */
627 fixed20_12 return_efficiency; /* 0.8 */
628 fixed20_12 sclk, bandwidth;
629 fixed20_12 a;
630
631 a.full = dfixed_const(1000);
632 sclk.full = dfixed_const(wm->sclk);
633 sclk.full = dfixed_div(sclk, a);
634 a.full = dfixed_const(10);
635 return_efficiency.full = dfixed_const(8);
636 return_efficiency.full = dfixed_div(return_efficiency, a);
637 a.full = dfixed_const(32);
638 bandwidth.full = dfixed_mul(a, sclk);
639 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
640
641 return dfixed_trunc(bandwidth);
642}
643
644static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
645{
646 return 32;
647}
648
649static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
650{
651 /* Calculate the DMIF Request Bandwidth */
652 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
653 fixed20_12 disp_clk, sclk, bandwidth;
654 fixed20_12 a, b1, b2;
655 u32 min_bandwidth;
656
657 a.full = dfixed_const(1000);
658 disp_clk.full = dfixed_const(wm->disp_clk);
659 disp_clk.full = dfixed_div(disp_clk, a);
660 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
661 b1.full = dfixed_mul(a, disp_clk);
662
663 a.full = dfixed_const(1000);
664 sclk.full = dfixed_const(wm->sclk);
665 sclk.full = dfixed_div(sclk, a);
666 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
667 b2.full = dfixed_mul(a, sclk);
668
669 a.full = dfixed_const(10);
670 disp_clk_request_efficiency.full = dfixed_const(8);
671 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
672
673 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
674
675 a.full = dfixed_const(min_bandwidth);
676 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
677
678 return dfixed_trunc(bandwidth);
679}
680
681static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
682{
683 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
684 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
685 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
686 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
687
688 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
689}
690
691static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
692{
693 /* Calculate the display mode Average Bandwidth
694 * DisplayMode should contain the source and destination dimensions,
695 * timing, etc.
696 */
697 fixed20_12 bpp;
698 fixed20_12 line_time;
699 fixed20_12 src_width;
700 fixed20_12 bandwidth;
701 fixed20_12 a;
702
703 a.full = dfixed_const(1000);
704 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
705 line_time.full = dfixed_div(line_time, a);
706 bpp.full = dfixed_const(wm->bytes_per_pixel);
707 src_width.full = dfixed_const(wm->src_width);
708 bandwidth.full = dfixed_mul(src_width, bpp);
709 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
710 bandwidth.full = dfixed_div(bandwidth, line_time);
711
712 return dfixed_trunc(bandwidth);
713}
714
715static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
716{
717 /* First calcualte the latency in ns */
718 u32 mc_latency = 2000; /* 2000 ns. */
719 u32 available_bandwidth = dce6_available_bandwidth(wm);
720 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
721 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
722 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
723 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
724 (wm->num_heads * cursor_line_pair_return_time);
725 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
726 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
727 u32 tmp, dmif_size = 12288;
728 fixed20_12 a, b, c;
729
730 if (wm->num_heads == 0)
731 return 0;
732
733 a.full = dfixed_const(2);
734 b.full = dfixed_const(1);
735 if ((wm->vsc.full > a.full) ||
736 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
737 (wm->vtaps >= 5) ||
738 ((wm->vsc.full >= a.full) && wm->interlaced))
739 max_src_lines_per_dst_line = 4;
740 else
741 max_src_lines_per_dst_line = 2;
742
743 a.full = dfixed_const(available_bandwidth);
744 b.full = dfixed_const(wm->num_heads);
745 a.full = dfixed_div(a, b);
746
747 b.full = dfixed_const(mc_latency + 512);
748 c.full = dfixed_const(wm->disp_clk);
749 b.full = dfixed_div(b, c);
750
751 c.full = dfixed_const(dmif_size);
752 b.full = dfixed_div(c, b);
753
754 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
755
756 b.full = dfixed_const(1000);
757 c.full = dfixed_const(wm->disp_clk);
758 b.full = dfixed_div(c, b);
759 c.full = dfixed_const(wm->bytes_per_pixel);
760 b.full = dfixed_mul(b, c);
761
762 lb_fill_bw = min(tmp, dfixed_trunc(b));
763
764 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
765 b.full = dfixed_const(1000);
766 c.full = dfixed_const(lb_fill_bw);
767 b.full = dfixed_div(c, b);
768 a.full = dfixed_div(a, b);
769 line_fill_time = dfixed_trunc(a);
770
771 if (line_fill_time < wm->active_time)
772 return latency;
773 else
774 return latency + (line_fill_time - wm->active_time);
775
776}
777
778static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
779{
780 if (dce6_average_bandwidth(wm) <=
781 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
782 return true;
783 else
784 return false;
785};
786
787static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
788{
789 if (dce6_average_bandwidth(wm) <=
790 (dce6_available_bandwidth(wm) / wm->num_heads))
791 return true;
792 else
793 return false;
794};
795
796static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
797{
798 u32 lb_partitions = wm->lb_size / wm->src_width;
799 u32 line_time = wm->active_time + wm->blank_time;
800 u32 latency_tolerant_lines;
801 u32 latency_hiding;
802 fixed20_12 a;
803
804 a.full = dfixed_const(1);
805 if (wm->vsc.full > a.full)
806 latency_tolerant_lines = 1;
807 else {
808 if (lb_partitions <= (wm->vtaps + 1))
809 latency_tolerant_lines = 1;
810 else
811 latency_tolerant_lines = 2;
812 }
813
814 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
815
816 if (dce6_latency_watermark(wm) <= latency_hiding)
817 return true;
818 else
819 return false;
820}
821
822static void dce6_program_watermarks(struct radeon_device *rdev,
823 struct radeon_crtc *radeon_crtc,
824 u32 lb_size, u32 num_heads)
825{
826 struct drm_display_mode *mode = &radeon_crtc->base.mode;
827 struct dce6_wm_params wm;
828 u32 pixel_period;
829 u32 line_time = 0;
830 u32 latency_watermark_a = 0, latency_watermark_b = 0;
831 u32 priority_a_mark = 0, priority_b_mark = 0;
832 u32 priority_a_cnt = PRIORITY_OFF;
833 u32 priority_b_cnt = PRIORITY_OFF;
834 u32 tmp, arb_control3;
835 fixed20_12 a, b, c;
836
837 if (radeon_crtc->base.enabled && num_heads && mode) {
838 pixel_period = 1000000 / (u32)mode->clock;
839 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
840 priority_a_cnt = 0;
841 priority_b_cnt = 0;
842
843 wm.yclk = rdev->pm.current_mclk * 10;
844 wm.sclk = rdev->pm.current_sclk * 10;
845 wm.disp_clk = mode->clock;
846 wm.src_width = mode->crtc_hdisplay;
847 wm.active_time = mode->crtc_hdisplay * pixel_period;
848 wm.blank_time = line_time - wm.active_time;
849 wm.interlaced = false;
850 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
851 wm.interlaced = true;
852 wm.vsc = radeon_crtc->vsc;
853 wm.vtaps = 1;
854 if (radeon_crtc->rmx_type != RMX_OFF)
855 wm.vtaps = 2;
856 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
857 wm.lb_size = lb_size;
ca7db22b
AD		 858 if (rdev->family == CHIP_ARUBA)
859 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
860 else
861 wm.dram_channels = si_get_number_of_dram_channels(rdev);
43b3cd99
AD		 862 wm.num_heads = num_heads;
863
864 /* set for high clocks */
865 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
866 /* set for low clocks */
867 /* wm.yclk = low clk; wm.sclk = low clk */
868 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
869
870 /* possibly force display priority to high */
871 /* should really do this at mode validation time... */
872 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
873 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
874 !dce6_check_latency_hiding(&wm) ||
875 (rdev->disp_priority == 2)) {
876 DRM_DEBUG_KMS("force priority to high\n");
877 priority_a_cnt |= PRIORITY_ALWAYS_ON;
878 priority_b_cnt |= PRIORITY_ALWAYS_ON;
879 }
880
881 a.full = dfixed_const(1000);
882 b.full = dfixed_const(mode->clock);
883 b.full = dfixed_div(b, a);
884 c.full = dfixed_const(latency_watermark_a);
885 c.full = dfixed_mul(c, b);
886 c.full = dfixed_mul(c, radeon_crtc->hsc);
887 c.full = dfixed_div(c, a);
888 a.full = dfixed_const(16);
889 c.full = dfixed_div(c, a);
890 priority_a_mark = dfixed_trunc(c);
891 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
892
893 a.full = dfixed_const(1000);
894 b.full = dfixed_const(mode->clock);
895 b.full = dfixed_div(b, a);
896 c.full = dfixed_const(latency_watermark_b);
897 c.full = dfixed_mul(c, b);
898 c.full = dfixed_mul(c, radeon_crtc->hsc);
899 c.full = dfixed_div(c, a);
900 a.full = dfixed_const(16);
901 c.full = dfixed_div(c, a);
902 priority_b_mark = dfixed_trunc(c);
903 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
904 }
905
906 /* select wm A */
907 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
908 tmp = arb_control3;
909 tmp &= ~LATENCY_WATERMARK_MASK(3);
910 tmp |= LATENCY_WATERMARK_MASK(1);
911 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
912 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
913 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
914 LATENCY_HIGH_WATERMARK(line_time)));
915 /* select wm B */
916 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
917 tmp &= ~LATENCY_WATERMARK_MASK(3);
918 tmp |= LATENCY_WATERMARK_MASK(2);
919 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
920 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
921 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
922 LATENCY_HIGH_WATERMARK(line_time)));
923 /* restore original selection */
924 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
925
926 /* write the priority marks */
927 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
928 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
929
930}
931
932void dce6_bandwidth_update(struct radeon_device *rdev)
933{
934 struct drm_display_mode *mode0 = NULL;
935 struct drm_display_mode *mode1 = NULL;
936 u32 num_heads = 0, lb_size;
937 int i;
938
939 radeon_update_display_priority(rdev);
940
941 for (i = 0; i < rdev->num_crtc; i++) {
942 if (rdev->mode_info.crtcs[i]->base.enabled)
943 num_heads++;
944 }
945 for (i = 0; i < rdev->num_crtc; i += 2) {
946 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
947 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
948 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
949 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
950 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
951 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
952 }
953}
954
0a96d72b
AD		 955/*
956 * Core functions
957 */
0a96d72b
AD		 958static void si_tiling_mode_table_init(struct radeon_device *rdev)
959{
960 const u32 num_tile_mode_states = 32;
961 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
962
963 switch (rdev->config.si.mem_row_size_in_kb) {
964 case 1:
965 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
966 break;
967 case 2:
968 default:
969 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
970 break;
971 case 4:
972 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
973 break;
974 }
975
976 if ((rdev->family == CHIP_TAHITI) ||
977 (rdev->family == CHIP_PITCAIRN)) {
978 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
979 switch (reg_offset) {
980 case 0: /* non-AA compressed depth or any compressed stencil */
981 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
982 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
983 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
984 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
985 NUM_BANKS(ADDR_SURF_16_BANK) |
986 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
987 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
988 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
989 break;
990 case 1: /* 2xAA/4xAA compressed depth only */
991 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
992 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
993 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
994 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
995 NUM_BANKS(ADDR_SURF_16_BANK) |
996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
999 break;
1000 case 2: /* 8xAA compressed depth only */
1001 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1003 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1005 NUM_BANKS(ADDR_SURF_16_BANK) |
1006 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1007 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1008 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1009 break;
1010 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1011 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1012 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1013 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1014 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1015 NUM_BANKS(ADDR_SURF_16_BANK) |
1016 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1017 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1018 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1019 break;
1020 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1021 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1022 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1023 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1025 NUM_BANKS(ADDR_SURF_16_BANK) |
1026 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1027 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1028 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1029 break;
1030 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1031 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1033 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1034 TILE_SPLIT(split_equal_to_row_size) |
1035 NUM_BANKS(ADDR_SURF_16_BANK) |
1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1039 break;
1040 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1041 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1043 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1044 TILE_SPLIT(split_equal_to_row_size) |
1045 NUM_BANKS(ADDR_SURF_16_BANK) |
1046 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1049 break;
1050 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1051 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1052 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1054 TILE_SPLIT(split_equal_to_row_size) |
1055 NUM_BANKS(ADDR_SURF_16_BANK) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1059 break;
1060 case 8: /* 1D and 1D Array Surfaces */
1061 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1062 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1063 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1065 NUM_BANKS(ADDR_SURF_16_BANK) |
1066 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1069 break;
1070 case 9: /* Displayable maps. */
1071 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1072 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1074 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1075 NUM_BANKS(ADDR_SURF_16_BANK) |
1076 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1077 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1078 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1079 break;
1080 case 10: /* Display 8bpp. */
1081 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1082 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1084 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1085 NUM_BANKS(ADDR_SURF_16_BANK) |
1086 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1089 break;
1090 case 11: /* Display 16bpp. */
1091 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1092 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1095 NUM_BANKS(ADDR_SURF_16_BANK) |
1096 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1097 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1098 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1099 break;
1100 case 12: /* Display 32bpp. */
1101 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1102 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1105 NUM_BANKS(ADDR_SURF_16_BANK) |
1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1109 break;
1110 case 13: /* Thin. */
1111 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1112 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1113 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1115 NUM_BANKS(ADDR_SURF_16_BANK) |
1116 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1117 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1118 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1119 break;
1120 case 14: /* Thin 8 bpp. */
1121 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1122 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1125 NUM_BANKS(ADDR_SURF_16_BANK) |
1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1129 break;
1130 case 15: /* Thin 16 bpp. */
1131 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1135 NUM_BANKS(ADDR_SURF_16_BANK) |
1136 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1139 break;
1140 case 16: /* Thin 32 bpp. */
1141 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1142 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1145 NUM_BANKS(ADDR_SURF_16_BANK) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1149 break;
1150 case 17: /* Thin 64 bpp. */
1151 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1154 TILE_SPLIT(split_equal_to_row_size) |
1155 NUM_BANKS(ADDR_SURF_16_BANK) |
1156 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1159 break;
1160 case 21: /* 8 bpp PRT. */
1161 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1162 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1164 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1165 NUM_BANKS(ADDR_SURF_16_BANK) |
1166 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1169 break;
1170 case 22: /* 16 bpp PRT */
1171 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1172 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1173 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1174 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1175 NUM_BANKS(ADDR_SURF_16_BANK) |
1176 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1179 break;
1180 case 23: /* 32 bpp PRT */
1181 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1182 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1183 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1184 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1185 NUM_BANKS(ADDR_SURF_16_BANK) |
1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1189 break;
1190 case 24: /* 64 bpp PRT */
1191 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1192 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1195 NUM_BANKS(ADDR_SURF_16_BANK) |
1196 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1199 break;
1200 case 25: /* 128 bpp PRT */
1201 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1205 NUM_BANKS(ADDR_SURF_8_BANK) |
1206 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1209 break;
1210 default:
1211 gb_tile_moden = 0;
1212 break;
1213 }
64d7b8be 1214 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
0a96d72b
AD		 1215 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1216 }
d0ae7fcc
AD		 1217 } else if ((rdev->family == CHIP_VERDE) ||
1218 (rdev->family == CHIP_OLAND)) {
0a96d72b
AD		 1219 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1220 switch (reg_offset) {
1221 case 0: /* non-AA compressed depth or any compressed stencil */
1222 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1223 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1224 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1226 NUM_BANKS(ADDR_SURF_16_BANK) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1230 break;
1231 case 1: /* 2xAA/4xAA compressed depth only */
1232 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1236 NUM_BANKS(ADDR_SURF_16_BANK) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1240 break;
1241 case 2: /* 8xAA compressed depth only */
1242 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1244 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1246 NUM_BANKS(ADDR_SURF_16_BANK) |
1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1250 break;
1251 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1252 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1253 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1254 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1256 NUM_BANKS(ADDR_SURF_16_BANK) |
1257 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1260 break;
1261 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1262 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1263 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1264 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1266 NUM_BANKS(ADDR_SURF_16_BANK) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1270 break;
1271 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1272 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1274 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1275 TILE_SPLIT(split_equal_to_row_size) |
1276 NUM_BANKS(ADDR_SURF_16_BANK) |
1277 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1280 break;
1281 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1282 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1283 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1284 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1285 TILE_SPLIT(split_equal_to_row_size) |
1286 NUM_BANKS(ADDR_SURF_16_BANK) |
1287 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1290 break;
1291 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1292 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1293 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1294 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1295 TILE_SPLIT(split_equal_to_row_size) |
1296 NUM_BANKS(ADDR_SURF_16_BANK) |
1297 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1298 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1299 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1300 break;
1301 case 8: /* 1D and 1D Array Surfaces */
1302 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1303 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1304 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1305 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1306 NUM_BANKS(ADDR_SURF_16_BANK) |
1307 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1310 break;
1311 case 9: /* Displayable maps. */
1312 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1313 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1314 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1315 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1316 NUM_BANKS(ADDR_SURF_16_BANK) |
1317 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1318 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1319 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1320 break;
1321 case 10: /* Display 8bpp. */
1322 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1323 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1324 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1325 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1326 NUM_BANKS(ADDR_SURF_16_BANK) |
1327 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1330 break;
1331 case 11: /* Display 16bpp. */
1332 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1333 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1334 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1335 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1336 NUM_BANKS(ADDR_SURF_16_BANK) |
1337 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1338 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1339 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1340 break;
1341 case 12: /* Display 32bpp. */
1342 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1343 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1344 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1345 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1346 NUM_BANKS(ADDR_SURF_16_BANK) |
1347 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1350 break;
1351 case 13: /* Thin. */
1352 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1353 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1354 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1355 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1356 NUM_BANKS(ADDR_SURF_16_BANK) |
1357 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1360 break;
1361 case 14: /* Thin 8 bpp. */
1362 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1363 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1364 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1365 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1366 NUM_BANKS(ADDR_SURF_16_BANK) |
1367 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1370 break;
1371 case 15: /* Thin 16 bpp. */
1372 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1373 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1374 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1375 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1376 NUM_BANKS(ADDR_SURF_16_BANK) |
1377 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1380 break;
1381 case 16: /* Thin 32 bpp. */
1382 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1383 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1384 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1385 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1386 NUM_BANKS(ADDR_SURF_16_BANK) |
1387 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1390 break;
1391 case 17: /* Thin 64 bpp. */
1392 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1393 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1394 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1395 TILE_SPLIT(split_equal_to_row_size) |
1396 NUM_BANKS(ADDR_SURF_16_BANK) |
1397 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1400 break;
1401 case 21: /* 8 bpp PRT. */
1402 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1403 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1404 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1405 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1406 NUM_BANKS(ADDR_SURF_16_BANK) |
1407 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1408 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1409 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1410 break;
1411 case 22: /* 16 bpp PRT */
1412 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1413 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1414 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1416 NUM_BANKS(ADDR_SURF_16_BANK) |
1417 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1420 break;
1421 case 23: /* 32 bpp PRT */
1422 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1424 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1425 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1426 NUM_BANKS(ADDR_SURF_16_BANK) |
1427 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1428 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1429 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1430 break;
1431 case 24: /* 64 bpp PRT */
1432 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1433 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1434 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1436 NUM_BANKS(ADDR_SURF_16_BANK) |
1437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1440 break;
1441 case 25: /* 128 bpp PRT */
1442 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1443 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1444 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1445 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1446 NUM_BANKS(ADDR_SURF_8_BANK) |
1447 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1448 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1449 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1450 break;
1451 default:
1452 gb_tile_moden = 0;
1453 break;
1454 }
64d7b8be 1455 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
0a96d72b
AD		 1456 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1457 }
1458 } else
1459 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1460}
1461
1a8ca750
AD		 1462static void si_select_se_sh(struct radeon_device *rdev,
1463 u32 se_num, u32 sh_num)
1464{
1465 u32 data = INSTANCE_BROADCAST_WRITES;
1466
1467 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
79b52d6a 1468 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1a8ca750
AD		 1469 else if (se_num == 0xffffffff)
1470 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1471 else if (sh_num == 0xffffffff)
1472 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1473 else
1474 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1475 WREG32(GRBM_GFX_INDEX, data);
1476}
1477
1478static u32 si_create_bitmask(u32 bit_width)
1479{
1480 u32 i, mask = 0;
1481
1482 for (i = 0; i < bit_width; i++) {
1483 mask <<= 1;
1484 mask |= 1;
1485 }
1486 return mask;
1487}
1488
1489static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1490{
1491 u32 data, mask;
1492
1493 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1494 if (data & 1)
1495 data &= INACTIVE_CUS_MASK;
1496 else
1497 data = 0;
1498 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1499
1500 data >>= INACTIVE_CUS_SHIFT;
1501
1502 mask = si_create_bitmask(cu_per_sh);
1503
1504 return ~data & mask;
1505}
1506
1507static void si_setup_spi(struct radeon_device *rdev,
1508 u32 se_num, u32 sh_per_se,
1509 u32 cu_per_sh)
1510{
1511 int i, j, k;
1512 u32 data, mask, active_cu;
1513
1514 for (i = 0; i < se_num; i++) {
1515 for (j = 0; j < sh_per_se; j++) {
1516 si_select_se_sh(rdev, i, j);
1517 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1518 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1519
1520 mask = 1;
1521 for (k = 0; k < 16; k++) {
1522 mask <<= k;
1523 if (active_cu & mask) {
1524 data &= ~mask;
1525 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1526 break;
1527 }
1528 }
1529 }
1530 }
1531 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1532}
1533
1534static u32 si_get_rb_disabled(struct radeon_device *rdev,
1535 u32 max_rb_num, u32 se_num,
1536 u32 sh_per_se)
1537{
1538 u32 data, mask;
1539
1540 data = RREG32(CC_RB_BACKEND_DISABLE);
1541 if (data & 1)
1542 data &= BACKEND_DISABLE_MASK;
1543 else
1544 data = 0;
1545 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1546
1547 data >>= BACKEND_DISABLE_SHIFT;
1548
1549 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1550
1551 return data & mask;
1552}
1553
1554static void si_setup_rb(struct radeon_device *rdev,
1555 u32 se_num, u32 sh_per_se,
1556 u32 max_rb_num)
1557{
1558 int i, j;
1559 u32 data, mask;
1560 u32 disabled_rbs = 0;
1561 u32 enabled_rbs = 0;
1562
1563 for (i = 0; i < se_num; i++) {
1564 for (j = 0; j < sh_per_se; j++) {
1565 si_select_se_sh(rdev, i, j);
1566 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1567 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1568 }
1569 }
1570 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1571
1572 mask = 1;
1573 for (i = 0; i < max_rb_num; i++) {
1574 if (!(disabled_rbs & mask))
1575 enabled_rbs |= mask;
1576 mask <<= 1;
1577 }
1578
1579 for (i = 0; i < se_num; i++) {
1580 si_select_se_sh(rdev, i, 0xffffffff);
1581 data = 0;
1582 for (j = 0; j < sh_per_se; j++) {
1583 switch (enabled_rbs & 3) {
1584 case 1:
1585 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1586 break;
1587 case 2:
1588 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1589 break;
1590 case 3:
1591 default:
1592 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1593 break;
1594 }
1595 enabled_rbs >>= 2;
1596 }
1597 WREG32(PA_SC_RASTER_CONFIG, data);
1598 }
1599 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1600}
1601
0a96d72b
AD		 1602static void si_gpu_init(struct radeon_device *rdev)
1603{
0a96d72b
AD		 1604 u32 gb_addr_config = 0;
1605 u32 mc_shared_chmap, mc_arb_ramcfg;
0a96d72b 1606 u32 sx_debug_1;
0a96d72b
AD		 1607 u32 hdp_host_path_cntl;
1608 u32 tmp;
1609 int i, j;
1610
1611 switch (rdev->family) {
1612 case CHIP_TAHITI:
1613 rdev->config.si.max_shader_engines = 2;
0a96d72b 1614 rdev->config.si.max_tile_pipes = 12;
1a8ca750
AD		 1615 rdev->config.si.max_cu_per_sh = 8;
1616 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1617 rdev->config.si.max_backends_per_se = 4;
1618 rdev->config.si.max_texture_channel_caches = 12;
1619 rdev->config.si.max_gprs = 256;
1620 rdev->config.si.max_gs_threads = 32;
1621 rdev->config.si.max_hw_contexts = 8;
1622
1623 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1624 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1625 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1626 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1627 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1628 break;
1629 case CHIP_PITCAIRN:
1630 rdev->config.si.max_shader_engines = 2;
0a96d72b 1631 rdev->config.si.max_tile_pipes = 8;
1a8ca750
AD		 1632 rdev->config.si.max_cu_per_sh = 5;
1633 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1634 rdev->config.si.max_backends_per_se = 4;
1635 rdev->config.si.max_texture_channel_caches = 8;
1636 rdev->config.si.max_gprs = 256;
1637 rdev->config.si.max_gs_threads = 32;
1638 rdev->config.si.max_hw_contexts = 8;
1639
1640 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1641 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1642 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1643 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1644 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1645 break;
1646 case CHIP_VERDE:
1647 default:
1648 rdev->config.si.max_shader_engines = 1;
0a96d72b 1649 rdev->config.si.max_tile_pipes = 4;
1a8ca750
AD		 1650 rdev->config.si.max_cu_per_sh = 2;
1651 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1652 rdev->config.si.max_backends_per_se = 4;
1653 rdev->config.si.max_texture_channel_caches = 4;
1654 rdev->config.si.max_gprs = 256;
1655 rdev->config.si.max_gs_threads = 32;
1656 rdev->config.si.max_hw_contexts = 8;
1657
d0ae7fcc
AD		 1658 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1659 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1660 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1661 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1662 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1663 break;
1664 case CHIP_OLAND:
1665 rdev->config.si.max_shader_engines = 1;
1666 rdev->config.si.max_tile_pipes = 4;
1667 rdev->config.si.max_cu_per_sh = 6;
1668 rdev->config.si.max_sh_per_se = 1;
1669 rdev->config.si.max_backends_per_se = 2;
1670 rdev->config.si.max_texture_channel_caches = 4;
1671 rdev->config.si.max_gprs = 256;
1672 rdev->config.si.max_gs_threads = 16;
1673 rdev->config.si.max_hw_contexts = 8;
1674
0a96d72b
AD		 1675 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1676 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1677 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1678 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1679 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1680 break;
1681 }
1682
1683 /* Initialize HDP */
1684 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1685 WREG32((0x2c14 + j), 0x00000000);
1686 WREG32((0x2c18 + j), 0x00000000);
1687 WREG32((0x2c1c + j), 0x00000000);
1688 WREG32((0x2c20 + j), 0x00000000);
1689 WREG32((0x2c24 + j), 0x00000000);
1690 }
1691
1692 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1693
1694 evergreen_fix_pci_max_read_req_size(rdev);
1695
1696 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1697
1698 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1699 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1700
0a96d72b 1701 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
0a96d72b
AD		 1702 rdev->config.si.mem_max_burst_length_bytes = 256;
1703 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1704 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1705 if (rdev->config.si.mem_row_size_in_kb > 4)
1706 rdev->config.si.mem_row_size_in_kb = 4;
1707 /* XXX use MC settings? */
1708 rdev->config.si.shader_engine_tile_size = 32;
1709 rdev->config.si.num_gpus = 1;
1710 rdev->config.si.multi_gpu_tile_size = 64;
1711
1a8ca750
AD		 1712 /* fix up row size */
1713 gb_addr_config &= ~ROW_SIZE_MASK;
0a96d72b
AD		 1714 switch (rdev->config.si.mem_row_size_in_kb) {
1715 case 1:
1716 default:
1717 gb_addr_config |= ROW_SIZE(0);
1718 break;
1719 case 2:
1720 gb_addr_config |= ROW_SIZE(1);
1721 break;
1722 case 4:
1723 gb_addr_config |= ROW_SIZE(2);
1724 break;
1725 }
1726
0a96d72b
AD		 1727 /* setup tiling info dword. gb_addr_config is not adequate since it does
1728 * not have bank info, so create a custom tiling dword.
1729 * bits 3:0 num_pipes
1730 * bits 7:4 num_banks
1731 * bits 11:8 group_size
1732 * bits 15:12 row_size
1733 */
1734 rdev->config.si.tile_config = 0;
1735 switch (rdev->config.si.num_tile_pipes) {
1736 case 1:
1737 rdev->config.si.tile_config |= (0 << 0);
1738 break;
1739 case 2:
1740 rdev->config.si.tile_config |= (1 << 0);
1741 break;
1742 case 4:
1743 rdev->config.si.tile_config |= (2 << 0);
1744 break;
1745 case 8:
1746 default:
1747 /* XXX what about 12? */
1748 rdev->config.si.tile_config |= (3 << 0);
1749 break;
dca571a6
CK		 1750 }
1751 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1752 case 0: /* four banks */
1a8ca750 1753 rdev->config.si.tile_config |= 0 << 4;
dca571a6
CK		 1754 break;
1755 case 1: /* eight banks */
1756 rdev->config.si.tile_config |= 1 << 4;
1757 break;
1758 case 2: /* sixteen banks */
1759 default:
1760 rdev->config.si.tile_config |= 2 << 4;
1761 break;
1762 }
0a96d72b
AD		 1763 rdev->config.si.tile_config |=
1764 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1765 rdev->config.si.tile_config |=
1766 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1767
0a96d72b
AD		 1768 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1769 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
7c1c7c18 1770 WREG32(DMIF_ADDR_CALC, gb_addr_config);
0a96d72b 1771 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
8c5fd7ef
AD		 1772 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1773 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
9a21059d
CK		 1774 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1775 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1776 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
0a96d72b 1777
1a8ca750 1778 si_tiling_mode_table_init(rdev);
0a96d72b 1779
1a8ca750
AD		 1780 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1781 rdev->config.si.max_sh_per_se,
1782 rdev->config.si.max_backends_per_se);
0a96d72b 1783
1a8ca750
AD		 1784 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1785 rdev->config.si.max_sh_per_se,
1786 rdev->config.si.max_cu_per_sh);
0a96d72b 1787
0a96d72b
AD		 1788
1789 /* set HW defaults for 3D engine */
1790 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1791 ROQ_IB2_START(0x2b)));
1792 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1793
1794 sx_debug_1 = RREG32(SX_DEBUG_1);
1795 WREG32(SX_DEBUG_1, sx_debug_1);
1796
1797 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1798
1799 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1800 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1801 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1802 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1803
1804 WREG32(VGT_NUM_INSTANCES, 1);
1805
1806 WREG32(CP_PERFMON_CNTL, 0);
1807
1808 WREG32(SQ_CONFIG, 0);
1809
1810 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1811 FORCE_EOV_MAX_REZ_CNT(255)));
1812
1813 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1814 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1815
1816 WREG32(VGT_GS_VERTEX_REUSE, 16);
1817 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1818
1819 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1820 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1821 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1822 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1823 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1824 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1825 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1826 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1827
1828 tmp = RREG32(HDP_MISC_CNTL);
1829 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1830 WREG32(HDP_MISC_CNTL, tmp);
1831
1832 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1833 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1834
1835 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1836
1837 udelay(50);
1838}
c476dde2 1839
2ece2e8b
AD		 1840/*
1841 * GPU scratch registers helpers function.
1842 */
1843static void si_scratch_init(struct radeon_device *rdev)
1844{
1845 int i;
1846
1847 rdev->scratch.num_reg = 7;
1848 rdev->scratch.reg_base = SCRATCH_REG0;
1849 for (i = 0; i < rdev->scratch.num_reg; i++) {
1850 rdev->scratch.free[i] = true;
1851 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1852 }
1853}
1854
1855void si_fence_ring_emit(struct radeon_device *rdev,
1856 struct radeon_fence *fence)
1857{
1858 struct radeon_ring *ring = &rdev->ring[fence->ring];
1859 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1860
1861 /* flush read cache over gart */
1862 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1863 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1864 radeon_ring_write(ring, 0);
1865 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1866 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1867 PACKET3_TC_ACTION_ENA |
1868 PACKET3_SH_KCACHE_ACTION_ENA |
1869 PACKET3_SH_ICACHE_ACTION_ENA);
1870 radeon_ring_write(ring, 0xFFFFFFFF);
1871 radeon_ring_write(ring, 0);
1872 radeon_ring_write(ring, 10); /* poll interval */
1873 /* EVENT_WRITE_EOP - flush caches, send int */
1874 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1875 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1876 radeon_ring_write(ring, addr & 0xffffffff);
1877 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1878 radeon_ring_write(ring, fence->seq);
1879 radeon_ring_write(ring, 0);
1880}
1881
1882/*
1883 * IB stuff
1884 */
1885void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1886{
876dc9f3 1887 struct radeon_ring *ring = &rdev->ring[ib->ring];
2ece2e8b
AD		 1888 u32 header;
1889
a85a7da4
AD		 1890 if (ib->is_const_ib) {
1891 /* set switch buffer packet before const IB */
1892 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1893 radeon_ring_write(ring, 0);
45df6803 1894
2ece2e8b 1895 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
a85a7da4 1896 } else {
89d35807 1897 u32 next_rptr;
a85a7da4 1898 if (ring->rptr_save_reg) {
89d35807 1899 next_rptr = ring->wptr + 3 + 4 + 8;
a85a7da4
AD		 1900 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1901 radeon_ring_write(ring, ((ring->rptr_save_reg -
1902 PACKET3_SET_CONFIG_REG_START) >> 2));
1903 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1904 } else if (rdev->wb.enabled) {
1905 next_rptr = ring->wptr + 5 + 4 + 8;
1906 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1907 radeon_ring_write(ring, (1 << 8));
1908 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1909 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1910 radeon_ring_write(ring, next_rptr);
a85a7da4
AD		 1911 }
1912
2ece2e8b 1913 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
a85a7da4 1914 }
2ece2e8b
AD		 1915
1916 radeon_ring_write(ring, header);
1917 radeon_ring_write(ring,
1918#ifdef __BIG_ENDIAN
1919 (2 << 0) |
1920#endif
1921 (ib->gpu_addr & 0xFFFFFFFC));
1922 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4bf3dd92
CK		 1923 radeon_ring_write(ring, ib->length_dw |
1924 (ib->vm ? (ib->vm->id << 24) : 0));
2ece2e8b 1925
a85a7da4
AD		 1926 if (!ib->is_const_ib) {
1927 /* flush read cache over gart for this vmid */
1928 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1929 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 1930 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
a85a7da4
AD		 1931 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1932 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1933 PACKET3_TC_ACTION_ENA |
1934 PACKET3_SH_KCACHE_ACTION_ENA |
1935 PACKET3_SH_ICACHE_ACTION_ENA);
1936 radeon_ring_write(ring, 0xFFFFFFFF);
1937 radeon_ring_write(ring, 0);
1938 radeon_ring_write(ring, 10); /* poll interval */
1939 }
2ece2e8b
AD		 1940}
1941
48c0c902
AD		 1942/*
1943 * CP.
1944 */
1945static void si_cp_enable(struct radeon_device *rdev, bool enable)
1946{
1947 if (enable)
1948 WREG32(CP_ME_CNTL, 0);
1949 else {
1950 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1951 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1952 WREG32(SCRATCH_UMSK, 0);
8c5fd7ef
AD		 1953 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1954 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1955 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
48c0c902
AD		 1956 }
1957 udelay(50);
1958}
1959
1960static int si_cp_load_microcode(struct radeon_device *rdev)
1961{
1962 const __be32 *fw_data;
1963 int i;
1964
1965 if (!rdev->me_fw || !rdev->pfp_fw)
1966 return -EINVAL;
1967
1968 si_cp_enable(rdev, false);
1969
1970 /* PFP */
1971 fw_data = (const __be32 *)rdev->pfp_fw->data;
1972 WREG32(CP_PFP_UCODE_ADDR, 0);
1973 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1974 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1975 WREG32(CP_PFP_UCODE_ADDR, 0);
1976
1977 /* CE */
1978 fw_data = (const __be32 *)rdev->ce_fw->data;
1979 WREG32(CP_CE_UCODE_ADDR, 0);
1980 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1981 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1982 WREG32(CP_CE_UCODE_ADDR, 0);
1983
1984 /* ME */
1985 fw_data = (const __be32 *)rdev->me_fw->data;
1986 WREG32(CP_ME_RAM_WADDR, 0);
1987 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1988 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1989 WREG32(CP_ME_RAM_WADDR, 0);
1990
1991 WREG32(CP_PFP_UCODE_ADDR, 0);
1992 WREG32(CP_CE_UCODE_ADDR, 0);
1993 WREG32(CP_ME_RAM_WADDR, 0);
1994 WREG32(CP_ME_RAM_RADDR, 0);
1995 return 0;
1996}
1997
1998static int si_cp_start(struct radeon_device *rdev)
1999{
2000 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2001 int r, i;
2002
2003 r = radeon_ring_lock(rdev, ring, 7 + 4);
2004 if (r) {
2005 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2006 return r;
2007 }
2008 /* init the CP */
2009 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2010 radeon_ring_write(ring, 0x1);
2011 radeon_ring_write(ring, 0x0);
2012 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
2013 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2014 radeon_ring_write(ring, 0);
2015 radeon_ring_write(ring, 0);
2016
2017 /* init the CE partitions */
2018 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2019 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2020 radeon_ring_write(ring, 0xc000);
2021 radeon_ring_write(ring, 0xe000);
2022 radeon_ring_unlock_commit(rdev, ring);
2023
2024 si_cp_enable(rdev, true);
2025
2026 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
2027 if (r) {
2028 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2029 return r;
2030 }
2031
2032 /* setup clear context state */
2033 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2034 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2035
2036 for (i = 0; i < si_default_size; i++)
2037 radeon_ring_write(ring, si_default_state[i]);
2038
2039 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2040 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2041
2042 /* set clear context state */
2043 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2044 radeon_ring_write(ring, 0);
2045
2046 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2047 radeon_ring_write(ring, 0x00000316);
2048 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2049 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2050
2051 radeon_ring_unlock_commit(rdev, ring);
2052
2053 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
2054 ring = &rdev->ring[i];
2055 r = radeon_ring_lock(rdev, ring, 2);
2056
2057 /* clear the compute context state */
2058 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2059 radeon_ring_write(ring, 0);
2060
2061 radeon_ring_unlock_commit(rdev, ring);
2062 }
2063
2064 return 0;
2065}
2066
2067static void si_cp_fini(struct radeon_device *rdev)
2068{
45df6803 2069 struct radeon_ring *ring;
48c0c902 2070 si_cp_enable(rdev, false);
45df6803
CK		 2071
2072 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2073 radeon_ring_fini(rdev, ring);
2074 radeon_scratch_free(rdev, ring->rptr_save_reg);
2075
2076 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2077 radeon_ring_fini(rdev, ring);
2078 radeon_scratch_free(rdev, ring->rptr_save_reg);
2079
2080 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2081 radeon_ring_fini(rdev, ring);
2082 radeon_scratch_free(rdev, ring->rptr_save_reg);
48c0c902
AD		 2083}
2084
2085static int si_cp_resume(struct radeon_device *rdev)
2086{
2087 struct radeon_ring *ring;
2088 u32 tmp;
2089 u32 rb_bufsz;
2090 int r;
2091
2092 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2093 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2094 SOFT_RESET_PA |
2095 SOFT_RESET_VGT |
2096 SOFT_RESET_SPI |
2097 SOFT_RESET_SX));
2098 RREG32(GRBM_SOFT_RESET);
2099 mdelay(15);
2100 WREG32(GRBM_SOFT_RESET, 0);
2101 RREG32(GRBM_SOFT_RESET);
2102
2103 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2104 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2105
2106 /* Set the write pointer delay */
2107 WREG32(CP_RB_WPTR_DELAY, 0);
2108
2109 WREG32(CP_DEBUG, 0);
2110 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2111
2112 /* ring 0 - compute and gfx */
2113 /* Set ring buffer size */
2114 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2115 rb_bufsz = drm_order(ring->ring_size / 8);
2116 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2117#ifdef __BIG_ENDIAN
2118 tmp |= BUF_SWAP_32BIT;
2119#endif
2120 WREG32(CP_RB0_CNTL, tmp);
2121
2122 /* Initialize the ring buffer's read and write pointers */
2123 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2124 ring->wptr = 0;
2125 WREG32(CP_RB0_WPTR, ring->wptr);
2126
48fc7f7e 2127 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2128 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2129 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2130
2131 if (rdev->wb.enabled)
2132 WREG32(SCRATCH_UMSK, 0xff);
2133 else {
2134 tmp |= RB_NO_UPDATE;
2135 WREG32(SCRATCH_UMSK, 0);
2136 }
2137
2138 mdelay(1);
2139 WREG32(CP_RB0_CNTL, tmp);
2140
2141 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2142
2143 ring->rptr = RREG32(CP_RB0_RPTR);
2144
2145 /* ring1 - compute only */
2146 /* Set ring buffer size */
2147 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2148 rb_bufsz = drm_order(ring->ring_size / 8);
2149 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2150#ifdef __BIG_ENDIAN
2151 tmp |= BUF_SWAP_32BIT;
2152#endif
2153 WREG32(CP_RB1_CNTL, tmp);
2154
2155 /* Initialize the ring buffer's read and write pointers */
2156 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2157 ring->wptr = 0;
2158 WREG32(CP_RB1_WPTR, ring->wptr);
2159
48fc7f7e 2160 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2161 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2162 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2163
2164 mdelay(1);
2165 WREG32(CP_RB1_CNTL, tmp);
2166
2167 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2168
2169 ring->rptr = RREG32(CP_RB1_RPTR);
2170
2171 /* ring2 - compute only */
2172 /* Set ring buffer size */
2173 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2174 rb_bufsz = drm_order(ring->ring_size / 8);
2175 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2176#ifdef __BIG_ENDIAN
2177 tmp |= BUF_SWAP_32BIT;
2178#endif
2179 WREG32(CP_RB2_CNTL, tmp);
2180
2181 /* Initialize the ring buffer's read and write pointers */
2182 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2183 ring->wptr = 0;
2184 WREG32(CP_RB2_WPTR, ring->wptr);
2185
48fc7f7e 2186 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2187 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2188 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2189
2190 mdelay(1);
2191 WREG32(CP_RB2_CNTL, tmp);
2192
2193 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2194
2195 ring->rptr = RREG32(CP_RB2_RPTR);
2196
2197 /* start the rings */
2198 si_cp_start(rdev);
2199 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2200 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2201 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2202 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2203 if (r) {
2204 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2205 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2206 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2207 return r;
2208 }
2209 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2210 if (r) {
2211 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2212 }
2213 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2214 if (r) {
2215 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2216 }
2217
2218 return 0;
2219}
2220
014bb209 2221static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
06bc6df0 2222{
014bb209 2223 u32 reset_mask = 0;
1c534671 2224 u32 tmp;
06bc6df0 2225
014bb209
AD		 2226 /* GRBM_STATUS */
2227 tmp = RREG32(GRBM_STATUS);
2228 if (tmp & (PA_BUSY | SC_BUSY |
2229 BCI_BUSY | SX_BUSY |
2230 TA_BUSY | VGT_BUSY |
2231 DB_BUSY | CB_BUSY |
2232 GDS_BUSY | SPI_BUSY |
2233 IA_BUSY | IA_BUSY_NO_DMA))
2234 reset_mask |= RADEON_RESET_GFX;
2235
2236 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2237 CP_BUSY | CP_COHERENCY_BUSY))
2238 reset_mask |= RADEON_RESET_CP;
2239
2240 if (tmp & GRBM_EE_BUSY)
2241 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2242
2243 /* GRBM_STATUS2 */
2244 tmp = RREG32(GRBM_STATUS2);
2245 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2246 reset_mask |= RADEON_RESET_RLC;
2247
2248 /* DMA_STATUS_REG 0 */
2249 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2250 if (!(tmp & DMA_IDLE))
2251 reset_mask |= RADEON_RESET_DMA;
2252
2253 /* DMA_STATUS_REG 1 */
2254 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2255 if (!(tmp & DMA_IDLE))
2256 reset_mask |= RADEON_RESET_DMA1;
2257
2258 /* SRBM_STATUS2 */
2259 tmp = RREG32(SRBM_STATUS2);
2260 if (tmp & DMA_BUSY)
2261 reset_mask |= RADEON_RESET_DMA;
2262
2263 if (tmp & DMA1_BUSY)
2264 reset_mask |= RADEON_RESET_DMA1;
2265
2266 /* SRBM_STATUS */
2267 tmp = RREG32(SRBM_STATUS);
2268
2269 if (tmp & IH_BUSY)
2270 reset_mask |= RADEON_RESET_IH;
2271
2272 if (tmp & SEM_BUSY)
2273 reset_mask |= RADEON_RESET_SEM;
2274
2275 if (tmp & GRBM_RQ_PENDING)
2276 reset_mask |= RADEON_RESET_GRBM;
2277
2278 if (tmp & VMC_BUSY)
2279 reset_mask |= RADEON_RESET_VMC;
19fc42ed 2280
014bb209
AD		 2281 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2282 MCC_BUSY | MCD_BUSY))
2283 reset_mask |= RADEON_RESET_MC;
2284
2285 if (evergreen_is_display_hung(rdev))
2286 reset_mask |= RADEON_RESET_DISPLAY;
2287
2288 /* VM_L2_STATUS */
2289 tmp = RREG32(VM_L2_STATUS);
2290 if (tmp & L2_BUSY)
2291 reset_mask |= RADEON_RESET_VMC;
2292
d808fc88
AD		 2293 /* Skip MC reset as it's mostly likely not hung, just busy */
2294 if (reset_mask & RADEON_RESET_MC) {
2295 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
2296 reset_mask &= ~RADEON_RESET_MC;
2297 }
2298
014bb209
AD		 2299 return reset_mask;
2300}
2301
2302static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2303{
2304 struct evergreen_mc_save save;
2305 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2306 u32 tmp;
19fc42ed 2307
06bc6df0 2308 if (reset_mask == 0)
014bb209 2309 return;
06bc6df0
AD		 2310
2311 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2312
1c534671 2313 evergreen_print_gpu_status_regs(rdev);
06bc6df0
AD		 2314 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2315 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2316 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2317 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2318
1c534671
AD		 2319 /* Disable CP parsing/prefetching */
2320 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2321
2322 if (reset_mask & RADEON_RESET_DMA) {
2323 /* dma0 */
2324 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2325 tmp &= ~DMA_RB_ENABLE;
2326 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
014bb209
AD		 2327 }
2328 if (reset_mask & RADEON_RESET_DMA1) {
1c534671
AD		 2329 /* dma1 */
2330 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2331 tmp &= ~DMA_RB_ENABLE;
2332 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2333 }
2334
f770d78a
AD		 2335 udelay(50);
2336
2337 evergreen_mc_stop(rdev, &save);
2338 if (evergreen_mc_wait_for_idle(rdev)) {
2339 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2340 }
2341
1c534671
AD		 2342 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2343 grbm_soft_reset = SOFT_RESET_CB |
2344 SOFT_RESET_DB |
2345 SOFT_RESET_GDS |
2346 SOFT_RESET_PA |
2347 SOFT_RESET_SC |
2348 SOFT_RESET_BCI |
2349 SOFT_RESET_SPI |
2350 SOFT_RESET_SX |
2351 SOFT_RESET_TC |
2352 SOFT_RESET_TA |
2353 SOFT_RESET_VGT |
2354 SOFT_RESET_IA;
2355 }
2356
2357 if (reset_mask & RADEON_RESET_CP) {
2358 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2359
2360 srbm_soft_reset |= SOFT_RESET_GRBM;
2361 }
06bc6df0
AD		 2362
2363 if (reset_mask & RADEON_RESET_DMA)
014bb209
AD		 2364 srbm_soft_reset |= SOFT_RESET_DMA;
2365
2366 if (reset_mask & RADEON_RESET_DMA1)
2367 srbm_soft_reset |= SOFT_RESET_DMA1;
2368
2369 if (reset_mask & RADEON_RESET_DISPLAY)
2370 srbm_soft_reset |= SOFT_RESET_DC;
2371
2372 if (reset_mask & RADEON_RESET_RLC)
2373 grbm_soft_reset |= SOFT_RESET_RLC;
2374
2375 if (reset_mask & RADEON_RESET_SEM)
2376 srbm_soft_reset |= SOFT_RESET_SEM;
2377
2378 if (reset_mask & RADEON_RESET_IH)
2379 srbm_soft_reset |= SOFT_RESET_IH;
2380
2381 if (reset_mask & RADEON_RESET_GRBM)
2382 srbm_soft_reset |= SOFT_RESET_GRBM;
2383
2384 if (reset_mask & RADEON_RESET_VMC)
2385 srbm_soft_reset |= SOFT_RESET_VMC;
2386
2387 if (reset_mask & RADEON_RESET_MC)
2388 srbm_soft_reset |= SOFT_RESET_MC;
1c534671
AD		 2389
2390 if (grbm_soft_reset) {
2391 tmp = RREG32(GRBM_SOFT_RESET);
2392 tmp |= grbm_soft_reset;
2393 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2394 WREG32(GRBM_SOFT_RESET, tmp);
2395 tmp = RREG32(GRBM_SOFT_RESET);
2396
2397 udelay(50);
2398
2399 tmp &= ~grbm_soft_reset;
2400 WREG32(GRBM_SOFT_RESET, tmp);
2401 tmp = RREG32(GRBM_SOFT_RESET);
2402 }
2403
2404 if (srbm_soft_reset) {
2405 tmp = RREG32(SRBM_SOFT_RESET);
2406 tmp |= srbm_soft_reset;
2407 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2408 WREG32(SRBM_SOFT_RESET, tmp);
2409 tmp = RREG32(SRBM_SOFT_RESET);
2410
2411 udelay(50);
2412
2413 tmp &= ~srbm_soft_reset;
2414 WREG32(SRBM_SOFT_RESET, tmp);
2415 tmp = RREG32(SRBM_SOFT_RESET);
2416 }
06bc6df0
AD		 2417
2418 /* Wait a little for things to settle down */
2419 udelay(50);
2420
c476dde2 2421 evergreen_mc_resume(rdev, &save);
1c534671
AD		 2422 udelay(50);
2423
1c534671 2424 evergreen_print_gpu_status_regs(rdev);
c476dde2
AD		 2425}
2426
2427int si_asic_reset(struct radeon_device *rdev)
2428{
014bb209
AD		 2429 u32 reset_mask;
2430
2431 reset_mask = si_gpu_check_soft_reset(rdev);
2432
2433 if (reset_mask)
2434 r600_set_bios_scratch_engine_hung(rdev, true);
2435
2436 si_gpu_soft_reset(rdev, reset_mask);
2437
2438 reset_mask = si_gpu_check_soft_reset(rdev);
2439
2440 if (!reset_mask)
2441 r600_set_bios_scratch_engine_hung(rdev, false);
2442
2443 return 0;
c476dde2
AD		 2444}
2445
123bc183
AD		 2446/**
2447 * si_gfx_is_lockup - Check if the GFX engine is locked up
2448 *
2449 * @rdev: radeon_device pointer
2450 * @ring: radeon_ring structure holding ring information
2451 *
2452 * Check if the GFX engine is locked up.
2453 * Returns true if the engine appears to be locked up, false if not.
2454 */
2455bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2456{
2457 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2458
2459 if (!(reset_mask & (RADEON_RESET_GFX |
2460 RADEON_RESET_COMPUTE |
2461 RADEON_RESET_CP))) {
2462 radeon_ring_lockup_update(ring);
2463 return false;
2464 }
2465 /* force CP activities */
2466 radeon_ring_force_activity(rdev, ring);
2467 return radeon_ring_test_lockup(rdev, ring);
2468}
2469
2470/**
2471 * si_dma_is_lockup - Check if the DMA engine is locked up
2472 *
2473 * @rdev: radeon_device pointer
2474 * @ring: radeon_ring structure holding ring information
2475 *
2476 * Check if the async DMA engine is locked up.
2477 * Returns true if the engine appears to be locked up, false if not.
2478 */
2479bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2480{
2481 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2482 u32 mask;
2483
2484 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2485 mask = RADEON_RESET_DMA;
2486 else
2487 mask = RADEON_RESET_DMA1;
2488
2489 if (!(reset_mask & mask)) {
2490 radeon_ring_lockup_update(ring);
2491 return false;
2492 }
2493 /* force ring activities */
2494 radeon_ring_force_activity(rdev, ring);
2495 return radeon_ring_test_lockup(rdev, ring);
2496}
2497
d2800ee5
AD		 2498/* MC */
2499static void si_mc_program(struct radeon_device *rdev)
2500{
2501 struct evergreen_mc_save save;
2502 u32 tmp;
2503 int i, j;
2504
2505 /* Initialize HDP */
2506 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2507 WREG32((0x2c14 + j), 0x00000000);
2508 WREG32((0x2c18 + j), 0x00000000);
2509 WREG32((0x2c1c + j), 0x00000000);
2510 WREG32((0x2c20 + j), 0x00000000);
2511 WREG32((0x2c24 + j), 0x00000000);
2512 }
2513 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2514
2515 evergreen_mc_stop(rdev, &save);
2516 if (radeon_mc_wait_for_idle(rdev)) {
2517 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2518 }
2519 /* Lockout access through VGA aperture*/
2520 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2521 /* Update configuration */
2522 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2523 rdev->mc.vram_start >> 12);
2524 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2525 rdev->mc.vram_end >> 12);
2526 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2527 rdev->vram_scratch.gpu_addr >> 12);
2528 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2529 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2530 WREG32(MC_VM_FB_LOCATION, tmp);
2531 /* XXX double check these! */
2532 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2533 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2534 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2535 WREG32(MC_VM_AGP_BASE, 0);
2536 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2537 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2538 if (radeon_mc_wait_for_idle(rdev)) {
2539 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2540 }
2541 evergreen_mc_resume(rdev, &save);
2542 /* we need to own VRAM, so turn off the VGA renderer here
2543 * to stop it overwriting our objects */
2544 rv515_vga_render_disable(rdev);
2545}
2546
d2800ee5
AD		 2547static void si_vram_gtt_location(struct radeon_device *rdev,
2548 struct radeon_mc *mc)
2549{
2550 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2551 /* leave room for at least 1024M GTT */
2552 dev_warn(rdev->dev, "limiting VRAM\n");
2553 mc->real_vram_size = 0xFFC0000000ULL;
2554 mc->mc_vram_size = 0xFFC0000000ULL;
2555 }
9ed8b1f9 2556 radeon_vram_location(rdev, &rdev->mc, 0);
d2800ee5 2557 rdev->mc.gtt_base_align = 0;
9ed8b1f9 2558 radeon_gtt_location(rdev, mc);
d2800ee5
AD		 2559}
2560
2561static int si_mc_init(struct radeon_device *rdev)
2562{
2563 u32 tmp;
2564 int chansize, numchan;
2565
2566 /* Get VRAM informations */
2567 rdev->mc.vram_is_ddr = true;
2568 tmp = RREG32(MC_ARB_RAMCFG);
2569 if (tmp & CHANSIZE_OVERRIDE) {
2570 chansize = 16;
2571 } else if (tmp & CHANSIZE_MASK) {
2572 chansize = 64;
2573 } else {
2574 chansize = 32;
2575 }
2576 tmp = RREG32(MC_SHARED_CHMAP);
2577 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2578 case 0:
2579 default:
2580 numchan = 1;
2581 break;
2582 case 1:
2583 numchan = 2;
2584 break;
2585 case 2:
2586 numchan = 4;
2587 break;
2588 case 3:
2589 numchan = 8;
2590 break;
2591 case 4:
2592 numchan = 3;
2593 break;
2594 case 5:
2595 numchan = 6;
2596 break;
2597 case 6:
2598 numchan = 10;
2599 break;
2600 case 7:
2601 numchan = 12;
2602 break;
2603 case 8:
2604 numchan = 16;
2605 break;
2606 }
2607 rdev->mc.vram_width = numchan * chansize;
2608 /* Could aper size report 0 ? */
2609 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2610 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2611 /* size in MB on si */
2612 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2613 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2614 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2615 si_vram_gtt_location(rdev, &rdev->mc);
2616 radeon_update_bandwidth_info(rdev);
2617
2618 return 0;
2619}
2620
2621/*
2622 * GART
2623 */
2624void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2625{
2626 /* flush hdp cache */
2627 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2628
2629 /* bits 0-15 are the VM contexts0-15 */
2630 WREG32(VM_INVALIDATE_REQUEST, 1);
2631}
2632
1109ca09 2633static int si_pcie_gart_enable(struct radeon_device *rdev)
d2800ee5
AD		 2634{
2635 int r, i;
2636
2637 if (rdev->gart.robj == NULL) {
2638 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2639 return -EINVAL;
2640 }
2641 r = radeon_gart_table_vram_pin(rdev);
2642 if (r)
2643 return r;
2644 radeon_gart_restore(rdev);
2645 /* Setup TLB control */
2646 WREG32(MC_VM_MX_L1_TLB_CNTL,
2647 (0xA << 7) |
2648 ENABLE_L1_TLB |
2649 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2650 ENABLE_ADVANCED_DRIVER_MODEL |
2651 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2652 /* Setup L2 cache */
2653 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2654 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2655 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2656 EFFECTIVE_L2_QUEUE_SIZE(7) |
2657 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2658 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2659 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2660 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2661 /* setup context0 */
2662 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2663 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2664 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2665 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2666 (u32)(rdev->dummy_page.addr >> 12));
2667 WREG32(VM_CONTEXT0_CNTL2, 0);
2668 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2669 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2670
2671 WREG32(0x15D4, 0);
2672 WREG32(0x15D8, 0);
2673 WREG32(0x15DC, 0);
2674
2675 /* empty context1-15 */
d2800ee5
AD		 2676 /* set vm size, must be a multiple of 4 */
2677 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
c21b328e 2678 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
23d4f1f2
AD		 2679 /* Assign the pt base to something valid for now; the pts used for
2680 * the VMs are determined by the application and setup and assigned
2681 * on the fly in the vm part of radeon_gart.c
2682 */
d2800ee5
AD		 2683 for (i = 1; i < 16; i++) {
2684 if (i < 8)
2685 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2686 rdev->gart.table_addr >> 12);
2687 else
2688 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2689 rdev->gart.table_addr >> 12);
2690 }
2691
2692 /* enable context1-15 */
2693 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2694 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 2695 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 2696 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 2697 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2698 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2699 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2700 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2701 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2702 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2703 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2704 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2705 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2706 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2707 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2708 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
d2800ee5
AD		 2709
2710 si_pcie_gart_tlb_flush(rdev);
2711 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2712 (unsigned)(rdev->mc.gtt_size >> 20),
2713 (unsigned long long)rdev->gart.table_addr);
2714 rdev->gart.ready = true;
2715 return 0;
2716}
2717
1109ca09 2718static void si_pcie_gart_disable(struct radeon_device *rdev)
d2800ee5
AD		 2719{
2720 /* Disable all tables */
2721 WREG32(VM_CONTEXT0_CNTL, 0);
2722 WREG32(VM_CONTEXT1_CNTL, 0);
2723 /* Setup TLB control */
2724 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2725 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2726 /* Setup L2 cache */
2727 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2728 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2729 EFFECTIVE_L2_QUEUE_SIZE(7) |
2730 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2731 WREG32(VM_L2_CNTL2, 0);
2732 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2733 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2734 radeon_gart_table_vram_unpin(rdev);
2735}
2736
1109ca09 2737static void si_pcie_gart_fini(struct radeon_device *rdev)
d2800ee5
AD		 2738{
2739 si_pcie_gart_disable(rdev);
2740 radeon_gart_table_vram_free(rdev);
2741 radeon_gart_fini(rdev);
2742}
2743
498dd8b3
AD		 2744/* vm parser */
2745static bool si_vm_reg_valid(u32 reg)
2746{
2747 /* context regs are fine */
2748 if (reg >= 0x28000)
2749 return true;
2750
2751 /* check config regs */
2752 switch (reg) {
2753 case GRBM_GFX_INDEX:
f418b88a 2754 case CP_STRMOUT_CNTL:
498dd8b3
AD		 2755 case VGT_VTX_VECT_EJECT_REG:
2756 case VGT_CACHE_INVALIDATION:
2757 case VGT_ESGS_RING_SIZE:
2758 case VGT_GSVS_RING_SIZE:
2759 case VGT_GS_VERTEX_REUSE:
2760 case VGT_PRIMITIVE_TYPE:
2761 case VGT_INDEX_TYPE:
2762 case VGT_NUM_INDICES:
2763 case VGT_NUM_INSTANCES:
2764 case VGT_TF_RING_SIZE:
2765 case VGT_HS_OFFCHIP_PARAM:
2766 case VGT_TF_MEMORY_BASE:
2767 case PA_CL_ENHANCE:
2768 case PA_SU_LINE_STIPPLE_VALUE:
2769 case PA_SC_LINE_STIPPLE_STATE:
2770 case PA_SC_ENHANCE:
2771 case SQC_CACHES:
2772 case SPI_STATIC_THREAD_MGMT_1:
2773 case SPI_STATIC_THREAD_MGMT_2:
2774 case SPI_STATIC_THREAD_MGMT_3:
2775 case SPI_PS_MAX_WAVE_ID:
2776 case SPI_CONFIG_CNTL:
2777 case SPI_CONFIG_CNTL_1:
2778 case TA_CNTL_AUX:
2779 return true;
2780 default:
2781 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2782 return false;
2783 }
2784}
2785
2786static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2787 u32 *ib, struct radeon_cs_packet *pkt)
2788{
2789 switch (pkt->opcode) {
2790 case PACKET3_NOP:
2791 case PACKET3_SET_BASE:
2792 case PACKET3_SET_CE_DE_COUNTERS:
2793 case PACKET3_LOAD_CONST_RAM:
2794 case PACKET3_WRITE_CONST_RAM:
2795 case PACKET3_WRITE_CONST_RAM_OFFSET:
2796 case PACKET3_DUMP_CONST_RAM:
2797 case PACKET3_INCREMENT_CE_COUNTER:
2798 case PACKET3_WAIT_ON_DE_COUNTER:
2799 case PACKET3_CE_WRITE:
2800 break;
2801 default:
2802 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2803 return -EINVAL;
2804 }
2805 return 0;
2806}
2807
2808static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2809 u32 *ib, struct radeon_cs_packet *pkt)
2810{
2811 u32 idx = pkt->idx + 1;
2812 u32 idx_value = ib[idx];
2813 u32 start_reg, end_reg, reg, i;
5aa709be 2814 u32 command, info;
498dd8b3
AD		 2815
2816 switch (pkt->opcode) {
2817 case PACKET3_NOP:
2818 case PACKET3_SET_BASE:
2819 case PACKET3_CLEAR_STATE:
2820 case PACKET3_INDEX_BUFFER_SIZE:
2821 case PACKET3_DISPATCH_DIRECT:
2822 case PACKET3_DISPATCH_INDIRECT:
2823 case PACKET3_ALLOC_GDS:
2824 case PACKET3_WRITE_GDS_RAM:
2825 case PACKET3_ATOMIC_GDS:
2826 case PACKET3_ATOMIC:
2827 case PACKET3_OCCLUSION_QUERY:
2828 case PACKET3_SET_PREDICATION:
2829 case PACKET3_COND_EXEC:
2830 case PACKET3_PRED_EXEC:
2831 case PACKET3_DRAW_INDIRECT:
2832 case PACKET3_DRAW_INDEX_INDIRECT:
2833 case PACKET3_INDEX_BASE:
2834 case PACKET3_DRAW_INDEX_2:
2835 case PACKET3_CONTEXT_CONTROL:
2836 case PACKET3_INDEX_TYPE:
2837 case PACKET3_DRAW_INDIRECT_MULTI:
2838 case PACKET3_DRAW_INDEX_AUTO:
2839 case PACKET3_DRAW_INDEX_IMMD:
2840 case PACKET3_NUM_INSTANCES:
2841 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2842 case PACKET3_STRMOUT_BUFFER_UPDATE:
2843 case PACKET3_DRAW_INDEX_OFFSET_2:
2844 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2845 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2846 case PACKET3_MPEG_INDEX:
2847 case PACKET3_WAIT_REG_MEM:
2848 case PACKET3_MEM_WRITE:
2849 case PACKET3_PFP_SYNC_ME:
2850 case PACKET3_SURFACE_SYNC:
2851 case PACKET3_EVENT_WRITE:
2852 case PACKET3_EVENT_WRITE_EOP:
2853 case PACKET3_EVENT_WRITE_EOS:
2854 case PACKET3_SET_CONTEXT_REG:
2855 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2856 case PACKET3_SET_SH_REG:
2857 case PACKET3_SET_SH_REG_OFFSET:
2858 case PACKET3_INCREMENT_DE_COUNTER:
2859 case PACKET3_WAIT_ON_CE_COUNTER:
2860 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2861 case PACKET3_ME_WRITE:
2862 break;
2863 case PACKET3_COPY_DATA:
2864 if ((idx_value & 0xf00) == 0) {
2865 reg = ib[idx + 3] * 4;
2866 if (!si_vm_reg_valid(reg))
2867 return -EINVAL;
2868 }
2869 break;
2870 case PACKET3_WRITE_DATA:
2871 if ((idx_value & 0xf00) == 0) {
2872 start_reg = ib[idx + 1] * 4;
2873 if (idx_value & 0x10000) {
2874 if (!si_vm_reg_valid(start_reg))
2875 return -EINVAL;
2876 } else {
2877 for (i = 0; i < (pkt->count - 2); i++) {
2878 reg = start_reg + (4 * i);
2879 if (!si_vm_reg_valid(reg))
2880 return -EINVAL;
2881 }
2882 }
2883 }
2884 break;
2885 case PACKET3_COND_WRITE:
2886 if (idx_value & 0x100) {
2887 reg = ib[idx + 5] * 4;
2888 if (!si_vm_reg_valid(reg))
2889 return -EINVAL;
2890 }
2891 break;
2892 case PACKET3_COPY_DW:
2893 if (idx_value & 0x2) {
2894 reg = ib[idx + 3] * 4;
2895 if (!si_vm_reg_valid(reg))
2896 return -EINVAL;
2897 }
2898 break;
2899 case PACKET3_SET_CONFIG_REG:
2900 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2901 end_reg = 4 * pkt->count + start_reg - 4;
2902 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2903 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2904 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2905 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2906 return -EINVAL;
2907 }
2908 for (i = 0; i < pkt->count; i++) {
2909 reg = start_reg + (4 * i);
2910 if (!si_vm_reg_valid(reg))
2911 return -EINVAL;
2912 }
2913 break;
5aa709be
AD		 2914 case PACKET3_CP_DMA:
2915 command = ib[idx + 4];
2916 info = ib[idx + 1];
2917 if (command & PACKET3_CP_DMA_CMD_SAS) {
2918 /* src address space is register */
2919 if (((info & 0x60000000) >> 29) == 0) {
2920 start_reg = idx_value << 2;
2921 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2922 reg = start_reg;
2923 if (!si_vm_reg_valid(reg)) {
2924 DRM_ERROR("CP DMA Bad SRC register\n");
2925 return -EINVAL;
2926 }
2927 } else {
2928 for (i = 0; i < (command & 0x1fffff); i++) {
2929 reg = start_reg + (4 * i);
2930 if (!si_vm_reg_valid(reg)) {
2931 DRM_ERROR("CP DMA Bad SRC register\n");
2932 return -EINVAL;
2933 }
2934 }
2935 }
2936 }
2937 }
2938 if (command & PACKET3_CP_DMA_CMD_DAS) {
2939 /* dst address space is register */
2940 if (((info & 0x00300000) >> 20) == 0) {
2941 start_reg = ib[idx + 2];
2942 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2943 reg = start_reg;
2944 if (!si_vm_reg_valid(reg)) {
2945 DRM_ERROR("CP DMA Bad DST register\n");
2946 return -EINVAL;
2947 }
2948 } else {
2949 for (i = 0; i < (command & 0x1fffff); i++) {
2950 reg = start_reg + (4 * i);
2951 if (!si_vm_reg_valid(reg)) {
2952 DRM_ERROR("CP DMA Bad DST register\n");
2953 return -EINVAL;
2954 }
2955 }
2956 }
2957 }
2958 }
2959 break;
498dd8b3
AD		 2960 default:
2961 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2962 return -EINVAL;
2963 }
2964 return 0;
2965}
2966
2967static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2968 u32 *ib, struct radeon_cs_packet *pkt)
2969{
2970 u32 idx = pkt->idx + 1;
2971 u32 idx_value = ib[idx];
2972 u32 start_reg, reg, i;
2973
2974 switch (pkt->opcode) {
2975 case PACKET3_NOP:
2976 case PACKET3_SET_BASE:
2977 case PACKET3_CLEAR_STATE:
2978 case PACKET3_DISPATCH_DIRECT:
2979 case PACKET3_DISPATCH_INDIRECT:
2980 case PACKET3_ALLOC_GDS:
2981 case PACKET3_WRITE_GDS_RAM:
2982 case PACKET3_ATOMIC_GDS:
2983 case PACKET3_ATOMIC:
2984 case PACKET3_OCCLUSION_QUERY:
2985 case PACKET3_SET_PREDICATION:
2986 case PACKET3_COND_EXEC:
2987 case PACKET3_PRED_EXEC:
2988 case PACKET3_CONTEXT_CONTROL:
2989 case PACKET3_STRMOUT_BUFFER_UPDATE:
2990 case PACKET3_WAIT_REG_MEM:
2991 case PACKET3_MEM_WRITE:
2992 case PACKET3_PFP_SYNC_ME:
2993 case PACKET3_SURFACE_SYNC:
2994 case PACKET3_EVENT_WRITE:
2995 case PACKET3_EVENT_WRITE_EOP:
2996 case PACKET3_EVENT_WRITE_EOS:
2997 case PACKET3_SET_CONTEXT_REG:
2998 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2999 case PACKET3_SET_SH_REG:
3000 case PACKET3_SET_SH_REG_OFFSET:
3001 case PACKET3_INCREMENT_DE_COUNTER:
3002 case PACKET3_WAIT_ON_CE_COUNTER:
3003 case PACKET3_WAIT_ON_AVAIL_BUFFER:
3004 case PACKET3_ME_WRITE:
3005 break;
3006 case PACKET3_COPY_DATA:
3007 if ((idx_value & 0xf00) == 0) {
3008 reg = ib[idx + 3] * 4;
3009 if (!si_vm_reg_valid(reg))
3010 return -EINVAL;
3011 }
3012 break;
3013 case PACKET3_WRITE_DATA:
3014 if ((idx_value & 0xf00) == 0) {
3015 start_reg = ib[idx + 1] * 4;
3016 if (idx_value & 0x10000) {
3017 if (!si_vm_reg_valid(start_reg))
3018 return -EINVAL;
3019 } else {
3020 for (i = 0; i < (pkt->count - 2); i++) {
3021 reg = start_reg + (4 * i);
3022 if (!si_vm_reg_valid(reg))
3023 return -EINVAL;
3024 }
3025 }
3026 }
3027 break;
3028 case PACKET3_COND_WRITE:
3029 if (idx_value & 0x100) {
3030 reg = ib[idx + 5] * 4;
3031 if (!si_vm_reg_valid(reg))
3032 return -EINVAL;
3033 }
3034 break;
3035 case PACKET3_COPY_DW:
3036 if (idx_value & 0x2) {
3037 reg = ib[idx + 3] * 4;
3038 if (!si_vm_reg_valid(reg))
3039 return -EINVAL;
3040 }
3041 break;
3042 default:
3043 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
3044 return -EINVAL;
3045 }
3046 return 0;
3047}
3048
3049int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3050{
3051 int ret = 0;
3052 u32 idx = 0;
3053 struct radeon_cs_packet pkt;
3054
3055 do {
3056 pkt.idx = idx;
4e872ae2
IH		 3057 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
3058 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
498dd8b3
AD		 3059 pkt.one_reg_wr = 0;
3060 switch (pkt.type) {
4e872ae2 3061 case RADEON_PACKET_TYPE0:
498dd8b3
AD		 3062 dev_err(rdev->dev, "Packet0 not allowed!\n");
3063 ret = -EINVAL;
3064 break;
4e872ae2 3065 case RADEON_PACKET_TYPE2:
498dd8b3
AD		 3066 idx += 1;
3067 break;
4e872ae2
IH		 3068 case RADEON_PACKET_TYPE3:
3069 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
498dd8b3
AD		 3070 if (ib->is_const_ib)
3071 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
3072 else {
876dc9f3 3073 switch (ib->ring) {
498dd8b3
AD		 3074 case RADEON_RING_TYPE_GFX_INDEX:
3075 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
3076 break;
3077 case CAYMAN_RING_TYPE_CP1_INDEX:
3078 case CAYMAN_RING_TYPE_CP2_INDEX:
3079 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
3080 break;
3081 default:
876dc9f3 3082 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
498dd8b3
AD		 3083 ret = -EINVAL;
3084 break;
3085 }
3086 }
3087 idx += pkt.count + 2;
3088 break;
3089 default:
3090 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3091 ret = -EINVAL;
3092 break;
3093 }
3094 if (ret)
3095 break;
3096 } while (idx < ib->length_dw);
3097
3098 return ret;
3099}
3100
d2800ee5
AD		 3101/*
3102 * vm
3103 */
3104int si_vm_init(struct radeon_device *rdev)
3105{
3106 /* number of VMs */
3107 rdev->vm_manager.nvm = 16;
3108 /* base offset of vram pages */
3109 rdev->vm_manager.vram_base_offset = 0;
3110
3111 return 0;
3112}
3113
3114void si_vm_fini(struct radeon_device *rdev)
3115{
3116}
3117
82ffd92b
AD		 3118/**
3119 * si_vm_set_page - update the page tables using the CP
3120 *
3121 * @rdev: radeon_device pointer
43f1214a 3122 * @ib: indirect buffer to fill with commands
82ffd92b
AD		 3123 * @pe: addr of the page entry
3124 * @addr: dst addr to write into pe
3125 * @count: number of page entries to update
3126 * @incr: increase next addr by incr bytes
3127 * @flags: access flags
3128 *
43f1214a 3129 * Update the page tables using the CP (SI).
82ffd92b 3130 */
43f1214a
AD		 3131void si_vm_set_page(struct radeon_device *rdev,
3132 struct radeon_ib *ib,
3133 uint64_t pe,
82ffd92b
AD		 3134 uint64_t addr, unsigned count,
3135 uint32_t incr, uint32_t flags)
d2800ee5 3136{
82ffd92b 3137 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
deab48f1
AD		 3138 uint64_t value;
3139 unsigned ndw;
3140
3141 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
3142 while (count) {
3143 ndw = 2 + count * 2;
3144 if (ndw > 0x3FFE)
3145 ndw = 0x3FFE;
3146
43f1214a
AD		 3147 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
3148 ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
3149 WRITE_DATA_DST_SEL(1));
3150 ib->ptr[ib->length_dw++] = pe;
3151 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
deab48f1
AD		 3152 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3153 if (flags & RADEON_VM_PAGE_SYSTEM) {
3154 value = radeon_vm_map_gart(rdev, addr);
3155 value &= 0xFFFFFFFFFFFFF000ULL;
3156 } else if (flags & RADEON_VM_PAGE_VALID) {
3157 value = addr;
3158 } else {
3159 value = 0;
3160 }
3161 addr += incr;
3162 value |= r600_flags;
43f1214a
AD		 3163 ib->ptr[ib->length_dw++] = value;
3164 ib->ptr[ib->length_dw++] = upper_32_bits(value);
deab48f1
AD		 3165 }
3166 }
3167 } else {
3168 /* DMA */
3169 if (flags & RADEON_VM_PAGE_SYSTEM) {
3170 while (count) {
3171 ndw = count * 2;
3172 if (ndw > 0xFFFFE)
3173 ndw = 0xFFFFE;
3174
3175 /* for non-physically contiguous pages (system) */
43f1214a
AD		 3176 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
3177 ib->ptr[ib->length_dw++] = pe;
3178 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
deab48f1
AD		 3179 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3180 if (flags & RADEON_VM_PAGE_SYSTEM) {
3181 value = radeon_vm_map_gart(rdev, addr);
3182 value &= 0xFFFFFFFFFFFFF000ULL;
3183 } else if (flags & RADEON_VM_PAGE_VALID) {
3184 value = addr;
3185 } else {
3186 value = 0;
3187 }
3188 addr += incr;
3189 value |= r600_flags;
43f1214a
AD		 3190 ib->ptr[ib->length_dw++] = value;
3191 ib->ptr[ib->length_dw++] = upper_32_bits(value);
deab48f1
AD		 3192 }
3193 }
3194 } else {
3195 while (count) {
3196 ndw = count * 2;
3197 if (ndw > 0xFFFFE)
3198 ndw = 0xFFFFE;
3199
3200 if (flags & RADEON_VM_PAGE_VALID)
3201 value = addr;
3202 else
3203 value = 0;
3204 /* for physically contiguous pages (vram) */
43f1214a
AD		 3205 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
3206 ib->ptr[ib->length_dw++] = pe; /* dst addr */
3207 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3208 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
3209 ib->ptr[ib->length_dw++] = 0;
3210 ib->ptr[ib->length_dw++] = value; /* value */
3211 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3212 ib->ptr[ib->length_dw++] = incr; /* increment size */
3213 ib->ptr[ib->length_dw++] = 0;
deab48f1
AD		 3214 pe += ndw * 4;
3215 addr += (ndw / 2) * incr;
3216 count -= ndw / 2;
3217 }
d7025d89 3218 }
43f1214a
AD		 3219 while (ib->length_dw & 0x7)
3220 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);
82ffd92b 3221 }
d2800ee5
AD		 3222}
3223
498522b4 3224void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
d2800ee5 3225{
498522b4 3226 struct radeon_ring *ring = &rdev->ring[ridx];
d2800ee5 3227
ee60e29f 3228 if (vm == NULL)
d2800ee5
AD		 3229 return;
3230
76c44f2c
AD		 3231 /* write new base address */
3232 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3233 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3234 WRITE_DATA_DST_SEL(0)));
3235
ee60e29f 3236 if (vm->id < 8) {
76c44f2c
AD		 3237 radeon_ring_write(ring,
3238 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
ee60e29f 3239 } else {
76c44f2c
AD		 3240 radeon_ring_write(ring,
3241 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
ee60e29f 3242 }
76c44f2c 3243 radeon_ring_write(ring, 0);
fa87e62d 3244 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 3245
d2800ee5 3246 /* flush hdp cache */
76c44f2c
AD		 3247 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3248 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3249 WRITE_DATA_DST_SEL(0)));
3250 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3251 radeon_ring_write(ring, 0);
ee60e29f
CK		 3252 radeon_ring_write(ring, 0x1);
3253
d2800ee5 3254 /* bits 0-15 are the VM contexts0-15 */
76c44f2c
AD		 3255 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3256 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3257 WRITE_DATA_DST_SEL(0)));
3258 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3259 radeon_ring_write(ring, 0);
498522b4 3260 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 3261
3262 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3263 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3264 radeon_ring_write(ring, 0x0);
d2800ee5
AD		 3265}
3266
8c5fd7ef
AD		 3267void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3268{
3269 struct radeon_ring *ring = &rdev->ring[ridx];
3270
3271 if (vm == NULL)
3272 return;
3273
3274 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3275 if (vm->id < 8) {
3276 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3277 } else {
3278 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3279 }
3280 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3281
3282 /* flush hdp cache */
3283 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3284 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3285 radeon_ring_write(ring, 1);
3286
3287 /* bits 0-7 are the VM contexts0-7 */
3288 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3289 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3290 radeon_ring_write(ring, 1 << vm->id);
3291}
3292
347e7592
AD		 3293/*
3294 * RLC
3295 */
c420c745 3296void si_rlc_fini(struct radeon_device *rdev)
347e7592
AD		 3297{
3298 int r;
3299
3300 /* save restore block */
3301 if (rdev->rlc.save_restore_obj) {
3302 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3303 if (unlikely(r != 0))
3304 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3305 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3306 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3307
3308 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3309 rdev->rlc.save_restore_obj = NULL;
3310 }
3311
3312 /* clear state block */
3313 if (rdev->rlc.clear_state_obj) {
3314 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3315 if (unlikely(r != 0))
3316 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3317 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3318 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3319
3320 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3321 rdev->rlc.clear_state_obj = NULL;
3322 }
3323}
3324
c420c745 3325int si_rlc_init(struct radeon_device *rdev)
347e7592
AD		 3326{
3327 int r;
3328
3329 /* save restore block */
3330 if (rdev->rlc.save_restore_obj == NULL) {
3331 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3332 RADEON_GEM_DOMAIN_VRAM, NULL,
3333 &rdev->rlc.save_restore_obj);
347e7592
AD		 3334 if (r) {
3335 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3336 return r;
3337 }
3338 }
3339
3340 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3341 if (unlikely(r != 0)) {
3342 si_rlc_fini(rdev);
3343 return r;
3344 }
3345 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3346 &rdev->rlc.save_restore_gpu_addr);
5273db70 3347 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
347e7592 3348 if (r) {
347e7592
AD		 3349 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3350 si_rlc_fini(rdev);
3351 return r;
3352 }
3353
3354 /* clear state block */
3355 if (rdev->rlc.clear_state_obj == NULL) {
3356 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3357 RADEON_GEM_DOMAIN_VRAM, NULL,
3358 &rdev->rlc.clear_state_obj);
347e7592
AD		 3359 if (r) {
3360 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3361 si_rlc_fini(rdev);
3362 return r;
3363 }
3364 }
3365 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3366 if (unlikely(r != 0)) {
3367 si_rlc_fini(rdev);
3368 return r;
3369 }
3370 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3371 &rdev->rlc.clear_state_gpu_addr);
5273db70 3372 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
347e7592 3373 if (r) {
347e7592
AD		 3374 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3375 si_rlc_fini(rdev);
3376 return r;
3377 }
3378
3379 return 0;
3380}
3381
3382static void si_rlc_stop(struct radeon_device *rdev)
3383{
3384 WREG32(RLC_CNTL, 0);
3385}
3386
3387static void si_rlc_start(struct radeon_device *rdev)
3388{
3389 WREG32(RLC_CNTL, RLC_ENABLE);
3390}
3391
3392static int si_rlc_resume(struct radeon_device *rdev)
3393{
3394 u32 i;
3395 const __be32 *fw_data;
3396
3397 if (!rdev->rlc_fw)
3398 return -EINVAL;
3399
3400 si_rlc_stop(rdev);
3401
3402 WREG32(RLC_RL_BASE, 0);
3403 WREG32(RLC_RL_SIZE, 0);
3404 WREG32(RLC_LB_CNTL, 0);
3405 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3406 WREG32(RLC_LB_CNTR_INIT, 0);
3407
3408 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3409 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3410
3411 WREG32(RLC_MC_CNTL, 0);
3412 WREG32(RLC_UCODE_CNTL, 0);
3413
3414 fw_data = (const __be32 *)rdev->rlc_fw->data;
3415 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3416 WREG32(RLC_UCODE_ADDR, i);
3417 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3418 }
3419 WREG32(RLC_UCODE_ADDR, 0);
3420
3421 si_rlc_start(rdev);
3422
3423 return 0;
3424}
3425
25a857fb
AD		 3426static void si_enable_interrupts(struct radeon_device *rdev)
3427{
3428 u32 ih_cntl = RREG32(IH_CNTL);
3429 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3430
3431 ih_cntl |= ENABLE_INTR;
3432 ih_rb_cntl |= IH_RB_ENABLE;
3433 WREG32(IH_CNTL, ih_cntl);
3434 WREG32(IH_RB_CNTL, ih_rb_cntl);
3435 rdev->ih.enabled = true;
3436}
3437
3438static void si_disable_interrupts(struct radeon_device *rdev)
3439{
3440 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3441 u32 ih_cntl = RREG32(IH_CNTL);
3442
3443 ih_rb_cntl &= ~IH_RB_ENABLE;
3444 ih_cntl &= ~ENABLE_INTR;
3445 WREG32(IH_RB_CNTL, ih_rb_cntl);
3446 WREG32(IH_CNTL, ih_cntl);
3447 /* set rptr, wptr to 0 */
3448 WREG32(IH_RB_RPTR, 0);
3449 WREG32(IH_RB_WPTR, 0);
3450 rdev->ih.enabled = false;
25a857fb
AD		 3451 rdev->ih.rptr = 0;
3452}
3453
3454static void si_disable_interrupt_state(struct radeon_device *rdev)
3455{
3456 u32 tmp;
3457
3458 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3459 WREG32(CP_INT_CNTL_RING1, 0);
3460 WREG32(CP_INT_CNTL_RING2, 0);
8c5fd7ef
AD		 3461 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3462 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3463 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3464 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
25a857fb
AD		 3465 WREG32(GRBM_INT_CNTL, 0);
3466 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3467 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3468 if (rdev->num_crtc >= 4) {
3469 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3470 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3471 }
3472 if (rdev->num_crtc >= 6) {
3473 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3474 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3475 }
3476
3477 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3478 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3479 if (rdev->num_crtc >= 4) {
3480 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3481 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3482 }
3483 if (rdev->num_crtc >= 6) {
3484 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3485 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3486 }
3487
3488 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3489
3490 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3491 WREG32(DC_HPD1_INT_CONTROL, tmp);
3492 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3493 WREG32(DC_HPD2_INT_CONTROL, tmp);
3494 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3495 WREG32(DC_HPD3_INT_CONTROL, tmp);
3496 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3497 WREG32(DC_HPD4_INT_CONTROL, tmp);
3498 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3499 WREG32(DC_HPD5_INT_CONTROL, tmp);
3500 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3501 WREG32(DC_HPD6_INT_CONTROL, tmp);
3502
3503}
3504
3505static int si_irq_init(struct radeon_device *rdev)
3506{
3507 int ret = 0;
3508 int rb_bufsz;
3509 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3510
3511 /* allocate ring */
3512 ret = r600_ih_ring_alloc(rdev);
3513 if (ret)
3514 return ret;
3515
3516 /* disable irqs */
3517 si_disable_interrupts(rdev);
3518
3519 /* init rlc */
3520 ret = si_rlc_resume(rdev);
3521 if (ret) {
3522 r600_ih_ring_fini(rdev);
3523 return ret;
3524 }
3525
3526 /* setup interrupt control */
3527 /* set dummy read address to ring address */
3528 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3529 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3530 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3531 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3532 */
3533 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3534 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3535 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3536 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3537
3538 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3539 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3540
3541 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3542 IH_WPTR_OVERFLOW_CLEAR |
3543 (rb_bufsz << 1));
3544
3545 if (rdev->wb.enabled)
3546 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3547
3548 /* set the writeback address whether it's enabled or not */
3549 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3550 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3551
3552 WREG32(IH_RB_CNTL, ih_rb_cntl);
3553
3554 /* set rptr, wptr to 0 */
3555 WREG32(IH_RB_RPTR, 0);
3556 WREG32(IH_RB_WPTR, 0);
3557
3558 /* Default settings for IH_CNTL (disabled at first) */
3559 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3560 /* RPTR_REARM only works if msi's are enabled */
3561 if (rdev->msi_enabled)
3562 ih_cntl |= RPTR_REARM;
3563 WREG32(IH_CNTL, ih_cntl);
3564
3565 /* force the active interrupt state to all disabled */
3566 si_disable_interrupt_state(rdev);
3567
2099810f
DA		 3568 pci_set_master(rdev->pdev);
3569
25a857fb
AD		 3570 /* enable irqs */
3571 si_enable_interrupts(rdev);
3572
3573 return ret;
3574}
3575
3576int si_irq_set(struct radeon_device *rdev)
3577{
3578 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3579 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3580 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3581 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3582 u32 grbm_int_cntl = 0;
3583 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
8c5fd7ef 3584 u32 dma_cntl, dma_cntl1;
25a857fb
AD		 3585
3586 if (!rdev->irq.installed) {
3587 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3588 return -EINVAL;
3589 }
3590 /* don't enable anything if the ih is disabled */
3591 if (!rdev->ih.enabled) {
3592 si_disable_interrupts(rdev);
3593 /* force the active interrupt state to all disabled */
3594 si_disable_interrupt_state(rdev);
3595 return 0;
3596 }
3597
3598 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3599 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3600 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3601 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3602 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3603 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3604
8c5fd7ef
AD		 3605 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3606 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3607
25a857fb 3608 /* enable CP interrupts on all rings */
736fc37f 3609 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
25a857fb
AD		 3610 DRM_DEBUG("si_irq_set: sw int gfx\n");
3611 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3612 }
736fc37f 3613 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
25a857fb
AD		 3614 DRM_DEBUG("si_irq_set: sw int cp1\n");
3615 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3616 }
736fc37f 3617 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
25a857fb
AD		 3618 DRM_DEBUG("si_irq_set: sw int cp2\n");
3619 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3620 }
8c5fd7ef
AD		 3621 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3622 DRM_DEBUG("si_irq_set: sw int dma\n");
3623 dma_cntl |= TRAP_ENABLE;
3624 }
3625
3626 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3627 DRM_DEBUG("si_irq_set: sw int dma1\n");
3628 dma_cntl1 |= TRAP_ENABLE;
3629 }
25a857fb 3630 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3631 atomic_read(&rdev->irq.pflip[0])) {
25a857fb
AD		 3632 DRM_DEBUG("si_irq_set: vblank 0\n");
3633 crtc1 |= VBLANK_INT_MASK;
3634 }
3635 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3636 atomic_read(&rdev->irq.pflip[1])) {
25a857fb
AD		 3637 DRM_DEBUG("si_irq_set: vblank 1\n");
3638 crtc2 |= VBLANK_INT_MASK;
3639 }
3640 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3641 atomic_read(&rdev->irq.pflip[2])) {
25a857fb
AD		 3642 DRM_DEBUG("si_irq_set: vblank 2\n");
3643 crtc3 |= VBLANK_INT_MASK;
3644 }
3645 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3646 atomic_read(&rdev->irq.pflip[3])) {
25a857fb
AD		 3647 DRM_DEBUG("si_irq_set: vblank 3\n");
3648 crtc4 |= VBLANK_INT_MASK;
3649 }
3650 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3651 atomic_read(&rdev->irq.pflip[4])) {
25a857fb
AD		 3652 DRM_DEBUG("si_irq_set: vblank 4\n");
3653 crtc5 |= VBLANK_INT_MASK;
3654 }
3655 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3656 atomic_read(&rdev->irq.pflip[5])) {
25a857fb
AD		 3657 DRM_DEBUG("si_irq_set: vblank 5\n");
3658 crtc6 |= VBLANK_INT_MASK;
3659 }
3660 if (rdev->irq.hpd[0]) {
3661 DRM_DEBUG("si_irq_set: hpd 1\n");
3662 hpd1 |= DC_HPDx_INT_EN;
3663 }
3664 if (rdev->irq.hpd[1]) {
3665 DRM_DEBUG("si_irq_set: hpd 2\n");
3666 hpd2 |= DC_HPDx_INT_EN;
3667 }
3668 if (rdev->irq.hpd[2]) {
3669 DRM_DEBUG("si_irq_set: hpd 3\n");
3670 hpd3 |= DC_HPDx_INT_EN;
3671 }
3672 if (rdev->irq.hpd[3]) {
3673 DRM_DEBUG("si_irq_set: hpd 4\n");
3674 hpd4 |= DC_HPDx_INT_EN;
3675 }
3676 if (rdev->irq.hpd[4]) {
3677 DRM_DEBUG("si_irq_set: hpd 5\n");
3678 hpd5 |= DC_HPDx_INT_EN;
3679 }
3680 if (rdev->irq.hpd[5]) {
3681 DRM_DEBUG("si_irq_set: hpd 6\n");
3682 hpd6 |= DC_HPDx_INT_EN;
3683 }
25a857fb
AD		 3684
3685 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3686 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3687 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3688
8c5fd7ef
AD		 3689 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3690 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3691
25a857fb
AD		 3692 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3693
3694 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3695 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3696 if (rdev->num_crtc >= 4) {
3697 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3698 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3699 }
3700 if (rdev->num_crtc >= 6) {
3701 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3702 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3703 }
3704
3705 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3706 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3707 if (rdev->num_crtc >= 4) {
3708 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3709 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3710 }
3711 if (rdev->num_crtc >= 6) {
3712 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3713 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3714 }
3715
3716 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3717 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3718 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3719 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3720 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3721 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3722
3723 return 0;
3724}
3725
3726static inline void si_irq_ack(struct radeon_device *rdev)
3727{
3728 u32 tmp;
3729
3730 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3731 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3732 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3733 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3734 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3735 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3736 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3737 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3738 if (rdev->num_crtc >= 4) {
3739 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3740 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3741 }
3742 if (rdev->num_crtc >= 6) {
3743 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3744 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3745 }
3746
3747 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3748 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3749 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3750 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3751 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3752 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3753 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3754 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3755 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3756 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3757 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3758 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3759
3760 if (rdev->num_crtc >= 4) {
3761 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3762 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3763 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3764 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3765 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3766 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3767 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3768 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3769 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3770 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3771 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3772 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3773 }
3774
3775 if (rdev->num_crtc >= 6) {
3776 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3777 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3778 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3779 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3780 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3781 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3782 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3783 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3784 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3785 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3786 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3787 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3788 }
3789
3790 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3791 tmp = RREG32(DC_HPD1_INT_CONTROL);
3792 tmp |= DC_HPDx_INT_ACK;
3793 WREG32(DC_HPD1_INT_CONTROL, tmp);
3794 }
3795 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3796 tmp = RREG32(DC_HPD2_INT_CONTROL);
3797 tmp |= DC_HPDx_INT_ACK;
3798 WREG32(DC_HPD2_INT_CONTROL, tmp);
3799 }
3800 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3801 tmp = RREG32(DC_HPD3_INT_CONTROL);
3802 tmp |= DC_HPDx_INT_ACK;
3803 WREG32(DC_HPD3_INT_CONTROL, tmp);
3804 }
3805 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3806 tmp = RREG32(DC_HPD4_INT_CONTROL);
3807 tmp |= DC_HPDx_INT_ACK;
3808 WREG32(DC_HPD4_INT_CONTROL, tmp);
3809 }
3810 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3811 tmp = RREG32(DC_HPD5_INT_CONTROL);
3812 tmp |= DC_HPDx_INT_ACK;
3813 WREG32(DC_HPD5_INT_CONTROL, tmp);
3814 }
3815 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3816 tmp = RREG32(DC_HPD5_INT_CONTROL);
3817 tmp |= DC_HPDx_INT_ACK;
3818 WREG32(DC_HPD6_INT_CONTROL, tmp);
3819 }
3820}
3821
3822static void si_irq_disable(struct radeon_device *rdev)
3823{
3824 si_disable_interrupts(rdev);
3825 /* Wait and acknowledge irq */
3826 mdelay(1);
3827 si_irq_ack(rdev);
3828 si_disable_interrupt_state(rdev);
3829}
3830
3831static void si_irq_suspend(struct radeon_device *rdev)
3832{
3833 si_irq_disable(rdev);
3834 si_rlc_stop(rdev);
3835}
3836
9b136d51
AD		 3837static void si_irq_fini(struct radeon_device *rdev)
3838{
3839 si_irq_suspend(rdev);
3840 r600_ih_ring_fini(rdev);
3841}
3842
25a857fb
AD		 3843static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3844{
3845 u32 wptr, tmp;
3846
3847 if (rdev->wb.enabled)
3848 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3849 else
3850 wptr = RREG32(IH_RB_WPTR);
3851
3852 if (wptr & RB_OVERFLOW) {
3853 /* When a ring buffer overflow happen start parsing interrupt
3854 * from the last not overwritten vector (wptr + 16). Hopefully
3855 * this should allow us to catchup.
3856 */
3857 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3858 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3859 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3860 tmp = RREG32(IH_RB_CNTL);
3861 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3862 WREG32(IH_RB_CNTL, tmp);
3863 }
3864 return (wptr & rdev->ih.ptr_mask);
3865}
3866
3867/* SI IV Ring
3868 * Each IV ring entry is 128 bits:
3869 * [7:0] - interrupt source id
3870 * [31:8] - reserved
3871 * [59:32] - interrupt source data
3872 * [63:60] - reserved
3873 * [71:64] - RINGID
3874 * [79:72] - VMID
3875 * [127:80] - reserved
3876 */
3877int si_irq_process(struct radeon_device *rdev)
3878{
3879 u32 wptr;
3880 u32 rptr;
3881 u32 src_id, src_data, ring_id;
3882 u32 ring_index;
25a857fb
AD		 3883 bool queue_hotplug = false;
3884
3885 if (!rdev->ih.enabled || rdev->shutdown)
3886 return IRQ_NONE;
3887
3888 wptr = si_get_ih_wptr(rdev);
c20dc369
CK		 3889
3890restart_ih:
3891 /* is somebody else already processing irqs? */
3892 if (atomic_xchg(&rdev->ih.lock, 1))
3893 return IRQ_NONE;
3894
25a857fb
AD		 3895 rptr = rdev->ih.rptr;
3896 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3897
25a857fb
AD		 3898 /* Order reading of wptr vs. reading of IH ring data */
3899 rmb();
3900
3901 /* display interrupts */
3902 si_irq_ack(rdev);
3903
25a857fb
AD		 3904 while (rptr != wptr) {
3905 /* wptr/rptr are in bytes! */
3906 ring_index = rptr / 4;
3907 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3908 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3909 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3910
3911 switch (src_id) {
3912 case 1: /* D1 vblank/vline */
3913 switch (src_data) {
3914 case 0: /* D1 vblank */
3915 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3916 if (rdev->irq.crtc_vblank_int[0]) {
3917 drm_handle_vblank(rdev->ddev, 0);
3918 rdev->pm.vblank_sync = true;
3919 wake_up(&rdev->irq.vblank_queue);
3920 }
736fc37f 3921 if (atomic_read(&rdev->irq.pflip[0]))
25a857fb
AD		 3922 radeon_crtc_handle_flip(rdev, 0);
3923 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3924 DRM_DEBUG("IH: D1 vblank\n");
3925 }
3926 break;
3927 case 1: /* D1 vline */
3928 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3929 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3930 DRM_DEBUG("IH: D1 vline\n");
3931 }
3932 break;
3933 default:
3934 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3935 break;
3936 }
3937 break;
3938 case 2: /* D2 vblank/vline */
3939 switch (src_data) {
3940 case 0: /* D2 vblank */
3941 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3942 if (rdev->irq.crtc_vblank_int[1]) {
3943 drm_handle_vblank(rdev->ddev, 1);
3944 rdev->pm.vblank_sync = true;
3945 wake_up(&rdev->irq.vblank_queue);
3946 }
736fc37f 3947 if (atomic_read(&rdev->irq.pflip[1]))
25a857fb
AD		 3948 radeon_crtc_handle_flip(rdev, 1);
3949 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3950 DRM_DEBUG("IH: D2 vblank\n");
3951 }
3952 break;
3953 case 1: /* D2 vline */
3954 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3955 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3956 DRM_DEBUG("IH: D2 vline\n");
3957 }
3958 break;
3959 default:
3960 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3961 break;
3962 }
3963 break;
3964 case 3: /* D3 vblank/vline */
3965 switch (src_data) {
3966 case 0: /* D3 vblank */
3967 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3968 if (rdev->irq.crtc_vblank_int[2]) {
3969 drm_handle_vblank(rdev->ddev, 2);
3970 rdev->pm.vblank_sync = true;
3971 wake_up(&rdev->irq.vblank_queue);
3972 }
736fc37f 3973 if (atomic_read(&rdev->irq.pflip[2]))
25a857fb
AD		 3974 radeon_crtc_handle_flip(rdev, 2);
3975 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3976 DRM_DEBUG("IH: D3 vblank\n");
3977 }
3978 break;
3979 case 1: /* D3 vline */
3980 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3981 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3982 DRM_DEBUG("IH: D3 vline\n");
3983 }
3984 break;
3985 default:
3986 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3987 break;
3988 }
3989 break;
3990 case 4: /* D4 vblank/vline */
3991 switch (src_data) {
3992 case 0: /* D4 vblank */
3993 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3994 if (rdev->irq.crtc_vblank_int[3]) {
3995 drm_handle_vblank(rdev->ddev, 3);
3996 rdev->pm.vblank_sync = true;
3997 wake_up(&rdev->irq.vblank_queue);
3998 }
736fc37f 3999 if (atomic_read(&rdev->irq.pflip[3]))
25a857fb
AD		 4000 radeon_crtc_handle_flip(rdev, 3);
4001 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
4002 DRM_DEBUG("IH: D4 vblank\n");
4003 }
4004 break;
4005 case 1: /* D4 vline */
4006 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
4007 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
4008 DRM_DEBUG("IH: D4 vline\n");
4009 }
4010 break;
4011 default:
4012 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4013 break;
4014 }
4015 break;
4016 case 5: /* D5 vblank/vline */
4017 switch (src_data) {
4018 case 0: /* D5 vblank */
4019 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
4020 if (rdev->irq.crtc_vblank_int[4]) {
4021 drm_handle_vblank(rdev->ddev, 4);
4022 rdev->pm.vblank_sync = true;
4023 wake_up(&rdev->irq.vblank_queue);
4024 }
736fc37f 4025 if (atomic_read(&rdev->irq.pflip[4]))
25a857fb
AD		 4026 radeon_crtc_handle_flip(rdev, 4);
4027 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
4028 DRM_DEBUG("IH: D5 vblank\n");
4029 }
4030 break;
4031 case 1: /* D5 vline */
4032 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
4033 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
4034 DRM_DEBUG("IH: D5 vline\n");
4035 }
4036 break;
4037 default:
4038 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4039 break;
4040 }
4041 break;
4042 case 6: /* D6 vblank/vline */
4043 switch (src_data) {
4044 case 0: /* D6 vblank */
4045 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
4046 if (rdev->irq.crtc_vblank_int[5]) {
4047 drm_handle_vblank(rdev->ddev, 5);
4048 rdev->pm.vblank_sync = true;
4049 wake_up(&rdev->irq.vblank_queue);
4050 }
736fc37f 4051 if (atomic_read(&rdev->irq.pflip[5]))
25a857fb
AD		 4052 radeon_crtc_handle_flip(rdev, 5);
4053 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
4054 DRM_DEBUG("IH: D6 vblank\n");
4055 }
4056 break;
4057 case 1: /* D6 vline */
4058 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
4059 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
4060 DRM_DEBUG("IH: D6 vline\n");
4061 }
4062 break;
4063 default:
4064 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4065 break;
4066 }
4067 break;
4068 case 42: /* HPD hotplug */
4069 switch (src_data) {
4070 case 0:
4071 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
4072 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
4073 queue_hotplug = true;
4074 DRM_DEBUG("IH: HPD1\n");
4075 }
4076 break;
4077 case 1:
4078 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
4079 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
4080 queue_hotplug = true;
4081 DRM_DEBUG("IH: HPD2\n");
4082 }
4083 break;
4084 case 2:
4085 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
4086 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
4087 queue_hotplug = true;
4088 DRM_DEBUG("IH: HPD3\n");
4089 }
4090 break;
4091 case 3:
4092 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
4093 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
4094 queue_hotplug = true;
4095 DRM_DEBUG("IH: HPD4\n");
4096 }
4097 break;
4098 case 4:
4099 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
4100 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
4101 queue_hotplug = true;
4102 DRM_DEBUG("IH: HPD5\n");
4103 }
4104 break;
4105 case 5:
4106 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4107 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
4108 queue_hotplug = true;
4109 DRM_DEBUG("IH: HPD6\n");
4110 }
4111 break;
4112 default:
4113 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4114 break;
4115 }
4116 break;
ae133a11
CK		 4117 case 146:
4118 case 147:
4119 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4120 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4121 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4122 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4123 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4124 /* reset addr and status */
4125 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4126 break;
25a857fb
AD		 4127 case 176: /* RINGID0 CP_INT */
4128 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4129 break;
4130 case 177: /* RINGID1 CP_INT */
4131 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4132 break;
4133 case 178: /* RINGID2 CP_INT */
4134 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4135 break;
4136 case 181: /* CP EOP event */
4137 DRM_DEBUG("IH: CP EOP\n");
4138 switch (ring_id) {
4139 case 0:
4140 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4141 break;
4142 case 1:
4143 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4144 break;
4145 case 2:
4146 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4147 break;
4148 }
4149 break;
8c5fd7ef
AD		 4150 case 224: /* DMA trap event */
4151 DRM_DEBUG("IH: DMA trap\n");
4152 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4153 break;
25a857fb
AD		 4154 case 233: /* GUI IDLE */
4155 DRM_DEBUG("IH: GUI idle\n");
25a857fb 4156 break;
8c5fd7ef
AD		 4157 case 244: /* DMA trap event */
4158 DRM_DEBUG("IH: DMA1 trap\n");
4159 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4160 break;
25a857fb
AD		 4161 default:
4162 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4163 break;
4164 }
4165
4166 /* wptr/rptr are in bytes! */
4167 rptr += 16;
4168 rptr &= rdev->ih.ptr_mask;
4169 }
25a857fb
AD		 4170 if (queue_hotplug)
4171 schedule_work(&rdev->hotplug_work);
4172 rdev->ih.rptr = rptr;
4173 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4174 atomic_set(&rdev->ih.lock, 0);
4175
4176 /* make sure wptr hasn't changed while processing */
4177 wptr = si_get_ih_wptr(rdev);
4178 if (wptr != rptr)
4179 goto restart_ih;
4180
25a857fb
AD		 4181 return IRQ_HANDLED;
4182}
4183
8c5fd7ef
AD		 4184/**
4185 * si_copy_dma - copy pages using the DMA engine
4186 *
4187 * @rdev: radeon_device pointer
4188 * @src_offset: src GPU address
4189 * @dst_offset: dst GPU address
4190 * @num_gpu_pages: number of GPU pages to xfer
4191 * @fence: radeon fence object
4192 *
4193 * Copy GPU paging using the DMA engine (SI).
4194 * Used by the radeon ttm implementation to move pages if
4195 * registered as the asic copy callback.
4196 */
4197int si_copy_dma(struct radeon_device *rdev,
4198 uint64_t src_offset, uint64_t dst_offset,
4199 unsigned num_gpu_pages,
4200 struct radeon_fence **fence)
4201{
4202 struct radeon_semaphore *sem = NULL;
4203 int ring_index = rdev->asic->copy.dma_ring_index;
4204 struct radeon_ring *ring = &rdev->ring[ring_index];
4205 u32 size_in_bytes, cur_size_in_bytes;
4206 int i, num_loops;
4207 int r = 0;
4208
4209 r = radeon_semaphore_create(rdev, &sem);
4210 if (r) {
4211 DRM_ERROR("radeon: moving bo (%d).\n", r);
4212 return r;
4213 }
4214
4215 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4216 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4217 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4218 if (r) {
4219 DRM_ERROR("radeon: moving bo (%d).\n", r);
4220 radeon_semaphore_free(rdev, &sem, NULL);
4221 return r;
4222 }
4223
4224 if (radeon_fence_need_sync(*fence, ring->idx)) {
4225 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4226 ring->idx);
4227 radeon_fence_note_sync(*fence, ring->idx);
4228 } else {
4229 radeon_semaphore_free(rdev, &sem, NULL);
4230 }
4231
4232 for (i = 0; i < num_loops; i++) {
4233 cur_size_in_bytes = size_in_bytes;
4234 if (cur_size_in_bytes > 0xFFFFF)
4235 cur_size_in_bytes = 0xFFFFF;
4236 size_in_bytes -= cur_size_in_bytes;
4237 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4238 radeon_ring_write(ring, dst_offset & 0xffffffff);
4239 radeon_ring_write(ring, src_offset & 0xffffffff);
4240 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4241 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4242 src_offset += cur_size_in_bytes;
4243 dst_offset += cur_size_in_bytes;
4244 }
4245
4246 r = radeon_fence_emit(rdev, fence, ring->idx);
4247 if (r) {
4248 radeon_ring_unlock_undo(rdev, ring);
4249 return r;
4250 }
4251
4252 radeon_ring_unlock_commit(rdev, ring);
4253 radeon_semaphore_free(rdev, &sem, *fence);
4254
4255 return r;
4256}
4257
9b136d51
AD		 4258/*
4259 * startup/shutdown callbacks
4260 */
4261static int si_startup(struct radeon_device *rdev)
4262{
4263 struct radeon_ring *ring;
4264 int r;
4265
4266 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4267 !rdev->rlc_fw || !rdev->mc_fw) {
4268 r = si_init_microcode(rdev);
4269 if (r) {
4270 DRM_ERROR("Failed to load firmware!\n");
4271 return r;
4272 }
4273 }
4274
4275 r = si_mc_load_microcode(rdev);
4276 if (r) {
4277 DRM_ERROR("Failed to load MC firmware!\n");
4278 return r;
4279 }
4280
4281 r = r600_vram_scratch_init(rdev);
4282 if (r)
4283 return r;
4284
4285 si_mc_program(rdev);
4286 r = si_pcie_gart_enable(rdev);
4287 if (r)
4288 return r;
4289 si_gpu_init(rdev);
4290
9b136d51
AD		 4291 /* allocate rlc buffers */
4292 r = si_rlc_init(rdev);
4293 if (r) {
4294 DRM_ERROR("Failed to init rlc BOs!\n");
4295 return r;
4296 }
4297
4298 /* allocate wb buffer */
4299 r = radeon_wb_init(rdev);
4300 if (r)
4301 return r;
4302
4303 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4304 if (r) {
4305 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4306 return r;
4307 }
4308
4309 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4310 if (r) {
4311 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4312 return r;
4313 }
4314
4315 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4316 if (r) {
4317 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4318 return r;
4319 }
4320
8c5fd7ef
AD		 4321 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4322 if (r) {
4323 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4324 return r;
4325 }
4326
4327 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4328 if (r) {
4329 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4330 return r;
4331 }
4332
f2ba57b5
CK		 4333 r = rv770_uvd_resume(rdev);
4334 if (!r) {
4335 r = radeon_fence_driver_start_ring(rdev,
4336 R600_RING_TYPE_UVD_INDEX);
4337 if (r)
4338 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
4339 }
4340 if (r)
4341 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4342
9b136d51
AD		 4343 /* Enable IRQ */
4344 r = si_irq_init(rdev);
4345 if (r) {
4346 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4347 radeon_irq_kms_fini(rdev);
4348 return r;
4349 }
4350 si_irq_set(rdev);
4351
4352 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4353 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4354 CP_RB0_RPTR, CP_RB0_WPTR,
4355 0, 0xfffff, RADEON_CP_PACKET2);
4356 if (r)
4357 return r;
4358
4359 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4360 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4361 CP_RB1_RPTR, CP_RB1_WPTR,
4362 0, 0xfffff, RADEON_CP_PACKET2);
4363 if (r)
4364 return r;
4365
4366 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4367 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4368 CP_RB2_RPTR, CP_RB2_WPTR,
4369 0, 0xfffff, RADEON_CP_PACKET2);
4370 if (r)
4371 return r;
4372
8c5fd7ef
AD		 4373 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4374 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4375 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4376 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4377 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4378 if (r)
4379 return r;
4380
4381 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4382 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4383 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4384 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4385 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4386 if (r)
4387 return r;
4388
9b136d51
AD		 4389 r = si_cp_load_microcode(rdev);
4390 if (r)
4391 return r;
4392 r = si_cp_resume(rdev);
4393 if (r)
4394 return r;
4395
8c5fd7ef
AD		 4396 r = cayman_dma_resume(rdev);
4397 if (r)
4398 return r;
4399
f2ba57b5
CK		 4400 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4401 if (ring->ring_size) {
4402 r = radeon_ring_init(rdev, ring, ring->ring_size,
4403 R600_WB_UVD_RPTR_OFFSET,
4404 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
4405 0, 0xfffff, RADEON_CP_PACKET2);
4406 if (!r)
4407 r = r600_uvd_init(rdev);
4408 if (r)
4409 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
4410 }
4411
2898c348
CK		 4412 r = radeon_ib_pool_init(rdev);
4413 if (r) {
4414 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
9b136d51 4415 return r;
2898c348 4416 }
9b136d51 4417
c6105f24
CK		 4418 r = radeon_vm_manager_init(rdev);
4419 if (r) {
4420 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
9b136d51 4421 return r;
c6105f24 4422 }
9b136d51
AD		 4423
4424 return 0;
4425}
4426
4427int si_resume(struct radeon_device *rdev)
4428{
4429 int r;
4430
4431 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4432 * posting will perform necessary task to bring back GPU into good
4433 * shape.
4434 */
4435 /* post card */
4436 atom_asic_init(rdev->mode_info.atom_context);
4437
4438 rdev->accel_working = true;
4439 r = si_startup(rdev);
4440 if (r) {
4441 DRM_ERROR("si startup failed on resume\n");
4442 rdev->accel_working = false;
4443 return r;
4444 }
4445
4446 return r;
4447
4448}
4449
4450int si_suspend(struct radeon_device *rdev)
4451{
fa3daf9a 4452 radeon_vm_manager_fini(rdev);
9b136d51 4453 si_cp_enable(rdev, false);
8c5fd7ef 4454 cayman_dma_stop(rdev);
f2ba57b5
CK		 4455 r600_uvd_rbc_stop(rdev);
4456 radeon_uvd_suspend(rdev);
9b136d51
AD		 4457 si_irq_suspend(rdev);
4458 radeon_wb_disable(rdev);
4459 si_pcie_gart_disable(rdev);
4460 return 0;
4461}
4462
4463/* Plan is to move initialization in that function and use
4464 * helper function so that radeon_device_init pretty much
4465 * do nothing more than calling asic specific function. This
4466 * should also allow to remove a bunch of callback function
4467 * like vram_info.
4468 */
4469int si_init(struct radeon_device *rdev)
4470{
4471 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4472 int r;
4473
9b136d51
AD		 4474 /* Read BIOS */
4475 if (!radeon_get_bios(rdev)) {
4476 if (ASIC_IS_AVIVO(rdev))
4477 return -EINVAL;
4478 }
4479 /* Must be an ATOMBIOS */
4480 if (!rdev->is_atom_bios) {
4481 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4482 return -EINVAL;
4483 }
4484 r = radeon_atombios_init(rdev);
4485 if (r)
4486 return r;
4487
4488 /* Post card if necessary */
4489 if (!radeon_card_posted(rdev)) {
4490 if (!rdev->bios) {
4491 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4492 return -EINVAL;
4493 }
4494 DRM_INFO("GPU not posted. posting now...\n");
4495 atom_asic_init(rdev->mode_info.atom_context);
4496 }
4497 /* Initialize scratch registers */
4498 si_scratch_init(rdev);
4499 /* Initialize surface registers */
4500 radeon_surface_init(rdev);
4501 /* Initialize clocks */
4502 radeon_get_clock_info(rdev->ddev);
4503
4504 /* Fence driver */
4505 r = radeon_fence_driver_init(rdev);
4506 if (r)
4507 return r;
4508
4509 /* initialize memory controller */
4510 r = si_mc_init(rdev);
4511 if (r)
4512 return r;
4513 /* Memory manager */
4514 r = radeon_bo_init(rdev);
4515 if (r)
4516 return r;
4517
4518 r = radeon_irq_kms_init(rdev);
4519 if (r)
4520 return r;
4521
4522 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4523 ring->ring_obj = NULL;
4524 r600_ring_init(rdev, ring, 1024 * 1024);
4525
4526 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4527 ring->ring_obj = NULL;
4528 r600_ring_init(rdev, ring, 1024 * 1024);
4529
4530 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4531 ring->ring_obj = NULL;
4532 r600_ring_init(rdev, ring, 1024 * 1024);
4533
8c5fd7ef
AD		 4534 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4535 ring->ring_obj = NULL;
4536 r600_ring_init(rdev, ring, 64 * 1024);
4537
4538 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4539 ring->ring_obj = NULL;
4540 r600_ring_init(rdev, ring, 64 * 1024);
4541
f2ba57b5
CK		 4542 r = radeon_uvd_init(rdev);
4543 if (!r) {
4544 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4545 ring->ring_obj = NULL;
4546 r600_ring_init(rdev, ring, 4096);
4547 }
4548
9b136d51
AD		 4549 rdev->ih.ring_obj = NULL;
4550 r600_ih_ring_init(rdev, 64 * 1024);
4551
4552 r = r600_pcie_gart_init(rdev);
4553 if (r)
4554 return r;
4555
9b136d51 4556 rdev->accel_working = true;
9b136d51
AD		 4557 r = si_startup(rdev);
4558 if (r) {
4559 dev_err(rdev->dev, "disabling GPU acceleration\n");
4560 si_cp_fini(rdev);
8c5fd7ef 4561 cayman_dma_fini(rdev);
9b136d51
AD		 4562 si_irq_fini(rdev);
4563 si_rlc_fini(rdev);
4564 radeon_wb_fini(rdev);
2898c348 4565 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4566 radeon_vm_manager_fini(rdev);
4567 radeon_irq_kms_fini(rdev);
4568 si_pcie_gart_fini(rdev);
4569 rdev->accel_working = false;
4570 }
4571
4572 /* Don't start up if the MC ucode is missing.
4573 * The default clocks and voltages before the MC ucode
4574 * is loaded are not suffient for advanced operations.
4575 */
4576 if (!rdev->mc_fw) {
4577 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4578 return -EINVAL;
4579 }
4580
4581 return 0;
4582}
4583
4584void si_fini(struct radeon_device *rdev)
4585{
9b136d51 4586 si_cp_fini(rdev);
8c5fd7ef 4587 cayman_dma_fini(rdev);
9b136d51
AD		 4588 si_irq_fini(rdev);
4589 si_rlc_fini(rdev);
4590 radeon_wb_fini(rdev);
4591 radeon_vm_manager_fini(rdev);
2898c348 4592 radeon_ib_pool_fini(rdev);
9b136d51 4593 radeon_irq_kms_fini(rdev);
f2ba57b5 4594 radeon_uvd_fini(rdev);
9b136d51
AD		 4595 si_pcie_gart_fini(rdev);
4596 r600_vram_scratch_fini(rdev);
4597 radeon_gem_fini(rdev);
9b136d51
AD		 4598 radeon_fence_driver_fini(rdev);
4599 radeon_bo_fini(rdev);
4600 radeon_atombios_fini(rdev);
4601 kfree(rdev->bios);
4602 rdev->bios = NULL;
4603}
4604
6759a0a7 4605/**
d0418894 4606 * si_get_gpu_clock_counter - return GPU clock counter snapshot
6759a0a7
MO		 4607 *
4608 * @rdev: radeon_device pointer
4609 *
4610 * Fetches a GPU clock counter snapshot (SI).
4611 * Returns the 64 bit clock counter snapshot.
4612 */
d0418894 4613uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
6759a0a7
MO		 4614{
4615 uint64_t clock;
4616
4617 mutex_lock(&rdev->gpu_clock_mutex);
4618 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4619 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4620 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4621 mutex_unlock(&rdev->gpu_clock_mutex);
4622 return clock;
4623}
2539eb02
CK		 4624
4625static int si_uvd_calc_post_div(unsigned target_freq,
4626 unsigned vco_freq,
4627 unsigned *div)
4628{
4629 /* target larger than vco frequency ? */
4630 if (vco_freq < target_freq)
4631 return -1; /* forget it */
4632
4633 /* Fclk = Fvco / PDIV */
4634 *div = vco_freq / target_freq;
4635
4636 /* we alway need a frequency less than or equal the target */
4637 if ((vco_freq / *div) > target_freq)
4638 *div += 1;
4639
4640 /* dividers above 5 must be even */
4641 if (*div > 5 && *div % 2)
4642 *div += 1;
4643
4644 /* out of range ? */
4645 if (*div >= 128)
4646 return -1; /* forget it */
4647
4648 return vco_freq / *div;
4649}
4650
4651static int si_uvd_send_upll_ctlreq(struct radeon_device *rdev)
4652{
4653 unsigned i;
4654
4655 /* assert UPLL_CTLREQ */
4656 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
4657
4658 /* wait for CTLACK and CTLACK2 to get asserted */
4659 for (i = 0; i < 100; ++i) {
4660 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
4661 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
4662 break;
4663 mdelay(10);
4664 }
4665 if (i == 100)
4666 return -ETIMEDOUT;
4667
4668 /* deassert UPLL_CTLREQ */
4669 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
4670
4671 return 0;
4672}
4673
4674int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
4675{
4676 /* start off with something large */
4677 int optimal_diff_score = 0x7FFFFFF;
4678 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
4679 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
4680 unsigned vco_freq;
4681 int r;
4682
4ed10835
CK		 4683 /* bypass vclk and dclk with bclk */
4684 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4685 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
4686 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
4687
4688 /* put PLL in bypass mode */
4689 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
4690
4691 if (!vclk || !dclk) {
4692 /* keep the Bypass mode, put PLL to sleep */
4693 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
4694 return 0;
4695 }
4696
2539eb02
CK		 4697 /* loop through vco from low to high */
4698 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
4699 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
4700 int calc_clk, diff_score, diff_vclk, diff_dclk;
4701 unsigned vclk_div, dclk_div;
4702
4703 /* fb div out of range ? */
4704 if (fb_div > 0x03FFFFFF)
4705 break; /* it can oly get worse */
4706
4707 /* calc vclk with current vco freq. */
4708 calc_clk = si_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
4709 if (calc_clk == -1)
4710 break; /* vco is too big, it has to stop. */
4711 diff_vclk = vclk - calc_clk;
4712
4713 /* calc dclk with current vco freq. */
4714 calc_clk = si_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
4715 if (calc_clk == -1)
4716 break; /* vco is too big, it has to stop. */
4717 diff_dclk = dclk - calc_clk;
4718
4719 /* determine if this vco setting is better than current optimal settings */
4720 diff_score = abs(diff_vclk) + abs(diff_dclk);
4721 if (diff_score < optimal_diff_score) {
4722 optimal_fb_div = fb_div;
4723 optimal_vclk_div = vclk_div;
4724 optimal_dclk_div = dclk_div;
4725 optimal_vco_freq = vco_freq;
4726 optimal_diff_score = diff_score;
4727 if (optimal_diff_score == 0)
4728 break; /* it can't get better than this */
4729 }
4730 }
4731
4732 /* set RESET_ANTI_MUX to 0 */
4733 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
4734
4735 /* set VCO_MODE to 1 */
4736 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
4737
4738 /* toggle UPLL_SLEEP to 1 then back to 0 */
4739 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
4740 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
4741
4742 /* deassert UPLL_RESET */
4743 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
4744
4745 mdelay(1);
4746
2539eb02
CK		 4747 r = si_uvd_send_upll_ctlreq(rdev);
4748 if (r)
4749 return r;
4750
4751 /* assert UPLL_RESET again */
4752 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
4753
4754 /* disable spread spectrum. */
4755 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
4756
4757 /* set feedback divider */
4758 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
4759
4760 /* set ref divider to 0 */
4761 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
4762
4763 if (optimal_vco_freq < 187500)
4764 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
4765 else
4766 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
4767
4768 /* set PDIV_A and PDIV_B */
4769 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4770 UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
4771 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
4772
4773 /* give the PLL some time to settle */
4774 mdelay(15);
4775
4776 /* deassert PLL_RESET */
4777 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
4778
4779 mdelay(15);
4780
4781 /* switch from bypass mode to normal mode */
4782 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
4783
4784 r = si_uvd_send_upll_ctlreq(rdev);
4785 if (r)
4786 return r;
4787
4788 /* switch VCLK and DCLK selection */
4789 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4790 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
4791 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
4792
4793 mdelay(100);
4794
4795 return 0;
4796}
Linux 6.x block layer and io_uring tree(s)