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drm/radeon/cayman: add VM CS checker support for CP DMA
[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c
CommitLineData
43b3cd99
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
0f0de06c
AD		 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
43b3cd99
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
43b3cd99
AD		 32#include "sid.h"
33#include "atom.h"
48c0c902 34#include "si_blit_shaders.h"
43b3cd99 35
0f0de06c
AD		 36#define SI_PFP_UCODE_SIZE 2144
37#define SI_PM4_UCODE_SIZE 2144
38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769
41
42MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53MODULE_FIRMWARE("radeon/VERDE_me.bin");
54MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
57
25a857fb
AD		 58extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59extern void r600_ih_ring_fini(struct radeon_device *rdev);
0a96d72b 60extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
c476dde2
AD		 61extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
ca7db22b 63extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
0a96d72b 64
1bd47d2e
AD		 65/* get temperature in millidegrees */
66int si_get_temp(struct radeon_device *rdev)
67{
68 u32 temp;
69 int actual_temp = 0;
70
71 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
72 CTF_TEMP_SHIFT;
73
74 if (temp & 0x200)
75 actual_temp = 255;
76 else
77 actual_temp = temp & 0x1ff;
78
79 actual_temp = (actual_temp * 1000);
80
81 return actual_temp;
82}
83
8b074dd6
AD		 84#define TAHITI_IO_MC_REGS_SIZE 36
85
86static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
87 {0x0000006f, 0x03044000},
88 {0x00000070, 0x0480c018},
89 {0x00000071, 0x00000040},
90 {0x00000072, 0x01000000},
91 {0x00000074, 0x000000ff},
92 {0x00000075, 0x00143400},
93 {0x00000076, 0x08ec0800},
94 {0x00000077, 0x040000cc},
95 {0x00000079, 0x00000000},
96 {0x0000007a, 0x21000409},
97 {0x0000007c, 0x00000000},
98 {0x0000007d, 0xe8000000},
99 {0x0000007e, 0x044408a8},
100 {0x0000007f, 0x00000003},
101 {0x00000080, 0x00000000},
102 {0x00000081, 0x01000000},
103 {0x00000082, 0x02000000},
104 {0x00000083, 0x00000000},
105 {0x00000084, 0xe3f3e4f4},
106 {0x00000085, 0x00052024},
107 {0x00000087, 0x00000000},
108 {0x00000088, 0x66036603},
109 {0x00000089, 0x01000000},
110 {0x0000008b, 0x1c0a0000},
111 {0x0000008c, 0xff010000},
112 {0x0000008e, 0xffffefff},
113 {0x0000008f, 0xfff3efff},
114 {0x00000090, 0xfff3efbf},
115 {0x00000094, 0x00101101},
116 {0x00000095, 0x00000fff},
117 {0x00000096, 0x00116fff},
118 {0x00000097, 0x60010000},
119 {0x00000098, 0x10010000},
120 {0x00000099, 0x00006000},
121 {0x0000009a, 0x00001000},
122 {0x0000009f, 0x00a77400}
123};
124
125static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
126 {0x0000006f, 0x03044000},
127 {0x00000070, 0x0480c018},
128 {0x00000071, 0x00000040},
129 {0x00000072, 0x01000000},
130 {0x00000074, 0x000000ff},
131 {0x00000075, 0x00143400},
132 {0x00000076, 0x08ec0800},
133 {0x00000077, 0x040000cc},
134 {0x00000079, 0x00000000},
135 {0x0000007a, 0x21000409},
136 {0x0000007c, 0x00000000},
137 {0x0000007d, 0xe8000000},
138 {0x0000007e, 0x044408a8},
139 {0x0000007f, 0x00000003},
140 {0x00000080, 0x00000000},
141 {0x00000081, 0x01000000},
142 {0x00000082, 0x02000000},
143 {0x00000083, 0x00000000},
144 {0x00000084, 0xe3f3e4f4},
145 {0x00000085, 0x00052024},
146 {0x00000087, 0x00000000},
147 {0x00000088, 0x66036603},
148 {0x00000089, 0x01000000},
149 {0x0000008b, 0x1c0a0000},
150 {0x0000008c, 0xff010000},
151 {0x0000008e, 0xffffefff},
152 {0x0000008f, 0xfff3efff},
153 {0x00000090, 0xfff3efbf},
154 {0x00000094, 0x00101101},
155 {0x00000095, 0x00000fff},
156 {0x00000096, 0x00116fff},
157 {0x00000097, 0x60010000},
158 {0x00000098, 0x10010000},
159 {0x00000099, 0x00006000},
160 {0x0000009a, 0x00001000},
161 {0x0000009f, 0x00a47400}
162};
163
164static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
165 {0x0000006f, 0x03044000},
166 {0x00000070, 0x0480c018},
167 {0x00000071, 0x00000040},
168 {0x00000072, 0x01000000},
169 {0x00000074, 0x000000ff},
170 {0x00000075, 0x00143400},
171 {0x00000076, 0x08ec0800},
172 {0x00000077, 0x040000cc},
173 {0x00000079, 0x00000000},
174 {0x0000007a, 0x21000409},
175 {0x0000007c, 0x00000000},
176 {0x0000007d, 0xe8000000},
177 {0x0000007e, 0x044408a8},
178 {0x0000007f, 0x00000003},
179 {0x00000080, 0x00000000},
180 {0x00000081, 0x01000000},
181 {0x00000082, 0x02000000},
182 {0x00000083, 0x00000000},
183 {0x00000084, 0xe3f3e4f4},
184 {0x00000085, 0x00052024},
185 {0x00000087, 0x00000000},
186 {0x00000088, 0x66036603},
187 {0x00000089, 0x01000000},
188 {0x0000008b, 0x1c0a0000},
189 {0x0000008c, 0xff010000},
190 {0x0000008e, 0xffffefff},
191 {0x0000008f, 0xfff3efff},
192 {0x00000090, 0xfff3efbf},
193 {0x00000094, 0x00101101},
194 {0x00000095, 0x00000fff},
195 {0x00000096, 0x00116fff},
196 {0x00000097, 0x60010000},
197 {0x00000098, 0x10010000},
198 {0x00000099, 0x00006000},
199 {0x0000009a, 0x00001000},
200 {0x0000009f, 0x00a37400}
201};
202
203/* ucode loading */
204static int si_mc_load_microcode(struct radeon_device *rdev)
205{
206 const __be32 *fw_data;
207 u32 running, blackout = 0;
208 u32 *io_mc_regs;
209 int i, ucode_size, regs_size;
210
211 if (!rdev->mc_fw)
212 return -EINVAL;
213
214 switch (rdev->family) {
215 case CHIP_TAHITI:
216 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
217 ucode_size = SI_MC_UCODE_SIZE;
218 regs_size = TAHITI_IO_MC_REGS_SIZE;
219 break;
220 case CHIP_PITCAIRN:
221 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
222 ucode_size = SI_MC_UCODE_SIZE;
223 regs_size = TAHITI_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_VERDE:
226 default:
227 io_mc_regs = (u32 *)&verde_io_mc_regs;
228 ucode_size = SI_MC_UCODE_SIZE;
229 regs_size = TAHITI_IO_MC_REGS_SIZE;
230 break;
231 }
232
233 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
234
235 if (running == 0) {
236 if (running) {
237 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
238 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
239 }
240
241 /* reset the engine and set to writable */
242 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
243 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
244
245 /* load mc io regs */
246 for (i = 0; i < regs_size; i++) {
247 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
248 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
249 }
250 /* load the MC ucode */
251 fw_data = (const __be32 *)rdev->mc_fw->data;
252 for (i = 0; i < ucode_size; i++)
253 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
254
255 /* put the engine back into the active state */
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
257 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
259
260 /* wait for training to complete */
261 for (i = 0; i < rdev->usec_timeout; i++) {
262 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
263 break;
264 udelay(1);
265 }
266 for (i = 0; i < rdev->usec_timeout; i++) {
267 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
268 break;
269 udelay(1);
270 }
271
272 if (running)
273 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
274 }
275
276 return 0;
277}
278
0f0de06c
AD		 279static int si_init_microcode(struct radeon_device *rdev)
280{
281 struct platform_device *pdev;
282 const char *chip_name;
283 const char *rlc_chip_name;
284 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
285 char fw_name[30];
286 int err;
287
288 DRM_DEBUG("\n");
289
290 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
291 err = IS_ERR(pdev);
292 if (err) {
293 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
294 return -EINVAL;
295 }
296
297 switch (rdev->family) {
298 case CHIP_TAHITI:
299 chip_name = "TAHITI";
300 rlc_chip_name = "TAHITI";
301 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
302 me_req_size = SI_PM4_UCODE_SIZE * 4;
303 ce_req_size = SI_CE_UCODE_SIZE * 4;
304 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
305 mc_req_size = SI_MC_UCODE_SIZE * 4;
306 break;
307 case CHIP_PITCAIRN:
308 chip_name = "PITCAIRN";
309 rlc_chip_name = "PITCAIRN";
310 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
311 me_req_size = SI_PM4_UCODE_SIZE * 4;
312 ce_req_size = SI_CE_UCODE_SIZE * 4;
313 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
314 mc_req_size = SI_MC_UCODE_SIZE * 4;
315 break;
316 case CHIP_VERDE:
317 chip_name = "VERDE";
318 rlc_chip_name = "VERDE";
319 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
320 me_req_size = SI_PM4_UCODE_SIZE * 4;
321 ce_req_size = SI_CE_UCODE_SIZE * 4;
322 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
323 mc_req_size = SI_MC_UCODE_SIZE * 4;
324 break;
325 default: BUG();
326 }
327
328 DRM_INFO("Loading %s Microcode\n", chip_name);
329
330 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
331 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
332 if (err)
333 goto out;
334 if (rdev->pfp_fw->size != pfp_req_size) {
335 printk(KERN_ERR
336 "si_cp: Bogus length %zu in firmware \"%s\"\n",
337 rdev->pfp_fw->size, fw_name);
338 err = -EINVAL;
339 goto out;
340 }
341
342 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
343 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
344 if (err)
345 goto out;
346 if (rdev->me_fw->size != me_req_size) {
347 printk(KERN_ERR
348 "si_cp: Bogus length %zu in firmware \"%s\"\n",
349 rdev->me_fw->size, fw_name);
350 err = -EINVAL;
351 }
352
353 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
354 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
355 if (err)
356 goto out;
357 if (rdev->ce_fw->size != ce_req_size) {
358 printk(KERN_ERR
359 "si_cp: Bogus length %zu in firmware \"%s\"\n",
360 rdev->ce_fw->size, fw_name);
361 err = -EINVAL;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
365 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->rlc_fw->size != rlc_req_size) {
369 printk(KERN_ERR
370 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
371 rdev->rlc_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
376 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->mc_fw->size != mc_req_size) {
380 printk(KERN_ERR
381 "si_mc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->mc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
386out:
387 platform_device_unregister(pdev);
388
389 if (err) {
390 if (err != -EINVAL)
391 printk(KERN_ERR
392 "si_cp: Failed to load firmware \"%s\"\n",
393 fw_name);
394 release_firmware(rdev->pfp_fw);
395 rdev->pfp_fw = NULL;
396 release_firmware(rdev->me_fw);
397 rdev->me_fw = NULL;
398 release_firmware(rdev->ce_fw);
399 rdev->ce_fw = NULL;
400 release_firmware(rdev->rlc_fw);
401 rdev->rlc_fw = NULL;
402 release_firmware(rdev->mc_fw);
403 rdev->mc_fw = NULL;
404 }
405 return err;
406}
407
43b3cd99
AD		 408/* watermark setup */
409static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
410 struct radeon_crtc *radeon_crtc,
411 struct drm_display_mode *mode,
412 struct drm_display_mode *other_mode)
413{
414 u32 tmp;
415 /*
416 * Line Buffer Setup
417 * There are 3 line buffers, each one shared by 2 display controllers.
418 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
419 * the display controllers. The paritioning is done via one of four
420 * preset allocations specified in bits 21:20:
421 * 0 - half lb
422 * 2 - whole lb, other crtc must be disabled
423 */
424 /* this can get tricky if we have two large displays on a paired group
425 * of crtcs. Ideally for multiple large displays we'd assign them to
426 * non-linked crtcs for maximum line buffer allocation.
427 */
428 if (radeon_crtc->base.enabled && mode) {
429 if (other_mode)
430 tmp = 0; /* 1/2 */
431 else
432 tmp = 2; /* whole */
433 } else
434 tmp = 0;
435
436 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
437 DC_LB_MEMORY_CONFIG(tmp));
438
439 if (radeon_crtc->base.enabled && mode) {
440 switch (tmp) {
441 case 0:
442 default:
443 return 4096 * 2;
444 case 2:
445 return 8192 * 2;
446 }
447 }
448
449 /* controller not enabled, so no lb used */
450 return 0;
451}
452
ca7db22b 453static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
43b3cd99
AD		 454{
455 u32 tmp = RREG32(MC_SHARED_CHMAP);
456
457 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
458 case 0:
459 default:
460 return 1;
461 case 1:
462 return 2;
463 case 2:
464 return 4;
465 case 3:
466 return 8;
467 case 4:
468 return 3;
469 case 5:
470 return 6;
471 case 6:
472 return 10;
473 case 7:
474 return 12;
475 case 8:
476 return 16;
477 }
478}
479
480struct dce6_wm_params {
481 u32 dram_channels; /* number of dram channels */
482 u32 yclk; /* bandwidth per dram data pin in kHz */
483 u32 sclk; /* engine clock in kHz */
484 u32 disp_clk; /* display clock in kHz */
485 u32 src_width; /* viewport width */
486 u32 active_time; /* active display time in ns */
487 u32 blank_time; /* blank time in ns */
488 bool interlaced; /* mode is interlaced */
489 fixed20_12 vsc; /* vertical scale ratio */
490 u32 num_heads; /* number of active crtcs */
491 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
492 u32 lb_size; /* line buffer allocated to pipe */
493 u32 vtaps; /* vertical scaler taps */
494};
495
496static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
497{
498 /* Calculate raw DRAM Bandwidth */
499 fixed20_12 dram_efficiency; /* 0.7 */
500 fixed20_12 yclk, dram_channels, bandwidth;
501 fixed20_12 a;
502
503 a.full = dfixed_const(1000);
504 yclk.full = dfixed_const(wm->yclk);
505 yclk.full = dfixed_div(yclk, a);
506 dram_channels.full = dfixed_const(wm->dram_channels * 4);
507 a.full = dfixed_const(10);
508 dram_efficiency.full = dfixed_const(7);
509 dram_efficiency.full = dfixed_div(dram_efficiency, a);
510 bandwidth.full = dfixed_mul(dram_channels, yclk);
511 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
512
513 return dfixed_trunc(bandwidth);
514}
515
516static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
517{
518 /* Calculate DRAM Bandwidth and the part allocated to display. */
519 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
520 fixed20_12 yclk, dram_channels, bandwidth;
521 fixed20_12 a;
522
523 a.full = dfixed_const(1000);
524 yclk.full = dfixed_const(wm->yclk);
525 yclk.full = dfixed_div(yclk, a);
526 dram_channels.full = dfixed_const(wm->dram_channels * 4);
527 a.full = dfixed_const(10);
528 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
529 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
530 bandwidth.full = dfixed_mul(dram_channels, yclk);
531 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
532
533 return dfixed_trunc(bandwidth);
534}
535
536static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
537{
538 /* Calculate the display Data return Bandwidth */
539 fixed20_12 return_efficiency; /* 0.8 */
540 fixed20_12 sclk, bandwidth;
541 fixed20_12 a;
542
543 a.full = dfixed_const(1000);
544 sclk.full = dfixed_const(wm->sclk);
545 sclk.full = dfixed_div(sclk, a);
546 a.full = dfixed_const(10);
547 return_efficiency.full = dfixed_const(8);
548 return_efficiency.full = dfixed_div(return_efficiency, a);
549 a.full = dfixed_const(32);
550 bandwidth.full = dfixed_mul(a, sclk);
551 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
552
553 return dfixed_trunc(bandwidth);
554}
555
556static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
557{
558 return 32;
559}
560
561static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
562{
563 /* Calculate the DMIF Request Bandwidth */
564 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
565 fixed20_12 disp_clk, sclk, bandwidth;
566 fixed20_12 a, b1, b2;
567 u32 min_bandwidth;
568
569 a.full = dfixed_const(1000);
570 disp_clk.full = dfixed_const(wm->disp_clk);
571 disp_clk.full = dfixed_div(disp_clk, a);
572 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
573 b1.full = dfixed_mul(a, disp_clk);
574
575 a.full = dfixed_const(1000);
576 sclk.full = dfixed_const(wm->sclk);
577 sclk.full = dfixed_div(sclk, a);
578 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
579 b2.full = dfixed_mul(a, sclk);
580
581 a.full = dfixed_const(10);
582 disp_clk_request_efficiency.full = dfixed_const(8);
583 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
584
585 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
586
587 a.full = dfixed_const(min_bandwidth);
588 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
589
590 return dfixed_trunc(bandwidth);
591}
592
593static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
594{
595 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
596 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
597 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
598 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
599
600 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
601}
602
603static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
604{
605 /* Calculate the display mode Average Bandwidth
606 * DisplayMode should contain the source and destination dimensions,
607 * timing, etc.
608 */
609 fixed20_12 bpp;
610 fixed20_12 line_time;
611 fixed20_12 src_width;
612 fixed20_12 bandwidth;
613 fixed20_12 a;
614
615 a.full = dfixed_const(1000);
616 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
617 line_time.full = dfixed_div(line_time, a);
618 bpp.full = dfixed_const(wm->bytes_per_pixel);
619 src_width.full = dfixed_const(wm->src_width);
620 bandwidth.full = dfixed_mul(src_width, bpp);
621 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
622 bandwidth.full = dfixed_div(bandwidth, line_time);
623
624 return dfixed_trunc(bandwidth);
625}
626
627static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
628{
629 /* First calcualte the latency in ns */
630 u32 mc_latency = 2000; /* 2000 ns. */
631 u32 available_bandwidth = dce6_available_bandwidth(wm);
632 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
633 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
634 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
635 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
636 (wm->num_heads * cursor_line_pair_return_time);
637 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
638 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
639 u32 tmp, dmif_size = 12288;
640 fixed20_12 a, b, c;
641
642 if (wm->num_heads == 0)
643 return 0;
644
645 a.full = dfixed_const(2);
646 b.full = dfixed_const(1);
647 if ((wm->vsc.full > a.full) ||
648 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
649 (wm->vtaps >= 5) ||
650 ((wm->vsc.full >= a.full) && wm->interlaced))
651 max_src_lines_per_dst_line = 4;
652 else
653 max_src_lines_per_dst_line = 2;
654
655 a.full = dfixed_const(available_bandwidth);
656 b.full = dfixed_const(wm->num_heads);
657 a.full = dfixed_div(a, b);
658
659 b.full = dfixed_const(mc_latency + 512);
660 c.full = dfixed_const(wm->disp_clk);
661 b.full = dfixed_div(b, c);
662
663 c.full = dfixed_const(dmif_size);
664 b.full = dfixed_div(c, b);
665
666 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
667
668 b.full = dfixed_const(1000);
669 c.full = dfixed_const(wm->disp_clk);
670 b.full = dfixed_div(c, b);
671 c.full = dfixed_const(wm->bytes_per_pixel);
672 b.full = dfixed_mul(b, c);
673
674 lb_fill_bw = min(tmp, dfixed_trunc(b));
675
676 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
677 b.full = dfixed_const(1000);
678 c.full = dfixed_const(lb_fill_bw);
679 b.full = dfixed_div(c, b);
680 a.full = dfixed_div(a, b);
681 line_fill_time = dfixed_trunc(a);
682
683 if (line_fill_time < wm->active_time)
684 return latency;
685 else
686 return latency + (line_fill_time - wm->active_time);
687
688}
689
690static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
691{
692 if (dce6_average_bandwidth(wm) <=
693 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
694 return true;
695 else
696 return false;
697};
698
699static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
700{
701 if (dce6_average_bandwidth(wm) <=
702 (dce6_available_bandwidth(wm) / wm->num_heads))
703 return true;
704 else
705 return false;
706};
707
708static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
709{
710 u32 lb_partitions = wm->lb_size / wm->src_width;
711 u32 line_time = wm->active_time + wm->blank_time;
712 u32 latency_tolerant_lines;
713 u32 latency_hiding;
714 fixed20_12 a;
715
716 a.full = dfixed_const(1);
717 if (wm->vsc.full > a.full)
718 latency_tolerant_lines = 1;
719 else {
720 if (lb_partitions <= (wm->vtaps + 1))
721 latency_tolerant_lines = 1;
722 else
723 latency_tolerant_lines = 2;
724 }
725
726 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
727
728 if (dce6_latency_watermark(wm) <= latency_hiding)
729 return true;
730 else
731 return false;
732}
733
734static void dce6_program_watermarks(struct radeon_device *rdev,
735 struct radeon_crtc *radeon_crtc,
736 u32 lb_size, u32 num_heads)
737{
738 struct drm_display_mode *mode = &radeon_crtc->base.mode;
739 struct dce6_wm_params wm;
740 u32 pixel_period;
741 u32 line_time = 0;
742 u32 latency_watermark_a = 0, latency_watermark_b = 0;
743 u32 priority_a_mark = 0, priority_b_mark = 0;
744 u32 priority_a_cnt = PRIORITY_OFF;
745 u32 priority_b_cnt = PRIORITY_OFF;
746 u32 tmp, arb_control3;
747 fixed20_12 a, b, c;
748
749 if (radeon_crtc->base.enabled && num_heads && mode) {
750 pixel_period = 1000000 / (u32)mode->clock;
751 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
752 priority_a_cnt = 0;
753 priority_b_cnt = 0;
754
755 wm.yclk = rdev->pm.current_mclk * 10;
756 wm.sclk = rdev->pm.current_sclk * 10;
757 wm.disp_clk = mode->clock;
758 wm.src_width = mode->crtc_hdisplay;
759 wm.active_time = mode->crtc_hdisplay * pixel_period;
760 wm.blank_time = line_time - wm.active_time;
761 wm.interlaced = false;
762 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
763 wm.interlaced = true;
764 wm.vsc = radeon_crtc->vsc;
765 wm.vtaps = 1;
766 if (radeon_crtc->rmx_type != RMX_OFF)
767 wm.vtaps = 2;
768 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
769 wm.lb_size = lb_size;
ca7db22b
AD		 770 if (rdev->family == CHIP_ARUBA)
771 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
772 else
773 wm.dram_channels = si_get_number_of_dram_channels(rdev);
43b3cd99
AD		 774 wm.num_heads = num_heads;
775
776 /* set for high clocks */
777 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
778 /* set for low clocks */
779 /* wm.yclk = low clk; wm.sclk = low clk */
780 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
781
782 /* possibly force display priority to high */
783 /* should really do this at mode validation time... */
784 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
785 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
786 !dce6_check_latency_hiding(&wm) ||
787 (rdev->disp_priority == 2)) {
788 DRM_DEBUG_KMS("force priority to high\n");
789 priority_a_cnt |= PRIORITY_ALWAYS_ON;
790 priority_b_cnt |= PRIORITY_ALWAYS_ON;
791 }
792
793 a.full = dfixed_const(1000);
794 b.full = dfixed_const(mode->clock);
795 b.full = dfixed_div(b, a);
796 c.full = dfixed_const(latency_watermark_a);
797 c.full = dfixed_mul(c, b);
798 c.full = dfixed_mul(c, radeon_crtc->hsc);
799 c.full = dfixed_div(c, a);
800 a.full = dfixed_const(16);
801 c.full = dfixed_div(c, a);
802 priority_a_mark = dfixed_trunc(c);
803 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
804
805 a.full = dfixed_const(1000);
806 b.full = dfixed_const(mode->clock);
807 b.full = dfixed_div(b, a);
808 c.full = dfixed_const(latency_watermark_b);
809 c.full = dfixed_mul(c, b);
810 c.full = dfixed_mul(c, radeon_crtc->hsc);
811 c.full = dfixed_div(c, a);
812 a.full = dfixed_const(16);
813 c.full = dfixed_div(c, a);
814 priority_b_mark = dfixed_trunc(c);
815 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
816 }
817
818 /* select wm A */
819 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
820 tmp = arb_control3;
821 tmp &= ~LATENCY_WATERMARK_MASK(3);
822 tmp |= LATENCY_WATERMARK_MASK(1);
823 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
824 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
825 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
826 LATENCY_HIGH_WATERMARK(line_time)));
827 /* select wm B */
828 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
829 tmp &= ~LATENCY_WATERMARK_MASK(3);
830 tmp |= LATENCY_WATERMARK_MASK(2);
831 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
832 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
833 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
834 LATENCY_HIGH_WATERMARK(line_time)));
835 /* restore original selection */
836 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
837
838 /* write the priority marks */
839 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
840 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
841
842}
843
844void dce6_bandwidth_update(struct radeon_device *rdev)
845{
846 struct drm_display_mode *mode0 = NULL;
847 struct drm_display_mode *mode1 = NULL;
848 u32 num_heads = 0, lb_size;
849 int i;
850
851 radeon_update_display_priority(rdev);
852
853 for (i = 0; i < rdev->num_crtc; i++) {
854 if (rdev->mode_info.crtcs[i]->base.enabled)
855 num_heads++;
856 }
857 for (i = 0; i < rdev->num_crtc; i += 2) {
858 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
859 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
860 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
861 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
862 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
863 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
864 }
865}
866
0a96d72b
AD		 867/*
868 * Core functions
869 */
0a96d72b
AD		 870static void si_tiling_mode_table_init(struct radeon_device *rdev)
871{
872 const u32 num_tile_mode_states = 32;
873 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
874
875 switch (rdev->config.si.mem_row_size_in_kb) {
876 case 1:
877 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
878 break;
879 case 2:
880 default:
881 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
882 break;
883 case 4:
884 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
885 break;
886 }
887
888 if ((rdev->family == CHIP_TAHITI) ||
889 (rdev->family == CHIP_PITCAIRN)) {
890 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
891 switch (reg_offset) {
892 case 0: /* non-AA compressed depth or any compressed stencil */
893 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
894 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
895 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
896 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
897 NUM_BANKS(ADDR_SURF_16_BANK) |
898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
901 break;
902 case 1: /* 2xAA/4xAA compressed depth only */
903 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
904 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
905 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
907 NUM_BANKS(ADDR_SURF_16_BANK) |
908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
911 break;
912 case 2: /* 8xAA compressed depth only */
913 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
914 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
915 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
917 NUM_BANKS(ADDR_SURF_16_BANK) |
918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
921 break;
922 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
923 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
924 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
925 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
926 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
927 NUM_BANKS(ADDR_SURF_16_BANK) |
928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
931 break;
932 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
933 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
934 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
935 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
937 NUM_BANKS(ADDR_SURF_16_BANK) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
941 break;
942 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
943 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
944 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
945 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
946 TILE_SPLIT(split_equal_to_row_size) |
947 NUM_BANKS(ADDR_SURF_16_BANK) |
948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
951 break;
952 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
953 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
954 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
955 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
956 TILE_SPLIT(split_equal_to_row_size) |
957 NUM_BANKS(ADDR_SURF_16_BANK) |
958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
961 break;
962 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
963 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
964 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
965 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
966 TILE_SPLIT(split_equal_to_row_size) |
967 NUM_BANKS(ADDR_SURF_16_BANK) |
968 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
971 break;
972 case 8: /* 1D and 1D Array Surfaces */
973 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
974 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
975 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
976 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
977 NUM_BANKS(ADDR_SURF_16_BANK) |
978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
981 break;
982 case 9: /* Displayable maps. */
983 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
984 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
985 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
987 NUM_BANKS(ADDR_SURF_16_BANK) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
991 break;
992 case 10: /* Display 8bpp. */
993 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
994 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
995 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
997 NUM_BANKS(ADDR_SURF_16_BANK) |
998 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1001 break;
1002 case 11: /* Display 16bpp. */
1003 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1004 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1005 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1007 NUM_BANKS(ADDR_SURF_16_BANK) |
1008 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1011 break;
1012 case 12: /* Display 32bpp. */
1013 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1014 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1017 NUM_BANKS(ADDR_SURF_16_BANK) |
1018 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1021 break;
1022 case 13: /* Thin. */
1023 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1024 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1027 NUM_BANKS(ADDR_SURF_16_BANK) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1031 break;
1032 case 14: /* Thin 8 bpp. */
1033 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1035 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1037 NUM_BANKS(ADDR_SURF_16_BANK) |
1038 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1041 break;
1042 case 15: /* Thin 16 bpp. */
1043 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1044 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1045 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1046 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1047 NUM_BANKS(ADDR_SURF_16_BANK) |
1048 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1049 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1050 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1051 break;
1052 case 16: /* Thin 32 bpp. */
1053 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1055 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1057 NUM_BANKS(ADDR_SURF_16_BANK) |
1058 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1059 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1060 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1061 break;
1062 case 17: /* Thin 64 bpp. */
1063 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1065 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1066 TILE_SPLIT(split_equal_to_row_size) |
1067 NUM_BANKS(ADDR_SURF_16_BANK) |
1068 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1069 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1070 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1071 break;
1072 case 21: /* 8 bpp PRT. */
1073 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1074 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1075 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1076 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1077 NUM_BANKS(ADDR_SURF_16_BANK) |
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1081 break;
1082 case 22: /* 16 bpp PRT */
1083 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1084 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1086 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1087 NUM_BANKS(ADDR_SURF_16_BANK) |
1088 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1089 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1090 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1091 break;
1092 case 23: /* 32 bpp PRT */
1093 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1094 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1097 NUM_BANKS(ADDR_SURF_16_BANK) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1101 break;
1102 case 24: /* 64 bpp PRT */
1103 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1105 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1107 NUM_BANKS(ADDR_SURF_16_BANK) |
1108 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1109 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1110 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1111 break;
1112 case 25: /* 128 bpp PRT */
1113 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1114 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1115 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1117 NUM_BANKS(ADDR_SURF_8_BANK) |
1118 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1121 break;
1122 default:
1123 gb_tile_moden = 0;
1124 break;
1125 }
1126 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1127 }
1128 } else if (rdev->family == CHIP_VERDE) {
1129 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1130 switch (reg_offset) {
1131 case 0: /* non-AA compressed depth or any compressed stencil */
1132 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1134 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1135 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1136 NUM_BANKS(ADDR_SURF_16_BANK) |
1137 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1140 break;
1141 case 1: /* 2xAA/4xAA compressed depth only */
1142 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1143 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1144 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1146 NUM_BANKS(ADDR_SURF_16_BANK) |
1147 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1149 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1150 break;
1151 case 2: /* 8xAA compressed depth only */
1152 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1153 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1154 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1155 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1156 NUM_BANKS(ADDR_SURF_16_BANK) |
1157 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1160 break;
1161 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1162 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1163 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1164 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1166 NUM_BANKS(ADDR_SURF_16_BANK) |
1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1170 break;
1171 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1172 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1173 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1174 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1175 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1176 NUM_BANKS(ADDR_SURF_16_BANK) |
1177 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1180 break;
1181 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1182 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1183 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1184 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1185 TILE_SPLIT(split_equal_to_row_size) |
1186 NUM_BANKS(ADDR_SURF_16_BANK) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1190 break;
1191 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1192 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1193 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1194 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1195 TILE_SPLIT(split_equal_to_row_size) |
1196 NUM_BANKS(ADDR_SURF_16_BANK) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1200 break;
1201 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1202 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1204 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1205 TILE_SPLIT(split_equal_to_row_size) |
1206 NUM_BANKS(ADDR_SURF_16_BANK) |
1207 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1210 break;
1211 case 8: /* 1D and 1D Array Surfaces */
1212 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1213 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1214 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1215 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1216 NUM_BANKS(ADDR_SURF_16_BANK) |
1217 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1219 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1220 break;
1221 case 9: /* Displayable maps. */
1222 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1223 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1224 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1226 NUM_BANKS(ADDR_SURF_16_BANK) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1230 break;
1231 case 10: /* Display 8bpp. */
1232 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1236 NUM_BANKS(ADDR_SURF_16_BANK) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1240 break;
1241 case 11: /* Display 16bpp. */
1242 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1246 NUM_BANKS(ADDR_SURF_16_BANK) |
1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1250 break;
1251 case 12: /* Display 32bpp. */
1252 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1253 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1254 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1256 NUM_BANKS(ADDR_SURF_16_BANK) |
1257 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1260 break;
1261 case 13: /* Thin. */
1262 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1263 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1264 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1266 NUM_BANKS(ADDR_SURF_16_BANK) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1270 break;
1271 case 14: /* Thin 8 bpp. */
1272 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1274 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1276 NUM_BANKS(ADDR_SURF_16_BANK) |
1277 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1280 break;
1281 case 15: /* Thin 16 bpp. */
1282 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1283 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1284 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1286 NUM_BANKS(ADDR_SURF_16_BANK) |
1287 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1290 break;
1291 case 16: /* Thin 32 bpp. */
1292 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1293 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1294 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1295 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1296 NUM_BANKS(ADDR_SURF_16_BANK) |
1297 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1298 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1299 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1300 break;
1301 case 17: /* Thin 64 bpp. */
1302 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1303 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1304 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1305 TILE_SPLIT(split_equal_to_row_size) |
1306 NUM_BANKS(ADDR_SURF_16_BANK) |
1307 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1310 break;
1311 case 21: /* 8 bpp PRT. */
1312 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1314 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1315 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1316 NUM_BANKS(ADDR_SURF_16_BANK) |
1317 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1318 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1319 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1320 break;
1321 case 22: /* 16 bpp PRT */
1322 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1323 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1324 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1325 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1326 NUM_BANKS(ADDR_SURF_16_BANK) |
1327 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1330 break;
1331 case 23: /* 32 bpp PRT */
1332 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1333 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1335 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1336 NUM_BANKS(ADDR_SURF_16_BANK) |
1337 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1338 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1339 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1340 break;
1341 case 24: /* 64 bpp PRT */
1342 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1343 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1344 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1345 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1346 NUM_BANKS(ADDR_SURF_16_BANK) |
1347 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1350 break;
1351 case 25: /* 128 bpp PRT */
1352 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1353 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1354 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1355 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1356 NUM_BANKS(ADDR_SURF_8_BANK) |
1357 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1360 break;
1361 default:
1362 gb_tile_moden = 0;
1363 break;
1364 }
1365 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1366 }
1367 } else
1368 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1369}
1370
1a8ca750
AD		 1371static void si_select_se_sh(struct radeon_device *rdev,
1372 u32 se_num, u32 sh_num)
1373{
1374 u32 data = INSTANCE_BROADCAST_WRITES;
1375
1376 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1377 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1378 else if (se_num == 0xffffffff)
1379 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1380 else if (sh_num == 0xffffffff)
1381 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1382 else
1383 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1384 WREG32(GRBM_GFX_INDEX, data);
1385}
1386
1387static u32 si_create_bitmask(u32 bit_width)
1388{
1389 u32 i, mask = 0;
1390
1391 for (i = 0; i < bit_width; i++) {
1392 mask <<= 1;
1393 mask |= 1;
1394 }
1395 return mask;
1396}
1397
1398static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1399{
1400 u32 data, mask;
1401
1402 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1403 if (data & 1)
1404 data &= INACTIVE_CUS_MASK;
1405 else
1406 data = 0;
1407 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1408
1409 data >>= INACTIVE_CUS_SHIFT;
1410
1411 mask = si_create_bitmask(cu_per_sh);
1412
1413 return ~data & mask;
1414}
1415
1416static void si_setup_spi(struct radeon_device *rdev,
1417 u32 se_num, u32 sh_per_se,
1418 u32 cu_per_sh)
1419{
1420 int i, j, k;
1421 u32 data, mask, active_cu;
1422
1423 for (i = 0; i < se_num; i++) {
1424 for (j = 0; j < sh_per_se; j++) {
1425 si_select_se_sh(rdev, i, j);
1426 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1427 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1428
1429 mask = 1;
1430 for (k = 0; k < 16; k++) {
1431 mask <<= k;
1432 if (active_cu & mask) {
1433 data &= ~mask;
1434 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1435 break;
1436 }
1437 }
1438 }
1439 }
1440 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1441}
1442
1443static u32 si_get_rb_disabled(struct radeon_device *rdev,
1444 u32 max_rb_num, u32 se_num,
1445 u32 sh_per_se)
1446{
1447 u32 data, mask;
1448
1449 data = RREG32(CC_RB_BACKEND_DISABLE);
1450 if (data & 1)
1451 data &= BACKEND_DISABLE_MASK;
1452 else
1453 data = 0;
1454 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1455
1456 data >>= BACKEND_DISABLE_SHIFT;
1457
1458 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1459
1460 return data & mask;
1461}
1462
1463static void si_setup_rb(struct radeon_device *rdev,
1464 u32 se_num, u32 sh_per_se,
1465 u32 max_rb_num)
1466{
1467 int i, j;
1468 u32 data, mask;
1469 u32 disabled_rbs = 0;
1470 u32 enabled_rbs = 0;
1471
1472 for (i = 0; i < se_num; i++) {
1473 for (j = 0; j < sh_per_se; j++) {
1474 si_select_se_sh(rdev, i, j);
1475 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1476 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1477 }
1478 }
1479 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1480
1481 mask = 1;
1482 for (i = 0; i < max_rb_num; i++) {
1483 if (!(disabled_rbs & mask))
1484 enabled_rbs |= mask;
1485 mask <<= 1;
1486 }
1487
1488 for (i = 0; i < se_num; i++) {
1489 si_select_se_sh(rdev, i, 0xffffffff);
1490 data = 0;
1491 for (j = 0; j < sh_per_se; j++) {
1492 switch (enabled_rbs & 3) {
1493 case 1:
1494 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1495 break;
1496 case 2:
1497 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1498 break;
1499 case 3:
1500 default:
1501 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1502 break;
1503 }
1504 enabled_rbs >>= 2;
1505 }
1506 WREG32(PA_SC_RASTER_CONFIG, data);
1507 }
1508 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1509}
1510
0a96d72b
AD		 1511static void si_gpu_init(struct radeon_device *rdev)
1512{
0a96d72b
AD		 1513 u32 gb_addr_config = 0;
1514 u32 mc_shared_chmap, mc_arb_ramcfg;
0a96d72b 1515 u32 sx_debug_1;
0a96d72b
AD		 1516 u32 hdp_host_path_cntl;
1517 u32 tmp;
1518 int i, j;
1519
1520 switch (rdev->family) {
1521 case CHIP_TAHITI:
1522 rdev->config.si.max_shader_engines = 2;
0a96d72b 1523 rdev->config.si.max_tile_pipes = 12;
1a8ca750
AD		 1524 rdev->config.si.max_cu_per_sh = 8;
1525 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1526 rdev->config.si.max_backends_per_se = 4;
1527 rdev->config.si.max_texture_channel_caches = 12;
1528 rdev->config.si.max_gprs = 256;
1529 rdev->config.si.max_gs_threads = 32;
1530 rdev->config.si.max_hw_contexts = 8;
1531
1532 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1533 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1534 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1535 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1536 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1537 break;
1538 case CHIP_PITCAIRN:
1539 rdev->config.si.max_shader_engines = 2;
0a96d72b 1540 rdev->config.si.max_tile_pipes = 8;
1a8ca750
AD		 1541 rdev->config.si.max_cu_per_sh = 5;
1542 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1543 rdev->config.si.max_backends_per_se = 4;
1544 rdev->config.si.max_texture_channel_caches = 8;
1545 rdev->config.si.max_gprs = 256;
1546 rdev->config.si.max_gs_threads = 32;
1547 rdev->config.si.max_hw_contexts = 8;
1548
1549 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1550 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1551 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1552 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1553 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1554 break;
1555 case CHIP_VERDE:
1556 default:
1557 rdev->config.si.max_shader_engines = 1;
0a96d72b 1558 rdev->config.si.max_tile_pipes = 4;
1a8ca750
AD		 1559 rdev->config.si.max_cu_per_sh = 2;
1560 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1561 rdev->config.si.max_backends_per_se = 4;
1562 rdev->config.si.max_texture_channel_caches = 4;
1563 rdev->config.si.max_gprs = 256;
1564 rdev->config.si.max_gs_threads = 32;
1565 rdev->config.si.max_hw_contexts = 8;
1566
1567 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1568 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1569 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1570 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1571 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1572 break;
1573 }
1574
1575 /* Initialize HDP */
1576 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1577 WREG32((0x2c14 + j), 0x00000000);
1578 WREG32((0x2c18 + j), 0x00000000);
1579 WREG32((0x2c1c + j), 0x00000000);
1580 WREG32((0x2c20 + j), 0x00000000);
1581 WREG32((0x2c24 + j), 0x00000000);
1582 }
1583
1584 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1585
1586 evergreen_fix_pci_max_read_req_size(rdev);
1587
1588 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1589
1590 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1591 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1592
0a96d72b 1593 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
0a96d72b
AD		 1594 rdev->config.si.mem_max_burst_length_bytes = 256;
1595 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1596 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1597 if (rdev->config.si.mem_row_size_in_kb > 4)
1598 rdev->config.si.mem_row_size_in_kb = 4;
1599 /* XXX use MC settings? */
1600 rdev->config.si.shader_engine_tile_size = 32;
1601 rdev->config.si.num_gpus = 1;
1602 rdev->config.si.multi_gpu_tile_size = 64;
1603
1a8ca750
AD		 1604 /* fix up row size */
1605 gb_addr_config &= ~ROW_SIZE_MASK;
0a96d72b
AD		 1606 switch (rdev->config.si.mem_row_size_in_kb) {
1607 case 1:
1608 default:
1609 gb_addr_config |= ROW_SIZE(0);
1610 break;
1611 case 2:
1612 gb_addr_config |= ROW_SIZE(1);
1613 break;
1614 case 4:
1615 gb_addr_config |= ROW_SIZE(2);
1616 break;
1617 }
1618
0a96d72b
AD		 1619 /* setup tiling info dword. gb_addr_config is not adequate since it does
1620 * not have bank info, so create a custom tiling dword.
1621 * bits 3:0 num_pipes
1622 * bits 7:4 num_banks
1623 * bits 11:8 group_size
1624 * bits 15:12 row_size
1625 */
1626 rdev->config.si.tile_config = 0;
1627 switch (rdev->config.si.num_tile_pipes) {
1628 case 1:
1629 rdev->config.si.tile_config |= (0 << 0);
1630 break;
1631 case 2:
1632 rdev->config.si.tile_config |= (1 << 0);
1633 break;
1634 case 4:
1635 rdev->config.si.tile_config |= (2 << 0);
1636 break;
1637 case 8:
1638 default:
1639 /* XXX what about 12? */
1640 rdev->config.si.tile_config |= (3 << 0);
1641 break;
dca571a6
CK		 1642 }
1643 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1644 case 0: /* four banks */
1a8ca750 1645 rdev->config.si.tile_config |= 0 << 4;
dca571a6
CK		 1646 break;
1647 case 1: /* eight banks */
1648 rdev->config.si.tile_config |= 1 << 4;
1649 break;
1650 case 2: /* sixteen banks */
1651 default:
1652 rdev->config.si.tile_config |= 2 << 4;
1653 break;
1654 }
0a96d72b
AD		 1655 rdev->config.si.tile_config |=
1656 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1657 rdev->config.si.tile_config |=
1658 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1659
0a96d72b
AD		 1660 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1661 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1662 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
8c5fd7ef
AD		 1663 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1664 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
0a96d72b 1665
1a8ca750 1666 si_tiling_mode_table_init(rdev);
0a96d72b 1667
1a8ca750
AD		 1668 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1669 rdev->config.si.max_sh_per_se,
1670 rdev->config.si.max_backends_per_se);
0a96d72b 1671
1a8ca750
AD		 1672 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1673 rdev->config.si.max_sh_per_se,
1674 rdev->config.si.max_cu_per_sh);
0a96d72b 1675
0a96d72b
AD		 1676
1677 /* set HW defaults for 3D engine */
1678 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1679 ROQ_IB2_START(0x2b)));
1680 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1681
1682 sx_debug_1 = RREG32(SX_DEBUG_1);
1683 WREG32(SX_DEBUG_1, sx_debug_1);
1684
1685 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1686
1687 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1688 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1689 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1690 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1691
1692 WREG32(VGT_NUM_INSTANCES, 1);
1693
1694 WREG32(CP_PERFMON_CNTL, 0);
1695
1696 WREG32(SQ_CONFIG, 0);
1697
1698 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1699 FORCE_EOV_MAX_REZ_CNT(255)));
1700
1701 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1702 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1703
1704 WREG32(VGT_GS_VERTEX_REUSE, 16);
1705 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1706
1707 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1708 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1709 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1710 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1711 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1712 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1713 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1714 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1715
1716 tmp = RREG32(HDP_MISC_CNTL);
1717 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1718 WREG32(HDP_MISC_CNTL, tmp);
1719
1720 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1721 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1722
1723 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1724
1725 udelay(50);
1726}
c476dde2 1727
2ece2e8b
AD		 1728/*
1729 * GPU scratch registers helpers function.
1730 */
1731static void si_scratch_init(struct radeon_device *rdev)
1732{
1733 int i;
1734
1735 rdev->scratch.num_reg = 7;
1736 rdev->scratch.reg_base = SCRATCH_REG0;
1737 for (i = 0; i < rdev->scratch.num_reg; i++) {
1738 rdev->scratch.free[i] = true;
1739 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1740 }
1741}
1742
1743void si_fence_ring_emit(struct radeon_device *rdev,
1744 struct radeon_fence *fence)
1745{
1746 struct radeon_ring *ring = &rdev->ring[fence->ring];
1747 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1748
1749 /* flush read cache over gart */
1750 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1751 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1752 radeon_ring_write(ring, 0);
1753 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1754 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1755 PACKET3_TC_ACTION_ENA |
1756 PACKET3_SH_KCACHE_ACTION_ENA |
1757 PACKET3_SH_ICACHE_ACTION_ENA);
1758 radeon_ring_write(ring, 0xFFFFFFFF);
1759 radeon_ring_write(ring, 0);
1760 radeon_ring_write(ring, 10); /* poll interval */
1761 /* EVENT_WRITE_EOP - flush caches, send int */
1762 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1763 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1764 radeon_ring_write(ring, addr & 0xffffffff);
1765 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1766 radeon_ring_write(ring, fence->seq);
1767 radeon_ring_write(ring, 0);
1768}
1769
1770/*
1771 * IB stuff
1772 */
1773void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1774{
876dc9f3 1775 struct radeon_ring *ring = &rdev->ring[ib->ring];
2ece2e8b
AD		 1776 u32 header;
1777
a85a7da4
AD		 1778 if (ib->is_const_ib) {
1779 /* set switch buffer packet before const IB */
1780 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1781 radeon_ring_write(ring, 0);
45df6803 1782
2ece2e8b 1783 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
a85a7da4 1784 } else {
89d35807 1785 u32 next_rptr;
a85a7da4 1786 if (ring->rptr_save_reg) {
89d35807 1787 next_rptr = ring->wptr + 3 + 4 + 8;
a85a7da4
AD		 1788 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1789 radeon_ring_write(ring, ((ring->rptr_save_reg -
1790 PACKET3_SET_CONFIG_REG_START) >> 2));
1791 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1792 } else if (rdev->wb.enabled) {
1793 next_rptr = ring->wptr + 5 + 4 + 8;
1794 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1795 radeon_ring_write(ring, (1 << 8));
1796 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1797 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1798 radeon_ring_write(ring, next_rptr);
a85a7da4
AD		 1799 }
1800
2ece2e8b 1801 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
a85a7da4 1802 }
2ece2e8b
AD		 1803
1804 radeon_ring_write(ring, header);
1805 radeon_ring_write(ring,
1806#ifdef __BIG_ENDIAN
1807 (2 << 0) |
1808#endif
1809 (ib->gpu_addr & 0xFFFFFFFC));
1810 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4bf3dd92
CK		 1811 radeon_ring_write(ring, ib->length_dw |
1812 (ib->vm ? (ib->vm->id << 24) : 0));
2ece2e8b 1813
a85a7da4
AD		 1814 if (!ib->is_const_ib) {
1815 /* flush read cache over gart for this vmid */
1816 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1817 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 1818 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
a85a7da4
AD		 1819 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1820 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1821 PACKET3_TC_ACTION_ENA |
1822 PACKET3_SH_KCACHE_ACTION_ENA |
1823 PACKET3_SH_ICACHE_ACTION_ENA);
1824 radeon_ring_write(ring, 0xFFFFFFFF);
1825 radeon_ring_write(ring, 0);
1826 radeon_ring_write(ring, 10); /* poll interval */
1827 }
2ece2e8b
AD		 1828}
1829
48c0c902
AD		 1830/*
1831 * CP.
1832 */
1833static void si_cp_enable(struct radeon_device *rdev, bool enable)
1834{
1835 if (enable)
1836 WREG32(CP_ME_CNTL, 0);
1837 else {
1838 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1839 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1840 WREG32(SCRATCH_UMSK, 0);
8c5fd7ef
AD		 1841 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1842 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1843 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
48c0c902
AD		 1844 }
1845 udelay(50);
1846}
1847
1848static int si_cp_load_microcode(struct radeon_device *rdev)
1849{
1850 const __be32 *fw_data;
1851 int i;
1852
1853 if (!rdev->me_fw || !rdev->pfp_fw)
1854 return -EINVAL;
1855
1856 si_cp_enable(rdev, false);
1857
1858 /* PFP */
1859 fw_data = (const __be32 *)rdev->pfp_fw->data;
1860 WREG32(CP_PFP_UCODE_ADDR, 0);
1861 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1862 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1863 WREG32(CP_PFP_UCODE_ADDR, 0);
1864
1865 /* CE */
1866 fw_data = (const __be32 *)rdev->ce_fw->data;
1867 WREG32(CP_CE_UCODE_ADDR, 0);
1868 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1869 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1870 WREG32(CP_CE_UCODE_ADDR, 0);
1871
1872 /* ME */
1873 fw_data = (const __be32 *)rdev->me_fw->data;
1874 WREG32(CP_ME_RAM_WADDR, 0);
1875 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1876 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1877 WREG32(CP_ME_RAM_WADDR, 0);
1878
1879 WREG32(CP_PFP_UCODE_ADDR, 0);
1880 WREG32(CP_CE_UCODE_ADDR, 0);
1881 WREG32(CP_ME_RAM_WADDR, 0);
1882 WREG32(CP_ME_RAM_RADDR, 0);
1883 return 0;
1884}
1885
1886static int si_cp_start(struct radeon_device *rdev)
1887{
1888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1889 int r, i;
1890
1891 r = radeon_ring_lock(rdev, ring, 7 + 4);
1892 if (r) {
1893 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1894 return r;
1895 }
1896 /* init the CP */
1897 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1898 radeon_ring_write(ring, 0x1);
1899 radeon_ring_write(ring, 0x0);
1900 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1901 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1902 radeon_ring_write(ring, 0);
1903 radeon_ring_write(ring, 0);
1904
1905 /* init the CE partitions */
1906 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1907 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1908 radeon_ring_write(ring, 0xc000);
1909 radeon_ring_write(ring, 0xe000);
1910 radeon_ring_unlock_commit(rdev, ring);
1911
1912 si_cp_enable(rdev, true);
1913
1914 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1915 if (r) {
1916 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1917 return r;
1918 }
1919
1920 /* setup clear context state */
1921 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1922 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1923
1924 for (i = 0; i < si_default_size; i++)
1925 radeon_ring_write(ring, si_default_state[i]);
1926
1927 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1928 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1929
1930 /* set clear context state */
1931 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1932 radeon_ring_write(ring, 0);
1933
1934 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1935 radeon_ring_write(ring, 0x00000316);
1936 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1937 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1938
1939 radeon_ring_unlock_commit(rdev, ring);
1940
1941 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1942 ring = &rdev->ring[i];
1943 r = radeon_ring_lock(rdev, ring, 2);
1944
1945 /* clear the compute context state */
1946 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
1947 radeon_ring_write(ring, 0);
1948
1949 radeon_ring_unlock_commit(rdev, ring);
1950 }
1951
1952 return 0;
1953}
1954
1955static void si_cp_fini(struct radeon_device *rdev)
1956{
45df6803 1957 struct radeon_ring *ring;
48c0c902 1958 si_cp_enable(rdev, false);
45df6803
CK		 1959
1960 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1961 radeon_ring_fini(rdev, ring);
1962 radeon_scratch_free(rdev, ring->rptr_save_reg);
1963
1964 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1965 radeon_ring_fini(rdev, ring);
1966 radeon_scratch_free(rdev, ring->rptr_save_reg);
1967
1968 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1969 radeon_ring_fini(rdev, ring);
1970 radeon_scratch_free(rdev, ring->rptr_save_reg);
48c0c902
AD		 1971}
1972
1973static int si_cp_resume(struct radeon_device *rdev)
1974{
1975 struct radeon_ring *ring;
1976 u32 tmp;
1977 u32 rb_bufsz;
1978 int r;
1979
1980 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1981 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1982 SOFT_RESET_PA |
1983 SOFT_RESET_VGT |
1984 SOFT_RESET_SPI |
1985 SOFT_RESET_SX));
1986 RREG32(GRBM_SOFT_RESET);
1987 mdelay(15);
1988 WREG32(GRBM_SOFT_RESET, 0);
1989 RREG32(GRBM_SOFT_RESET);
1990
1991 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1992 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1993
1994 /* Set the write pointer delay */
1995 WREG32(CP_RB_WPTR_DELAY, 0);
1996
1997 WREG32(CP_DEBUG, 0);
1998 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1999
2000 /* ring 0 - compute and gfx */
2001 /* Set ring buffer size */
2002 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2003 rb_bufsz = drm_order(ring->ring_size / 8);
2004 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2005#ifdef __BIG_ENDIAN
2006 tmp |= BUF_SWAP_32BIT;
2007#endif
2008 WREG32(CP_RB0_CNTL, tmp);
2009
2010 /* Initialize the ring buffer's read and write pointers */
2011 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2012 ring->wptr = 0;
2013 WREG32(CP_RB0_WPTR, ring->wptr);
2014
2015 /* set the wb address wether it's enabled or not */
2016 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2017 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2018
2019 if (rdev->wb.enabled)
2020 WREG32(SCRATCH_UMSK, 0xff);
2021 else {
2022 tmp |= RB_NO_UPDATE;
2023 WREG32(SCRATCH_UMSK, 0);
2024 }
2025
2026 mdelay(1);
2027 WREG32(CP_RB0_CNTL, tmp);
2028
2029 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2030
2031 ring->rptr = RREG32(CP_RB0_RPTR);
2032
2033 /* ring1 - compute only */
2034 /* Set ring buffer size */
2035 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2036 rb_bufsz = drm_order(ring->ring_size / 8);
2037 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2038#ifdef __BIG_ENDIAN
2039 tmp |= BUF_SWAP_32BIT;
2040#endif
2041 WREG32(CP_RB1_CNTL, tmp);
2042
2043 /* Initialize the ring buffer's read and write pointers */
2044 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2045 ring->wptr = 0;
2046 WREG32(CP_RB1_WPTR, ring->wptr);
2047
2048 /* set the wb address wether it's enabled or not */
2049 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2050 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2051
2052 mdelay(1);
2053 WREG32(CP_RB1_CNTL, tmp);
2054
2055 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2056
2057 ring->rptr = RREG32(CP_RB1_RPTR);
2058
2059 /* ring2 - compute only */
2060 /* Set ring buffer size */
2061 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2062 rb_bufsz = drm_order(ring->ring_size / 8);
2063 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2064#ifdef __BIG_ENDIAN
2065 tmp |= BUF_SWAP_32BIT;
2066#endif
2067 WREG32(CP_RB2_CNTL, tmp);
2068
2069 /* Initialize the ring buffer's read and write pointers */
2070 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2071 ring->wptr = 0;
2072 WREG32(CP_RB2_WPTR, ring->wptr);
2073
2074 /* set the wb address wether it's enabled or not */
2075 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2076 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2077
2078 mdelay(1);
2079 WREG32(CP_RB2_CNTL, tmp);
2080
2081 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2082
2083 ring->rptr = RREG32(CP_RB2_RPTR);
2084
2085 /* start the rings */
2086 si_cp_start(rdev);
2087 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2088 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2089 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2090 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2091 if (r) {
2092 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2093 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2094 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2095 return r;
2096 }
2097 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2098 if (r) {
2099 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2100 }
2101 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2102 if (r) {
2103 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2104 }
2105
2106 return 0;
2107}
2108
c476dde2
AD		 2109bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2110{
2111 u32 srbm_status;
2112 u32 grbm_status, grbm_status2;
2113 u32 grbm_status_se0, grbm_status_se1;
c476dde2
AD		 2114
2115 srbm_status = RREG32(SRBM_STATUS);
2116 grbm_status = RREG32(GRBM_STATUS);
2117 grbm_status2 = RREG32(GRBM_STATUS2);
2118 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2119 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2120 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2121 radeon_ring_lockup_update(ring);
c476dde2
AD		 2122 return false;
2123 }
2124 /* force CP activities */
7b9ef16b 2125 radeon_ring_force_activity(rdev, ring);
069211e5 2126 return radeon_ring_test_lockup(rdev, ring);
c476dde2
AD		 2127}
2128
2129static int si_gpu_soft_reset(struct radeon_device *rdev)
2130{
2131 struct evergreen_mc_save save;
2132 u32 grbm_reset = 0;
2133
2134 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2135 return 0;
2136
2137 dev_info(rdev->dev, "GPU softreset \n");
2138 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2139 RREG32(GRBM_STATUS));
2140 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2141 RREG32(GRBM_STATUS2));
2142 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2143 RREG32(GRBM_STATUS_SE0));
2144 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2145 RREG32(GRBM_STATUS_SE1));
2146 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2147 RREG32(SRBM_STATUS));
2148 evergreen_mc_stop(rdev, &save);
2149 if (radeon_mc_wait_for_idle(rdev)) {
2150 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2151 }
2152 /* Disable CP parsing/prefetching */
2153 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2154
2155 /* reset all the gfx blocks */
2156 grbm_reset = (SOFT_RESET_CP |
2157 SOFT_RESET_CB |
2158 SOFT_RESET_DB |
2159 SOFT_RESET_GDS |
2160 SOFT_RESET_PA |
2161 SOFT_RESET_SC |
6f789301 2162 SOFT_RESET_BCI |
c476dde2
AD		 2163 SOFT_RESET_SPI |
2164 SOFT_RESET_SX |
2165 SOFT_RESET_TC |
2166 SOFT_RESET_TA |
2167 SOFT_RESET_VGT |
2168 SOFT_RESET_IA);
2169
2170 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2171 WREG32(GRBM_SOFT_RESET, grbm_reset);
2172 (void)RREG32(GRBM_SOFT_RESET);
2173 udelay(50);
2174 WREG32(GRBM_SOFT_RESET, 0);
2175 (void)RREG32(GRBM_SOFT_RESET);
2176 /* Wait a little for things to settle down */
2177 udelay(50);
2178 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2179 RREG32(GRBM_STATUS));
2180 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2181 RREG32(GRBM_STATUS2));
2182 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2183 RREG32(GRBM_STATUS_SE0));
2184 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2185 RREG32(GRBM_STATUS_SE1));
2186 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2187 RREG32(SRBM_STATUS));
2188 evergreen_mc_resume(rdev, &save);
2189 return 0;
2190}
2191
2192int si_asic_reset(struct radeon_device *rdev)
2193{
2194 return si_gpu_soft_reset(rdev);
2195}
2196
d2800ee5
AD		 2197/* MC */
2198static void si_mc_program(struct radeon_device *rdev)
2199{
2200 struct evergreen_mc_save save;
2201 u32 tmp;
2202 int i, j;
2203
2204 /* Initialize HDP */
2205 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2206 WREG32((0x2c14 + j), 0x00000000);
2207 WREG32((0x2c18 + j), 0x00000000);
2208 WREG32((0x2c1c + j), 0x00000000);
2209 WREG32((0x2c20 + j), 0x00000000);
2210 WREG32((0x2c24 + j), 0x00000000);
2211 }
2212 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2213
2214 evergreen_mc_stop(rdev, &save);
2215 if (radeon_mc_wait_for_idle(rdev)) {
2216 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2217 }
2218 /* Lockout access through VGA aperture*/
2219 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2220 /* Update configuration */
2221 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2222 rdev->mc.vram_start >> 12);
2223 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2224 rdev->mc.vram_end >> 12);
2225 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2226 rdev->vram_scratch.gpu_addr >> 12);
2227 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2228 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2229 WREG32(MC_VM_FB_LOCATION, tmp);
2230 /* XXX double check these! */
2231 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2232 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2233 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2234 WREG32(MC_VM_AGP_BASE, 0);
2235 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2236 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2237 if (radeon_mc_wait_for_idle(rdev)) {
2238 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2239 }
2240 evergreen_mc_resume(rdev, &save);
2241 /* we need to own VRAM, so turn off the VGA renderer here
2242 * to stop it overwriting our objects */
2243 rv515_vga_render_disable(rdev);
2244}
2245
2246/* SI MC address space is 40 bits */
2247static void si_vram_location(struct radeon_device *rdev,
2248 struct radeon_mc *mc, u64 base)
2249{
2250 mc->vram_start = base;
2251 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2252 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2253 mc->real_vram_size = mc->aper_size;
2254 mc->mc_vram_size = mc->aper_size;
2255 }
2256 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2257 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2258 mc->mc_vram_size >> 20, mc->vram_start,
2259 mc->vram_end, mc->real_vram_size >> 20);
2260}
2261
2262static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2263{
2264 u64 size_af, size_bf;
2265
2266 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2267 size_bf = mc->vram_start & ~mc->gtt_base_align;
2268 if (size_bf > size_af) {
2269 if (mc->gtt_size > size_bf) {
2270 dev_warn(rdev->dev, "limiting GTT\n");
2271 mc->gtt_size = size_bf;
2272 }
2273 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2274 } else {
2275 if (mc->gtt_size > size_af) {
2276 dev_warn(rdev->dev, "limiting GTT\n");
2277 mc->gtt_size = size_af;
2278 }
2279 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2280 }
2281 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2282 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2283 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2284}
2285
2286static void si_vram_gtt_location(struct radeon_device *rdev,
2287 struct radeon_mc *mc)
2288{
2289 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2290 /* leave room for at least 1024M GTT */
2291 dev_warn(rdev->dev, "limiting VRAM\n");
2292 mc->real_vram_size = 0xFFC0000000ULL;
2293 mc->mc_vram_size = 0xFFC0000000ULL;
2294 }
2295 si_vram_location(rdev, &rdev->mc, 0);
2296 rdev->mc.gtt_base_align = 0;
2297 si_gtt_location(rdev, mc);
2298}
2299
2300static int si_mc_init(struct radeon_device *rdev)
2301{
2302 u32 tmp;
2303 int chansize, numchan;
2304
2305 /* Get VRAM informations */
2306 rdev->mc.vram_is_ddr = true;
2307 tmp = RREG32(MC_ARB_RAMCFG);
2308 if (tmp & CHANSIZE_OVERRIDE) {
2309 chansize = 16;
2310 } else if (tmp & CHANSIZE_MASK) {
2311 chansize = 64;
2312 } else {
2313 chansize = 32;
2314 }
2315 tmp = RREG32(MC_SHARED_CHMAP);
2316 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2317 case 0:
2318 default:
2319 numchan = 1;
2320 break;
2321 case 1:
2322 numchan = 2;
2323 break;
2324 case 2:
2325 numchan = 4;
2326 break;
2327 case 3:
2328 numchan = 8;
2329 break;
2330 case 4:
2331 numchan = 3;
2332 break;
2333 case 5:
2334 numchan = 6;
2335 break;
2336 case 6:
2337 numchan = 10;
2338 break;
2339 case 7:
2340 numchan = 12;
2341 break;
2342 case 8:
2343 numchan = 16;
2344 break;
2345 }
2346 rdev->mc.vram_width = numchan * chansize;
2347 /* Could aper size report 0 ? */
2348 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2349 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2350 /* size in MB on si */
2351 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2352 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2353 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2354 si_vram_gtt_location(rdev, &rdev->mc);
2355 radeon_update_bandwidth_info(rdev);
2356
2357 return 0;
2358}
2359
2360/*
2361 * GART
2362 */
2363void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2364{
2365 /* flush hdp cache */
2366 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2367
2368 /* bits 0-15 are the VM contexts0-15 */
2369 WREG32(VM_INVALIDATE_REQUEST, 1);
2370}
2371
1109ca09 2372static int si_pcie_gart_enable(struct radeon_device *rdev)
d2800ee5
AD		 2373{
2374 int r, i;
2375
2376 if (rdev->gart.robj == NULL) {
2377 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2378 return -EINVAL;
2379 }
2380 r = radeon_gart_table_vram_pin(rdev);
2381 if (r)
2382 return r;
2383 radeon_gart_restore(rdev);
2384 /* Setup TLB control */
2385 WREG32(MC_VM_MX_L1_TLB_CNTL,
2386 (0xA << 7) |
2387 ENABLE_L1_TLB |
2388 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2389 ENABLE_ADVANCED_DRIVER_MODEL |
2390 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2391 /* Setup L2 cache */
2392 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2393 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2394 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2395 EFFECTIVE_L2_QUEUE_SIZE(7) |
2396 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2397 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2398 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2399 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2400 /* setup context0 */
2401 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2402 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2403 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2404 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2405 (u32)(rdev->dummy_page.addr >> 12));
2406 WREG32(VM_CONTEXT0_CNTL2, 0);
2407 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2408 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2409
2410 WREG32(0x15D4, 0);
2411 WREG32(0x15D8, 0);
2412 WREG32(0x15DC, 0);
2413
2414 /* empty context1-15 */
d2800ee5
AD		 2415 /* set vm size, must be a multiple of 4 */
2416 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
c21b328e 2417 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
23d4f1f2
AD		 2418 /* Assign the pt base to something valid for now; the pts used for
2419 * the VMs are determined by the application and setup and assigned
2420 * on the fly in the vm part of radeon_gart.c
2421 */
d2800ee5
AD		 2422 for (i = 1; i < 16; i++) {
2423 if (i < 8)
2424 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2425 rdev->gart.table_addr >> 12);
2426 else
2427 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2428 rdev->gart.table_addr >> 12);
2429 }
2430
2431 /* enable context1-15 */
2432 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2433 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 2434 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 2435 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 2436 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2437 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2438 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2439 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2440 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2441 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2442 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2443 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2444 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2445 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2446 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2447 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
d2800ee5
AD		 2448
2449 si_pcie_gart_tlb_flush(rdev);
2450 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2451 (unsigned)(rdev->mc.gtt_size >> 20),
2452 (unsigned long long)rdev->gart.table_addr);
2453 rdev->gart.ready = true;
2454 return 0;
2455}
2456
1109ca09 2457static void si_pcie_gart_disable(struct radeon_device *rdev)
d2800ee5
AD		 2458{
2459 /* Disable all tables */
2460 WREG32(VM_CONTEXT0_CNTL, 0);
2461 WREG32(VM_CONTEXT1_CNTL, 0);
2462 /* Setup TLB control */
2463 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2464 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2465 /* Setup L2 cache */
2466 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2467 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2468 EFFECTIVE_L2_QUEUE_SIZE(7) |
2469 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2470 WREG32(VM_L2_CNTL2, 0);
2471 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2472 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2473 radeon_gart_table_vram_unpin(rdev);
2474}
2475
1109ca09 2476static void si_pcie_gart_fini(struct radeon_device *rdev)
d2800ee5
AD		 2477{
2478 si_pcie_gart_disable(rdev);
2479 radeon_gart_table_vram_free(rdev);
2480 radeon_gart_fini(rdev);
2481}
2482
498dd8b3
AD		 2483/* vm parser */
2484static bool si_vm_reg_valid(u32 reg)
2485{
2486 /* context regs are fine */
2487 if (reg >= 0x28000)
2488 return true;
2489
2490 /* check config regs */
2491 switch (reg) {
2492 case GRBM_GFX_INDEX:
f418b88a 2493 case CP_STRMOUT_CNTL:
498dd8b3
AD		 2494 case VGT_VTX_VECT_EJECT_REG:
2495 case VGT_CACHE_INVALIDATION:
2496 case VGT_ESGS_RING_SIZE:
2497 case VGT_GSVS_RING_SIZE:
2498 case VGT_GS_VERTEX_REUSE:
2499 case VGT_PRIMITIVE_TYPE:
2500 case VGT_INDEX_TYPE:
2501 case VGT_NUM_INDICES:
2502 case VGT_NUM_INSTANCES:
2503 case VGT_TF_RING_SIZE:
2504 case VGT_HS_OFFCHIP_PARAM:
2505 case VGT_TF_MEMORY_BASE:
2506 case PA_CL_ENHANCE:
2507 case PA_SU_LINE_STIPPLE_VALUE:
2508 case PA_SC_LINE_STIPPLE_STATE:
2509 case PA_SC_ENHANCE:
2510 case SQC_CACHES:
2511 case SPI_STATIC_THREAD_MGMT_1:
2512 case SPI_STATIC_THREAD_MGMT_2:
2513 case SPI_STATIC_THREAD_MGMT_3:
2514 case SPI_PS_MAX_WAVE_ID:
2515 case SPI_CONFIG_CNTL:
2516 case SPI_CONFIG_CNTL_1:
2517 case TA_CNTL_AUX:
2518 return true;
2519 default:
2520 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2521 return false;
2522 }
2523}
2524
2525static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2526 u32 *ib, struct radeon_cs_packet *pkt)
2527{
2528 switch (pkt->opcode) {
2529 case PACKET3_NOP:
2530 case PACKET3_SET_BASE:
2531 case PACKET3_SET_CE_DE_COUNTERS:
2532 case PACKET3_LOAD_CONST_RAM:
2533 case PACKET3_WRITE_CONST_RAM:
2534 case PACKET3_WRITE_CONST_RAM_OFFSET:
2535 case PACKET3_DUMP_CONST_RAM:
2536 case PACKET3_INCREMENT_CE_COUNTER:
2537 case PACKET3_WAIT_ON_DE_COUNTER:
2538 case PACKET3_CE_WRITE:
2539 break;
2540 default:
2541 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2542 return -EINVAL;
2543 }
2544 return 0;
2545}
2546
2547static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2548 u32 *ib, struct radeon_cs_packet *pkt)
2549{
2550 u32 idx = pkt->idx + 1;
2551 u32 idx_value = ib[idx];
2552 u32 start_reg, end_reg, reg, i;
2553
2554 switch (pkt->opcode) {
2555 case PACKET3_NOP:
2556 case PACKET3_SET_BASE:
2557 case PACKET3_CLEAR_STATE:
2558 case PACKET3_INDEX_BUFFER_SIZE:
2559 case PACKET3_DISPATCH_DIRECT:
2560 case PACKET3_DISPATCH_INDIRECT:
2561 case PACKET3_ALLOC_GDS:
2562 case PACKET3_WRITE_GDS_RAM:
2563 case PACKET3_ATOMIC_GDS:
2564 case PACKET3_ATOMIC:
2565 case PACKET3_OCCLUSION_QUERY:
2566 case PACKET3_SET_PREDICATION:
2567 case PACKET3_COND_EXEC:
2568 case PACKET3_PRED_EXEC:
2569 case PACKET3_DRAW_INDIRECT:
2570 case PACKET3_DRAW_INDEX_INDIRECT:
2571 case PACKET3_INDEX_BASE:
2572 case PACKET3_DRAW_INDEX_2:
2573 case PACKET3_CONTEXT_CONTROL:
2574 case PACKET3_INDEX_TYPE:
2575 case PACKET3_DRAW_INDIRECT_MULTI:
2576 case PACKET3_DRAW_INDEX_AUTO:
2577 case PACKET3_DRAW_INDEX_IMMD:
2578 case PACKET3_NUM_INSTANCES:
2579 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2580 case PACKET3_STRMOUT_BUFFER_UPDATE:
2581 case PACKET3_DRAW_INDEX_OFFSET_2:
2582 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2583 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2584 case PACKET3_MPEG_INDEX:
2585 case PACKET3_WAIT_REG_MEM:
2586 case PACKET3_MEM_WRITE:
2587 case PACKET3_PFP_SYNC_ME:
2588 case PACKET3_SURFACE_SYNC:
2589 case PACKET3_EVENT_WRITE:
2590 case PACKET3_EVENT_WRITE_EOP:
2591 case PACKET3_EVENT_WRITE_EOS:
2592 case PACKET3_SET_CONTEXT_REG:
2593 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2594 case PACKET3_SET_SH_REG:
2595 case PACKET3_SET_SH_REG_OFFSET:
2596 case PACKET3_INCREMENT_DE_COUNTER:
2597 case PACKET3_WAIT_ON_CE_COUNTER:
2598 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2599 case PACKET3_ME_WRITE:
2600 break;
2601 case PACKET3_COPY_DATA:
2602 if ((idx_value & 0xf00) == 0) {
2603 reg = ib[idx + 3] * 4;
2604 if (!si_vm_reg_valid(reg))
2605 return -EINVAL;
2606 }
2607 break;
2608 case PACKET3_WRITE_DATA:
2609 if ((idx_value & 0xf00) == 0) {
2610 start_reg = ib[idx + 1] * 4;
2611 if (idx_value & 0x10000) {
2612 if (!si_vm_reg_valid(start_reg))
2613 return -EINVAL;
2614 } else {
2615 for (i = 0; i < (pkt->count - 2); i++) {
2616 reg = start_reg + (4 * i);
2617 if (!si_vm_reg_valid(reg))
2618 return -EINVAL;
2619 }
2620 }
2621 }
2622 break;
2623 case PACKET3_COND_WRITE:
2624 if (idx_value & 0x100) {
2625 reg = ib[idx + 5] * 4;
2626 if (!si_vm_reg_valid(reg))
2627 return -EINVAL;
2628 }
2629 break;
2630 case PACKET3_COPY_DW:
2631 if (idx_value & 0x2) {
2632 reg = ib[idx + 3] * 4;
2633 if (!si_vm_reg_valid(reg))
2634 return -EINVAL;
2635 }
2636 break;
2637 case PACKET3_SET_CONFIG_REG:
2638 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2639 end_reg = 4 * pkt->count + start_reg - 4;
2640 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2641 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2642 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2643 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2644 return -EINVAL;
2645 }
2646 for (i = 0; i < pkt->count; i++) {
2647 reg = start_reg + (4 * i);
2648 if (!si_vm_reg_valid(reg))
2649 return -EINVAL;
2650 }
2651 break;
2652 default:
2653 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2654 return -EINVAL;
2655 }
2656 return 0;
2657}
2658
2659static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2660 u32 *ib, struct radeon_cs_packet *pkt)
2661{
2662 u32 idx = pkt->idx + 1;
2663 u32 idx_value = ib[idx];
2664 u32 start_reg, reg, i;
2665
2666 switch (pkt->opcode) {
2667 case PACKET3_NOP:
2668 case PACKET3_SET_BASE:
2669 case PACKET3_CLEAR_STATE:
2670 case PACKET3_DISPATCH_DIRECT:
2671 case PACKET3_DISPATCH_INDIRECT:
2672 case PACKET3_ALLOC_GDS:
2673 case PACKET3_WRITE_GDS_RAM:
2674 case PACKET3_ATOMIC_GDS:
2675 case PACKET3_ATOMIC:
2676 case PACKET3_OCCLUSION_QUERY:
2677 case PACKET3_SET_PREDICATION:
2678 case PACKET3_COND_EXEC:
2679 case PACKET3_PRED_EXEC:
2680 case PACKET3_CONTEXT_CONTROL:
2681 case PACKET3_STRMOUT_BUFFER_UPDATE:
2682 case PACKET3_WAIT_REG_MEM:
2683 case PACKET3_MEM_WRITE:
2684 case PACKET3_PFP_SYNC_ME:
2685 case PACKET3_SURFACE_SYNC:
2686 case PACKET3_EVENT_WRITE:
2687 case PACKET3_EVENT_WRITE_EOP:
2688 case PACKET3_EVENT_WRITE_EOS:
2689 case PACKET3_SET_CONTEXT_REG:
2690 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2691 case PACKET3_SET_SH_REG:
2692 case PACKET3_SET_SH_REG_OFFSET:
2693 case PACKET3_INCREMENT_DE_COUNTER:
2694 case PACKET3_WAIT_ON_CE_COUNTER:
2695 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2696 case PACKET3_ME_WRITE:
2697 break;
2698 case PACKET3_COPY_DATA:
2699 if ((idx_value & 0xf00) == 0) {
2700 reg = ib[idx + 3] * 4;
2701 if (!si_vm_reg_valid(reg))
2702 return -EINVAL;
2703 }
2704 break;
2705 case PACKET3_WRITE_DATA:
2706 if ((idx_value & 0xf00) == 0) {
2707 start_reg = ib[idx + 1] * 4;
2708 if (idx_value & 0x10000) {
2709 if (!si_vm_reg_valid(start_reg))
2710 return -EINVAL;
2711 } else {
2712 for (i = 0; i < (pkt->count - 2); i++) {
2713 reg = start_reg + (4 * i);
2714 if (!si_vm_reg_valid(reg))
2715 return -EINVAL;
2716 }
2717 }
2718 }
2719 break;
2720 case PACKET3_COND_WRITE:
2721 if (idx_value & 0x100) {
2722 reg = ib[idx + 5] * 4;
2723 if (!si_vm_reg_valid(reg))
2724 return -EINVAL;
2725 }
2726 break;
2727 case PACKET3_COPY_DW:
2728 if (idx_value & 0x2) {
2729 reg = ib[idx + 3] * 4;
2730 if (!si_vm_reg_valid(reg))
2731 return -EINVAL;
2732 }
2733 break;
2734 default:
2735 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2736 return -EINVAL;
2737 }
2738 return 0;
2739}
2740
2741int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2742{
2743 int ret = 0;
2744 u32 idx = 0;
2745 struct radeon_cs_packet pkt;
2746
2747 do {
2748 pkt.idx = idx;
2749 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2750 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2751 pkt.one_reg_wr = 0;
2752 switch (pkt.type) {
2753 case PACKET_TYPE0:
2754 dev_err(rdev->dev, "Packet0 not allowed!\n");
2755 ret = -EINVAL;
2756 break;
2757 case PACKET_TYPE2:
2758 idx += 1;
2759 break;
2760 case PACKET_TYPE3:
2761 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2762 if (ib->is_const_ib)
2763 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2764 else {
876dc9f3 2765 switch (ib->ring) {
498dd8b3
AD		 2766 case RADEON_RING_TYPE_GFX_INDEX:
2767 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2768 break;
2769 case CAYMAN_RING_TYPE_CP1_INDEX:
2770 case CAYMAN_RING_TYPE_CP2_INDEX:
2771 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2772 break;
2773 default:
876dc9f3 2774 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
498dd8b3
AD		 2775 ret = -EINVAL;
2776 break;
2777 }
2778 }
2779 idx += pkt.count + 2;
2780 break;
2781 default:
2782 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2783 ret = -EINVAL;
2784 break;
2785 }
2786 if (ret)
2787 break;
2788 } while (idx < ib->length_dw);
2789
2790 return ret;
2791}
2792
d2800ee5
AD		 2793/*
2794 * vm
2795 */
2796int si_vm_init(struct radeon_device *rdev)
2797{
2798 /* number of VMs */
2799 rdev->vm_manager.nvm = 16;
2800 /* base offset of vram pages */
2801 rdev->vm_manager.vram_base_offset = 0;
2802
2803 return 0;
2804}
2805
2806void si_vm_fini(struct radeon_device *rdev)
2807{
2808}
2809
82ffd92b
AD		 2810/**
2811 * si_vm_set_page - update the page tables using the CP
2812 *
2813 * @rdev: radeon_device pointer
2814 * @pe: addr of the page entry
2815 * @addr: dst addr to write into pe
2816 * @count: number of page entries to update
2817 * @incr: increase next addr by incr bytes
2818 * @flags: access flags
2819 *
2820 * Update the page tables using the CP (cayman-si).
2821 */
2822void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2823 uint64_t addr, unsigned count,
2824 uint32_t incr, uint32_t flags)
d2800ee5 2825{
82ffd92b
AD		 2826 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
2827 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
deab48f1
AD		 2828 uint64_t value;
2829 unsigned ndw;
2830
2831 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2832 while (count) {
2833 ndw = 2 + count * 2;
2834 if (ndw > 0x3FFE)
2835 ndw = 0x3FFE;
2836
2837 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
2838 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2839 WRITE_DATA_DST_SEL(1)));
2840 radeon_ring_write(ring, pe);
2841 radeon_ring_write(ring, upper_32_bits(pe));
2842 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
2843 if (flags & RADEON_VM_PAGE_SYSTEM) {
2844 value = radeon_vm_map_gart(rdev, addr);
2845 value &= 0xFFFFFFFFFFFFF000ULL;
2846 } else if (flags & RADEON_VM_PAGE_VALID) {
2847 value = addr;
2848 } else {
2849 value = 0;
2850 }
2851 addr += incr;
2852 value |= r600_flags;
2853 radeon_ring_write(ring, value);
2854 radeon_ring_write(ring, upper_32_bits(value));
2855 }
2856 }
2857 } else {
2858 /* DMA */
2859 if (flags & RADEON_VM_PAGE_SYSTEM) {
2860 while (count) {
2861 ndw = count * 2;
2862 if (ndw > 0xFFFFE)
2863 ndw = 0xFFFFE;
2864
2865 /* for non-physically contiguous pages (system) */
2866 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw));
2867 radeon_ring_write(ring, pe);
2868 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
2869 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2870 if (flags & RADEON_VM_PAGE_SYSTEM) {
2871 value = radeon_vm_map_gart(rdev, addr);
2872 value &= 0xFFFFFFFFFFFFF000ULL;
2873 } else if (flags & RADEON_VM_PAGE_VALID) {
2874 value = addr;
2875 } else {
2876 value = 0;
2877 }
2878 addr += incr;
2879 value |= r600_flags;
2880 radeon_ring_write(ring, value);
2881 radeon_ring_write(ring, upper_32_bits(value));
2882 }
2883 }
2884 } else {
2885 while (count) {
2886 ndw = count * 2;
2887 if (ndw > 0xFFFFE)
2888 ndw = 0xFFFFE;
2889
2890 if (flags & RADEON_VM_PAGE_VALID)
2891 value = addr;
2892 else
2893 value = 0;
2894 /* for physically contiguous pages (vram) */
2895 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw));
2896 radeon_ring_write(ring, pe); /* dst addr */
2897 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
2898 radeon_ring_write(ring, r600_flags); /* mask */
2899 radeon_ring_write(ring, 0);
2900 radeon_ring_write(ring, value); /* value */
2901 radeon_ring_write(ring, upper_32_bits(value));
2902 radeon_ring_write(ring, incr); /* increment size */
2903 radeon_ring_write(ring, 0);
2904 pe += ndw * 4;
2905 addr += (ndw / 2) * incr;
2906 count -= ndw / 2;
2907 }
d7025d89 2908 }
82ffd92b 2909 }
d2800ee5
AD		 2910}
2911
498522b4 2912void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
d2800ee5 2913{
498522b4 2914 struct radeon_ring *ring = &rdev->ring[ridx];
d2800ee5 2915
ee60e29f 2916 if (vm == NULL)
d2800ee5
AD		 2917 return;
2918
76c44f2c
AD		 2919 /* write new base address */
2920 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2921 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2922 WRITE_DATA_DST_SEL(0)));
2923
ee60e29f 2924 if (vm->id < 8) {
76c44f2c
AD		 2925 radeon_ring_write(ring,
2926 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
ee60e29f 2927 } else {
76c44f2c
AD		 2928 radeon_ring_write(ring,
2929 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
ee60e29f 2930 }
76c44f2c 2931 radeon_ring_write(ring, 0);
fa87e62d 2932 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 2933
d2800ee5 2934 /* flush hdp cache */
76c44f2c
AD		 2935 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2936 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2937 WRITE_DATA_DST_SEL(0)));
2938 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
2939 radeon_ring_write(ring, 0);
ee60e29f
CK		 2940 radeon_ring_write(ring, 0x1);
2941
d2800ee5 2942 /* bits 0-15 are the VM contexts0-15 */
76c44f2c
AD		 2943 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2944 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2945 WRITE_DATA_DST_SEL(0)));
2946 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2947 radeon_ring_write(ring, 0);
498522b4 2948 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 2949
2950 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2951 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2952 radeon_ring_write(ring, 0x0);
d2800ee5
AD		 2953}
2954
8c5fd7ef
AD		 2955void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2956{
2957 struct radeon_ring *ring = &rdev->ring[ridx];
2958
2959 if (vm == NULL)
2960 return;
2961
2962 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
2963 if (vm->id < 8) {
2964 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2965 } else {
2966 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
2967 }
2968 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2969
2970 /* flush hdp cache */
2971 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
2972 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2973 radeon_ring_write(ring, 1);
2974
2975 /* bits 0-7 are the VM contexts0-7 */
2976 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
2977 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2978 radeon_ring_write(ring, 1 << vm->id);
2979}
2980
347e7592
AD		 2981/*
2982 * RLC
2983 */
c420c745 2984void si_rlc_fini(struct radeon_device *rdev)
347e7592
AD		 2985{
2986 int r;
2987
2988 /* save restore block */
2989 if (rdev->rlc.save_restore_obj) {
2990 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2991 if (unlikely(r != 0))
2992 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
2993 radeon_bo_unpin(rdev->rlc.save_restore_obj);
2994 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2995
2996 radeon_bo_unref(&rdev->rlc.save_restore_obj);
2997 rdev->rlc.save_restore_obj = NULL;
2998 }
2999
3000 /* clear state block */
3001 if (rdev->rlc.clear_state_obj) {
3002 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3003 if (unlikely(r != 0))
3004 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3005 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3006 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3007
3008 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3009 rdev->rlc.clear_state_obj = NULL;
3010 }
3011}
3012
c420c745 3013int si_rlc_init(struct radeon_device *rdev)
347e7592
AD		 3014{
3015 int r;
3016
3017 /* save restore block */
3018 if (rdev->rlc.save_restore_obj == NULL) {
3019 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3020 RADEON_GEM_DOMAIN_VRAM, NULL,
3021 &rdev->rlc.save_restore_obj);
347e7592
AD		 3022 if (r) {
3023 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3024 return r;
3025 }
3026 }
3027
3028 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3029 if (unlikely(r != 0)) {
3030 si_rlc_fini(rdev);
3031 return r;
3032 }
3033 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3034 &rdev->rlc.save_restore_gpu_addr);
5273db70 3035 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
347e7592 3036 if (r) {
347e7592
AD		 3037 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3038 si_rlc_fini(rdev);
3039 return r;
3040 }
3041
3042 /* clear state block */
3043 if (rdev->rlc.clear_state_obj == NULL) {
3044 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3045 RADEON_GEM_DOMAIN_VRAM, NULL,
3046 &rdev->rlc.clear_state_obj);
347e7592
AD		 3047 if (r) {
3048 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3049 si_rlc_fini(rdev);
3050 return r;
3051 }
3052 }
3053 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3054 if (unlikely(r != 0)) {
3055 si_rlc_fini(rdev);
3056 return r;
3057 }
3058 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3059 &rdev->rlc.clear_state_gpu_addr);
5273db70 3060 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
347e7592 3061 if (r) {
347e7592
AD		 3062 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3063 si_rlc_fini(rdev);
3064 return r;
3065 }
3066
3067 return 0;
3068}
3069
3070static void si_rlc_stop(struct radeon_device *rdev)
3071{
3072 WREG32(RLC_CNTL, 0);
3073}
3074
3075static void si_rlc_start(struct radeon_device *rdev)
3076{
3077 WREG32(RLC_CNTL, RLC_ENABLE);
3078}
3079
3080static int si_rlc_resume(struct radeon_device *rdev)
3081{
3082 u32 i;
3083 const __be32 *fw_data;
3084
3085 if (!rdev->rlc_fw)
3086 return -EINVAL;
3087
3088 si_rlc_stop(rdev);
3089
3090 WREG32(RLC_RL_BASE, 0);
3091 WREG32(RLC_RL_SIZE, 0);
3092 WREG32(RLC_LB_CNTL, 0);
3093 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3094 WREG32(RLC_LB_CNTR_INIT, 0);
3095
3096 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3097 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3098
3099 WREG32(RLC_MC_CNTL, 0);
3100 WREG32(RLC_UCODE_CNTL, 0);
3101
3102 fw_data = (const __be32 *)rdev->rlc_fw->data;
3103 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3104 WREG32(RLC_UCODE_ADDR, i);
3105 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3106 }
3107 WREG32(RLC_UCODE_ADDR, 0);
3108
3109 si_rlc_start(rdev);
3110
3111 return 0;
3112}
3113
25a857fb
AD		 3114static void si_enable_interrupts(struct radeon_device *rdev)
3115{
3116 u32 ih_cntl = RREG32(IH_CNTL);
3117 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3118
3119 ih_cntl |= ENABLE_INTR;
3120 ih_rb_cntl |= IH_RB_ENABLE;
3121 WREG32(IH_CNTL, ih_cntl);
3122 WREG32(IH_RB_CNTL, ih_rb_cntl);
3123 rdev->ih.enabled = true;
3124}
3125
3126static void si_disable_interrupts(struct radeon_device *rdev)
3127{
3128 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3129 u32 ih_cntl = RREG32(IH_CNTL);
3130
3131 ih_rb_cntl &= ~IH_RB_ENABLE;
3132 ih_cntl &= ~ENABLE_INTR;
3133 WREG32(IH_RB_CNTL, ih_rb_cntl);
3134 WREG32(IH_CNTL, ih_cntl);
3135 /* set rptr, wptr to 0 */
3136 WREG32(IH_RB_RPTR, 0);
3137 WREG32(IH_RB_WPTR, 0);
3138 rdev->ih.enabled = false;
25a857fb
AD		 3139 rdev->ih.rptr = 0;
3140}
3141
3142static void si_disable_interrupt_state(struct radeon_device *rdev)
3143{
3144 u32 tmp;
3145
3146 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3147 WREG32(CP_INT_CNTL_RING1, 0);
3148 WREG32(CP_INT_CNTL_RING2, 0);
8c5fd7ef
AD		 3149 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3150 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3151 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3152 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
25a857fb
AD		 3153 WREG32(GRBM_INT_CNTL, 0);
3154 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3155 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3156 if (rdev->num_crtc >= 4) {
3157 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3158 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3159 }
3160 if (rdev->num_crtc >= 6) {
3161 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3162 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3163 }
3164
3165 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3166 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3167 if (rdev->num_crtc >= 4) {
3168 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3169 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3170 }
3171 if (rdev->num_crtc >= 6) {
3172 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3173 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3174 }
3175
3176 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3177
3178 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3179 WREG32(DC_HPD1_INT_CONTROL, tmp);
3180 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3181 WREG32(DC_HPD2_INT_CONTROL, tmp);
3182 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3183 WREG32(DC_HPD3_INT_CONTROL, tmp);
3184 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3185 WREG32(DC_HPD4_INT_CONTROL, tmp);
3186 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3187 WREG32(DC_HPD5_INT_CONTROL, tmp);
3188 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3189 WREG32(DC_HPD6_INT_CONTROL, tmp);
3190
3191}
3192
3193static int si_irq_init(struct radeon_device *rdev)
3194{
3195 int ret = 0;
3196 int rb_bufsz;
3197 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3198
3199 /* allocate ring */
3200 ret = r600_ih_ring_alloc(rdev);
3201 if (ret)
3202 return ret;
3203
3204 /* disable irqs */
3205 si_disable_interrupts(rdev);
3206
3207 /* init rlc */
3208 ret = si_rlc_resume(rdev);
3209 if (ret) {
3210 r600_ih_ring_fini(rdev);
3211 return ret;
3212 }
3213
3214 /* setup interrupt control */
3215 /* set dummy read address to ring address */
3216 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3217 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3218 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3219 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3220 */
3221 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3222 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3223 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3224 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3225
3226 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3227 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3228
3229 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3230 IH_WPTR_OVERFLOW_CLEAR |
3231 (rb_bufsz << 1));
3232
3233 if (rdev->wb.enabled)
3234 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3235
3236 /* set the writeback address whether it's enabled or not */
3237 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3238 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3239
3240 WREG32(IH_RB_CNTL, ih_rb_cntl);
3241
3242 /* set rptr, wptr to 0 */
3243 WREG32(IH_RB_RPTR, 0);
3244 WREG32(IH_RB_WPTR, 0);
3245
3246 /* Default settings for IH_CNTL (disabled at first) */
3247 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3248 /* RPTR_REARM only works if msi's are enabled */
3249 if (rdev->msi_enabled)
3250 ih_cntl |= RPTR_REARM;
3251 WREG32(IH_CNTL, ih_cntl);
3252
3253 /* force the active interrupt state to all disabled */
3254 si_disable_interrupt_state(rdev);
3255
2099810f
DA		 3256 pci_set_master(rdev->pdev);
3257
25a857fb
AD		 3258 /* enable irqs */
3259 si_enable_interrupts(rdev);
3260
3261 return ret;
3262}
3263
3264int si_irq_set(struct radeon_device *rdev)
3265{
3266 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3267 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3268 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3269 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3270 u32 grbm_int_cntl = 0;
3271 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
8c5fd7ef 3272 u32 dma_cntl, dma_cntl1;
25a857fb
AD		 3273
3274 if (!rdev->irq.installed) {
3275 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3276 return -EINVAL;
3277 }
3278 /* don't enable anything if the ih is disabled */
3279 if (!rdev->ih.enabled) {
3280 si_disable_interrupts(rdev);
3281 /* force the active interrupt state to all disabled */
3282 si_disable_interrupt_state(rdev);
3283 return 0;
3284 }
3285
3286 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3287 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3288 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3289 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3290 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3291 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3292
8c5fd7ef
AD		 3293 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3294 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3295
25a857fb 3296 /* enable CP interrupts on all rings */
736fc37f 3297 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
25a857fb
AD		 3298 DRM_DEBUG("si_irq_set: sw int gfx\n");
3299 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3300 }
736fc37f 3301 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
25a857fb
AD		 3302 DRM_DEBUG("si_irq_set: sw int cp1\n");
3303 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3304 }
736fc37f 3305 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
25a857fb
AD		 3306 DRM_DEBUG("si_irq_set: sw int cp2\n");
3307 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3308 }
8c5fd7ef
AD		 3309 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3310 DRM_DEBUG("si_irq_set: sw int dma\n");
3311 dma_cntl |= TRAP_ENABLE;
3312 }
3313
3314 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3315 DRM_DEBUG("si_irq_set: sw int dma1\n");
3316 dma_cntl1 |= TRAP_ENABLE;
3317 }
25a857fb 3318 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3319 atomic_read(&rdev->irq.pflip[0])) {
25a857fb
AD		 3320 DRM_DEBUG("si_irq_set: vblank 0\n");
3321 crtc1 |= VBLANK_INT_MASK;
3322 }
3323 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3324 atomic_read(&rdev->irq.pflip[1])) {
25a857fb
AD		 3325 DRM_DEBUG("si_irq_set: vblank 1\n");
3326 crtc2 |= VBLANK_INT_MASK;
3327 }
3328 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3329 atomic_read(&rdev->irq.pflip[2])) {
25a857fb
AD		 3330 DRM_DEBUG("si_irq_set: vblank 2\n");
3331 crtc3 |= VBLANK_INT_MASK;
3332 }
3333 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3334 atomic_read(&rdev->irq.pflip[3])) {
25a857fb
AD		 3335 DRM_DEBUG("si_irq_set: vblank 3\n");
3336 crtc4 |= VBLANK_INT_MASK;
3337 }
3338 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3339 atomic_read(&rdev->irq.pflip[4])) {
25a857fb
AD		 3340 DRM_DEBUG("si_irq_set: vblank 4\n");
3341 crtc5 |= VBLANK_INT_MASK;
3342 }
3343 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3344 atomic_read(&rdev->irq.pflip[5])) {
25a857fb
AD		 3345 DRM_DEBUG("si_irq_set: vblank 5\n");
3346 crtc6 |= VBLANK_INT_MASK;
3347 }
3348 if (rdev->irq.hpd[0]) {
3349 DRM_DEBUG("si_irq_set: hpd 1\n");
3350 hpd1 |= DC_HPDx_INT_EN;
3351 }
3352 if (rdev->irq.hpd[1]) {
3353 DRM_DEBUG("si_irq_set: hpd 2\n");
3354 hpd2 |= DC_HPDx_INT_EN;
3355 }
3356 if (rdev->irq.hpd[2]) {
3357 DRM_DEBUG("si_irq_set: hpd 3\n");
3358 hpd3 |= DC_HPDx_INT_EN;
3359 }
3360 if (rdev->irq.hpd[3]) {
3361 DRM_DEBUG("si_irq_set: hpd 4\n");
3362 hpd4 |= DC_HPDx_INT_EN;
3363 }
3364 if (rdev->irq.hpd[4]) {
3365 DRM_DEBUG("si_irq_set: hpd 5\n");
3366 hpd5 |= DC_HPDx_INT_EN;
3367 }
3368 if (rdev->irq.hpd[5]) {
3369 DRM_DEBUG("si_irq_set: hpd 6\n");
3370 hpd6 |= DC_HPDx_INT_EN;
3371 }
25a857fb
AD		 3372
3373 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3374 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3375 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3376
8c5fd7ef
AD		 3377 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3378 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3379
25a857fb
AD		 3380 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3381
3382 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3383 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3384 if (rdev->num_crtc >= 4) {
3385 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3386 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3387 }
3388 if (rdev->num_crtc >= 6) {
3389 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3390 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3391 }
3392
3393 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3394 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3395 if (rdev->num_crtc >= 4) {
3396 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3397 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3398 }
3399 if (rdev->num_crtc >= 6) {
3400 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3401 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3402 }
3403
3404 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3405 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3406 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3407 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3408 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3409 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3410
3411 return 0;
3412}
3413
3414static inline void si_irq_ack(struct radeon_device *rdev)
3415{
3416 u32 tmp;
3417
3418 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3419 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3420 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3421 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3422 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3423 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3424 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3425 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3426 if (rdev->num_crtc >= 4) {
3427 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3428 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3429 }
3430 if (rdev->num_crtc >= 6) {
3431 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3432 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3433 }
3434
3435 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3436 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3437 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3438 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3439 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3440 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3441 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3442 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3443 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3444 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3445 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3446 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3447
3448 if (rdev->num_crtc >= 4) {
3449 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3450 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3451 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3452 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3453 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3454 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3455 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3456 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3457 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3458 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3459 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3460 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3461 }
3462
3463 if (rdev->num_crtc >= 6) {
3464 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3465 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3466 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3467 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3468 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3469 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3470 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3471 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3472 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3473 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3474 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3475 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3476 }
3477
3478 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3479 tmp = RREG32(DC_HPD1_INT_CONTROL);
3480 tmp |= DC_HPDx_INT_ACK;
3481 WREG32(DC_HPD1_INT_CONTROL, tmp);
3482 }
3483 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3484 tmp = RREG32(DC_HPD2_INT_CONTROL);
3485 tmp |= DC_HPDx_INT_ACK;
3486 WREG32(DC_HPD2_INT_CONTROL, tmp);
3487 }
3488 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3489 tmp = RREG32(DC_HPD3_INT_CONTROL);
3490 tmp |= DC_HPDx_INT_ACK;
3491 WREG32(DC_HPD3_INT_CONTROL, tmp);
3492 }
3493 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3494 tmp = RREG32(DC_HPD4_INT_CONTROL);
3495 tmp |= DC_HPDx_INT_ACK;
3496 WREG32(DC_HPD4_INT_CONTROL, tmp);
3497 }
3498 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3499 tmp = RREG32(DC_HPD5_INT_CONTROL);
3500 tmp |= DC_HPDx_INT_ACK;
3501 WREG32(DC_HPD5_INT_CONTROL, tmp);
3502 }
3503 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3504 tmp = RREG32(DC_HPD5_INT_CONTROL);
3505 tmp |= DC_HPDx_INT_ACK;
3506 WREG32(DC_HPD6_INT_CONTROL, tmp);
3507 }
3508}
3509
3510static void si_irq_disable(struct radeon_device *rdev)
3511{
3512 si_disable_interrupts(rdev);
3513 /* Wait and acknowledge irq */
3514 mdelay(1);
3515 si_irq_ack(rdev);
3516 si_disable_interrupt_state(rdev);
3517}
3518
3519static void si_irq_suspend(struct radeon_device *rdev)
3520{
3521 si_irq_disable(rdev);
3522 si_rlc_stop(rdev);
3523}
3524
9b136d51
AD		 3525static void si_irq_fini(struct radeon_device *rdev)
3526{
3527 si_irq_suspend(rdev);
3528 r600_ih_ring_fini(rdev);
3529}
3530
25a857fb
AD		 3531static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3532{
3533 u32 wptr, tmp;
3534
3535 if (rdev->wb.enabled)
3536 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3537 else
3538 wptr = RREG32(IH_RB_WPTR);
3539
3540 if (wptr & RB_OVERFLOW) {
3541 /* When a ring buffer overflow happen start parsing interrupt
3542 * from the last not overwritten vector (wptr + 16). Hopefully
3543 * this should allow us to catchup.
3544 */
3545 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3546 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3547 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3548 tmp = RREG32(IH_RB_CNTL);
3549 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3550 WREG32(IH_RB_CNTL, tmp);
3551 }
3552 return (wptr & rdev->ih.ptr_mask);
3553}
3554
3555/* SI IV Ring
3556 * Each IV ring entry is 128 bits:
3557 * [7:0] - interrupt source id
3558 * [31:8] - reserved
3559 * [59:32] - interrupt source data
3560 * [63:60] - reserved
3561 * [71:64] - RINGID
3562 * [79:72] - VMID
3563 * [127:80] - reserved
3564 */
3565int si_irq_process(struct radeon_device *rdev)
3566{
3567 u32 wptr;
3568 u32 rptr;
3569 u32 src_id, src_data, ring_id;
3570 u32 ring_index;
25a857fb
AD		 3571 bool queue_hotplug = false;
3572
3573 if (!rdev->ih.enabled || rdev->shutdown)
3574 return IRQ_NONE;
3575
3576 wptr = si_get_ih_wptr(rdev);
c20dc369
CK		 3577
3578restart_ih:
3579 /* is somebody else already processing irqs? */
3580 if (atomic_xchg(&rdev->ih.lock, 1))
3581 return IRQ_NONE;
3582
25a857fb
AD		 3583 rptr = rdev->ih.rptr;
3584 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3585
25a857fb
AD		 3586 /* Order reading of wptr vs. reading of IH ring data */
3587 rmb();
3588
3589 /* display interrupts */
3590 si_irq_ack(rdev);
3591
25a857fb
AD		 3592 while (rptr != wptr) {
3593 /* wptr/rptr are in bytes! */
3594 ring_index = rptr / 4;
3595 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3596 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3597 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3598
3599 switch (src_id) {
3600 case 1: /* D1 vblank/vline */
3601 switch (src_data) {
3602 case 0: /* D1 vblank */
3603 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3604 if (rdev->irq.crtc_vblank_int[0]) {
3605 drm_handle_vblank(rdev->ddev, 0);
3606 rdev->pm.vblank_sync = true;
3607 wake_up(&rdev->irq.vblank_queue);
3608 }
736fc37f 3609 if (atomic_read(&rdev->irq.pflip[0]))
25a857fb
AD		 3610 radeon_crtc_handle_flip(rdev, 0);
3611 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3612 DRM_DEBUG("IH: D1 vblank\n");
3613 }
3614 break;
3615 case 1: /* D1 vline */
3616 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3617 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3618 DRM_DEBUG("IH: D1 vline\n");
3619 }
3620 break;
3621 default:
3622 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3623 break;
3624 }
3625 break;
3626 case 2: /* D2 vblank/vline */
3627 switch (src_data) {
3628 case 0: /* D2 vblank */
3629 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3630 if (rdev->irq.crtc_vblank_int[1]) {
3631 drm_handle_vblank(rdev->ddev, 1);
3632 rdev->pm.vblank_sync = true;
3633 wake_up(&rdev->irq.vblank_queue);
3634 }
736fc37f 3635 if (atomic_read(&rdev->irq.pflip[1]))
25a857fb
AD		 3636 radeon_crtc_handle_flip(rdev, 1);
3637 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3638 DRM_DEBUG("IH: D2 vblank\n");
3639 }
3640 break;
3641 case 1: /* D2 vline */
3642 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3643 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3644 DRM_DEBUG("IH: D2 vline\n");
3645 }
3646 break;
3647 default:
3648 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3649 break;
3650 }
3651 break;
3652 case 3: /* D3 vblank/vline */
3653 switch (src_data) {
3654 case 0: /* D3 vblank */
3655 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3656 if (rdev->irq.crtc_vblank_int[2]) {
3657 drm_handle_vblank(rdev->ddev, 2);
3658 rdev->pm.vblank_sync = true;
3659 wake_up(&rdev->irq.vblank_queue);
3660 }
736fc37f 3661 if (atomic_read(&rdev->irq.pflip[2]))
25a857fb
AD		 3662 radeon_crtc_handle_flip(rdev, 2);
3663 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3664 DRM_DEBUG("IH: D3 vblank\n");
3665 }
3666 break;
3667 case 1: /* D3 vline */
3668 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3669 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3670 DRM_DEBUG("IH: D3 vline\n");
3671 }
3672 break;
3673 default:
3674 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3675 break;
3676 }
3677 break;
3678 case 4: /* D4 vblank/vline */
3679 switch (src_data) {
3680 case 0: /* D4 vblank */
3681 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3682 if (rdev->irq.crtc_vblank_int[3]) {
3683 drm_handle_vblank(rdev->ddev, 3);
3684 rdev->pm.vblank_sync = true;
3685 wake_up(&rdev->irq.vblank_queue);
3686 }
736fc37f 3687 if (atomic_read(&rdev->irq.pflip[3]))
25a857fb
AD		 3688 radeon_crtc_handle_flip(rdev, 3);
3689 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3690 DRM_DEBUG("IH: D4 vblank\n");
3691 }
3692 break;
3693 case 1: /* D4 vline */
3694 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3695 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3696 DRM_DEBUG("IH: D4 vline\n");
3697 }
3698 break;
3699 default:
3700 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3701 break;
3702 }
3703 break;
3704 case 5: /* D5 vblank/vline */
3705 switch (src_data) {
3706 case 0: /* D5 vblank */
3707 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3708 if (rdev->irq.crtc_vblank_int[4]) {
3709 drm_handle_vblank(rdev->ddev, 4);
3710 rdev->pm.vblank_sync = true;
3711 wake_up(&rdev->irq.vblank_queue);
3712 }
736fc37f 3713 if (atomic_read(&rdev->irq.pflip[4]))
25a857fb
AD		 3714 radeon_crtc_handle_flip(rdev, 4);
3715 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3716 DRM_DEBUG("IH: D5 vblank\n");
3717 }
3718 break;
3719 case 1: /* D5 vline */
3720 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3721 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3722 DRM_DEBUG("IH: D5 vline\n");
3723 }
3724 break;
3725 default:
3726 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3727 break;
3728 }
3729 break;
3730 case 6: /* D6 vblank/vline */
3731 switch (src_data) {
3732 case 0: /* D6 vblank */
3733 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3734 if (rdev->irq.crtc_vblank_int[5]) {
3735 drm_handle_vblank(rdev->ddev, 5);
3736 rdev->pm.vblank_sync = true;
3737 wake_up(&rdev->irq.vblank_queue);
3738 }
736fc37f 3739 if (atomic_read(&rdev->irq.pflip[5]))
25a857fb
AD		 3740 radeon_crtc_handle_flip(rdev, 5);
3741 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3742 DRM_DEBUG("IH: D6 vblank\n");
3743 }
3744 break;
3745 case 1: /* D6 vline */
3746 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3747 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3748 DRM_DEBUG("IH: D6 vline\n");
3749 }
3750 break;
3751 default:
3752 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3753 break;
3754 }
3755 break;
3756 case 42: /* HPD hotplug */
3757 switch (src_data) {
3758 case 0:
3759 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3760 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3761 queue_hotplug = true;
3762 DRM_DEBUG("IH: HPD1\n");
3763 }
3764 break;
3765 case 1:
3766 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3767 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3768 queue_hotplug = true;
3769 DRM_DEBUG("IH: HPD2\n");
3770 }
3771 break;
3772 case 2:
3773 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3774 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3775 queue_hotplug = true;
3776 DRM_DEBUG("IH: HPD3\n");
3777 }
3778 break;
3779 case 3:
3780 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3781 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3782 queue_hotplug = true;
3783 DRM_DEBUG("IH: HPD4\n");
3784 }
3785 break;
3786 case 4:
3787 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3788 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3789 queue_hotplug = true;
3790 DRM_DEBUG("IH: HPD5\n");
3791 }
3792 break;
3793 case 5:
3794 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3795 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3796 queue_hotplug = true;
3797 DRM_DEBUG("IH: HPD6\n");
3798 }
3799 break;
3800 default:
3801 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3802 break;
3803 }
3804 break;
ae133a11
CK		 3805 case 146:
3806 case 147:
3807 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3808 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3809 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3810 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3811 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3812 /* reset addr and status */
3813 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3814 break;
25a857fb
AD		 3815 case 176: /* RINGID0 CP_INT */
3816 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3817 break;
3818 case 177: /* RINGID1 CP_INT */
3819 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3820 break;
3821 case 178: /* RINGID2 CP_INT */
3822 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3823 break;
3824 case 181: /* CP EOP event */
3825 DRM_DEBUG("IH: CP EOP\n");
3826 switch (ring_id) {
3827 case 0:
3828 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3829 break;
3830 case 1:
3831 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3832 break;
3833 case 2:
3834 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3835 break;
3836 }
3837 break;
8c5fd7ef
AD		 3838 case 224: /* DMA trap event */
3839 DRM_DEBUG("IH: DMA trap\n");
3840 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3841 break;
25a857fb
AD		 3842 case 233: /* GUI IDLE */
3843 DRM_DEBUG("IH: GUI idle\n");
25a857fb 3844 break;
8c5fd7ef
AD		 3845 case 244: /* DMA trap event */
3846 DRM_DEBUG("IH: DMA1 trap\n");
3847 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3848 break;
25a857fb
AD		 3849 default:
3850 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3851 break;
3852 }
3853
3854 /* wptr/rptr are in bytes! */
3855 rptr += 16;
3856 rptr &= rdev->ih.ptr_mask;
3857 }
25a857fb
AD		 3858 if (queue_hotplug)
3859 schedule_work(&rdev->hotplug_work);
3860 rdev->ih.rptr = rptr;
3861 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3862 atomic_set(&rdev->ih.lock, 0);
3863
3864 /* make sure wptr hasn't changed while processing */
3865 wptr = si_get_ih_wptr(rdev);
3866 if (wptr != rptr)
3867 goto restart_ih;
3868
25a857fb
AD		 3869 return IRQ_HANDLED;
3870}
3871
8c5fd7ef
AD		 3872/**
3873 * si_copy_dma - copy pages using the DMA engine
3874 *
3875 * @rdev: radeon_device pointer
3876 * @src_offset: src GPU address
3877 * @dst_offset: dst GPU address
3878 * @num_gpu_pages: number of GPU pages to xfer
3879 * @fence: radeon fence object
3880 *
3881 * Copy GPU paging using the DMA engine (SI).
3882 * Used by the radeon ttm implementation to move pages if
3883 * registered as the asic copy callback.
3884 */
3885int si_copy_dma(struct radeon_device *rdev,
3886 uint64_t src_offset, uint64_t dst_offset,
3887 unsigned num_gpu_pages,
3888 struct radeon_fence **fence)
3889{
3890 struct radeon_semaphore *sem = NULL;
3891 int ring_index = rdev->asic->copy.dma_ring_index;
3892 struct radeon_ring *ring = &rdev->ring[ring_index];
3893 u32 size_in_bytes, cur_size_in_bytes;
3894 int i, num_loops;
3895 int r = 0;
3896
3897 r = radeon_semaphore_create(rdev, &sem);
3898 if (r) {
3899 DRM_ERROR("radeon: moving bo (%d).\n", r);
3900 return r;
3901 }
3902
3903 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3904 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
3905 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3906 if (r) {
3907 DRM_ERROR("radeon: moving bo (%d).\n", r);
3908 radeon_semaphore_free(rdev, &sem, NULL);
3909 return r;
3910 }
3911
3912 if (radeon_fence_need_sync(*fence, ring->idx)) {
3913 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3914 ring->idx);
3915 radeon_fence_note_sync(*fence, ring->idx);
3916 } else {
3917 radeon_semaphore_free(rdev, &sem, NULL);
3918 }
3919
3920 for (i = 0; i < num_loops; i++) {
3921 cur_size_in_bytes = size_in_bytes;
3922 if (cur_size_in_bytes > 0xFFFFF)
3923 cur_size_in_bytes = 0xFFFFF;
3924 size_in_bytes -= cur_size_in_bytes;
3925 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
3926 radeon_ring_write(ring, dst_offset & 0xffffffff);
3927 radeon_ring_write(ring, src_offset & 0xffffffff);
3928 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3929 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3930 src_offset += cur_size_in_bytes;
3931 dst_offset += cur_size_in_bytes;
3932 }
3933
3934 r = radeon_fence_emit(rdev, fence, ring->idx);
3935 if (r) {
3936 radeon_ring_unlock_undo(rdev, ring);
3937 return r;
3938 }
3939
3940 radeon_ring_unlock_commit(rdev, ring);
3941 radeon_semaphore_free(rdev, &sem, *fence);
3942
3943 return r;
3944}
3945
9b136d51
AD		 3946/*
3947 * startup/shutdown callbacks
3948 */
3949static int si_startup(struct radeon_device *rdev)
3950{
3951 struct radeon_ring *ring;
3952 int r;
3953
3954 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
3955 !rdev->rlc_fw || !rdev->mc_fw) {
3956 r = si_init_microcode(rdev);
3957 if (r) {
3958 DRM_ERROR("Failed to load firmware!\n");
3959 return r;
3960 }
3961 }
3962
3963 r = si_mc_load_microcode(rdev);
3964 if (r) {
3965 DRM_ERROR("Failed to load MC firmware!\n");
3966 return r;
3967 }
3968
3969 r = r600_vram_scratch_init(rdev);
3970 if (r)
3971 return r;
3972
3973 si_mc_program(rdev);
3974 r = si_pcie_gart_enable(rdev);
3975 if (r)
3976 return r;
3977 si_gpu_init(rdev);
3978
3979#if 0
3980 r = evergreen_blit_init(rdev);
3981 if (r) {
3982 r600_blit_fini(rdev);
3983 rdev->asic->copy = NULL;
3984 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3985 }
3986#endif
3987 /* allocate rlc buffers */
3988 r = si_rlc_init(rdev);
3989 if (r) {
3990 DRM_ERROR("Failed to init rlc BOs!\n");
3991 return r;
3992 }
3993
3994 /* allocate wb buffer */
3995 r = radeon_wb_init(rdev);
3996 if (r)
3997 return r;
3998
3999 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4000 if (r) {
4001 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4002 return r;
4003 }
4004
4005 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4006 if (r) {
4007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4008 return r;
4009 }
4010
4011 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4012 if (r) {
4013 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4014 return r;
4015 }
4016
8c5fd7ef
AD		 4017 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4018 if (r) {
4019 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4020 return r;
4021 }
4022
4023 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4024 if (r) {
4025 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4026 return r;
4027 }
4028
9b136d51
AD		 4029 /* Enable IRQ */
4030 r = si_irq_init(rdev);
4031 if (r) {
4032 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4033 radeon_irq_kms_fini(rdev);
4034 return r;
4035 }
4036 si_irq_set(rdev);
4037
4038 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4039 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4040 CP_RB0_RPTR, CP_RB0_WPTR,
4041 0, 0xfffff, RADEON_CP_PACKET2);
4042 if (r)
4043 return r;
4044
4045 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4046 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4047 CP_RB1_RPTR, CP_RB1_WPTR,
4048 0, 0xfffff, RADEON_CP_PACKET2);
4049 if (r)
4050 return r;
4051
4052 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4053 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4054 CP_RB2_RPTR, CP_RB2_WPTR,
4055 0, 0xfffff, RADEON_CP_PACKET2);
4056 if (r)
4057 return r;
4058
8c5fd7ef
AD		 4059 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4060 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4061 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4062 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4063 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4064 if (r)
4065 return r;
4066
4067 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4068 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4069 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4070 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4071 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4072 if (r)
4073 return r;
4074
9b136d51
AD		 4075 r = si_cp_load_microcode(rdev);
4076 if (r)
4077 return r;
4078 r = si_cp_resume(rdev);
4079 if (r)
4080 return r;
4081
8c5fd7ef
AD		 4082 r = cayman_dma_resume(rdev);
4083 if (r)
4084 return r;
4085
2898c348
CK		 4086 r = radeon_ib_pool_init(rdev);
4087 if (r) {
4088 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
9b136d51 4089 return r;
2898c348 4090 }
9b136d51 4091
c6105f24
CK		 4092 r = radeon_vm_manager_init(rdev);
4093 if (r) {
4094 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
9b136d51 4095 return r;
c6105f24 4096 }
9b136d51
AD		 4097
4098 return 0;
4099}
4100
4101int si_resume(struct radeon_device *rdev)
4102{
4103 int r;
4104
4105 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4106 * posting will perform necessary task to bring back GPU into good
4107 * shape.
4108 */
4109 /* post card */
4110 atom_asic_init(rdev->mode_info.atom_context);
4111
4112 rdev->accel_working = true;
4113 r = si_startup(rdev);
4114 if (r) {
4115 DRM_ERROR("si startup failed on resume\n");
4116 rdev->accel_working = false;
4117 return r;
4118 }
4119
4120 return r;
4121
4122}
4123
4124int si_suspend(struct radeon_device *rdev)
4125{
9b136d51 4126 si_cp_enable(rdev, false);
8c5fd7ef 4127 cayman_dma_stop(rdev);
9b136d51
AD		 4128 si_irq_suspend(rdev);
4129 radeon_wb_disable(rdev);
4130 si_pcie_gart_disable(rdev);
4131 return 0;
4132}
4133
4134/* Plan is to move initialization in that function and use
4135 * helper function so that radeon_device_init pretty much
4136 * do nothing more than calling asic specific function. This
4137 * should also allow to remove a bunch of callback function
4138 * like vram_info.
4139 */
4140int si_init(struct radeon_device *rdev)
4141{
4142 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4143 int r;
4144
9b136d51
AD		 4145 /* Read BIOS */
4146 if (!radeon_get_bios(rdev)) {
4147 if (ASIC_IS_AVIVO(rdev))
4148 return -EINVAL;
4149 }
4150 /* Must be an ATOMBIOS */
4151 if (!rdev->is_atom_bios) {
4152 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4153 return -EINVAL;
4154 }
4155 r = radeon_atombios_init(rdev);
4156 if (r)
4157 return r;
4158
4159 /* Post card if necessary */
4160 if (!radeon_card_posted(rdev)) {
4161 if (!rdev->bios) {
4162 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4163 return -EINVAL;
4164 }
4165 DRM_INFO("GPU not posted. posting now...\n");
4166 atom_asic_init(rdev->mode_info.atom_context);
4167 }
4168 /* Initialize scratch registers */
4169 si_scratch_init(rdev);
4170 /* Initialize surface registers */
4171 radeon_surface_init(rdev);
4172 /* Initialize clocks */
4173 radeon_get_clock_info(rdev->ddev);
4174
4175 /* Fence driver */
4176 r = radeon_fence_driver_init(rdev);
4177 if (r)
4178 return r;
4179
4180 /* initialize memory controller */
4181 r = si_mc_init(rdev);
4182 if (r)
4183 return r;
4184 /* Memory manager */
4185 r = radeon_bo_init(rdev);
4186 if (r)
4187 return r;
4188
4189 r = radeon_irq_kms_init(rdev);
4190 if (r)
4191 return r;
4192
4193 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4194 ring->ring_obj = NULL;
4195 r600_ring_init(rdev, ring, 1024 * 1024);
4196
4197 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4198 ring->ring_obj = NULL;
4199 r600_ring_init(rdev, ring, 1024 * 1024);
4200
4201 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4202 ring->ring_obj = NULL;
4203 r600_ring_init(rdev, ring, 1024 * 1024);
4204
8c5fd7ef
AD		 4205 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4206 ring->ring_obj = NULL;
4207 r600_ring_init(rdev, ring, 64 * 1024);
4208
4209 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4210 ring->ring_obj = NULL;
4211 r600_ring_init(rdev, ring, 64 * 1024);
4212
9b136d51
AD		 4213 rdev->ih.ring_obj = NULL;
4214 r600_ih_ring_init(rdev, 64 * 1024);
4215
4216 r = r600_pcie_gart_init(rdev);
4217 if (r)
4218 return r;
4219
9b136d51 4220 rdev->accel_working = true;
9b136d51
AD		 4221 r = si_startup(rdev);
4222 if (r) {
4223 dev_err(rdev->dev, "disabling GPU acceleration\n");
4224 si_cp_fini(rdev);
8c5fd7ef 4225 cayman_dma_fini(rdev);
9b136d51
AD		 4226 si_irq_fini(rdev);
4227 si_rlc_fini(rdev);
4228 radeon_wb_fini(rdev);
2898c348 4229 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4230 radeon_vm_manager_fini(rdev);
4231 radeon_irq_kms_fini(rdev);
4232 si_pcie_gart_fini(rdev);
4233 rdev->accel_working = false;
4234 }
4235
4236 /* Don't start up if the MC ucode is missing.
4237 * The default clocks and voltages before the MC ucode
4238 * is loaded are not suffient for advanced operations.
4239 */
4240 if (!rdev->mc_fw) {
4241 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4242 return -EINVAL;
4243 }
4244
4245 return 0;
4246}
4247
4248void si_fini(struct radeon_device *rdev)
4249{
4250#if 0
4251 r600_blit_fini(rdev);
4252#endif
4253 si_cp_fini(rdev);
8c5fd7ef 4254 cayman_dma_fini(rdev);
9b136d51
AD		 4255 si_irq_fini(rdev);
4256 si_rlc_fini(rdev);
4257 radeon_wb_fini(rdev);
4258 radeon_vm_manager_fini(rdev);
2898c348 4259 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4260 radeon_irq_kms_fini(rdev);
4261 si_pcie_gart_fini(rdev);
4262 r600_vram_scratch_fini(rdev);
4263 radeon_gem_fini(rdev);
9b136d51
AD		 4264 radeon_fence_driver_fini(rdev);
4265 radeon_bo_fini(rdev);
4266 radeon_atombios_fini(rdev);
4267 kfree(rdev->bios);
4268 rdev->bios = NULL;
4269}
4270
6759a0a7
MO		 4271/**
4272 * si_get_gpu_clock - return GPU clock counter snapshot
4273 *
4274 * @rdev: radeon_device pointer
4275 *
4276 * Fetches a GPU clock counter snapshot (SI).
4277 * Returns the 64 bit clock counter snapshot.
4278 */
4279uint64_t si_get_gpu_clock(struct radeon_device *rdev)
4280{
4281 uint64_t clock;
4282
4283 mutex_lock(&rdev->gpu_clock_mutex);
4284 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4285 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4286 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4287 mutex_unlock(&rdev->gpu_clock_mutex);
4288 return clock;
4289}
Linux 6.x block layer and io_uring tree(s)