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drm/radeon: properly handle crtc powergating
[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c
CommitLineData
43b3cd99
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
0f0de06c
AD		 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
43b3cd99
AD		 28#include "drmP.h"
29#include "radeon.h"
30#include "radeon_asic.h"
31#include "radeon_drm.h"
32#include "sid.h"
33#include "atom.h"
48c0c902 34#include "si_blit_shaders.h"
43b3cd99 35
0f0de06c
AD		 36#define SI_PFP_UCODE_SIZE 2144
37#define SI_PM4_UCODE_SIZE 2144
38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769
41
42MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53MODULE_FIRMWARE("radeon/VERDE_me.bin");
54MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
57
25a857fb
AD		 58extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59extern void r600_ih_ring_fini(struct radeon_device *rdev);
0a96d72b 60extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
c476dde2
AD		 61extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
ca7db22b 63extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
0a96d72b 64
1bd47d2e
AD		 65/* get temperature in millidegrees */
66int si_get_temp(struct radeon_device *rdev)
67{
68 u32 temp;
69 int actual_temp = 0;
70
71 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
72 CTF_TEMP_SHIFT;
73
74 if (temp & 0x200)
75 actual_temp = 255;
76 else
77 actual_temp = temp & 0x1ff;
78
79 actual_temp = (actual_temp * 1000);
80
81 return actual_temp;
82}
83
8b074dd6
AD		 84#define TAHITI_IO_MC_REGS_SIZE 36
85
86static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
87 {0x0000006f, 0x03044000},
88 {0x00000070, 0x0480c018},
89 {0x00000071, 0x00000040},
90 {0x00000072, 0x01000000},
91 {0x00000074, 0x000000ff},
92 {0x00000075, 0x00143400},
93 {0x00000076, 0x08ec0800},
94 {0x00000077, 0x040000cc},
95 {0x00000079, 0x00000000},
96 {0x0000007a, 0x21000409},
97 {0x0000007c, 0x00000000},
98 {0x0000007d, 0xe8000000},
99 {0x0000007e, 0x044408a8},
100 {0x0000007f, 0x00000003},
101 {0x00000080, 0x00000000},
102 {0x00000081, 0x01000000},
103 {0x00000082, 0x02000000},
104 {0x00000083, 0x00000000},
105 {0x00000084, 0xe3f3e4f4},
106 {0x00000085, 0x00052024},
107 {0x00000087, 0x00000000},
108 {0x00000088, 0x66036603},
109 {0x00000089, 0x01000000},
110 {0x0000008b, 0x1c0a0000},
111 {0x0000008c, 0xff010000},
112 {0x0000008e, 0xffffefff},
113 {0x0000008f, 0xfff3efff},
114 {0x00000090, 0xfff3efbf},
115 {0x00000094, 0x00101101},
116 {0x00000095, 0x00000fff},
117 {0x00000096, 0x00116fff},
118 {0x00000097, 0x60010000},
119 {0x00000098, 0x10010000},
120 {0x00000099, 0x00006000},
121 {0x0000009a, 0x00001000},
122 {0x0000009f, 0x00a77400}
123};
124
125static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
126 {0x0000006f, 0x03044000},
127 {0x00000070, 0x0480c018},
128 {0x00000071, 0x00000040},
129 {0x00000072, 0x01000000},
130 {0x00000074, 0x000000ff},
131 {0x00000075, 0x00143400},
132 {0x00000076, 0x08ec0800},
133 {0x00000077, 0x040000cc},
134 {0x00000079, 0x00000000},
135 {0x0000007a, 0x21000409},
136 {0x0000007c, 0x00000000},
137 {0x0000007d, 0xe8000000},
138 {0x0000007e, 0x044408a8},
139 {0x0000007f, 0x00000003},
140 {0x00000080, 0x00000000},
141 {0x00000081, 0x01000000},
142 {0x00000082, 0x02000000},
143 {0x00000083, 0x00000000},
144 {0x00000084, 0xe3f3e4f4},
145 {0x00000085, 0x00052024},
146 {0x00000087, 0x00000000},
147 {0x00000088, 0x66036603},
148 {0x00000089, 0x01000000},
149 {0x0000008b, 0x1c0a0000},
150 {0x0000008c, 0xff010000},
151 {0x0000008e, 0xffffefff},
152 {0x0000008f, 0xfff3efff},
153 {0x00000090, 0xfff3efbf},
154 {0x00000094, 0x00101101},
155 {0x00000095, 0x00000fff},
156 {0x00000096, 0x00116fff},
157 {0x00000097, 0x60010000},
158 {0x00000098, 0x10010000},
159 {0x00000099, 0x00006000},
160 {0x0000009a, 0x00001000},
161 {0x0000009f, 0x00a47400}
162};
163
164static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
165 {0x0000006f, 0x03044000},
166 {0x00000070, 0x0480c018},
167 {0x00000071, 0x00000040},
168 {0x00000072, 0x01000000},
169 {0x00000074, 0x000000ff},
170 {0x00000075, 0x00143400},
171 {0x00000076, 0x08ec0800},
172 {0x00000077, 0x040000cc},
173 {0x00000079, 0x00000000},
174 {0x0000007a, 0x21000409},
175 {0x0000007c, 0x00000000},
176 {0x0000007d, 0xe8000000},
177 {0x0000007e, 0x044408a8},
178 {0x0000007f, 0x00000003},
179 {0x00000080, 0x00000000},
180 {0x00000081, 0x01000000},
181 {0x00000082, 0x02000000},
182 {0x00000083, 0x00000000},
183 {0x00000084, 0xe3f3e4f4},
184 {0x00000085, 0x00052024},
185 {0x00000087, 0x00000000},
186 {0x00000088, 0x66036603},
187 {0x00000089, 0x01000000},
188 {0x0000008b, 0x1c0a0000},
189 {0x0000008c, 0xff010000},
190 {0x0000008e, 0xffffefff},
191 {0x0000008f, 0xfff3efff},
192 {0x00000090, 0xfff3efbf},
193 {0x00000094, 0x00101101},
194 {0x00000095, 0x00000fff},
195 {0x00000096, 0x00116fff},
196 {0x00000097, 0x60010000},
197 {0x00000098, 0x10010000},
198 {0x00000099, 0x00006000},
199 {0x0000009a, 0x00001000},
200 {0x0000009f, 0x00a37400}
201};
202
203/* ucode loading */
204static int si_mc_load_microcode(struct radeon_device *rdev)
205{
206 const __be32 *fw_data;
207 u32 running, blackout = 0;
208 u32 *io_mc_regs;
209 int i, ucode_size, regs_size;
210
211 if (!rdev->mc_fw)
212 return -EINVAL;
213
214 switch (rdev->family) {
215 case CHIP_TAHITI:
216 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
217 ucode_size = SI_MC_UCODE_SIZE;
218 regs_size = TAHITI_IO_MC_REGS_SIZE;
219 break;
220 case CHIP_PITCAIRN:
221 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
222 ucode_size = SI_MC_UCODE_SIZE;
223 regs_size = TAHITI_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_VERDE:
226 default:
227 io_mc_regs = (u32 *)&verde_io_mc_regs;
228 ucode_size = SI_MC_UCODE_SIZE;
229 regs_size = TAHITI_IO_MC_REGS_SIZE;
230 break;
231 }
232
233 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
234
235 if (running == 0) {
236 if (running) {
237 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
238 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
239 }
240
241 /* reset the engine and set to writable */
242 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
243 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
244
245 /* load mc io regs */
246 for (i = 0; i < regs_size; i++) {
247 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
248 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
249 }
250 /* load the MC ucode */
251 fw_data = (const __be32 *)rdev->mc_fw->data;
252 for (i = 0; i < ucode_size; i++)
253 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
254
255 /* put the engine back into the active state */
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
257 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
259
260 /* wait for training to complete */
261 for (i = 0; i < rdev->usec_timeout; i++) {
262 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
263 break;
264 udelay(1);
265 }
266 for (i = 0; i < rdev->usec_timeout; i++) {
267 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
268 break;
269 udelay(1);
270 }
271
272 if (running)
273 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
274 }
275
276 return 0;
277}
278
0f0de06c
AD		 279static int si_init_microcode(struct radeon_device *rdev)
280{
281 struct platform_device *pdev;
282 const char *chip_name;
283 const char *rlc_chip_name;
284 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
285 char fw_name[30];
286 int err;
287
288 DRM_DEBUG("\n");
289
290 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
291 err = IS_ERR(pdev);
292 if (err) {
293 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
294 return -EINVAL;
295 }
296
297 switch (rdev->family) {
298 case CHIP_TAHITI:
299 chip_name = "TAHITI";
300 rlc_chip_name = "TAHITI";
301 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
302 me_req_size = SI_PM4_UCODE_SIZE * 4;
303 ce_req_size = SI_CE_UCODE_SIZE * 4;
304 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
305 mc_req_size = SI_MC_UCODE_SIZE * 4;
306 break;
307 case CHIP_PITCAIRN:
308 chip_name = "PITCAIRN";
309 rlc_chip_name = "PITCAIRN";
310 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
311 me_req_size = SI_PM4_UCODE_SIZE * 4;
312 ce_req_size = SI_CE_UCODE_SIZE * 4;
313 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
314 mc_req_size = SI_MC_UCODE_SIZE * 4;
315 break;
316 case CHIP_VERDE:
317 chip_name = "VERDE";
318 rlc_chip_name = "VERDE";
319 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
320 me_req_size = SI_PM4_UCODE_SIZE * 4;
321 ce_req_size = SI_CE_UCODE_SIZE * 4;
322 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
323 mc_req_size = SI_MC_UCODE_SIZE * 4;
324 break;
325 default: BUG();
326 }
327
328 DRM_INFO("Loading %s Microcode\n", chip_name);
329
330 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
331 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
332 if (err)
333 goto out;
334 if (rdev->pfp_fw->size != pfp_req_size) {
335 printk(KERN_ERR
336 "si_cp: Bogus length %zu in firmware \"%s\"\n",
337 rdev->pfp_fw->size, fw_name);
338 err = -EINVAL;
339 goto out;
340 }
341
342 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
343 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
344 if (err)
345 goto out;
346 if (rdev->me_fw->size != me_req_size) {
347 printk(KERN_ERR
348 "si_cp: Bogus length %zu in firmware \"%s\"\n",
349 rdev->me_fw->size, fw_name);
350 err = -EINVAL;
351 }
352
353 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
354 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
355 if (err)
356 goto out;
357 if (rdev->ce_fw->size != ce_req_size) {
358 printk(KERN_ERR
359 "si_cp: Bogus length %zu in firmware \"%s\"\n",
360 rdev->ce_fw->size, fw_name);
361 err = -EINVAL;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
365 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->rlc_fw->size != rlc_req_size) {
369 printk(KERN_ERR
370 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
371 rdev->rlc_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
376 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->mc_fw->size != mc_req_size) {
380 printk(KERN_ERR
381 "si_mc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->mc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
386out:
387 platform_device_unregister(pdev);
388
389 if (err) {
390 if (err != -EINVAL)
391 printk(KERN_ERR
392 "si_cp: Failed to load firmware \"%s\"\n",
393 fw_name);
394 release_firmware(rdev->pfp_fw);
395 rdev->pfp_fw = NULL;
396 release_firmware(rdev->me_fw);
397 rdev->me_fw = NULL;
398 release_firmware(rdev->ce_fw);
399 rdev->ce_fw = NULL;
400 release_firmware(rdev->rlc_fw);
401 rdev->rlc_fw = NULL;
402 release_firmware(rdev->mc_fw);
403 rdev->mc_fw = NULL;
404 }
405 return err;
406}
407
43b3cd99
AD		 408/* watermark setup */
409static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
410 struct radeon_crtc *radeon_crtc,
411 struct drm_display_mode *mode,
412 struct drm_display_mode *other_mode)
413{
414 u32 tmp;
415 /*
416 * Line Buffer Setup
417 * There are 3 line buffers, each one shared by 2 display controllers.
418 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
419 * the display controllers. The paritioning is done via one of four
420 * preset allocations specified in bits 21:20:
421 * 0 - half lb
422 * 2 - whole lb, other crtc must be disabled
423 */
424 /* this can get tricky if we have two large displays on a paired group
425 * of crtcs. Ideally for multiple large displays we'd assign them to
426 * non-linked crtcs for maximum line buffer allocation.
427 */
428 if (radeon_crtc->base.enabled && mode) {
429 if (other_mode)
430 tmp = 0; /* 1/2 */
431 else
432 tmp = 2; /* whole */
433 } else
434 tmp = 0;
435
436 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
437 DC_LB_MEMORY_CONFIG(tmp));
438
439 if (radeon_crtc->base.enabled && mode) {
440 switch (tmp) {
441 case 0:
442 default:
443 return 4096 * 2;
444 case 2:
445 return 8192 * 2;
446 }
447 }
448
449 /* controller not enabled, so no lb used */
450 return 0;
451}
452
ca7db22b 453static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
43b3cd99
AD		 454{
455 u32 tmp = RREG32(MC_SHARED_CHMAP);
456
457 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
458 case 0:
459 default:
460 return 1;
461 case 1:
462 return 2;
463 case 2:
464 return 4;
465 case 3:
466 return 8;
467 case 4:
468 return 3;
469 case 5:
470 return 6;
471 case 6:
472 return 10;
473 case 7:
474 return 12;
475 case 8:
476 return 16;
477 }
478}
479
480struct dce6_wm_params {
481 u32 dram_channels; /* number of dram channels */
482 u32 yclk; /* bandwidth per dram data pin in kHz */
483 u32 sclk; /* engine clock in kHz */
484 u32 disp_clk; /* display clock in kHz */
485 u32 src_width; /* viewport width */
486 u32 active_time; /* active display time in ns */
487 u32 blank_time; /* blank time in ns */
488 bool interlaced; /* mode is interlaced */
489 fixed20_12 vsc; /* vertical scale ratio */
490 u32 num_heads; /* number of active crtcs */
491 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
492 u32 lb_size; /* line buffer allocated to pipe */
493 u32 vtaps; /* vertical scaler taps */
494};
495
496static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
497{
498 /* Calculate raw DRAM Bandwidth */
499 fixed20_12 dram_efficiency; /* 0.7 */
500 fixed20_12 yclk, dram_channels, bandwidth;
501 fixed20_12 a;
502
503 a.full = dfixed_const(1000);
504 yclk.full = dfixed_const(wm->yclk);
505 yclk.full = dfixed_div(yclk, a);
506 dram_channels.full = dfixed_const(wm->dram_channels * 4);
507 a.full = dfixed_const(10);
508 dram_efficiency.full = dfixed_const(7);
509 dram_efficiency.full = dfixed_div(dram_efficiency, a);
510 bandwidth.full = dfixed_mul(dram_channels, yclk);
511 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
512
513 return dfixed_trunc(bandwidth);
514}
515
516static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
517{
518 /* Calculate DRAM Bandwidth and the part allocated to display. */
519 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
520 fixed20_12 yclk, dram_channels, bandwidth;
521 fixed20_12 a;
522
523 a.full = dfixed_const(1000);
524 yclk.full = dfixed_const(wm->yclk);
525 yclk.full = dfixed_div(yclk, a);
526 dram_channels.full = dfixed_const(wm->dram_channels * 4);
527 a.full = dfixed_const(10);
528 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
529 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
530 bandwidth.full = dfixed_mul(dram_channels, yclk);
531 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
532
533 return dfixed_trunc(bandwidth);
534}
535
536static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
537{
538 /* Calculate the display Data return Bandwidth */
539 fixed20_12 return_efficiency; /* 0.8 */
540 fixed20_12 sclk, bandwidth;
541 fixed20_12 a;
542
543 a.full = dfixed_const(1000);
544 sclk.full = dfixed_const(wm->sclk);
545 sclk.full = dfixed_div(sclk, a);
546 a.full = dfixed_const(10);
547 return_efficiency.full = dfixed_const(8);
548 return_efficiency.full = dfixed_div(return_efficiency, a);
549 a.full = dfixed_const(32);
550 bandwidth.full = dfixed_mul(a, sclk);
551 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
552
553 return dfixed_trunc(bandwidth);
554}
555
556static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
557{
558 return 32;
559}
560
561static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
562{
563 /* Calculate the DMIF Request Bandwidth */
564 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
565 fixed20_12 disp_clk, sclk, bandwidth;
566 fixed20_12 a, b1, b2;
567 u32 min_bandwidth;
568
569 a.full = dfixed_const(1000);
570 disp_clk.full = dfixed_const(wm->disp_clk);
571 disp_clk.full = dfixed_div(disp_clk, a);
572 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
573 b1.full = dfixed_mul(a, disp_clk);
574
575 a.full = dfixed_const(1000);
576 sclk.full = dfixed_const(wm->sclk);
577 sclk.full = dfixed_div(sclk, a);
578 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
579 b2.full = dfixed_mul(a, sclk);
580
581 a.full = dfixed_const(10);
582 disp_clk_request_efficiency.full = dfixed_const(8);
583 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
584
585 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
586
587 a.full = dfixed_const(min_bandwidth);
588 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
589
590 return dfixed_trunc(bandwidth);
591}
592
593static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
594{
595 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
596 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
597 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
598 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
599
600 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
601}
602
603static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
604{
605 /* Calculate the display mode Average Bandwidth
606 * DisplayMode should contain the source and destination dimensions,
607 * timing, etc.
608 */
609 fixed20_12 bpp;
610 fixed20_12 line_time;
611 fixed20_12 src_width;
612 fixed20_12 bandwidth;
613 fixed20_12 a;
614
615 a.full = dfixed_const(1000);
616 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
617 line_time.full = dfixed_div(line_time, a);
618 bpp.full = dfixed_const(wm->bytes_per_pixel);
619 src_width.full = dfixed_const(wm->src_width);
620 bandwidth.full = dfixed_mul(src_width, bpp);
621 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
622 bandwidth.full = dfixed_div(bandwidth, line_time);
623
624 return dfixed_trunc(bandwidth);
625}
626
627static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
628{
629 /* First calcualte the latency in ns */
630 u32 mc_latency = 2000; /* 2000 ns. */
631 u32 available_bandwidth = dce6_available_bandwidth(wm);
632 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
633 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
634 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
635 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
636 (wm->num_heads * cursor_line_pair_return_time);
637 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
638 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
639 u32 tmp, dmif_size = 12288;
640 fixed20_12 a, b, c;
641
642 if (wm->num_heads == 0)
643 return 0;
644
645 a.full = dfixed_const(2);
646 b.full = dfixed_const(1);
647 if ((wm->vsc.full > a.full) ||
648 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
649 (wm->vtaps >= 5) ||
650 ((wm->vsc.full >= a.full) && wm->interlaced))
651 max_src_lines_per_dst_line = 4;
652 else
653 max_src_lines_per_dst_line = 2;
654
655 a.full = dfixed_const(available_bandwidth);
656 b.full = dfixed_const(wm->num_heads);
657 a.full = dfixed_div(a, b);
658
659 b.full = dfixed_const(mc_latency + 512);
660 c.full = dfixed_const(wm->disp_clk);
661 b.full = dfixed_div(b, c);
662
663 c.full = dfixed_const(dmif_size);
664 b.full = dfixed_div(c, b);
665
666 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
667
668 b.full = dfixed_const(1000);
669 c.full = dfixed_const(wm->disp_clk);
670 b.full = dfixed_div(c, b);
671 c.full = dfixed_const(wm->bytes_per_pixel);
672 b.full = dfixed_mul(b, c);
673
674 lb_fill_bw = min(tmp, dfixed_trunc(b));
675
676 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
677 b.full = dfixed_const(1000);
678 c.full = dfixed_const(lb_fill_bw);
679 b.full = dfixed_div(c, b);
680 a.full = dfixed_div(a, b);
681 line_fill_time = dfixed_trunc(a);
682
683 if (line_fill_time < wm->active_time)
684 return latency;
685 else
686 return latency + (line_fill_time - wm->active_time);
687
688}
689
690static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
691{
692 if (dce6_average_bandwidth(wm) <=
693 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
694 return true;
695 else
696 return false;
697};
698
699static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
700{
701 if (dce6_average_bandwidth(wm) <=
702 (dce6_available_bandwidth(wm) / wm->num_heads))
703 return true;
704 else
705 return false;
706};
707
708static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
709{
710 u32 lb_partitions = wm->lb_size / wm->src_width;
711 u32 line_time = wm->active_time + wm->blank_time;
712 u32 latency_tolerant_lines;
713 u32 latency_hiding;
714 fixed20_12 a;
715
716 a.full = dfixed_const(1);
717 if (wm->vsc.full > a.full)
718 latency_tolerant_lines = 1;
719 else {
720 if (lb_partitions <= (wm->vtaps + 1))
721 latency_tolerant_lines = 1;
722 else
723 latency_tolerant_lines = 2;
724 }
725
726 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
727
728 if (dce6_latency_watermark(wm) <= latency_hiding)
729 return true;
730 else
731 return false;
732}
733
734static void dce6_program_watermarks(struct radeon_device *rdev,
735 struct radeon_crtc *radeon_crtc,
736 u32 lb_size, u32 num_heads)
737{
738 struct drm_display_mode *mode = &radeon_crtc->base.mode;
739 struct dce6_wm_params wm;
740 u32 pixel_period;
741 u32 line_time = 0;
742 u32 latency_watermark_a = 0, latency_watermark_b = 0;
743 u32 priority_a_mark = 0, priority_b_mark = 0;
744 u32 priority_a_cnt = PRIORITY_OFF;
745 u32 priority_b_cnt = PRIORITY_OFF;
746 u32 tmp, arb_control3;
747 fixed20_12 a, b, c;
748
749 if (radeon_crtc->base.enabled && num_heads && mode) {
750 pixel_period = 1000000 / (u32)mode->clock;
751 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
752 priority_a_cnt = 0;
753 priority_b_cnt = 0;
754
755 wm.yclk = rdev->pm.current_mclk * 10;
756 wm.sclk = rdev->pm.current_sclk * 10;
757 wm.disp_clk = mode->clock;
758 wm.src_width = mode->crtc_hdisplay;
759 wm.active_time = mode->crtc_hdisplay * pixel_period;
760 wm.blank_time = line_time - wm.active_time;
761 wm.interlaced = false;
762 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
763 wm.interlaced = true;
764 wm.vsc = radeon_crtc->vsc;
765 wm.vtaps = 1;
766 if (radeon_crtc->rmx_type != RMX_OFF)
767 wm.vtaps = 2;
768 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
769 wm.lb_size = lb_size;
ca7db22b
AD		 770 if (rdev->family == CHIP_ARUBA)
771 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
772 else
773 wm.dram_channels = si_get_number_of_dram_channels(rdev);
43b3cd99
AD		 774 wm.num_heads = num_heads;
775
776 /* set for high clocks */
777 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
778 /* set for low clocks */
779 /* wm.yclk = low clk; wm.sclk = low clk */
780 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
781
782 /* possibly force display priority to high */
783 /* should really do this at mode validation time... */
784 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
785 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
786 !dce6_check_latency_hiding(&wm) ||
787 (rdev->disp_priority == 2)) {
788 DRM_DEBUG_KMS("force priority to high\n");
789 priority_a_cnt |= PRIORITY_ALWAYS_ON;
790 priority_b_cnt |= PRIORITY_ALWAYS_ON;
791 }
792
793 a.full = dfixed_const(1000);
794 b.full = dfixed_const(mode->clock);
795 b.full = dfixed_div(b, a);
796 c.full = dfixed_const(latency_watermark_a);
797 c.full = dfixed_mul(c, b);
798 c.full = dfixed_mul(c, radeon_crtc->hsc);
799 c.full = dfixed_div(c, a);
800 a.full = dfixed_const(16);
801 c.full = dfixed_div(c, a);
802 priority_a_mark = dfixed_trunc(c);
803 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
804
805 a.full = dfixed_const(1000);
806 b.full = dfixed_const(mode->clock);
807 b.full = dfixed_div(b, a);
808 c.full = dfixed_const(latency_watermark_b);
809 c.full = dfixed_mul(c, b);
810 c.full = dfixed_mul(c, radeon_crtc->hsc);
811 c.full = dfixed_div(c, a);
812 a.full = dfixed_const(16);
813 c.full = dfixed_div(c, a);
814 priority_b_mark = dfixed_trunc(c);
815 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
816 }
817
818 /* select wm A */
819 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
820 tmp = arb_control3;
821 tmp &= ~LATENCY_WATERMARK_MASK(3);
822 tmp |= LATENCY_WATERMARK_MASK(1);
823 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
824 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
825 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
826 LATENCY_HIGH_WATERMARK(line_time)));
827 /* select wm B */
828 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
829 tmp &= ~LATENCY_WATERMARK_MASK(3);
830 tmp |= LATENCY_WATERMARK_MASK(2);
831 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
832 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
833 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
834 LATENCY_HIGH_WATERMARK(line_time)));
835 /* restore original selection */
836 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
837
838 /* write the priority marks */
839 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
840 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
841
842}
843
844void dce6_bandwidth_update(struct radeon_device *rdev)
845{
846 struct drm_display_mode *mode0 = NULL;
847 struct drm_display_mode *mode1 = NULL;
848 u32 num_heads = 0, lb_size;
849 int i;
850
851 radeon_update_display_priority(rdev);
852
853 for (i = 0; i < rdev->num_crtc; i++) {
854 if (rdev->mode_info.crtcs[i]->base.enabled)
855 num_heads++;
856 }
857 for (i = 0; i < rdev->num_crtc; i += 2) {
858 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
859 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
860 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
861 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
862 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
863 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
864 }
865}
866
0a96d72b
AD		 867/*
868 * Core functions
869 */
0a96d72b
AD		 870static void si_tiling_mode_table_init(struct radeon_device *rdev)
871{
872 const u32 num_tile_mode_states = 32;
873 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
874
875 switch (rdev->config.si.mem_row_size_in_kb) {
876 case 1:
877 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
878 break;
879 case 2:
880 default:
881 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
882 break;
883 case 4:
884 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
885 break;
886 }
887
888 if ((rdev->family == CHIP_TAHITI) ||
889 (rdev->family == CHIP_PITCAIRN)) {
890 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
891 switch (reg_offset) {
892 case 0: /* non-AA compressed depth or any compressed stencil */
893 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
894 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
895 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
896 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
897 NUM_BANKS(ADDR_SURF_16_BANK) |
898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
901 break;
902 case 1: /* 2xAA/4xAA compressed depth only */
903 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
904 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
905 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
907 NUM_BANKS(ADDR_SURF_16_BANK) |
908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
911 break;
912 case 2: /* 8xAA compressed depth only */
913 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
914 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
915 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
917 NUM_BANKS(ADDR_SURF_16_BANK) |
918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
921 break;
922 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
923 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
924 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
925 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
926 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
927 NUM_BANKS(ADDR_SURF_16_BANK) |
928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
931 break;
932 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
933 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
934 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
935 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
937 NUM_BANKS(ADDR_SURF_16_BANK) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
941 break;
942 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
943 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
944 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
945 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
946 TILE_SPLIT(split_equal_to_row_size) |
947 NUM_BANKS(ADDR_SURF_16_BANK) |
948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
951 break;
952 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
953 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
954 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
955 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
956 TILE_SPLIT(split_equal_to_row_size) |
957 NUM_BANKS(ADDR_SURF_16_BANK) |
958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
961 break;
962 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
963 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
964 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
965 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
966 TILE_SPLIT(split_equal_to_row_size) |
967 NUM_BANKS(ADDR_SURF_16_BANK) |
968 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
971 break;
972 case 8: /* 1D and 1D Array Surfaces */
973 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
974 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
975 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
976 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
977 NUM_BANKS(ADDR_SURF_16_BANK) |
978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
981 break;
982 case 9: /* Displayable maps. */
983 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
984 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
985 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
987 NUM_BANKS(ADDR_SURF_16_BANK) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
991 break;
992 case 10: /* Display 8bpp. */
993 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
994 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
995 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
997 NUM_BANKS(ADDR_SURF_16_BANK) |
998 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1001 break;
1002 case 11: /* Display 16bpp. */
1003 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1004 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1005 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1007 NUM_BANKS(ADDR_SURF_16_BANK) |
1008 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1011 break;
1012 case 12: /* Display 32bpp. */
1013 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1014 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1017 NUM_BANKS(ADDR_SURF_16_BANK) |
1018 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1021 break;
1022 case 13: /* Thin. */
1023 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1024 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1027 NUM_BANKS(ADDR_SURF_16_BANK) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1031 break;
1032 case 14: /* Thin 8 bpp. */
1033 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1035 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1037 NUM_BANKS(ADDR_SURF_16_BANK) |
1038 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1041 break;
1042 case 15: /* Thin 16 bpp. */
1043 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1044 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1045 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1046 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1047 NUM_BANKS(ADDR_SURF_16_BANK) |
1048 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1049 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1050 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1051 break;
1052 case 16: /* Thin 32 bpp. */
1053 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1055 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1057 NUM_BANKS(ADDR_SURF_16_BANK) |
1058 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1059 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1060 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1061 break;
1062 case 17: /* Thin 64 bpp. */
1063 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1065 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1066 TILE_SPLIT(split_equal_to_row_size) |
1067 NUM_BANKS(ADDR_SURF_16_BANK) |
1068 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1069 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1070 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1071 break;
1072 case 21: /* 8 bpp PRT. */
1073 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1074 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1075 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1076 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1077 NUM_BANKS(ADDR_SURF_16_BANK) |
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1081 break;
1082 case 22: /* 16 bpp PRT */
1083 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1084 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1086 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1087 NUM_BANKS(ADDR_SURF_16_BANK) |
1088 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1089 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1090 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1091 break;
1092 case 23: /* 32 bpp PRT */
1093 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1094 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1097 NUM_BANKS(ADDR_SURF_16_BANK) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1101 break;
1102 case 24: /* 64 bpp PRT */
1103 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1105 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1107 NUM_BANKS(ADDR_SURF_16_BANK) |
1108 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1109 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1110 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1111 break;
1112 case 25: /* 128 bpp PRT */
1113 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1114 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1115 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1117 NUM_BANKS(ADDR_SURF_8_BANK) |
1118 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1121 break;
1122 default:
1123 gb_tile_moden = 0;
1124 break;
1125 }
1126 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1127 }
1128 } else if (rdev->family == CHIP_VERDE) {
1129 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1130 switch (reg_offset) {
1131 case 0: /* non-AA compressed depth or any compressed stencil */
1132 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1134 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1135 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1136 NUM_BANKS(ADDR_SURF_16_BANK) |
1137 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1140 break;
1141 case 1: /* 2xAA/4xAA compressed depth only */
1142 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1143 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1144 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1146 NUM_BANKS(ADDR_SURF_16_BANK) |
1147 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1149 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1150 break;
1151 case 2: /* 8xAA compressed depth only */
1152 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1153 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1154 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1155 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1156 NUM_BANKS(ADDR_SURF_16_BANK) |
1157 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1160 break;
1161 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1162 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1163 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1164 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1166 NUM_BANKS(ADDR_SURF_16_BANK) |
1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1170 break;
1171 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1172 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1173 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1174 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1175 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1176 NUM_BANKS(ADDR_SURF_16_BANK) |
1177 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1180 break;
1181 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1182 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1183 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1184 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1185 TILE_SPLIT(split_equal_to_row_size) |
1186 NUM_BANKS(ADDR_SURF_16_BANK) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1190 break;
1191 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1192 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1193 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1194 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1195 TILE_SPLIT(split_equal_to_row_size) |
1196 NUM_BANKS(ADDR_SURF_16_BANK) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1200 break;
1201 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1202 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1204 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1205 TILE_SPLIT(split_equal_to_row_size) |
1206 NUM_BANKS(ADDR_SURF_16_BANK) |
1207 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1210 break;
1211 case 8: /* 1D and 1D Array Surfaces */
1212 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1213 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1214 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1215 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1216 NUM_BANKS(ADDR_SURF_16_BANK) |
1217 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1219 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1220 break;
1221 case 9: /* Displayable maps. */
1222 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1223 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1224 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1226 NUM_BANKS(ADDR_SURF_16_BANK) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1230 break;
1231 case 10: /* Display 8bpp. */
1232 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1236 NUM_BANKS(ADDR_SURF_16_BANK) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1240 break;
1241 case 11: /* Display 16bpp. */
1242 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1246 NUM_BANKS(ADDR_SURF_16_BANK) |
1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1250 break;
1251 case 12: /* Display 32bpp. */
1252 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1253 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1254 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1256 NUM_BANKS(ADDR_SURF_16_BANK) |
1257 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1260 break;
1261 case 13: /* Thin. */
1262 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1263 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1264 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1266 NUM_BANKS(ADDR_SURF_16_BANK) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1270 break;
1271 case 14: /* Thin 8 bpp. */
1272 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1274 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1276 NUM_BANKS(ADDR_SURF_16_BANK) |
1277 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1280 break;
1281 case 15: /* Thin 16 bpp. */
1282 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1283 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1284 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1286 NUM_BANKS(ADDR_SURF_16_BANK) |
1287 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1290 break;
1291 case 16: /* Thin 32 bpp. */
1292 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1293 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1294 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1295 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1296 NUM_BANKS(ADDR_SURF_16_BANK) |
1297 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1298 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1299 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1300 break;
1301 case 17: /* Thin 64 bpp. */
1302 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1303 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1304 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1305 TILE_SPLIT(split_equal_to_row_size) |
1306 NUM_BANKS(ADDR_SURF_16_BANK) |
1307 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1310 break;
1311 case 21: /* 8 bpp PRT. */
1312 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1314 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1315 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1316 NUM_BANKS(ADDR_SURF_16_BANK) |
1317 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1318 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1319 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1320 break;
1321 case 22: /* 16 bpp PRT */
1322 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1323 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1324 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1325 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1326 NUM_BANKS(ADDR_SURF_16_BANK) |
1327 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1330 break;
1331 case 23: /* 32 bpp PRT */
1332 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1333 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1335 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1336 NUM_BANKS(ADDR_SURF_16_BANK) |
1337 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1338 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1339 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1340 break;
1341 case 24: /* 64 bpp PRT */
1342 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1343 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1344 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1345 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1346 NUM_BANKS(ADDR_SURF_16_BANK) |
1347 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1350 break;
1351 case 25: /* 128 bpp PRT */
1352 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1353 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1354 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1355 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1356 NUM_BANKS(ADDR_SURF_8_BANK) |
1357 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1360 break;
1361 default:
1362 gb_tile_moden = 0;
1363 break;
1364 }
1365 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1366 }
1367 } else
1368 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1369}
1370
1a8ca750
AD		 1371static void si_select_se_sh(struct radeon_device *rdev,
1372 u32 se_num, u32 sh_num)
1373{
1374 u32 data = INSTANCE_BROADCAST_WRITES;
1375
1376 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1377 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1378 else if (se_num == 0xffffffff)
1379 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1380 else if (sh_num == 0xffffffff)
1381 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1382 else
1383 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1384 WREG32(GRBM_GFX_INDEX, data);
1385}
1386
1387static u32 si_create_bitmask(u32 bit_width)
1388{
1389 u32 i, mask = 0;
1390
1391 for (i = 0; i < bit_width; i++) {
1392 mask <<= 1;
1393 mask |= 1;
1394 }
1395 return mask;
1396}
1397
1398static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1399{
1400 u32 data, mask;
1401
1402 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1403 if (data & 1)
1404 data &= INACTIVE_CUS_MASK;
1405 else
1406 data = 0;
1407 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1408
1409 data >>= INACTIVE_CUS_SHIFT;
1410
1411 mask = si_create_bitmask(cu_per_sh);
1412
1413 return ~data & mask;
1414}
1415
1416static void si_setup_spi(struct radeon_device *rdev,
1417 u32 se_num, u32 sh_per_se,
1418 u32 cu_per_sh)
1419{
1420 int i, j, k;
1421 u32 data, mask, active_cu;
1422
1423 for (i = 0; i < se_num; i++) {
1424 for (j = 0; j < sh_per_se; j++) {
1425 si_select_se_sh(rdev, i, j);
1426 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1427 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1428
1429 mask = 1;
1430 for (k = 0; k < 16; k++) {
1431 mask <<= k;
1432 if (active_cu & mask) {
1433 data &= ~mask;
1434 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1435 break;
1436 }
1437 }
1438 }
1439 }
1440 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1441}
1442
1443static u32 si_get_rb_disabled(struct radeon_device *rdev,
1444 u32 max_rb_num, u32 se_num,
1445 u32 sh_per_se)
1446{
1447 u32 data, mask;
1448
1449 data = RREG32(CC_RB_BACKEND_DISABLE);
1450 if (data & 1)
1451 data &= BACKEND_DISABLE_MASK;
1452 else
1453 data = 0;
1454 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1455
1456 data >>= BACKEND_DISABLE_SHIFT;
1457
1458 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1459
1460 return data & mask;
1461}
1462
1463static void si_setup_rb(struct radeon_device *rdev,
1464 u32 se_num, u32 sh_per_se,
1465 u32 max_rb_num)
1466{
1467 int i, j;
1468 u32 data, mask;
1469 u32 disabled_rbs = 0;
1470 u32 enabled_rbs = 0;
1471
1472 for (i = 0; i < se_num; i++) {
1473 for (j = 0; j < sh_per_se; j++) {
1474 si_select_se_sh(rdev, i, j);
1475 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1476 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1477 }
1478 }
1479 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1480
1481 mask = 1;
1482 for (i = 0; i < max_rb_num; i++) {
1483 if (!(disabled_rbs & mask))
1484 enabled_rbs |= mask;
1485 mask <<= 1;
1486 }
1487
1488 for (i = 0; i < se_num; i++) {
1489 si_select_se_sh(rdev, i, 0xffffffff);
1490 data = 0;
1491 for (j = 0; j < sh_per_se; j++) {
1492 switch (enabled_rbs & 3) {
1493 case 1:
1494 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1495 break;
1496 case 2:
1497 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1498 break;
1499 case 3:
1500 default:
1501 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1502 break;
1503 }
1504 enabled_rbs >>= 2;
1505 }
1506 WREG32(PA_SC_RASTER_CONFIG, data);
1507 }
1508 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1509}
1510
0a96d72b
AD		 1511static void si_gpu_init(struct radeon_device *rdev)
1512{
0a96d72b
AD		 1513 u32 gb_addr_config = 0;
1514 u32 mc_shared_chmap, mc_arb_ramcfg;
0a96d72b 1515 u32 sx_debug_1;
0a96d72b
AD		 1516 u32 hdp_host_path_cntl;
1517 u32 tmp;
1518 int i, j;
1519
1520 switch (rdev->family) {
1521 case CHIP_TAHITI:
1522 rdev->config.si.max_shader_engines = 2;
0a96d72b 1523 rdev->config.si.max_tile_pipes = 12;
1a8ca750
AD		 1524 rdev->config.si.max_cu_per_sh = 8;
1525 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1526 rdev->config.si.max_backends_per_se = 4;
1527 rdev->config.si.max_texture_channel_caches = 12;
1528 rdev->config.si.max_gprs = 256;
1529 rdev->config.si.max_gs_threads = 32;
1530 rdev->config.si.max_hw_contexts = 8;
1531
1532 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1533 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1534 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1535 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1536 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1537 break;
1538 case CHIP_PITCAIRN:
1539 rdev->config.si.max_shader_engines = 2;
0a96d72b 1540 rdev->config.si.max_tile_pipes = 8;
1a8ca750
AD		 1541 rdev->config.si.max_cu_per_sh = 5;
1542 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1543 rdev->config.si.max_backends_per_se = 4;
1544 rdev->config.si.max_texture_channel_caches = 8;
1545 rdev->config.si.max_gprs = 256;
1546 rdev->config.si.max_gs_threads = 32;
1547 rdev->config.si.max_hw_contexts = 8;
1548
1549 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1550 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1551 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1552 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1553 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1554 break;
1555 case CHIP_VERDE:
1556 default:
1557 rdev->config.si.max_shader_engines = 1;
0a96d72b 1558 rdev->config.si.max_tile_pipes = 4;
1a8ca750
AD		 1559 rdev->config.si.max_cu_per_sh = 2;
1560 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1561 rdev->config.si.max_backends_per_se = 4;
1562 rdev->config.si.max_texture_channel_caches = 4;
1563 rdev->config.si.max_gprs = 256;
1564 rdev->config.si.max_gs_threads = 32;
1565 rdev->config.si.max_hw_contexts = 8;
1566
1567 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1568 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1569 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1570 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1571 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1572 break;
1573 }
1574
1575 /* Initialize HDP */
1576 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1577 WREG32((0x2c14 + j), 0x00000000);
1578 WREG32((0x2c18 + j), 0x00000000);
1579 WREG32((0x2c1c + j), 0x00000000);
1580 WREG32((0x2c20 + j), 0x00000000);
1581 WREG32((0x2c24 + j), 0x00000000);
1582 }
1583
1584 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1585
1586 evergreen_fix_pci_max_read_req_size(rdev);
1587
1588 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1589
1590 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1591 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1592
0a96d72b 1593 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
0a96d72b
AD		 1594 rdev->config.si.mem_max_burst_length_bytes = 256;
1595 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1596 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1597 if (rdev->config.si.mem_row_size_in_kb > 4)
1598 rdev->config.si.mem_row_size_in_kb = 4;
1599 /* XXX use MC settings? */
1600 rdev->config.si.shader_engine_tile_size = 32;
1601 rdev->config.si.num_gpus = 1;
1602 rdev->config.si.multi_gpu_tile_size = 64;
1603
1a8ca750
AD		 1604 /* fix up row size */
1605 gb_addr_config &= ~ROW_SIZE_MASK;
0a96d72b
AD		 1606 switch (rdev->config.si.mem_row_size_in_kb) {
1607 case 1:
1608 default:
1609 gb_addr_config |= ROW_SIZE(0);
1610 break;
1611 case 2:
1612 gb_addr_config |= ROW_SIZE(1);
1613 break;
1614 case 4:
1615 gb_addr_config |= ROW_SIZE(2);
1616 break;
1617 }
1618
0a96d72b
AD		 1619 /* setup tiling info dword. gb_addr_config is not adequate since it does
1620 * not have bank info, so create a custom tiling dword.
1621 * bits 3:0 num_pipes
1622 * bits 7:4 num_banks
1623 * bits 11:8 group_size
1624 * bits 15:12 row_size
1625 */
1626 rdev->config.si.tile_config = 0;
1627 switch (rdev->config.si.num_tile_pipes) {
1628 case 1:
1629 rdev->config.si.tile_config |= (0 << 0);
1630 break;
1631 case 2:
1632 rdev->config.si.tile_config |= (1 << 0);
1633 break;
1634 case 4:
1635 rdev->config.si.tile_config |= (2 << 0);
1636 break;
1637 case 8:
1638 default:
1639 /* XXX what about 12? */
1640 rdev->config.si.tile_config |= (3 << 0);
1641 break;
1642 }
1a8ca750
AD		 1643 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1644 rdev->config.si.tile_config |= 1 << 4;
1645 else
1646 rdev->config.si.tile_config |= 0 << 4;
0a96d72b
AD		 1647 rdev->config.si.tile_config |=
1648 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1649 rdev->config.si.tile_config |=
1650 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1651
0a96d72b
AD		 1652 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1653 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1654 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1655
1a8ca750 1656 si_tiling_mode_table_init(rdev);
0a96d72b 1657
1a8ca750
AD		 1658 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1659 rdev->config.si.max_sh_per_se,
1660 rdev->config.si.max_backends_per_se);
0a96d72b 1661
1a8ca750
AD		 1662 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1663 rdev->config.si.max_sh_per_se,
1664 rdev->config.si.max_cu_per_sh);
0a96d72b 1665
0a96d72b
AD		 1666
1667 /* set HW defaults for 3D engine */
1668 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1669 ROQ_IB2_START(0x2b)));
1670 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1671
1672 sx_debug_1 = RREG32(SX_DEBUG_1);
1673 WREG32(SX_DEBUG_1, sx_debug_1);
1674
1675 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1676
1677 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1678 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1679 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1680 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1681
1682 WREG32(VGT_NUM_INSTANCES, 1);
1683
1684 WREG32(CP_PERFMON_CNTL, 0);
1685
1686 WREG32(SQ_CONFIG, 0);
1687
1688 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1689 FORCE_EOV_MAX_REZ_CNT(255)));
1690
1691 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1692 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1693
1694 WREG32(VGT_GS_VERTEX_REUSE, 16);
1695 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1696
1697 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1698 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1699 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1700 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1701 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1702 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1703 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1704 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1705
1706 tmp = RREG32(HDP_MISC_CNTL);
1707 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1708 WREG32(HDP_MISC_CNTL, tmp);
1709
1710 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1711 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1712
1713 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1714
1715 udelay(50);
1716}
c476dde2 1717
2ece2e8b
AD		 1718/*
1719 * GPU scratch registers helpers function.
1720 */
1721static void si_scratch_init(struct radeon_device *rdev)
1722{
1723 int i;
1724
1725 rdev->scratch.num_reg = 7;
1726 rdev->scratch.reg_base = SCRATCH_REG0;
1727 for (i = 0; i < rdev->scratch.num_reg; i++) {
1728 rdev->scratch.free[i] = true;
1729 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1730 }
1731}
1732
1733void si_fence_ring_emit(struct radeon_device *rdev,
1734 struct radeon_fence *fence)
1735{
1736 struct radeon_ring *ring = &rdev->ring[fence->ring];
1737 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1738
1739 /* flush read cache over gart */
1740 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1741 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1742 radeon_ring_write(ring, 0);
1743 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1744 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1745 PACKET3_TC_ACTION_ENA |
1746 PACKET3_SH_KCACHE_ACTION_ENA |
1747 PACKET3_SH_ICACHE_ACTION_ENA);
1748 radeon_ring_write(ring, 0xFFFFFFFF);
1749 radeon_ring_write(ring, 0);
1750 radeon_ring_write(ring, 10); /* poll interval */
1751 /* EVENT_WRITE_EOP - flush caches, send int */
1752 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1753 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1754 radeon_ring_write(ring, addr & 0xffffffff);
1755 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1756 radeon_ring_write(ring, fence->seq);
1757 radeon_ring_write(ring, 0);
1758}
1759
1760/*
1761 * IB stuff
1762 */
1763void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1764{
876dc9f3 1765 struct radeon_ring *ring = &rdev->ring[ib->ring];
2ece2e8b
AD		 1766 u32 header;
1767
a85a7da4
AD		 1768 if (ib->is_const_ib) {
1769 /* set switch buffer packet before const IB */
1770 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1771 radeon_ring_write(ring, 0);
45df6803 1772
2ece2e8b 1773 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
a85a7da4 1774 } else {
89d35807 1775 u32 next_rptr;
a85a7da4 1776 if (ring->rptr_save_reg) {
89d35807 1777 next_rptr = ring->wptr + 3 + 4 + 8;
a85a7da4
AD		 1778 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1779 radeon_ring_write(ring, ((ring->rptr_save_reg -
1780 PACKET3_SET_CONFIG_REG_START) >> 2));
1781 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1782 } else if (rdev->wb.enabled) {
1783 next_rptr = ring->wptr + 5 + 4 + 8;
1784 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1785 radeon_ring_write(ring, (1 << 8));
1786 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1787 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1788 radeon_ring_write(ring, next_rptr);
a85a7da4
AD		 1789 }
1790
2ece2e8b 1791 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
a85a7da4 1792 }
2ece2e8b
AD		 1793
1794 radeon_ring_write(ring, header);
1795 radeon_ring_write(ring,
1796#ifdef __BIG_ENDIAN
1797 (2 << 0) |
1798#endif
1799 (ib->gpu_addr & 0xFFFFFFFC));
1800 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1801 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1802
a85a7da4
AD		 1803 if (!ib->is_const_ib) {
1804 /* flush read cache over gart for this vmid */
1805 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1806 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1807 radeon_ring_write(ring, ib->vm_id);
1808 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1809 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1810 PACKET3_TC_ACTION_ENA |
1811 PACKET3_SH_KCACHE_ACTION_ENA |
1812 PACKET3_SH_ICACHE_ACTION_ENA);
1813 radeon_ring_write(ring, 0xFFFFFFFF);
1814 radeon_ring_write(ring, 0);
1815 radeon_ring_write(ring, 10); /* poll interval */
1816 }
2ece2e8b
AD		 1817}
1818
48c0c902
AD		 1819/*
1820 * CP.
1821 */
1822static void si_cp_enable(struct radeon_device *rdev, bool enable)
1823{
1824 if (enable)
1825 WREG32(CP_ME_CNTL, 0);
1826 else {
1827 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1828 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1829 WREG32(SCRATCH_UMSK, 0);
1830 }
1831 udelay(50);
1832}
1833
1834static int si_cp_load_microcode(struct radeon_device *rdev)
1835{
1836 const __be32 *fw_data;
1837 int i;
1838
1839 if (!rdev->me_fw || !rdev->pfp_fw)
1840 return -EINVAL;
1841
1842 si_cp_enable(rdev, false);
1843
1844 /* PFP */
1845 fw_data = (const __be32 *)rdev->pfp_fw->data;
1846 WREG32(CP_PFP_UCODE_ADDR, 0);
1847 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1848 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1849 WREG32(CP_PFP_UCODE_ADDR, 0);
1850
1851 /* CE */
1852 fw_data = (const __be32 *)rdev->ce_fw->data;
1853 WREG32(CP_CE_UCODE_ADDR, 0);
1854 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1855 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1856 WREG32(CP_CE_UCODE_ADDR, 0);
1857
1858 /* ME */
1859 fw_data = (const __be32 *)rdev->me_fw->data;
1860 WREG32(CP_ME_RAM_WADDR, 0);
1861 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1862 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1863 WREG32(CP_ME_RAM_WADDR, 0);
1864
1865 WREG32(CP_PFP_UCODE_ADDR, 0);
1866 WREG32(CP_CE_UCODE_ADDR, 0);
1867 WREG32(CP_ME_RAM_WADDR, 0);
1868 WREG32(CP_ME_RAM_RADDR, 0);
1869 return 0;
1870}
1871
1872static int si_cp_start(struct radeon_device *rdev)
1873{
1874 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1875 int r, i;
1876
1877 r = radeon_ring_lock(rdev, ring, 7 + 4);
1878 if (r) {
1879 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1880 return r;
1881 }
1882 /* init the CP */
1883 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1884 radeon_ring_write(ring, 0x1);
1885 radeon_ring_write(ring, 0x0);
1886 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1887 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1888 radeon_ring_write(ring, 0);
1889 radeon_ring_write(ring, 0);
1890
1891 /* init the CE partitions */
1892 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1893 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1894 radeon_ring_write(ring, 0xc000);
1895 radeon_ring_write(ring, 0xe000);
1896 radeon_ring_unlock_commit(rdev, ring);
1897
1898 si_cp_enable(rdev, true);
1899
1900 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1901 if (r) {
1902 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1903 return r;
1904 }
1905
1906 /* setup clear context state */
1907 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1908 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1909
1910 for (i = 0; i < si_default_size; i++)
1911 radeon_ring_write(ring, si_default_state[i]);
1912
1913 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1914 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1915
1916 /* set clear context state */
1917 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1918 radeon_ring_write(ring, 0);
1919
1920 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1921 radeon_ring_write(ring, 0x00000316);
1922 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1923 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1924
1925 radeon_ring_unlock_commit(rdev, ring);
1926
1927 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1928 ring = &rdev->ring[i];
1929 r = radeon_ring_lock(rdev, ring, 2);
1930
1931 /* clear the compute context state */
1932 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
1933 radeon_ring_write(ring, 0);
1934
1935 radeon_ring_unlock_commit(rdev, ring);
1936 }
1937
1938 return 0;
1939}
1940
1941static void si_cp_fini(struct radeon_device *rdev)
1942{
45df6803 1943 struct radeon_ring *ring;
48c0c902 1944 si_cp_enable(rdev, false);
45df6803
CK		 1945
1946 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1947 radeon_ring_fini(rdev, ring);
1948 radeon_scratch_free(rdev, ring->rptr_save_reg);
1949
1950 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1951 radeon_ring_fini(rdev, ring);
1952 radeon_scratch_free(rdev, ring->rptr_save_reg);
1953
1954 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1955 radeon_ring_fini(rdev, ring);
1956 radeon_scratch_free(rdev, ring->rptr_save_reg);
48c0c902
AD		 1957}
1958
1959static int si_cp_resume(struct radeon_device *rdev)
1960{
1961 struct radeon_ring *ring;
1962 u32 tmp;
1963 u32 rb_bufsz;
1964 int r;
1965
1966 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1967 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1968 SOFT_RESET_PA |
1969 SOFT_RESET_VGT |
1970 SOFT_RESET_SPI |
1971 SOFT_RESET_SX));
1972 RREG32(GRBM_SOFT_RESET);
1973 mdelay(15);
1974 WREG32(GRBM_SOFT_RESET, 0);
1975 RREG32(GRBM_SOFT_RESET);
1976
1977 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1978 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1979
1980 /* Set the write pointer delay */
1981 WREG32(CP_RB_WPTR_DELAY, 0);
1982
1983 WREG32(CP_DEBUG, 0);
1984 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1985
1986 /* ring 0 - compute and gfx */
1987 /* Set ring buffer size */
1988 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1989 rb_bufsz = drm_order(ring->ring_size / 8);
1990 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1991#ifdef __BIG_ENDIAN
1992 tmp |= BUF_SWAP_32BIT;
1993#endif
1994 WREG32(CP_RB0_CNTL, tmp);
1995
1996 /* Initialize the ring buffer's read and write pointers */
1997 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1998 ring->wptr = 0;
1999 WREG32(CP_RB0_WPTR, ring->wptr);
2000
2001 /* set the wb address wether it's enabled or not */
2002 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2003 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2004
2005 if (rdev->wb.enabled)
2006 WREG32(SCRATCH_UMSK, 0xff);
2007 else {
2008 tmp |= RB_NO_UPDATE;
2009 WREG32(SCRATCH_UMSK, 0);
2010 }
2011
2012 mdelay(1);
2013 WREG32(CP_RB0_CNTL, tmp);
2014
2015 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2016
2017 ring->rptr = RREG32(CP_RB0_RPTR);
2018
2019 /* ring1 - compute only */
2020 /* Set ring buffer size */
2021 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2022 rb_bufsz = drm_order(ring->ring_size / 8);
2023 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2024#ifdef __BIG_ENDIAN
2025 tmp |= BUF_SWAP_32BIT;
2026#endif
2027 WREG32(CP_RB1_CNTL, tmp);
2028
2029 /* Initialize the ring buffer's read and write pointers */
2030 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2031 ring->wptr = 0;
2032 WREG32(CP_RB1_WPTR, ring->wptr);
2033
2034 /* set the wb address wether it's enabled or not */
2035 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2036 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2037
2038 mdelay(1);
2039 WREG32(CP_RB1_CNTL, tmp);
2040
2041 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2042
2043 ring->rptr = RREG32(CP_RB1_RPTR);
2044
2045 /* ring2 - compute only */
2046 /* Set ring buffer size */
2047 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2048 rb_bufsz = drm_order(ring->ring_size / 8);
2049 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2050#ifdef __BIG_ENDIAN
2051 tmp |= BUF_SWAP_32BIT;
2052#endif
2053 WREG32(CP_RB2_CNTL, tmp);
2054
2055 /* Initialize the ring buffer's read and write pointers */
2056 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2057 ring->wptr = 0;
2058 WREG32(CP_RB2_WPTR, ring->wptr);
2059
2060 /* set the wb address wether it's enabled or not */
2061 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2062 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2063
2064 mdelay(1);
2065 WREG32(CP_RB2_CNTL, tmp);
2066
2067 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2068
2069 ring->rptr = RREG32(CP_RB2_RPTR);
2070
2071 /* start the rings */
2072 si_cp_start(rdev);
2073 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2074 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2075 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2076 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2077 if (r) {
2078 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2079 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2080 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2081 return r;
2082 }
2083 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2084 if (r) {
2085 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2086 }
2087 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2088 if (r) {
2089 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2090 }
2091
2092 return 0;
2093}
2094
c476dde2
AD		 2095bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2096{
2097 u32 srbm_status;
2098 u32 grbm_status, grbm_status2;
2099 u32 grbm_status_se0, grbm_status_se1;
c476dde2
AD		 2100
2101 srbm_status = RREG32(SRBM_STATUS);
2102 grbm_status = RREG32(GRBM_STATUS);
2103 grbm_status2 = RREG32(GRBM_STATUS2);
2104 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2105 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2106 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2107 radeon_ring_lockup_update(ring);
c476dde2
AD		 2108 return false;
2109 }
2110 /* force CP activities */
7b9ef16b 2111 radeon_ring_force_activity(rdev, ring);
069211e5 2112 return radeon_ring_test_lockup(rdev, ring);
c476dde2
AD		 2113}
2114
2115static int si_gpu_soft_reset(struct radeon_device *rdev)
2116{
2117 struct evergreen_mc_save save;
2118 u32 grbm_reset = 0;
2119
2120 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2121 return 0;
2122
2123 dev_info(rdev->dev, "GPU softreset \n");
2124 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2125 RREG32(GRBM_STATUS));
2126 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2127 RREG32(GRBM_STATUS2));
2128 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2129 RREG32(GRBM_STATUS_SE0));
2130 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2131 RREG32(GRBM_STATUS_SE1));
2132 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2133 RREG32(SRBM_STATUS));
2134 evergreen_mc_stop(rdev, &save);
2135 if (radeon_mc_wait_for_idle(rdev)) {
2136 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2137 }
2138 /* Disable CP parsing/prefetching */
2139 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2140
2141 /* reset all the gfx blocks */
2142 grbm_reset = (SOFT_RESET_CP |
2143 SOFT_RESET_CB |
2144 SOFT_RESET_DB |
2145 SOFT_RESET_GDS |
2146 SOFT_RESET_PA |
2147 SOFT_RESET_SC |
6f789301 2148 SOFT_RESET_BCI |
c476dde2
AD		 2149 SOFT_RESET_SPI |
2150 SOFT_RESET_SX |
2151 SOFT_RESET_TC |
2152 SOFT_RESET_TA |
2153 SOFT_RESET_VGT |
2154 SOFT_RESET_IA);
2155
2156 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2157 WREG32(GRBM_SOFT_RESET, grbm_reset);
2158 (void)RREG32(GRBM_SOFT_RESET);
2159 udelay(50);
2160 WREG32(GRBM_SOFT_RESET, 0);
2161 (void)RREG32(GRBM_SOFT_RESET);
2162 /* Wait a little for things to settle down */
2163 udelay(50);
2164 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2165 RREG32(GRBM_STATUS));
2166 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2167 RREG32(GRBM_STATUS2));
2168 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2169 RREG32(GRBM_STATUS_SE0));
2170 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2171 RREG32(GRBM_STATUS_SE1));
2172 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2173 RREG32(SRBM_STATUS));
2174 evergreen_mc_resume(rdev, &save);
2175 return 0;
2176}
2177
2178int si_asic_reset(struct radeon_device *rdev)
2179{
2180 return si_gpu_soft_reset(rdev);
2181}
2182
d2800ee5
AD		 2183/* MC */
2184static void si_mc_program(struct radeon_device *rdev)
2185{
2186 struct evergreen_mc_save save;
2187 u32 tmp;
2188 int i, j;
2189
2190 /* Initialize HDP */
2191 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2192 WREG32((0x2c14 + j), 0x00000000);
2193 WREG32((0x2c18 + j), 0x00000000);
2194 WREG32((0x2c1c + j), 0x00000000);
2195 WREG32((0x2c20 + j), 0x00000000);
2196 WREG32((0x2c24 + j), 0x00000000);
2197 }
2198 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2199
2200 evergreen_mc_stop(rdev, &save);
2201 if (radeon_mc_wait_for_idle(rdev)) {
2202 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2203 }
2204 /* Lockout access through VGA aperture*/
2205 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2206 /* Update configuration */
2207 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2208 rdev->mc.vram_start >> 12);
2209 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2210 rdev->mc.vram_end >> 12);
2211 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2212 rdev->vram_scratch.gpu_addr >> 12);
2213 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2214 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2215 WREG32(MC_VM_FB_LOCATION, tmp);
2216 /* XXX double check these! */
2217 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2218 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2219 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2220 WREG32(MC_VM_AGP_BASE, 0);
2221 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2222 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2223 if (radeon_mc_wait_for_idle(rdev)) {
2224 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2225 }
2226 evergreen_mc_resume(rdev, &save);
2227 /* we need to own VRAM, so turn off the VGA renderer here
2228 * to stop it overwriting our objects */
2229 rv515_vga_render_disable(rdev);
2230}
2231
2232/* SI MC address space is 40 bits */
2233static void si_vram_location(struct radeon_device *rdev,
2234 struct radeon_mc *mc, u64 base)
2235{
2236 mc->vram_start = base;
2237 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2238 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2239 mc->real_vram_size = mc->aper_size;
2240 mc->mc_vram_size = mc->aper_size;
2241 }
2242 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2243 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2244 mc->mc_vram_size >> 20, mc->vram_start,
2245 mc->vram_end, mc->real_vram_size >> 20);
2246}
2247
2248static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2249{
2250 u64 size_af, size_bf;
2251
2252 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2253 size_bf = mc->vram_start & ~mc->gtt_base_align;
2254 if (size_bf > size_af) {
2255 if (mc->gtt_size > size_bf) {
2256 dev_warn(rdev->dev, "limiting GTT\n");
2257 mc->gtt_size = size_bf;
2258 }
2259 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2260 } else {
2261 if (mc->gtt_size > size_af) {
2262 dev_warn(rdev->dev, "limiting GTT\n");
2263 mc->gtt_size = size_af;
2264 }
2265 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2266 }
2267 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2268 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2269 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2270}
2271
2272static void si_vram_gtt_location(struct radeon_device *rdev,
2273 struct radeon_mc *mc)
2274{
2275 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2276 /* leave room for at least 1024M GTT */
2277 dev_warn(rdev->dev, "limiting VRAM\n");
2278 mc->real_vram_size = 0xFFC0000000ULL;
2279 mc->mc_vram_size = 0xFFC0000000ULL;
2280 }
2281 si_vram_location(rdev, &rdev->mc, 0);
2282 rdev->mc.gtt_base_align = 0;
2283 si_gtt_location(rdev, mc);
2284}
2285
2286static int si_mc_init(struct radeon_device *rdev)
2287{
2288 u32 tmp;
2289 int chansize, numchan;
2290
2291 /* Get VRAM informations */
2292 rdev->mc.vram_is_ddr = true;
2293 tmp = RREG32(MC_ARB_RAMCFG);
2294 if (tmp & CHANSIZE_OVERRIDE) {
2295 chansize = 16;
2296 } else if (tmp & CHANSIZE_MASK) {
2297 chansize = 64;
2298 } else {
2299 chansize = 32;
2300 }
2301 tmp = RREG32(MC_SHARED_CHMAP);
2302 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2303 case 0:
2304 default:
2305 numchan = 1;
2306 break;
2307 case 1:
2308 numchan = 2;
2309 break;
2310 case 2:
2311 numchan = 4;
2312 break;
2313 case 3:
2314 numchan = 8;
2315 break;
2316 case 4:
2317 numchan = 3;
2318 break;
2319 case 5:
2320 numchan = 6;
2321 break;
2322 case 6:
2323 numchan = 10;
2324 break;
2325 case 7:
2326 numchan = 12;
2327 break;
2328 case 8:
2329 numchan = 16;
2330 break;
2331 }
2332 rdev->mc.vram_width = numchan * chansize;
2333 /* Could aper size report 0 ? */
2334 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2335 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2336 /* size in MB on si */
2337 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2338 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2339 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2340 si_vram_gtt_location(rdev, &rdev->mc);
2341 radeon_update_bandwidth_info(rdev);
2342
2343 return 0;
2344}
2345
2346/*
2347 * GART
2348 */
2349void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2350{
2351 /* flush hdp cache */
2352 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2353
2354 /* bits 0-15 are the VM contexts0-15 */
2355 WREG32(VM_INVALIDATE_REQUEST, 1);
2356}
2357
2358int si_pcie_gart_enable(struct radeon_device *rdev)
2359{
2360 int r, i;
2361
2362 if (rdev->gart.robj == NULL) {
2363 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2364 return -EINVAL;
2365 }
2366 r = radeon_gart_table_vram_pin(rdev);
2367 if (r)
2368 return r;
2369 radeon_gart_restore(rdev);
2370 /* Setup TLB control */
2371 WREG32(MC_VM_MX_L1_TLB_CNTL,
2372 (0xA << 7) |
2373 ENABLE_L1_TLB |
2374 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2375 ENABLE_ADVANCED_DRIVER_MODEL |
2376 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2377 /* Setup L2 cache */
2378 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2379 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2380 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2381 EFFECTIVE_L2_QUEUE_SIZE(7) |
2382 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2383 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2384 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2385 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2386 /* setup context0 */
2387 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2388 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2389 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2390 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2391 (u32)(rdev->dummy_page.addr >> 12));
2392 WREG32(VM_CONTEXT0_CNTL2, 0);
2393 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2394 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2395
2396 WREG32(0x15D4, 0);
2397 WREG32(0x15D8, 0);
2398 WREG32(0x15DC, 0);
2399
2400 /* empty context1-15 */
c21b328e 2401 /* FIXME start with 4G, once using 2 level pt switch to full
d2800ee5
AD		 2402 * vm size space
2403 */
2404 /* set vm size, must be a multiple of 4 */
2405 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
c21b328e 2406 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
d2800ee5
AD		 2407 for (i = 1; i < 16; i++) {
2408 if (i < 8)
2409 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2410 rdev->gart.table_addr >> 12);
2411 else
2412 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2413 rdev->gart.table_addr >> 12);
2414 }
2415
2416 /* enable context1-15 */
2417 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2418 (u32)(rdev->dummy_page.addr >> 12));
2419 WREG32(VM_CONTEXT1_CNTL2, 0);
2420 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2421 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2422
2423 si_pcie_gart_tlb_flush(rdev);
2424 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2425 (unsigned)(rdev->mc.gtt_size >> 20),
2426 (unsigned long long)rdev->gart.table_addr);
2427 rdev->gart.ready = true;
2428 return 0;
2429}
2430
2431void si_pcie_gart_disable(struct radeon_device *rdev)
2432{
2433 /* Disable all tables */
2434 WREG32(VM_CONTEXT0_CNTL, 0);
2435 WREG32(VM_CONTEXT1_CNTL, 0);
2436 /* Setup TLB control */
2437 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2438 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2439 /* Setup L2 cache */
2440 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2441 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2442 EFFECTIVE_L2_QUEUE_SIZE(7) |
2443 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2444 WREG32(VM_L2_CNTL2, 0);
2445 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2446 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2447 radeon_gart_table_vram_unpin(rdev);
2448}
2449
2450void si_pcie_gart_fini(struct radeon_device *rdev)
2451{
2452 si_pcie_gart_disable(rdev);
2453 radeon_gart_table_vram_free(rdev);
2454 radeon_gart_fini(rdev);
2455}
2456
498dd8b3
AD		 2457/* vm parser */
2458static bool si_vm_reg_valid(u32 reg)
2459{
2460 /* context regs are fine */
2461 if (reg >= 0x28000)
2462 return true;
2463
2464 /* check config regs */
2465 switch (reg) {
2466 case GRBM_GFX_INDEX:
2467 case VGT_VTX_VECT_EJECT_REG:
2468 case VGT_CACHE_INVALIDATION:
2469 case VGT_ESGS_RING_SIZE:
2470 case VGT_GSVS_RING_SIZE:
2471 case VGT_GS_VERTEX_REUSE:
2472 case VGT_PRIMITIVE_TYPE:
2473 case VGT_INDEX_TYPE:
2474 case VGT_NUM_INDICES:
2475 case VGT_NUM_INSTANCES:
2476 case VGT_TF_RING_SIZE:
2477 case VGT_HS_OFFCHIP_PARAM:
2478 case VGT_TF_MEMORY_BASE:
2479 case PA_CL_ENHANCE:
2480 case PA_SU_LINE_STIPPLE_VALUE:
2481 case PA_SC_LINE_STIPPLE_STATE:
2482 case PA_SC_ENHANCE:
2483 case SQC_CACHES:
2484 case SPI_STATIC_THREAD_MGMT_1:
2485 case SPI_STATIC_THREAD_MGMT_2:
2486 case SPI_STATIC_THREAD_MGMT_3:
2487 case SPI_PS_MAX_WAVE_ID:
2488 case SPI_CONFIG_CNTL:
2489 case SPI_CONFIG_CNTL_1:
2490 case TA_CNTL_AUX:
2491 return true;
2492 default:
2493 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2494 return false;
2495 }
2496}
2497
2498static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2499 u32 *ib, struct radeon_cs_packet *pkt)
2500{
2501 switch (pkt->opcode) {
2502 case PACKET3_NOP:
2503 case PACKET3_SET_BASE:
2504 case PACKET3_SET_CE_DE_COUNTERS:
2505 case PACKET3_LOAD_CONST_RAM:
2506 case PACKET3_WRITE_CONST_RAM:
2507 case PACKET3_WRITE_CONST_RAM_OFFSET:
2508 case PACKET3_DUMP_CONST_RAM:
2509 case PACKET3_INCREMENT_CE_COUNTER:
2510 case PACKET3_WAIT_ON_DE_COUNTER:
2511 case PACKET3_CE_WRITE:
2512 break;
2513 default:
2514 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2515 return -EINVAL;
2516 }
2517 return 0;
2518}
2519
2520static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2521 u32 *ib, struct radeon_cs_packet *pkt)
2522{
2523 u32 idx = pkt->idx + 1;
2524 u32 idx_value = ib[idx];
2525 u32 start_reg, end_reg, reg, i;
2526
2527 switch (pkt->opcode) {
2528 case PACKET3_NOP:
2529 case PACKET3_SET_BASE:
2530 case PACKET3_CLEAR_STATE:
2531 case PACKET3_INDEX_BUFFER_SIZE:
2532 case PACKET3_DISPATCH_DIRECT:
2533 case PACKET3_DISPATCH_INDIRECT:
2534 case PACKET3_ALLOC_GDS:
2535 case PACKET3_WRITE_GDS_RAM:
2536 case PACKET3_ATOMIC_GDS:
2537 case PACKET3_ATOMIC:
2538 case PACKET3_OCCLUSION_QUERY:
2539 case PACKET3_SET_PREDICATION:
2540 case PACKET3_COND_EXEC:
2541 case PACKET3_PRED_EXEC:
2542 case PACKET3_DRAW_INDIRECT:
2543 case PACKET3_DRAW_INDEX_INDIRECT:
2544 case PACKET3_INDEX_BASE:
2545 case PACKET3_DRAW_INDEX_2:
2546 case PACKET3_CONTEXT_CONTROL:
2547 case PACKET3_INDEX_TYPE:
2548 case PACKET3_DRAW_INDIRECT_MULTI:
2549 case PACKET3_DRAW_INDEX_AUTO:
2550 case PACKET3_DRAW_INDEX_IMMD:
2551 case PACKET3_NUM_INSTANCES:
2552 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2553 case PACKET3_STRMOUT_BUFFER_UPDATE:
2554 case PACKET3_DRAW_INDEX_OFFSET_2:
2555 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2556 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2557 case PACKET3_MPEG_INDEX:
2558 case PACKET3_WAIT_REG_MEM:
2559 case PACKET3_MEM_WRITE:
2560 case PACKET3_PFP_SYNC_ME:
2561 case PACKET3_SURFACE_SYNC:
2562 case PACKET3_EVENT_WRITE:
2563 case PACKET3_EVENT_WRITE_EOP:
2564 case PACKET3_EVENT_WRITE_EOS:
2565 case PACKET3_SET_CONTEXT_REG:
2566 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2567 case PACKET3_SET_SH_REG:
2568 case PACKET3_SET_SH_REG_OFFSET:
2569 case PACKET3_INCREMENT_DE_COUNTER:
2570 case PACKET3_WAIT_ON_CE_COUNTER:
2571 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2572 case PACKET3_ME_WRITE:
2573 break;
2574 case PACKET3_COPY_DATA:
2575 if ((idx_value & 0xf00) == 0) {
2576 reg = ib[idx + 3] * 4;
2577 if (!si_vm_reg_valid(reg))
2578 return -EINVAL;
2579 }
2580 break;
2581 case PACKET3_WRITE_DATA:
2582 if ((idx_value & 0xf00) == 0) {
2583 start_reg = ib[idx + 1] * 4;
2584 if (idx_value & 0x10000) {
2585 if (!si_vm_reg_valid(start_reg))
2586 return -EINVAL;
2587 } else {
2588 for (i = 0; i < (pkt->count - 2); i++) {
2589 reg = start_reg + (4 * i);
2590 if (!si_vm_reg_valid(reg))
2591 return -EINVAL;
2592 }
2593 }
2594 }
2595 break;
2596 case PACKET3_COND_WRITE:
2597 if (idx_value & 0x100) {
2598 reg = ib[idx + 5] * 4;
2599 if (!si_vm_reg_valid(reg))
2600 return -EINVAL;
2601 }
2602 break;
2603 case PACKET3_COPY_DW:
2604 if (idx_value & 0x2) {
2605 reg = ib[idx + 3] * 4;
2606 if (!si_vm_reg_valid(reg))
2607 return -EINVAL;
2608 }
2609 break;
2610 case PACKET3_SET_CONFIG_REG:
2611 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2612 end_reg = 4 * pkt->count + start_reg - 4;
2613 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2614 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2615 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2616 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2617 return -EINVAL;
2618 }
2619 for (i = 0; i < pkt->count; i++) {
2620 reg = start_reg + (4 * i);
2621 if (!si_vm_reg_valid(reg))
2622 return -EINVAL;
2623 }
2624 break;
2625 default:
2626 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2627 return -EINVAL;
2628 }
2629 return 0;
2630}
2631
2632static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2633 u32 *ib, struct radeon_cs_packet *pkt)
2634{
2635 u32 idx = pkt->idx + 1;
2636 u32 idx_value = ib[idx];
2637 u32 start_reg, reg, i;
2638
2639 switch (pkt->opcode) {
2640 case PACKET3_NOP:
2641 case PACKET3_SET_BASE:
2642 case PACKET3_CLEAR_STATE:
2643 case PACKET3_DISPATCH_DIRECT:
2644 case PACKET3_DISPATCH_INDIRECT:
2645 case PACKET3_ALLOC_GDS:
2646 case PACKET3_WRITE_GDS_RAM:
2647 case PACKET3_ATOMIC_GDS:
2648 case PACKET3_ATOMIC:
2649 case PACKET3_OCCLUSION_QUERY:
2650 case PACKET3_SET_PREDICATION:
2651 case PACKET3_COND_EXEC:
2652 case PACKET3_PRED_EXEC:
2653 case PACKET3_CONTEXT_CONTROL:
2654 case PACKET3_STRMOUT_BUFFER_UPDATE:
2655 case PACKET3_WAIT_REG_MEM:
2656 case PACKET3_MEM_WRITE:
2657 case PACKET3_PFP_SYNC_ME:
2658 case PACKET3_SURFACE_SYNC:
2659 case PACKET3_EVENT_WRITE:
2660 case PACKET3_EVENT_WRITE_EOP:
2661 case PACKET3_EVENT_WRITE_EOS:
2662 case PACKET3_SET_CONTEXT_REG:
2663 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2664 case PACKET3_SET_SH_REG:
2665 case PACKET3_SET_SH_REG_OFFSET:
2666 case PACKET3_INCREMENT_DE_COUNTER:
2667 case PACKET3_WAIT_ON_CE_COUNTER:
2668 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2669 case PACKET3_ME_WRITE:
2670 break;
2671 case PACKET3_COPY_DATA:
2672 if ((idx_value & 0xf00) == 0) {
2673 reg = ib[idx + 3] * 4;
2674 if (!si_vm_reg_valid(reg))
2675 return -EINVAL;
2676 }
2677 break;
2678 case PACKET3_WRITE_DATA:
2679 if ((idx_value & 0xf00) == 0) {
2680 start_reg = ib[idx + 1] * 4;
2681 if (idx_value & 0x10000) {
2682 if (!si_vm_reg_valid(start_reg))
2683 return -EINVAL;
2684 } else {
2685 for (i = 0; i < (pkt->count - 2); i++) {
2686 reg = start_reg + (4 * i);
2687 if (!si_vm_reg_valid(reg))
2688 return -EINVAL;
2689 }
2690 }
2691 }
2692 break;
2693 case PACKET3_COND_WRITE:
2694 if (idx_value & 0x100) {
2695 reg = ib[idx + 5] * 4;
2696 if (!si_vm_reg_valid(reg))
2697 return -EINVAL;
2698 }
2699 break;
2700 case PACKET3_COPY_DW:
2701 if (idx_value & 0x2) {
2702 reg = ib[idx + 3] * 4;
2703 if (!si_vm_reg_valid(reg))
2704 return -EINVAL;
2705 }
2706 break;
2707 default:
2708 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2709 return -EINVAL;
2710 }
2711 return 0;
2712}
2713
2714int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2715{
2716 int ret = 0;
2717 u32 idx = 0;
2718 struct radeon_cs_packet pkt;
2719
2720 do {
2721 pkt.idx = idx;
2722 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2723 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2724 pkt.one_reg_wr = 0;
2725 switch (pkt.type) {
2726 case PACKET_TYPE0:
2727 dev_err(rdev->dev, "Packet0 not allowed!\n");
2728 ret = -EINVAL;
2729 break;
2730 case PACKET_TYPE2:
2731 idx += 1;
2732 break;
2733 case PACKET_TYPE3:
2734 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2735 if (ib->is_const_ib)
2736 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2737 else {
876dc9f3 2738 switch (ib->ring) {
498dd8b3
AD		 2739 case RADEON_RING_TYPE_GFX_INDEX:
2740 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2741 break;
2742 case CAYMAN_RING_TYPE_CP1_INDEX:
2743 case CAYMAN_RING_TYPE_CP2_INDEX:
2744 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2745 break;
2746 default:
876dc9f3 2747 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
498dd8b3
AD		 2748 ret = -EINVAL;
2749 break;
2750 }
2751 }
2752 idx += pkt.count + 2;
2753 break;
2754 default:
2755 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2756 ret = -EINVAL;
2757 break;
2758 }
2759 if (ret)
2760 break;
2761 } while (idx < ib->length_dw);
2762
2763 return ret;
2764}
2765
d2800ee5
AD		 2766/*
2767 * vm
2768 */
2769int si_vm_init(struct radeon_device *rdev)
2770{
2771 /* number of VMs */
2772 rdev->vm_manager.nvm = 16;
2773 /* base offset of vram pages */
2774 rdev->vm_manager.vram_base_offset = 0;
2775
2776 return 0;
2777}
2778
2779void si_vm_fini(struct radeon_device *rdev)
2780{
2781}
2782
2783int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
2784{
2785 if (id < 8)
2786 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
2787 else
2788 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
2789 vm->pt_gpu_addr >> 12);
2790 /* flush hdp cache */
2791 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2792 /* bits 0-15 are the VM contexts0-15 */
2793 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
2794 return 0;
2795}
2796
2797void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
2798{
2799 if (vm->id < 8)
2800 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
2801 else
2802 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
2803 /* flush hdp cache */
2804 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2805 /* bits 0-15 are the VM contexts0-15 */
2806 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2807}
2808
2809void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
2810{
2811 if (vm->id == -1)
2812 return;
2813
2814 /* flush hdp cache */
2815 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2816 /* bits 0-15 are the VM contexts0-15 */
2817 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2818}
2819
347e7592
AD		 2820/*
2821 * RLC
2822 */
c420c745 2823void si_rlc_fini(struct radeon_device *rdev)
347e7592
AD		 2824{
2825 int r;
2826
2827 /* save restore block */
2828 if (rdev->rlc.save_restore_obj) {
2829 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2830 if (unlikely(r != 0))
2831 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
2832 radeon_bo_unpin(rdev->rlc.save_restore_obj);
2833 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2834
2835 radeon_bo_unref(&rdev->rlc.save_restore_obj);
2836 rdev->rlc.save_restore_obj = NULL;
2837 }
2838
2839 /* clear state block */
2840 if (rdev->rlc.clear_state_obj) {
2841 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
2842 if (unlikely(r != 0))
2843 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
2844 radeon_bo_unpin(rdev->rlc.clear_state_obj);
2845 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
2846
2847 radeon_bo_unref(&rdev->rlc.clear_state_obj);
2848 rdev->rlc.clear_state_obj = NULL;
2849 }
2850}
2851
c420c745 2852int si_rlc_init(struct radeon_device *rdev)
347e7592
AD		 2853{
2854 int r;
2855
2856 /* save restore block */
2857 if (rdev->rlc.save_restore_obj == NULL) {
2858 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 2859 RADEON_GEM_DOMAIN_VRAM, NULL,
2860 &rdev->rlc.save_restore_obj);
347e7592
AD		 2861 if (r) {
2862 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
2863 return r;
2864 }
2865 }
2866
2867 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2868 if (unlikely(r != 0)) {
2869 si_rlc_fini(rdev);
2870 return r;
2871 }
2872 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
2873 &rdev->rlc.save_restore_gpu_addr);
5273db70 2874 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
347e7592 2875 if (r) {
347e7592
AD		 2876 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
2877 si_rlc_fini(rdev);
2878 return r;
2879 }
2880
2881 /* clear state block */
2882 if (rdev->rlc.clear_state_obj == NULL) {
2883 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 2884 RADEON_GEM_DOMAIN_VRAM, NULL,
2885 &rdev->rlc.clear_state_obj);
347e7592
AD		 2886 if (r) {
2887 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
2888 si_rlc_fini(rdev);
2889 return r;
2890 }
2891 }
2892 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
2893 if (unlikely(r != 0)) {
2894 si_rlc_fini(rdev);
2895 return r;
2896 }
2897 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
2898 &rdev->rlc.clear_state_gpu_addr);
5273db70 2899 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
347e7592 2900 if (r) {
347e7592
AD		 2901 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
2902 si_rlc_fini(rdev);
2903 return r;
2904 }
2905
2906 return 0;
2907}
2908
2909static void si_rlc_stop(struct radeon_device *rdev)
2910{
2911 WREG32(RLC_CNTL, 0);
2912}
2913
2914static void si_rlc_start(struct radeon_device *rdev)
2915{
2916 WREG32(RLC_CNTL, RLC_ENABLE);
2917}
2918
2919static int si_rlc_resume(struct radeon_device *rdev)
2920{
2921 u32 i;
2922 const __be32 *fw_data;
2923
2924 if (!rdev->rlc_fw)
2925 return -EINVAL;
2926
2927 si_rlc_stop(rdev);
2928
2929 WREG32(RLC_RL_BASE, 0);
2930 WREG32(RLC_RL_SIZE, 0);
2931 WREG32(RLC_LB_CNTL, 0);
2932 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2933 WREG32(RLC_LB_CNTR_INIT, 0);
2934
2935 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2936 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2937
2938 WREG32(RLC_MC_CNTL, 0);
2939 WREG32(RLC_UCODE_CNTL, 0);
2940
2941 fw_data = (const __be32 *)rdev->rlc_fw->data;
2942 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
2943 WREG32(RLC_UCODE_ADDR, i);
2944 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2945 }
2946 WREG32(RLC_UCODE_ADDR, 0);
2947
2948 si_rlc_start(rdev);
2949
2950 return 0;
2951}
2952
25a857fb
AD		 2953static void si_enable_interrupts(struct radeon_device *rdev)
2954{
2955 u32 ih_cntl = RREG32(IH_CNTL);
2956 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2957
2958 ih_cntl |= ENABLE_INTR;
2959 ih_rb_cntl |= IH_RB_ENABLE;
2960 WREG32(IH_CNTL, ih_cntl);
2961 WREG32(IH_RB_CNTL, ih_rb_cntl);
2962 rdev->ih.enabled = true;
2963}
2964
2965static void si_disable_interrupts(struct radeon_device *rdev)
2966{
2967 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2968 u32 ih_cntl = RREG32(IH_CNTL);
2969
2970 ih_rb_cntl &= ~IH_RB_ENABLE;
2971 ih_cntl &= ~ENABLE_INTR;
2972 WREG32(IH_RB_CNTL, ih_rb_cntl);
2973 WREG32(IH_CNTL, ih_cntl);
2974 /* set rptr, wptr to 0 */
2975 WREG32(IH_RB_RPTR, 0);
2976 WREG32(IH_RB_WPTR, 0);
2977 rdev->ih.enabled = false;
25a857fb
AD		 2978 rdev->ih.rptr = 0;
2979}
2980
2981static void si_disable_interrupt_state(struct radeon_device *rdev)
2982{
2983 u32 tmp;
2984
2985 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2986 WREG32(CP_INT_CNTL_RING1, 0);
2987 WREG32(CP_INT_CNTL_RING2, 0);
2988 WREG32(GRBM_INT_CNTL, 0);
2989 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2990 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2991 if (rdev->num_crtc >= 4) {
2992 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2993 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2994 }
2995 if (rdev->num_crtc >= 6) {
2996 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2997 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2998 }
2999
3000 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3001 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3002 if (rdev->num_crtc >= 4) {
3003 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3004 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3005 }
3006 if (rdev->num_crtc >= 6) {
3007 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3008 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3009 }
3010
3011 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3012
3013 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3014 WREG32(DC_HPD1_INT_CONTROL, tmp);
3015 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3016 WREG32(DC_HPD2_INT_CONTROL, tmp);
3017 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3018 WREG32(DC_HPD3_INT_CONTROL, tmp);
3019 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3020 WREG32(DC_HPD4_INT_CONTROL, tmp);
3021 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3022 WREG32(DC_HPD5_INT_CONTROL, tmp);
3023 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3024 WREG32(DC_HPD6_INT_CONTROL, tmp);
3025
3026}
3027
3028static int si_irq_init(struct radeon_device *rdev)
3029{
3030 int ret = 0;
3031 int rb_bufsz;
3032 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3033
3034 /* allocate ring */
3035 ret = r600_ih_ring_alloc(rdev);
3036 if (ret)
3037 return ret;
3038
3039 /* disable irqs */
3040 si_disable_interrupts(rdev);
3041
3042 /* init rlc */
3043 ret = si_rlc_resume(rdev);
3044 if (ret) {
3045 r600_ih_ring_fini(rdev);
3046 return ret;
3047 }
3048
3049 /* setup interrupt control */
3050 /* set dummy read address to ring address */
3051 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3052 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3053 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3054 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3055 */
3056 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3057 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3058 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3059 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3060
3061 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3062 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3063
3064 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3065 IH_WPTR_OVERFLOW_CLEAR |
3066 (rb_bufsz << 1));
3067
3068 if (rdev->wb.enabled)
3069 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3070
3071 /* set the writeback address whether it's enabled or not */
3072 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3073 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3074
3075 WREG32(IH_RB_CNTL, ih_rb_cntl);
3076
3077 /* set rptr, wptr to 0 */
3078 WREG32(IH_RB_RPTR, 0);
3079 WREG32(IH_RB_WPTR, 0);
3080
3081 /* Default settings for IH_CNTL (disabled at first) */
3082 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3083 /* RPTR_REARM only works if msi's are enabled */
3084 if (rdev->msi_enabled)
3085 ih_cntl |= RPTR_REARM;
3086 WREG32(IH_CNTL, ih_cntl);
3087
3088 /* force the active interrupt state to all disabled */
3089 si_disable_interrupt_state(rdev);
3090
2099810f
DA		 3091 pci_set_master(rdev->pdev);
3092
25a857fb
AD		 3093 /* enable irqs */
3094 si_enable_interrupts(rdev);
3095
3096 return ret;
3097}
3098
3099int si_irq_set(struct radeon_device *rdev)
3100{
3101 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3102 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3103 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3104 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3105 u32 grbm_int_cntl = 0;
3106 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3107
3108 if (!rdev->irq.installed) {
3109 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3110 return -EINVAL;
3111 }
3112 /* don't enable anything if the ih is disabled */
3113 if (!rdev->ih.enabled) {
3114 si_disable_interrupts(rdev);
3115 /* force the active interrupt state to all disabled */
3116 si_disable_interrupt_state(rdev);
3117 return 0;
3118 }
3119
3120 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3121 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3122 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3123 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3124 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3125 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3126
3127 /* enable CP interrupts on all rings */
736fc37f 3128 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
25a857fb
AD		 3129 DRM_DEBUG("si_irq_set: sw int gfx\n");
3130 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3131 }
736fc37f 3132 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
25a857fb
AD		 3133 DRM_DEBUG("si_irq_set: sw int cp1\n");
3134 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3135 }
736fc37f 3136 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
25a857fb
AD		 3137 DRM_DEBUG("si_irq_set: sw int cp2\n");
3138 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3139 }
3140 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3141 atomic_read(&rdev->irq.pflip[0])) {
25a857fb
AD		 3142 DRM_DEBUG("si_irq_set: vblank 0\n");
3143 crtc1 |= VBLANK_INT_MASK;
3144 }
3145 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3146 atomic_read(&rdev->irq.pflip[1])) {
25a857fb
AD		 3147 DRM_DEBUG("si_irq_set: vblank 1\n");
3148 crtc2 |= VBLANK_INT_MASK;
3149 }
3150 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3151 atomic_read(&rdev->irq.pflip[2])) {
25a857fb
AD		 3152 DRM_DEBUG("si_irq_set: vblank 2\n");
3153 crtc3 |= VBLANK_INT_MASK;
3154 }
3155 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3156 atomic_read(&rdev->irq.pflip[3])) {
25a857fb
AD		 3157 DRM_DEBUG("si_irq_set: vblank 3\n");
3158 crtc4 |= VBLANK_INT_MASK;
3159 }
3160 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3161 atomic_read(&rdev->irq.pflip[4])) {
25a857fb
AD		 3162 DRM_DEBUG("si_irq_set: vblank 4\n");
3163 crtc5 |= VBLANK_INT_MASK;
3164 }
3165 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3166 atomic_read(&rdev->irq.pflip[5])) {
25a857fb
AD		 3167 DRM_DEBUG("si_irq_set: vblank 5\n");
3168 crtc6 |= VBLANK_INT_MASK;
3169 }
3170 if (rdev->irq.hpd[0]) {
3171 DRM_DEBUG("si_irq_set: hpd 1\n");
3172 hpd1 |= DC_HPDx_INT_EN;
3173 }
3174 if (rdev->irq.hpd[1]) {
3175 DRM_DEBUG("si_irq_set: hpd 2\n");
3176 hpd2 |= DC_HPDx_INT_EN;
3177 }
3178 if (rdev->irq.hpd[2]) {
3179 DRM_DEBUG("si_irq_set: hpd 3\n");
3180 hpd3 |= DC_HPDx_INT_EN;
3181 }
3182 if (rdev->irq.hpd[3]) {
3183 DRM_DEBUG("si_irq_set: hpd 4\n");
3184 hpd4 |= DC_HPDx_INT_EN;
3185 }
3186 if (rdev->irq.hpd[4]) {
3187 DRM_DEBUG("si_irq_set: hpd 5\n");
3188 hpd5 |= DC_HPDx_INT_EN;
3189 }
3190 if (rdev->irq.hpd[5]) {
3191 DRM_DEBUG("si_irq_set: hpd 6\n");
3192 hpd6 |= DC_HPDx_INT_EN;
3193 }
3194 if (rdev->irq.gui_idle) {
3195 DRM_DEBUG("gui idle\n");
3196 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3197 }
3198
3199 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3200 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3201 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3202
3203 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3204
3205 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3206 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3207 if (rdev->num_crtc >= 4) {
3208 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3209 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3210 }
3211 if (rdev->num_crtc >= 6) {
3212 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3213 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3214 }
3215
3216 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3217 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3218 if (rdev->num_crtc >= 4) {
3219 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3220 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3221 }
3222 if (rdev->num_crtc >= 6) {
3223 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3224 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3225 }
3226
3227 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3228 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3229 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3230 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3231 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3232 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3233
3234 return 0;
3235}
3236
3237static inline void si_irq_ack(struct radeon_device *rdev)
3238{
3239 u32 tmp;
3240
3241 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3242 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3243 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3244 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3245 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3246 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3247 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3248 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3249 if (rdev->num_crtc >= 4) {
3250 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3251 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3252 }
3253 if (rdev->num_crtc >= 6) {
3254 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3255 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3256 }
3257
3258 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3259 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3260 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3261 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3262 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3263 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3264 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3265 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3266 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3267 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3268 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3269 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3270
3271 if (rdev->num_crtc >= 4) {
3272 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3273 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3274 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3275 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3276 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3277 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3278 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3279 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3280 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3281 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3282 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3283 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3284 }
3285
3286 if (rdev->num_crtc >= 6) {
3287 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3288 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3289 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3290 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3291 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3292 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3293 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3294 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3295 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3296 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3297 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3298 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3299 }
3300
3301 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3302 tmp = RREG32(DC_HPD1_INT_CONTROL);
3303 tmp |= DC_HPDx_INT_ACK;
3304 WREG32(DC_HPD1_INT_CONTROL, tmp);
3305 }
3306 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3307 tmp = RREG32(DC_HPD2_INT_CONTROL);
3308 tmp |= DC_HPDx_INT_ACK;
3309 WREG32(DC_HPD2_INT_CONTROL, tmp);
3310 }
3311 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3312 tmp = RREG32(DC_HPD3_INT_CONTROL);
3313 tmp |= DC_HPDx_INT_ACK;
3314 WREG32(DC_HPD3_INT_CONTROL, tmp);
3315 }
3316 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3317 tmp = RREG32(DC_HPD4_INT_CONTROL);
3318 tmp |= DC_HPDx_INT_ACK;
3319 WREG32(DC_HPD4_INT_CONTROL, tmp);
3320 }
3321 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3322 tmp = RREG32(DC_HPD5_INT_CONTROL);
3323 tmp |= DC_HPDx_INT_ACK;
3324 WREG32(DC_HPD5_INT_CONTROL, tmp);
3325 }
3326 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3327 tmp = RREG32(DC_HPD5_INT_CONTROL);
3328 tmp |= DC_HPDx_INT_ACK;
3329 WREG32(DC_HPD6_INT_CONTROL, tmp);
3330 }
3331}
3332
3333static void si_irq_disable(struct radeon_device *rdev)
3334{
3335 si_disable_interrupts(rdev);
3336 /* Wait and acknowledge irq */
3337 mdelay(1);
3338 si_irq_ack(rdev);
3339 si_disable_interrupt_state(rdev);
3340}
3341
3342static void si_irq_suspend(struct radeon_device *rdev)
3343{
3344 si_irq_disable(rdev);
3345 si_rlc_stop(rdev);
3346}
3347
9b136d51
AD		 3348static void si_irq_fini(struct radeon_device *rdev)
3349{
3350 si_irq_suspend(rdev);
3351 r600_ih_ring_fini(rdev);
3352}
3353
25a857fb
AD		 3354static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3355{
3356 u32 wptr, tmp;
3357
3358 if (rdev->wb.enabled)
3359 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3360 else
3361 wptr = RREG32(IH_RB_WPTR);
3362
3363 if (wptr & RB_OVERFLOW) {
3364 /* When a ring buffer overflow happen start parsing interrupt
3365 * from the last not overwritten vector (wptr + 16). Hopefully
3366 * this should allow us to catchup.
3367 */
3368 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3369 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3370 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3371 tmp = RREG32(IH_RB_CNTL);
3372 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3373 WREG32(IH_RB_CNTL, tmp);
3374 }
3375 return (wptr & rdev->ih.ptr_mask);
3376}
3377
3378/* SI IV Ring
3379 * Each IV ring entry is 128 bits:
3380 * [7:0] - interrupt source id
3381 * [31:8] - reserved
3382 * [59:32] - interrupt source data
3383 * [63:60] - reserved
3384 * [71:64] - RINGID
3385 * [79:72] - VMID
3386 * [127:80] - reserved
3387 */
3388int si_irq_process(struct radeon_device *rdev)
3389{
3390 u32 wptr;
3391 u32 rptr;
3392 u32 src_id, src_data, ring_id;
3393 u32 ring_index;
25a857fb
AD		 3394 bool queue_hotplug = false;
3395
3396 if (!rdev->ih.enabled || rdev->shutdown)
3397 return IRQ_NONE;
3398
3399 wptr = si_get_ih_wptr(rdev);
c20dc369
CK		 3400
3401restart_ih:
3402 /* is somebody else already processing irqs? */
3403 if (atomic_xchg(&rdev->ih.lock, 1))
3404 return IRQ_NONE;
3405
25a857fb
AD		 3406 rptr = rdev->ih.rptr;
3407 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3408
25a857fb
AD		 3409 /* Order reading of wptr vs. reading of IH ring data */
3410 rmb();
3411
3412 /* display interrupts */
3413 si_irq_ack(rdev);
3414
25a857fb
AD		 3415 while (rptr != wptr) {
3416 /* wptr/rptr are in bytes! */
3417 ring_index = rptr / 4;
3418 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3419 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3420 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3421
3422 switch (src_id) {
3423 case 1: /* D1 vblank/vline */
3424 switch (src_data) {
3425 case 0: /* D1 vblank */
3426 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3427 if (rdev->irq.crtc_vblank_int[0]) {
3428 drm_handle_vblank(rdev->ddev, 0);
3429 rdev->pm.vblank_sync = true;
3430 wake_up(&rdev->irq.vblank_queue);
3431 }
736fc37f 3432 if (atomic_read(&rdev->irq.pflip[0]))
25a857fb
AD		 3433 radeon_crtc_handle_flip(rdev, 0);
3434 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3435 DRM_DEBUG("IH: D1 vblank\n");
3436 }
3437 break;
3438 case 1: /* D1 vline */
3439 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3440 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3441 DRM_DEBUG("IH: D1 vline\n");
3442 }
3443 break;
3444 default:
3445 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3446 break;
3447 }
3448 break;
3449 case 2: /* D2 vblank/vline */
3450 switch (src_data) {
3451 case 0: /* D2 vblank */
3452 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3453 if (rdev->irq.crtc_vblank_int[1]) {
3454 drm_handle_vblank(rdev->ddev, 1);
3455 rdev->pm.vblank_sync = true;
3456 wake_up(&rdev->irq.vblank_queue);
3457 }
736fc37f 3458 if (atomic_read(&rdev->irq.pflip[1]))
25a857fb
AD		 3459 radeon_crtc_handle_flip(rdev, 1);
3460 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3461 DRM_DEBUG("IH: D2 vblank\n");
3462 }
3463 break;
3464 case 1: /* D2 vline */
3465 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3466 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3467 DRM_DEBUG("IH: D2 vline\n");
3468 }
3469 break;
3470 default:
3471 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3472 break;
3473 }
3474 break;
3475 case 3: /* D3 vblank/vline */
3476 switch (src_data) {
3477 case 0: /* D3 vblank */
3478 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3479 if (rdev->irq.crtc_vblank_int[2]) {
3480 drm_handle_vblank(rdev->ddev, 2);
3481 rdev->pm.vblank_sync = true;
3482 wake_up(&rdev->irq.vblank_queue);
3483 }
736fc37f 3484 if (atomic_read(&rdev->irq.pflip[2]))
25a857fb
AD		 3485 radeon_crtc_handle_flip(rdev, 2);
3486 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3487 DRM_DEBUG("IH: D3 vblank\n");
3488 }
3489 break;
3490 case 1: /* D3 vline */
3491 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3492 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3493 DRM_DEBUG("IH: D3 vline\n");
3494 }
3495 break;
3496 default:
3497 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3498 break;
3499 }
3500 break;
3501 case 4: /* D4 vblank/vline */
3502 switch (src_data) {
3503 case 0: /* D4 vblank */
3504 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3505 if (rdev->irq.crtc_vblank_int[3]) {
3506 drm_handle_vblank(rdev->ddev, 3);
3507 rdev->pm.vblank_sync = true;
3508 wake_up(&rdev->irq.vblank_queue);
3509 }
736fc37f 3510 if (atomic_read(&rdev->irq.pflip[3]))
25a857fb
AD		 3511 radeon_crtc_handle_flip(rdev, 3);
3512 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3513 DRM_DEBUG("IH: D4 vblank\n");
3514 }
3515 break;
3516 case 1: /* D4 vline */
3517 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3518 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3519 DRM_DEBUG("IH: D4 vline\n");
3520 }
3521 break;
3522 default:
3523 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3524 break;
3525 }
3526 break;
3527 case 5: /* D5 vblank/vline */
3528 switch (src_data) {
3529 case 0: /* D5 vblank */
3530 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3531 if (rdev->irq.crtc_vblank_int[4]) {
3532 drm_handle_vblank(rdev->ddev, 4);
3533 rdev->pm.vblank_sync = true;
3534 wake_up(&rdev->irq.vblank_queue);
3535 }
736fc37f 3536 if (atomic_read(&rdev->irq.pflip[4]))
25a857fb
AD		 3537 radeon_crtc_handle_flip(rdev, 4);
3538 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3539 DRM_DEBUG("IH: D5 vblank\n");
3540 }
3541 break;
3542 case 1: /* D5 vline */
3543 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3544 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3545 DRM_DEBUG("IH: D5 vline\n");
3546 }
3547 break;
3548 default:
3549 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3550 break;
3551 }
3552 break;
3553 case 6: /* D6 vblank/vline */
3554 switch (src_data) {
3555 case 0: /* D6 vblank */
3556 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3557 if (rdev->irq.crtc_vblank_int[5]) {
3558 drm_handle_vblank(rdev->ddev, 5);
3559 rdev->pm.vblank_sync = true;
3560 wake_up(&rdev->irq.vblank_queue);
3561 }
736fc37f 3562 if (atomic_read(&rdev->irq.pflip[5]))
25a857fb
AD		 3563 radeon_crtc_handle_flip(rdev, 5);
3564 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3565 DRM_DEBUG("IH: D6 vblank\n");
3566 }
3567 break;
3568 case 1: /* D6 vline */
3569 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3570 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3571 DRM_DEBUG("IH: D6 vline\n");
3572 }
3573 break;
3574 default:
3575 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3576 break;
3577 }
3578 break;
3579 case 42: /* HPD hotplug */
3580 switch (src_data) {
3581 case 0:
3582 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3583 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3584 queue_hotplug = true;
3585 DRM_DEBUG("IH: HPD1\n");
3586 }
3587 break;
3588 case 1:
3589 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3590 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3591 queue_hotplug = true;
3592 DRM_DEBUG("IH: HPD2\n");
3593 }
3594 break;
3595 case 2:
3596 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3597 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3598 queue_hotplug = true;
3599 DRM_DEBUG("IH: HPD3\n");
3600 }
3601 break;
3602 case 3:
3603 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3604 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3605 queue_hotplug = true;
3606 DRM_DEBUG("IH: HPD4\n");
3607 }
3608 break;
3609 case 4:
3610 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3611 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3612 queue_hotplug = true;
3613 DRM_DEBUG("IH: HPD5\n");
3614 }
3615 break;
3616 case 5:
3617 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3618 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3619 queue_hotplug = true;
3620 DRM_DEBUG("IH: HPD6\n");
3621 }
3622 break;
3623 default:
3624 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3625 break;
3626 }
3627 break;
3628 case 176: /* RINGID0 CP_INT */
3629 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3630 break;
3631 case 177: /* RINGID1 CP_INT */
3632 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3633 break;
3634 case 178: /* RINGID2 CP_INT */
3635 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3636 break;
3637 case 181: /* CP EOP event */
3638 DRM_DEBUG("IH: CP EOP\n");
3639 switch (ring_id) {
3640 case 0:
3641 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3642 break;
3643 case 1:
3644 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3645 break;
3646 case 2:
3647 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3648 break;
3649 }
3650 break;
3651 case 233: /* GUI IDLE */
3652 DRM_DEBUG("IH: GUI idle\n");
25a857fb
AD		 3653 wake_up(&rdev->irq.idle_queue);
3654 break;
3655 default:
3656 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3657 break;
3658 }
3659
3660 /* wptr/rptr are in bytes! */
3661 rptr += 16;
3662 rptr &= rdev->ih.ptr_mask;
3663 }
25a857fb
AD		 3664 if (queue_hotplug)
3665 schedule_work(&rdev->hotplug_work);
3666 rdev->ih.rptr = rptr;
3667 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3668 atomic_set(&rdev->ih.lock, 0);
3669
3670 /* make sure wptr hasn't changed while processing */
3671 wptr = si_get_ih_wptr(rdev);
3672 if (wptr != rptr)
3673 goto restart_ih;
3674
25a857fb
AD		 3675 return IRQ_HANDLED;
3676}
3677
9b136d51
AD		 3678/*
3679 * startup/shutdown callbacks
3680 */
3681static int si_startup(struct radeon_device *rdev)
3682{
3683 struct radeon_ring *ring;
3684 int r;
3685
3686 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
3687 !rdev->rlc_fw || !rdev->mc_fw) {
3688 r = si_init_microcode(rdev);
3689 if (r) {
3690 DRM_ERROR("Failed to load firmware!\n");
3691 return r;
3692 }
3693 }
3694
3695 r = si_mc_load_microcode(rdev);
3696 if (r) {
3697 DRM_ERROR("Failed to load MC firmware!\n");
3698 return r;
3699 }
3700
3701 r = r600_vram_scratch_init(rdev);
3702 if (r)
3703 return r;
3704
3705 si_mc_program(rdev);
3706 r = si_pcie_gart_enable(rdev);
3707 if (r)
3708 return r;
3709 si_gpu_init(rdev);
3710
3711#if 0
3712 r = evergreen_blit_init(rdev);
3713 if (r) {
3714 r600_blit_fini(rdev);
3715 rdev->asic->copy = NULL;
3716 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3717 }
3718#endif
3719 /* allocate rlc buffers */
3720 r = si_rlc_init(rdev);
3721 if (r) {
3722 DRM_ERROR("Failed to init rlc BOs!\n");
3723 return r;
3724 }
3725
3726 /* allocate wb buffer */
3727 r = radeon_wb_init(rdev);
3728 if (r)
3729 return r;
3730
3731 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3732 if (r) {
3733 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3734 return r;
3735 }
3736
3737 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3738 if (r) {
3739 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3740 return r;
3741 }
3742
3743 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3744 if (r) {
3745 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3746 return r;
3747 }
3748
3749 /* Enable IRQ */
3750 r = si_irq_init(rdev);
3751 if (r) {
3752 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3753 radeon_irq_kms_fini(rdev);
3754 return r;
3755 }
3756 si_irq_set(rdev);
3757
3758 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3759 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3760 CP_RB0_RPTR, CP_RB0_WPTR,
3761 0, 0xfffff, RADEON_CP_PACKET2);
3762 if (r)
3763 return r;
3764
3765 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3766 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
3767 CP_RB1_RPTR, CP_RB1_WPTR,
3768 0, 0xfffff, RADEON_CP_PACKET2);
3769 if (r)
3770 return r;
3771
3772 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3773 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
3774 CP_RB2_RPTR, CP_RB2_WPTR,
3775 0, 0xfffff, RADEON_CP_PACKET2);
3776 if (r)
3777 return r;
3778
3779 r = si_cp_load_microcode(rdev);
3780 if (r)
3781 return r;
3782 r = si_cp_resume(rdev);
3783 if (r)
3784 return r;
3785
2898c348
CK		 3786 r = radeon_ib_pool_init(rdev);
3787 if (r) {
3788 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
9b136d51 3789 return r;
2898c348 3790 }
9b136d51 3791
c6105f24
CK		 3792 r = radeon_vm_manager_init(rdev);
3793 if (r) {
3794 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
9b136d51 3795 return r;
c6105f24 3796 }
9b136d51
AD		 3797
3798 return 0;
3799}
3800
3801int si_resume(struct radeon_device *rdev)
3802{
3803 int r;
3804
3805 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3806 * posting will perform necessary task to bring back GPU into good
3807 * shape.
3808 */
3809 /* post card */
3810 atom_asic_init(rdev->mode_info.atom_context);
3811
3812 rdev->accel_working = true;
3813 r = si_startup(rdev);
3814 if (r) {
3815 DRM_ERROR("si startup failed on resume\n");
3816 rdev->accel_working = false;
3817 return r;
3818 }
3819
3820 return r;
3821
3822}
3823
3824int si_suspend(struct radeon_device *rdev)
3825{
9b136d51
AD		 3826 si_cp_enable(rdev, false);
3827 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3828 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3829 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3830 si_irq_suspend(rdev);
3831 radeon_wb_disable(rdev);
3832 si_pcie_gart_disable(rdev);
3833 return 0;
3834}
3835
3836/* Plan is to move initialization in that function and use
3837 * helper function so that radeon_device_init pretty much
3838 * do nothing more than calling asic specific function. This
3839 * should also allow to remove a bunch of callback function
3840 * like vram_info.
3841 */
3842int si_init(struct radeon_device *rdev)
3843{
3844 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3845 int r;
3846
9b136d51
AD		 3847 /* Read BIOS */
3848 if (!radeon_get_bios(rdev)) {
3849 if (ASIC_IS_AVIVO(rdev))
3850 return -EINVAL;
3851 }
3852 /* Must be an ATOMBIOS */
3853 if (!rdev->is_atom_bios) {
3854 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
3855 return -EINVAL;
3856 }
3857 r = radeon_atombios_init(rdev);
3858 if (r)
3859 return r;
3860
3861 /* Post card if necessary */
3862 if (!radeon_card_posted(rdev)) {
3863 if (!rdev->bios) {
3864 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3865 return -EINVAL;
3866 }
3867 DRM_INFO("GPU not posted. posting now...\n");
3868 atom_asic_init(rdev->mode_info.atom_context);
3869 }
3870 /* Initialize scratch registers */
3871 si_scratch_init(rdev);
3872 /* Initialize surface registers */
3873 radeon_surface_init(rdev);
3874 /* Initialize clocks */
3875 radeon_get_clock_info(rdev->ddev);
3876
3877 /* Fence driver */
3878 r = radeon_fence_driver_init(rdev);
3879 if (r)
3880 return r;
3881
3882 /* initialize memory controller */
3883 r = si_mc_init(rdev);
3884 if (r)
3885 return r;
3886 /* Memory manager */
3887 r = radeon_bo_init(rdev);
3888 if (r)
3889 return r;
3890
3891 r = radeon_irq_kms_init(rdev);
3892 if (r)
3893 return r;
3894
3895 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3896 ring->ring_obj = NULL;
3897 r600_ring_init(rdev, ring, 1024 * 1024);
3898
3899 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3900 ring->ring_obj = NULL;
3901 r600_ring_init(rdev, ring, 1024 * 1024);
3902
3903 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3904 ring->ring_obj = NULL;
3905 r600_ring_init(rdev, ring, 1024 * 1024);
3906
3907 rdev->ih.ring_obj = NULL;
3908 r600_ih_ring_init(rdev, 64 * 1024);
3909
3910 r = r600_pcie_gart_init(rdev);
3911 if (r)
3912 return r;
3913
9b136d51 3914 rdev->accel_working = true;
9b136d51
AD		 3915 r = si_startup(rdev);
3916 if (r) {
3917 dev_err(rdev->dev, "disabling GPU acceleration\n");
3918 si_cp_fini(rdev);
3919 si_irq_fini(rdev);
3920 si_rlc_fini(rdev);
3921 radeon_wb_fini(rdev);
2898c348 3922 radeon_ib_pool_fini(rdev);
9b136d51
AD		 3923 radeon_vm_manager_fini(rdev);
3924 radeon_irq_kms_fini(rdev);
3925 si_pcie_gart_fini(rdev);
3926 rdev->accel_working = false;
3927 }
3928
3929 /* Don't start up if the MC ucode is missing.
3930 * The default clocks and voltages before the MC ucode
3931 * is loaded are not suffient for advanced operations.
3932 */
3933 if (!rdev->mc_fw) {
3934 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3935 return -EINVAL;
3936 }
3937
3938 return 0;
3939}
3940
3941void si_fini(struct radeon_device *rdev)
3942{
3943#if 0
3944 r600_blit_fini(rdev);
3945#endif
3946 si_cp_fini(rdev);
3947 si_irq_fini(rdev);
3948 si_rlc_fini(rdev);
3949 radeon_wb_fini(rdev);
3950 radeon_vm_manager_fini(rdev);
2898c348 3951 radeon_ib_pool_fini(rdev);
9b136d51
AD		 3952 radeon_irq_kms_fini(rdev);
3953 si_pcie_gart_fini(rdev);
3954 r600_vram_scratch_fini(rdev);
3955 radeon_gem_fini(rdev);
9b136d51
AD		 3956 radeon_fence_driver_fini(rdev);
3957 radeon_bo_fini(rdev);
3958 radeon_atombios_fini(rdev);
3959 kfree(rdev->bios);
3960 rdev->bios = NULL;
3961}
3962
Linux 6.x block layer and io_uring tree(s)