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drm/radeon: add Oland chip family
[linux-2.6-block.git] / drivers / gpu / drm / radeon / si.c
CommitLineData
43b3cd99
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
0f0de06c
AD		 24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
43b3cd99
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
43b3cd99
AD		 32#include "sid.h"
33#include "atom.h"
48c0c902 34#include "si_blit_shaders.h"
43b3cd99 35
0f0de06c
AD		 36#define SI_PFP_UCODE_SIZE 2144
37#define SI_PM4_UCODE_SIZE 2144
38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769
41
42MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53MODULE_FIRMWARE("radeon/VERDE_me.bin");
54MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
57
25a857fb
AD		 58extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59extern void r600_ih_ring_fini(struct radeon_device *rdev);
0a96d72b 60extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
c476dde2
AD		 61extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
ca7db22b 63extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
1c534671 64extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
014bb209 65extern bool evergreen_is_display_hung(struct radeon_device *rdev);
0a96d72b 66
1bd47d2e
AD		 67/* get temperature in millidegrees */
68int si_get_temp(struct radeon_device *rdev)
69{
70 u32 temp;
71 int actual_temp = 0;
72
73 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
74 CTF_TEMP_SHIFT;
75
76 if (temp & 0x200)
77 actual_temp = 255;
78 else
79 actual_temp = temp & 0x1ff;
80
81 actual_temp = (actual_temp * 1000);
82
83 return actual_temp;
84}
85
8b074dd6
AD		 86#define TAHITI_IO_MC_REGS_SIZE 36
87
88static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
89 {0x0000006f, 0x03044000},
90 {0x00000070, 0x0480c018},
91 {0x00000071, 0x00000040},
92 {0x00000072, 0x01000000},
93 {0x00000074, 0x000000ff},
94 {0x00000075, 0x00143400},
95 {0x00000076, 0x08ec0800},
96 {0x00000077, 0x040000cc},
97 {0x00000079, 0x00000000},
98 {0x0000007a, 0x21000409},
99 {0x0000007c, 0x00000000},
100 {0x0000007d, 0xe8000000},
101 {0x0000007e, 0x044408a8},
102 {0x0000007f, 0x00000003},
103 {0x00000080, 0x00000000},
104 {0x00000081, 0x01000000},
105 {0x00000082, 0x02000000},
106 {0x00000083, 0x00000000},
107 {0x00000084, 0xe3f3e4f4},
108 {0x00000085, 0x00052024},
109 {0x00000087, 0x00000000},
110 {0x00000088, 0x66036603},
111 {0x00000089, 0x01000000},
112 {0x0000008b, 0x1c0a0000},
113 {0x0000008c, 0xff010000},
114 {0x0000008e, 0xffffefff},
115 {0x0000008f, 0xfff3efff},
116 {0x00000090, 0xfff3efbf},
117 {0x00000094, 0x00101101},
118 {0x00000095, 0x00000fff},
119 {0x00000096, 0x00116fff},
120 {0x00000097, 0x60010000},
121 {0x00000098, 0x10010000},
122 {0x00000099, 0x00006000},
123 {0x0000009a, 0x00001000},
124 {0x0000009f, 0x00a77400}
125};
126
127static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
128 {0x0000006f, 0x03044000},
129 {0x00000070, 0x0480c018},
130 {0x00000071, 0x00000040},
131 {0x00000072, 0x01000000},
132 {0x00000074, 0x000000ff},
133 {0x00000075, 0x00143400},
134 {0x00000076, 0x08ec0800},
135 {0x00000077, 0x040000cc},
136 {0x00000079, 0x00000000},
137 {0x0000007a, 0x21000409},
138 {0x0000007c, 0x00000000},
139 {0x0000007d, 0xe8000000},
140 {0x0000007e, 0x044408a8},
141 {0x0000007f, 0x00000003},
142 {0x00000080, 0x00000000},
143 {0x00000081, 0x01000000},
144 {0x00000082, 0x02000000},
145 {0x00000083, 0x00000000},
146 {0x00000084, 0xe3f3e4f4},
147 {0x00000085, 0x00052024},
148 {0x00000087, 0x00000000},
149 {0x00000088, 0x66036603},
150 {0x00000089, 0x01000000},
151 {0x0000008b, 0x1c0a0000},
152 {0x0000008c, 0xff010000},
153 {0x0000008e, 0xffffefff},
154 {0x0000008f, 0xfff3efff},
155 {0x00000090, 0xfff3efbf},
156 {0x00000094, 0x00101101},
157 {0x00000095, 0x00000fff},
158 {0x00000096, 0x00116fff},
159 {0x00000097, 0x60010000},
160 {0x00000098, 0x10010000},
161 {0x00000099, 0x00006000},
162 {0x0000009a, 0x00001000},
163 {0x0000009f, 0x00a47400}
164};
165
166static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
167 {0x0000006f, 0x03044000},
168 {0x00000070, 0x0480c018},
169 {0x00000071, 0x00000040},
170 {0x00000072, 0x01000000},
171 {0x00000074, 0x000000ff},
172 {0x00000075, 0x00143400},
173 {0x00000076, 0x08ec0800},
174 {0x00000077, 0x040000cc},
175 {0x00000079, 0x00000000},
176 {0x0000007a, 0x21000409},
177 {0x0000007c, 0x00000000},
178 {0x0000007d, 0xe8000000},
179 {0x0000007e, 0x044408a8},
180 {0x0000007f, 0x00000003},
181 {0x00000080, 0x00000000},
182 {0x00000081, 0x01000000},
183 {0x00000082, 0x02000000},
184 {0x00000083, 0x00000000},
185 {0x00000084, 0xe3f3e4f4},
186 {0x00000085, 0x00052024},
187 {0x00000087, 0x00000000},
188 {0x00000088, 0x66036603},
189 {0x00000089, 0x01000000},
190 {0x0000008b, 0x1c0a0000},
191 {0x0000008c, 0xff010000},
192 {0x0000008e, 0xffffefff},
193 {0x0000008f, 0xfff3efff},
194 {0x00000090, 0xfff3efbf},
195 {0x00000094, 0x00101101},
196 {0x00000095, 0x00000fff},
197 {0x00000096, 0x00116fff},
198 {0x00000097, 0x60010000},
199 {0x00000098, 0x10010000},
200 {0x00000099, 0x00006000},
201 {0x0000009a, 0x00001000},
202 {0x0000009f, 0x00a37400}
203};
204
205/* ucode loading */
206static int si_mc_load_microcode(struct radeon_device *rdev)
207{
208 const __be32 *fw_data;
209 u32 running, blackout = 0;
210 u32 *io_mc_regs;
211 int i, ucode_size, regs_size;
212
213 if (!rdev->mc_fw)
214 return -EINVAL;
215
216 switch (rdev->family) {
217 case CHIP_TAHITI:
218 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
219 ucode_size = SI_MC_UCODE_SIZE;
220 regs_size = TAHITI_IO_MC_REGS_SIZE;
221 break;
222 case CHIP_PITCAIRN:
223 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
224 ucode_size = SI_MC_UCODE_SIZE;
225 regs_size = TAHITI_IO_MC_REGS_SIZE;
226 break;
227 case CHIP_VERDE:
228 default:
229 io_mc_regs = (u32 *)&verde_io_mc_regs;
230 ucode_size = SI_MC_UCODE_SIZE;
231 regs_size = TAHITI_IO_MC_REGS_SIZE;
232 break;
233 }
234
235 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
236
237 if (running == 0) {
238 if (running) {
239 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
240 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
241 }
242
243 /* reset the engine and set to writable */
244 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
245 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
246
247 /* load mc io regs */
248 for (i = 0; i < regs_size; i++) {
249 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
250 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
251 }
252 /* load the MC ucode */
253 fw_data = (const __be32 *)rdev->mc_fw->data;
254 for (i = 0; i < ucode_size; i++)
255 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
256
257 /* put the engine back into the active state */
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
259 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
260 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
261
262 /* wait for training to complete */
263 for (i = 0; i < rdev->usec_timeout; i++) {
264 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
265 break;
266 udelay(1);
267 }
268 for (i = 0; i < rdev->usec_timeout; i++) {
269 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
270 break;
271 udelay(1);
272 }
273
274 if (running)
275 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
276 }
277
278 return 0;
279}
280
0f0de06c
AD		 281static int si_init_microcode(struct radeon_device *rdev)
282{
283 struct platform_device *pdev;
284 const char *chip_name;
285 const char *rlc_chip_name;
286 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
287 char fw_name[30];
288 int err;
289
290 DRM_DEBUG("\n");
291
292 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
293 err = IS_ERR(pdev);
294 if (err) {
295 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
296 return -EINVAL;
297 }
298
299 switch (rdev->family) {
300 case CHIP_TAHITI:
301 chip_name = "TAHITI";
302 rlc_chip_name = "TAHITI";
303 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
304 me_req_size = SI_PM4_UCODE_SIZE * 4;
305 ce_req_size = SI_CE_UCODE_SIZE * 4;
306 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
307 mc_req_size = SI_MC_UCODE_SIZE * 4;
308 break;
309 case CHIP_PITCAIRN:
310 chip_name = "PITCAIRN";
311 rlc_chip_name = "PITCAIRN";
312 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
313 me_req_size = SI_PM4_UCODE_SIZE * 4;
314 ce_req_size = SI_CE_UCODE_SIZE * 4;
315 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
316 mc_req_size = SI_MC_UCODE_SIZE * 4;
317 break;
318 case CHIP_VERDE:
319 chip_name = "VERDE";
320 rlc_chip_name = "VERDE";
321 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
322 me_req_size = SI_PM4_UCODE_SIZE * 4;
323 ce_req_size = SI_CE_UCODE_SIZE * 4;
324 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
325 mc_req_size = SI_MC_UCODE_SIZE * 4;
326 break;
327 default: BUG();
328 }
329
330 DRM_INFO("Loading %s Microcode\n", chip_name);
331
332 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
333 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
334 if (err)
335 goto out;
336 if (rdev->pfp_fw->size != pfp_req_size) {
337 printk(KERN_ERR
338 "si_cp: Bogus length %zu in firmware \"%s\"\n",
339 rdev->pfp_fw->size, fw_name);
340 err = -EINVAL;
341 goto out;
342 }
343
344 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
345 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
346 if (err)
347 goto out;
348 if (rdev->me_fw->size != me_req_size) {
349 printk(KERN_ERR
350 "si_cp: Bogus length %zu in firmware \"%s\"\n",
351 rdev->me_fw->size, fw_name);
352 err = -EINVAL;
353 }
354
355 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
356 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
357 if (err)
358 goto out;
359 if (rdev->ce_fw->size != ce_req_size) {
360 printk(KERN_ERR
361 "si_cp: Bogus length %zu in firmware \"%s\"\n",
362 rdev->ce_fw->size, fw_name);
363 err = -EINVAL;
364 }
365
366 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
367 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
368 if (err)
369 goto out;
370 if (rdev->rlc_fw->size != rlc_req_size) {
371 printk(KERN_ERR
372 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
373 rdev->rlc_fw->size, fw_name);
374 err = -EINVAL;
375 }
376
377 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
378 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
379 if (err)
380 goto out;
381 if (rdev->mc_fw->size != mc_req_size) {
382 printk(KERN_ERR
383 "si_mc: Bogus length %zu in firmware \"%s\"\n",
384 rdev->mc_fw->size, fw_name);
385 err = -EINVAL;
386 }
387
388out:
389 platform_device_unregister(pdev);
390
391 if (err) {
392 if (err != -EINVAL)
393 printk(KERN_ERR
394 "si_cp: Failed to load firmware \"%s\"\n",
395 fw_name);
396 release_firmware(rdev->pfp_fw);
397 rdev->pfp_fw = NULL;
398 release_firmware(rdev->me_fw);
399 rdev->me_fw = NULL;
400 release_firmware(rdev->ce_fw);
401 rdev->ce_fw = NULL;
402 release_firmware(rdev->rlc_fw);
403 rdev->rlc_fw = NULL;
404 release_firmware(rdev->mc_fw);
405 rdev->mc_fw = NULL;
406 }
407 return err;
408}
409
43b3cd99
AD		 410/* watermark setup */
411static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
412 struct radeon_crtc *radeon_crtc,
413 struct drm_display_mode *mode,
414 struct drm_display_mode *other_mode)
415{
416 u32 tmp;
417 /*
418 * Line Buffer Setup
419 * There are 3 line buffers, each one shared by 2 display controllers.
420 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
421 * the display controllers. The paritioning is done via one of four
422 * preset allocations specified in bits 21:20:
423 * 0 - half lb
424 * 2 - whole lb, other crtc must be disabled
425 */
426 /* this can get tricky if we have two large displays on a paired group
427 * of crtcs. Ideally for multiple large displays we'd assign them to
428 * non-linked crtcs for maximum line buffer allocation.
429 */
430 if (radeon_crtc->base.enabled && mode) {
431 if (other_mode)
432 tmp = 0; /* 1/2 */
433 else
434 tmp = 2; /* whole */
435 } else
436 tmp = 0;
437
438 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
439 DC_LB_MEMORY_CONFIG(tmp));
440
441 if (radeon_crtc->base.enabled && mode) {
442 switch (tmp) {
443 case 0:
444 default:
445 return 4096 * 2;
446 case 2:
447 return 8192 * 2;
448 }
449 }
450
451 /* controller not enabled, so no lb used */
452 return 0;
453}
454
ca7db22b 455static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
43b3cd99
AD		 456{
457 u32 tmp = RREG32(MC_SHARED_CHMAP);
458
459 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
460 case 0:
461 default:
462 return 1;
463 case 1:
464 return 2;
465 case 2:
466 return 4;
467 case 3:
468 return 8;
469 case 4:
470 return 3;
471 case 5:
472 return 6;
473 case 6:
474 return 10;
475 case 7:
476 return 12;
477 case 8:
478 return 16;
479 }
480}
481
482struct dce6_wm_params {
483 u32 dram_channels; /* number of dram channels */
484 u32 yclk; /* bandwidth per dram data pin in kHz */
485 u32 sclk; /* engine clock in kHz */
486 u32 disp_clk; /* display clock in kHz */
487 u32 src_width; /* viewport width */
488 u32 active_time; /* active display time in ns */
489 u32 blank_time; /* blank time in ns */
490 bool interlaced; /* mode is interlaced */
491 fixed20_12 vsc; /* vertical scale ratio */
492 u32 num_heads; /* number of active crtcs */
493 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
494 u32 lb_size; /* line buffer allocated to pipe */
495 u32 vtaps; /* vertical scaler taps */
496};
497
498static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
499{
500 /* Calculate raw DRAM Bandwidth */
501 fixed20_12 dram_efficiency; /* 0.7 */
502 fixed20_12 yclk, dram_channels, bandwidth;
503 fixed20_12 a;
504
505 a.full = dfixed_const(1000);
506 yclk.full = dfixed_const(wm->yclk);
507 yclk.full = dfixed_div(yclk, a);
508 dram_channels.full = dfixed_const(wm->dram_channels * 4);
509 a.full = dfixed_const(10);
510 dram_efficiency.full = dfixed_const(7);
511 dram_efficiency.full = dfixed_div(dram_efficiency, a);
512 bandwidth.full = dfixed_mul(dram_channels, yclk);
513 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
514
515 return dfixed_trunc(bandwidth);
516}
517
518static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
519{
520 /* Calculate DRAM Bandwidth and the part allocated to display. */
521 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
522 fixed20_12 yclk, dram_channels, bandwidth;
523 fixed20_12 a;
524
525 a.full = dfixed_const(1000);
526 yclk.full = dfixed_const(wm->yclk);
527 yclk.full = dfixed_div(yclk, a);
528 dram_channels.full = dfixed_const(wm->dram_channels * 4);
529 a.full = dfixed_const(10);
530 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
531 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
532 bandwidth.full = dfixed_mul(dram_channels, yclk);
533 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
534
535 return dfixed_trunc(bandwidth);
536}
537
538static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
539{
540 /* Calculate the display Data return Bandwidth */
541 fixed20_12 return_efficiency; /* 0.8 */
542 fixed20_12 sclk, bandwidth;
543 fixed20_12 a;
544
545 a.full = dfixed_const(1000);
546 sclk.full = dfixed_const(wm->sclk);
547 sclk.full = dfixed_div(sclk, a);
548 a.full = dfixed_const(10);
549 return_efficiency.full = dfixed_const(8);
550 return_efficiency.full = dfixed_div(return_efficiency, a);
551 a.full = dfixed_const(32);
552 bandwidth.full = dfixed_mul(a, sclk);
553 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
554
555 return dfixed_trunc(bandwidth);
556}
557
558static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
559{
560 return 32;
561}
562
563static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
564{
565 /* Calculate the DMIF Request Bandwidth */
566 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
567 fixed20_12 disp_clk, sclk, bandwidth;
568 fixed20_12 a, b1, b2;
569 u32 min_bandwidth;
570
571 a.full = dfixed_const(1000);
572 disp_clk.full = dfixed_const(wm->disp_clk);
573 disp_clk.full = dfixed_div(disp_clk, a);
574 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
575 b1.full = dfixed_mul(a, disp_clk);
576
577 a.full = dfixed_const(1000);
578 sclk.full = dfixed_const(wm->sclk);
579 sclk.full = dfixed_div(sclk, a);
580 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
581 b2.full = dfixed_mul(a, sclk);
582
583 a.full = dfixed_const(10);
584 disp_clk_request_efficiency.full = dfixed_const(8);
585 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
586
587 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
588
589 a.full = dfixed_const(min_bandwidth);
590 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
591
592 return dfixed_trunc(bandwidth);
593}
594
595static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
596{
597 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
598 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
599 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
600 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
601
602 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
603}
604
605static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
606{
607 /* Calculate the display mode Average Bandwidth
608 * DisplayMode should contain the source and destination dimensions,
609 * timing, etc.
610 */
611 fixed20_12 bpp;
612 fixed20_12 line_time;
613 fixed20_12 src_width;
614 fixed20_12 bandwidth;
615 fixed20_12 a;
616
617 a.full = dfixed_const(1000);
618 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
619 line_time.full = dfixed_div(line_time, a);
620 bpp.full = dfixed_const(wm->bytes_per_pixel);
621 src_width.full = dfixed_const(wm->src_width);
622 bandwidth.full = dfixed_mul(src_width, bpp);
623 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
624 bandwidth.full = dfixed_div(bandwidth, line_time);
625
626 return dfixed_trunc(bandwidth);
627}
628
629static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
630{
631 /* First calcualte the latency in ns */
632 u32 mc_latency = 2000; /* 2000 ns. */
633 u32 available_bandwidth = dce6_available_bandwidth(wm);
634 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
635 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
636 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
637 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
638 (wm->num_heads * cursor_line_pair_return_time);
639 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
640 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
641 u32 tmp, dmif_size = 12288;
642 fixed20_12 a, b, c;
643
644 if (wm->num_heads == 0)
645 return 0;
646
647 a.full = dfixed_const(2);
648 b.full = dfixed_const(1);
649 if ((wm->vsc.full > a.full) ||
650 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
651 (wm->vtaps >= 5) ||
652 ((wm->vsc.full >= a.full) && wm->interlaced))
653 max_src_lines_per_dst_line = 4;
654 else
655 max_src_lines_per_dst_line = 2;
656
657 a.full = dfixed_const(available_bandwidth);
658 b.full = dfixed_const(wm->num_heads);
659 a.full = dfixed_div(a, b);
660
661 b.full = dfixed_const(mc_latency + 512);
662 c.full = dfixed_const(wm->disp_clk);
663 b.full = dfixed_div(b, c);
664
665 c.full = dfixed_const(dmif_size);
666 b.full = dfixed_div(c, b);
667
668 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
669
670 b.full = dfixed_const(1000);
671 c.full = dfixed_const(wm->disp_clk);
672 b.full = dfixed_div(c, b);
673 c.full = dfixed_const(wm->bytes_per_pixel);
674 b.full = dfixed_mul(b, c);
675
676 lb_fill_bw = min(tmp, dfixed_trunc(b));
677
678 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
679 b.full = dfixed_const(1000);
680 c.full = dfixed_const(lb_fill_bw);
681 b.full = dfixed_div(c, b);
682 a.full = dfixed_div(a, b);
683 line_fill_time = dfixed_trunc(a);
684
685 if (line_fill_time < wm->active_time)
686 return latency;
687 else
688 return latency + (line_fill_time - wm->active_time);
689
690}
691
692static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
693{
694 if (dce6_average_bandwidth(wm) <=
695 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
696 return true;
697 else
698 return false;
699};
700
701static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
702{
703 if (dce6_average_bandwidth(wm) <=
704 (dce6_available_bandwidth(wm) / wm->num_heads))
705 return true;
706 else
707 return false;
708};
709
710static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
711{
712 u32 lb_partitions = wm->lb_size / wm->src_width;
713 u32 line_time = wm->active_time + wm->blank_time;
714 u32 latency_tolerant_lines;
715 u32 latency_hiding;
716 fixed20_12 a;
717
718 a.full = dfixed_const(1);
719 if (wm->vsc.full > a.full)
720 latency_tolerant_lines = 1;
721 else {
722 if (lb_partitions <= (wm->vtaps + 1))
723 latency_tolerant_lines = 1;
724 else
725 latency_tolerant_lines = 2;
726 }
727
728 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
729
730 if (dce6_latency_watermark(wm) <= latency_hiding)
731 return true;
732 else
733 return false;
734}
735
736static void dce6_program_watermarks(struct radeon_device *rdev,
737 struct radeon_crtc *radeon_crtc,
738 u32 lb_size, u32 num_heads)
739{
740 struct drm_display_mode *mode = &radeon_crtc->base.mode;
741 struct dce6_wm_params wm;
742 u32 pixel_period;
743 u32 line_time = 0;
744 u32 latency_watermark_a = 0, latency_watermark_b = 0;
745 u32 priority_a_mark = 0, priority_b_mark = 0;
746 u32 priority_a_cnt = PRIORITY_OFF;
747 u32 priority_b_cnt = PRIORITY_OFF;
748 u32 tmp, arb_control3;
749 fixed20_12 a, b, c;
750
751 if (radeon_crtc->base.enabled && num_heads && mode) {
752 pixel_period = 1000000 / (u32)mode->clock;
753 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
754 priority_a_cnt = 0;
755 priority_b_cnt = 0;
756
757 wm.yclk = rdev->pm.current_mclk * 10;
758 wm.sclk = rdev->pm.current_sclk * 10;
759 wm.disp_clk = mode->clock;
760 wm.src_width = mode->crtc_hdisplay;
761 wm.active_time = mode->crtc_hdisplay * pixel_period;
762 wm.blank_time = line_time - wm.active_time;
763 wm.interlaced = false;
764 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
765 wm.interlaced = true;
766 wm.vsc = radeon_crtc->vsc;
767 wm.vtaps = 1;
768 if (radeon_crtc->rmx_type != RMX_OFF)
769 wm.vtaps = 2;
770 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
771 wm.lb_size = lb_size;
ca7db22b
AD		 772 if (rdev->family == CHIP_ARUBA)
773 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
774 else
775 wm.dram_channels = si_get_number_of_dram_channels(rdev);
43b3cd99
AD		 776 wm.num_heads = num_heads;
777
778 /* set for high clocks */
779 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
780 /* set for low clocks */
781 /* wm.yclk = low clk; wm.sclk = low clk */
782 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
783
784 /* possibly force display priority to high */
785 /* should really do this at mode validation time... */
786 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
787 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
788 !dce6_check_latency_hiding(&wm) ||
789 (rdev->disp_priority == 2)) {
790 DRM_DEBUG_KMS("force priority to high\n");
791 priority_a_cnt |= PRIORITY_ALWAYS_ON;
792 priority_b_cnt |= PRIORITY_ALWAYS_ON;
793 }
794
795 a.full = dfixed_const(1000);
796 b.full = dfixed_const(mode->clock);
797 b.full = dfixed_div(b, a);
798 c.full = dfixed_const(latency_watermark_a);
799 c.full = dfixed_mul(c, b);
800 c.full = dfixed_mul(c, radeon_crtc->hsc);
801 c.full = dfixed_div(c, a);
802 a.full = dfixed_const(16);
803 c.full = dfixed_div(c, a);
804 priority_a_mark = dfixed_trunc(c);
805 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
806
807 a.full = dfixed_const(1000);
808 b.full = dfixed_const(mode->clock);
809 b.full = dfixed_div(b, a);
810 c.full = dfixed_const(latency_watermark_b);
811 c.full = dfixed_mul(c, b);
812 c.full = dfixed_mul(c, radeon_crtc->hsc);
813 c.full = dfixed_div(c, a);
814 a.full = dfixed_const(16);
815 c.full = dfixed_div(c, a);
816 priority_b_mark = dfixed_trunc(c);
817 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
818 }
819
820 /* select wm A */
821 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
822 tmp = arb_control3;
823 tmp &= ~LATENCY_WATERMARK_MASK(3);
824 tmp |= LATENCY_WATERMARK_MASK(1);
825 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
826 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
827 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
828 LATENCY_HIGH_WATERMARK(line_time)));
829 /* select wm B */
830 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
831 tmp &= ~LATENCY_WATERMARK_MASK(3);
832 tmp |= LATENCY_WATERMARK_MASK(2);
833 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
834 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
835 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
836 LATENCY_HIGH_WATERMARK(line_time)));
837 /* restore original selection */
838 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
839
840 /* write the priority marks */
841 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
842 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
843
844}
845
846void dce6_bandwidth_update(struct radeon_device *rdev)
847{
848 struct drm_display_mode *mode0 = NULL;
849 struct drm_display_mode *mode1 = NULL;
850 u32 num_heads = 0, lb_size;
851 int i;
852
853 radeon_update_display_priority(rdev);
854
855 for (i = 0; i < rdev->num_crtc; i++) {
856 if (rdev->mode_info.crtcs[i]->base.enabled)
857 num_heads++;
858 }
859 for (i = 0; i < rdev->num_crtc; i += 2) {
860 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
861 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
862 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
863 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
864 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
865 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
866 }
867}
868
0a96d72b
AD		 869/*
870 * Core functions
871 */
0a96d72b
AD		 872static void si_tiling_mode_table_init(struct radeon_device *rdev)
873{
874 const u32 num_tile_mode_states = 32;
875 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
876
877 switch (rdev->config.si.mem_row_size_in_kb) {
878 case 1:
879 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
880 break;
881 case 2:
882 default:
883 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
884 break;
885 case 4:
886 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
887 break;
888 }
889
890 if ((rdev->family == CHIP_TAHITI) ||
891 (rdev->family == CHIP_PITCAIRN)) {
892 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
893 switch (reg_offset) {
894 case 0: /* non-AA compressed depth or any compressed stencil */
895 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
896 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
897 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
898 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
899 NUM_BANKS(ADDR_SURF_16_BANK) |
900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
903 break;
904 case 1: /* 2xAA/4xAA compressed depth only */
905 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
906 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
907 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
909 NUM_BANKS(ADDR_SURF_16_BANK) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
913 break;
914 case 2: /* 8xAA compressed depth only */
915 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
917 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
918 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
919 NUM_BANKS(ADDR_SURF_16_BANK) |
920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
923 break;
924 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
925 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
927 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
929 NUM_BANKS(ADDR_SURF_16_BANK) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
933 break;
934 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
935 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
936 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
937 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
938 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
939 NUM_BANKS(ADDR_SURF_16_BANK) |
940 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
941 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
942 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
943 break;
944 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
945 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
947 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
948 TILE_SPLIT(split_equal_to_row_size) |
949 NUM_BANKS(ADDR_SURF_16_BANK) |
950 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
953 break;
954 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
957 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
958 TILE_SPLIT(split_equal_to_row_size) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
961 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
962 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
963 break;
964 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
965 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
967 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
968 TILE_SPLIT(split_equal_to_row_size) |
969 NUM_BANKS(ADDR_SURF_16_BANK) |
970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
973 break;
974 case 8: /* 1D and 1D Array Surfaces */
975 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
976 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
977 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
979 NUM_BANKS(ADDR_SURF_16_BANK) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
983 break;
984 case 9: /* Displayable maps. */
985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
986 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
987 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
989 NUM_BANKS(ADDR_SURF_16_BANK) |
990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
993 break;
994 case 10: /* Display 8bpp. */
995 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
996 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
997 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
998 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
999 NUM_BANKS(ADDR_SURF_16_BANK) |
1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1003 break;
1004 case 11: /* Display 16bpp. */
1005 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1006 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1008 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1009 NUM_BANKS(ADDR_SURF_16_BANK) |
1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1013 break;
1014 case 12: /* Display 32bpp. */
1015 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1016 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1017 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1019 NUM_BANKS(ADDR_SURF_16_BANK) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1023 break;
1024 case 13: /* Thin. */
1025 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1026 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1027 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1029 NUM_BANKS(ADDR_SURF_16_BANK) |
1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1033 break;
1034 case 14: /* Thin 8 bpp. */
1035 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1036 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1037 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1039 NUM_BANKS(ADDR_SURF_16_BANK) |
1040 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1043 break;
1044 case 15: /* Thin 16 bpp. */
1045 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1047 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1049 NUM_BANKS(ADDR_SURF_16_BANK) |
1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1053 break;
1054 case 16: /* Thin 32 bpp. */
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1057 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1059 NUM_BANKS(ADDR_SURF_16_BANK) |
1060 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1063 break;
1064 case 17: /* Thin 64 bpp. */
1065 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1067 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1068 TILE_SPLIT(split_equal_to_row_size) |
1069 NUM_BANKS(ADDR_SURF_16_BANK) |
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1073 break;
1074 case 21: /* 8 bpp PRT. */
1075 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1076 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1079 NUM_BANKS(ADDR_SURF_16_BANK) |
1080 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1081 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1082 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1083 break;
1084 case 22: /* 16 bpp PRT */
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1089 NUM_BANKS(ADDR_SURF_16_BANK) |
1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1093 break;
1094 case 23: /* 32 bpp PRT */
1095 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 NUM_BANKS(ADDR_SURF_16_BANK) |
1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1103 break;
1104 case 24: /* 64 bpp PRT */
1105 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1109 NUM_BANKS(ADDR_SURF_16_BANK) |
1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1113 break;
1114 case 25: /* 128 bpp PRT */
1115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1119 NUM_BANKS(ADDR_SURF_8_BANK) |
1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1123 break;
1124 default:
1125 gb_tile_moden = 0;
1126 break;
1127 }
1128 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1129 }
1130 } else if (rdev->family == CHIP_VERDE) {
1131 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1132 switch (reg_offset) {
1133 case 0: /* non-AA compressed depth or any compressed stencil */
1134 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1135 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1136 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1138 NUM_BANKS(ADDR_SURF_16_BANK) |
1139 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1141 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1142 break;
1143 case 1: /* 2xAA/4xAA compressed depth only */
1144 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1145 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1146 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1147 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1148 NUM_BANKS(ADDR_SURF_16_BANK) |
1149 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1152 break;
1153 case 2: /* 8xAA compressed depth only */
1154 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1155 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1156 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1158 NUM_BANKS(ADDR_SURF_16_BANK) |
1159 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1162 break;
1163 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1164 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1165 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1166 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1167 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1168 NUM_BANKS(ADDR_SURF_16_BANK) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1172 break;
1173 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1174 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1175 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1176 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1177 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1178 NUM_BANKS(ADDR_SURF_16_BANK) |
1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1182 break;
1183 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1184 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1185 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1186 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1187 TILE_SPLIT(split_equal_to_row_size) |
1188 NUM_BANKS(ADDR_SURF_16_BANK) |
1189 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1192 break;
1193 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1194 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1196 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1197 TILE_SPLIT(split_equal_to_row_size) |
1198 NUM_BANKS(ADDR_SURF_16_BANK) |
1199 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1202 break;
1203 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1204 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1206 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1207 TILE_SPLIT(split_equal_to_row_size) |
1208 NUM_BANKS(ADDR_SURF_16_BANK) |
1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1212 break;
1213 case 8: /* 1D and 1D Array Surfaces */
1214 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1215 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1216 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1218 NUM_BANKS(ADDR_SURF_16_BANK) |
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1222 break;
1223 case 9: /* Displayable maps. */
1224 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1228 NUM_BANKS(ADDR_SURF_16_BANK) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1232 break;
1233 case 10: /* Display 8bpp. */
1234 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1238 NUM_BANKS(ADDR_SURF_16_BANK) |
1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1242 break;
1243 case 11: /* Display 16bpp. */
1244 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1248 NUM_BANKS(ADDR_SURF_16_BANK) |
1249 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1252 break;
1253 case 12: /* Display 32bpp. */
1254 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1255 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1258 NUM_BANKS(ADDR_SURF_16_BANK) |
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1262 break;
1263 case 13: /* Thin. */
1264 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1265 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1268 NUM_BANKS(ADDR_SURF_16_BANK) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1272 break;
1273 case 14: /* Thin 8 bpp. */
1274 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1275 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1278 NUM_BANKS(ADDR_SURF_16_BANK) |
1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1282 break;
1283 case 15: /* Thin 16 bpp. */
1284 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1285 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1286 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1288 NUM_BANKS(ADDR_SURF_16_BANK) |
1289 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1292 break;
1293 case 16: /* Thin 32 bpp. */
1294 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1295 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1296 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1297 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1298 NUM_BANKS(ADDR_SURF_16_BANK) |
1299 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1300 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1301 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1302 break;
1303 case 17: /* Thin 64 bpp. */
1304 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1305 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1306 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1307 TILE_SPLIT(split_equal_to_row_size) |
1308 NUM_BANKS(ADDR_SURF_16_BANK) |
1309 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1310 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1311 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1312 break;
1313 case 21: /* 8 bpp PRT. */
1314 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1315 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1316 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1318 NUM_BANKS(ADDR_SURF_16_BANK) |
1319 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1322 break;
1323 case 22: /* 16 bpp PRT */
1324 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1326 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1327 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1328 NUM_BANKS(ADDR_SURF_16_BANK) |
1329 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1330 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1331 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1332 break;
1333 case 23: /* 32 bpp PRT */
1334 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1335 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1336 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1337 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1338 NUM_BANKS(ADDR_SURF_16_BANK) |
1339 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1342 break;
1343 case 24: /* 64 bpp PRT */
1344 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1347 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1348 NUM_BANKS(ADDR_SURF_16_BANK) |
1349 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1352 break;
1353 case 25: /* 128 bpp PRT */
1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1356 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1357 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1358 NUM_BANKS(ADDR_SURF_8_BANK) |
1359 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1362 break;
1363 default:
1364 gb_tile_moden = 0;
1365 break;
1366 }
1367 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1368 }
1369 } else
1370 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1371}
1372
1a8ca750
AD		 1373static void si_select_se_sh(struct radeon_device *rdev,
1374 u32 se_num, u32 sh_num)
1375{
1376 u32 data = INSTANCE_BROADCAST_WRITES;
1377
1378 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1379 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1380 else if (se_num == 0xffffffff)
1381 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1382 else if (sh_num == 0xffffffff)
1383 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1384 else
1385 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1386 WREG32(GRBM_GFX_INDEX, data);
1387}
1388
1389static u32 si_create_bitmask(u32 bit_width)
1390{
1391 u32 i, mask = 0;
1392
1393 for (i = 0; i < bit_width; i++) {
1394 mask <<= 1;
1395 mask |= 1;
1396 }
1397 return mask;
1398}
1399
1400static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1401{
1402 u32 data, mask;
1403
1404 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1405 if (data & 1)
1406 data &= INACTIVE_CUS_MASK;
1407 else
1408 data = 0;
1409 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1410
1411 data >>= INACTIVE_CUS_SHIFT;
1412
1413 mask = si_create_bitmask(cu_per_sh);
1414
1415 return ~data & mask;
1416}
1417
1418static void si_setup_spi(struct radeon_device *rdev,
1419 u32 se_num, u32 sh_per_se,
1420 u32 cu_per_sh)
1421{
1422 int i, j, k;
1423 u32 data, mask, active_cu;
1424
1425 for (i = 0; i < se_num; i++) {
1426 for (j = 0; j < sh_per_se; j++) {
1427 si_select_se_sh(rdev, i, j);
1428 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1429 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1430
1431 mask = 1;
1432 for (k = 0; k < 16; k++) {
1433 mask <<= k;
1434 if (active_cu & mask) {
1435 data &= ~mask;
1436 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1437 break;
1438 }
1439 }
1440 }
1441 }
1442 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1443}
1444
1445static u32 si_get_rb_disabled(struct radeon_device *rdev,
1446 u32 max_rb_num, u32 se_num,
1447 u32 sh_per_se)
1448{
1449 u32 data, mask;
1450
1451 data = RREG32(CC_RB_BACKEND_DISABLE);
1452 if (data & 1)
1453 data &= BACKEND_DISABLE_MASK;
1454 else
1455 data = 0;
1456 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1457
1458 data >>= BACKEND_DISABLE_SHIFT;
1459
1460 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1461
1462 return data & mask;
1463}
1464
1465static void si_setup_rb(struct radeon_device *rdev,
1466 u32 se_num, u32 sh_per_se,
1467 u32 max_rb_num)
1468{
1469 int i, j;
1470 u32 data, mask;
1471 u32 disabled_rbs = 0;
1472 u32 enabled_rbs = 0;
1473
1474 for (i = 0; i < se_num; i++) {
1475 for (j = 0; j < sh_per_se; j++) {
1476 si_select_se_sh(rdev, i, j);
1477 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1478 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1479 }
1480 }
1481 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1482
1483 mask = 1;
1484 for (i = 0; i < max_rb_num; i++) {
1485 if (!(disabled_rbs & mask))
1486 enabled_rbs |= mask;
1487 mask <<= 1;
1488 }
1489
1490 for (i = 0; i < se_num; i++) {
1491 si_select_se_sh(rdev, i, 0xffffffff);
1492 data = 0;
1493 for (j = 0; j < sh_per_se; j++) {
1494 switch (enabled_rbs & 3) {
1495 case 1:
1496 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1497 break;
1498 case 2:
1499 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1500 break;
1501 case 3:
1502 default:
1503 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1504 break;
1505 }
1506 enabled_rbs >>= 2;
1507 }
1508 WREG32(PA_SC_RASTER_CONFIG, data);
1509 }
1510 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1511}
1512
0a96d72b
AD		 1513static void si_gpu_init(struct radeon_device *rdev)
1514{
0a96d72b
AD		 1515 u32 gb_addr_config = 0;
1516 u32 mc_shared_chmap, mc_arb_ramcfg;
0a96d72b 1517 u32 sx_debug_1;
0a96d72b
AD		 1518 u32 hdp_host_path_cntl;
1519 u32 tmp;
1520 int i, j;
1521
1522 switch (rdev->family) {
1523 case CHIP_TAHITI:
1524 rdev->config.si.max_shader_engines = 2;
0a96d72b 1525 rdev->config.si.max_tile_pipes = 12;
1a8ca750
AD		 1526 rdev->config.si.max_cu_per_sh = 8;
1527 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1528 rdev->config.si.max_backends_per_se = 4;
1529 rdev->config.si.max_texture_channel_caches = 12;
1530 rdev->config.si.max_gprs = 256;
1531 rdev->config.si.max_gs_threads = 32;
1532 rdev->config.si.max_hw_contexts = 8;
1533
1534 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1535 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1536 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1537 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1538 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1539 break;
1540 case CHIP_PITCAIRN:
1541 rdev->config.si.max_shader_engines = 2;
0a96d72b 1542 rdev->config.si.max_tile_pipes = 8;
1a8ca750
AD		 1543 rdev->config.si.max_cu_per_sh = 5;
1544 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1545 rdev->config.si.max_backends_per_se = 4;
1546 rdev->config.si.max_texture_channel_caches = 8;
1547 rdev->config.si.max_gprs = 256;
1548 rdev->config.si.max_gs_threads = 32;
1549 rdev->config.si.max_hw_contexts = 8;
1550
1551 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1552 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1553 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1554 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1555 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1556 break;
1557 case CHIP_VERDE:
1558 default:
1559 rdev->config.si.max_shader_engines = 1;
0a96d72b 1560 rdev->config.si.max_tile_pipes = 4;
1a8ca750
AD		 1561 rdev->config.si.max_cu_per_sh = 2;
1562 rdev->config.si.max_sh_per_se = 2;
0a96d72b
AD		 1563 rdev->config.si.max_backends_per_se = 4;
1564 rdev->config.si.max_texture_channel_caches = 4;
1565 rdev->config.si.max_gprs = 256;
1566 rdev->config.si.max_gs_threads = 32;
1567 rdev->config.si.max_hw_contexts = 8;
1568
1569 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1570 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1571 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1572 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1a8ca750 1573 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
0a96d72b
AD		 1574 break;
1575 }
1576
1577 /* Initialize HDP */
1578 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1579 WREG32((0x2c14 + j), 0x00000000);
1580 WREG32((0x2c18 + j), 0x00000000);
1581 WREG32((0x2c1c + j), 0x00000000);
1582 WREG32((0x2c20 + j), 0x00000000);
1583 WREG32((0x2c24 + j), 0x00000000);
1584 }
1585
1586 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1587
1588 evergreen_fix_pci_max_read_req_size(rdev);
1589
1590 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1591
1592 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1593 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1594
0a96d72b 1595 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
0a96d72b
AD		 1596 rdev->config.si.mem_max_burst_length_bytes = 256;
1597 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1598 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1599 if (rdev->config.si.mem_row_size_in_kb > 4)
1600 rdev->config.si.mem_row_size_in_kb = 4;
1601 /* XXX use MC settings? */
1602 rdev->config.si.shader_engine_tile_size = 32;
1603 rdev->config.si.num_gpus = 1;
1604 rdev->config.si.multi_gpu_tile_size = 64;
1605
1a8ca750
AD		 1606 /* fix up row size */
1607 gb_addr_config &= ~ROW_SIZE_MASK;
0a96d72b
AD		 1608 switch (rdev->config.si.mem_row_size_in_kb) {
1609 case 1:
1610 default:
1611 gb_addr_config |= ROW_SIZE(0);
1612 break;
1613 case 2:
1614 gb_addr_config |= ROW_SIZE(1);
1615 break;
1616 case 4:
1617 gb_addr_config |= ROW_SIZE(2);
1618 break;
1619 }
1620
0a96d72b
AD		 1621 /* setup tiling info dword. gb_addr_config is not adequate since it does
1622 * not have bank info, so create a custom tiling dword.
1623 * bits 3:0 num_pipes
1624 * bits 7:4 num_banks
1625 * bits 11:8 group_size
1626 * bits 15:12 row_size
1627 */
1628 rdev->config.si.tile_config = 0;
1629 switch (rdev->config.si.num_tile_pipes) {
1630 case 1:
1631 rdev->config.si.tile_config |= (0 << 0);
1632 break;
1633 case 2:
1634 rdev->config.si.tile_config |= (1 << 0);
1635 break;
1636 case 4:
1637 rdev->config.si.tile_config |= (2 << 0);
1638 break;
1639 case 8:
1640 default:
1641 /* XXX what about 12? */
1642 rdev->config.si.tile_config |= (3 << 0);
1643 break;
dca571a6
CK		 1644 }
1645 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1646 case 0: /* four banks */
1a8ca750 1647 rdev->config.si.tile_config |= 0 << 4;
dca571a6
CK		 1648 break;
1649 case 1: /* eight banks */
1650 rdev->config.si.tile_config |= 1 << 4;
1651 break;
1652 case 2: /* sixteen banks */
1653 default:
1654 rdev->config.si.tile_config |= 2 << 4;
1655 break;
1656 }
0a96d72b
AD		 1657 rdev->config.si.tile_config |=
1658 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1659 rdev->config.si.tile_config |=
1660 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1661
0a96d72b
AD		 1662 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1663 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1664 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
8c5fd7ef
AD		 1665 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1666 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
0a96d72b 1667
1a8ca750 1668 si_tiling_mode_table_init(rdev);
0a96d72b 1669
1a8ca750
AD		 1670 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1671 rdev->config.si.max_sh_per_se,
1672 rdev->config.si.max_backends_per_se);
0a96d72b 1673
1a8ca750
AD		 1674 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1675 rdev->config.si.max_sh_per_se,
1676 rdev->config.si.max_cu_per_sh);
0a96d72b 1677
0a96d72b
AD		 1678
1679 /* set HW defaults for 3D engine */
1680 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1681 ROQ_IB2_START(0x2b)));
1682 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1683
1684 sx_debug_1 = RREG32(SX_DEBUG_1);
1685 WREG32(SX_DEBUG_1, sx_debug_1);
1686
1687 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1688
1689 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1690 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1691 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1692 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1693
1694 WREG32(VGT_NUM_INSTANCES, 1);
1695
1696 WREG32(CP_PERFMON_CNTL, 0);
1697
1698 WREG32(SQ_CONFIG, 0);
1699
1700 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1701 FORCE_EOV_MAX_REZ_CNT(255)));
1702
1703 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1704 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1705
1706 WREG32(VGT_GS_VERTEX_REUSE, 16);
1707 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1708
1709 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1710 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1711 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1712 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1713 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1714 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1715 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1716 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1717
1718 tmp = RREG32(HDP_MISC_CNTL);
1719 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1720 WREG32(HDP_MISC_CNTL, tmp);
1721
1722 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1723 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1724
1725 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1726
1727 udelay(50);
1728}
c476dde2 1729
2ece2e8b
AD		 1730/*
1731 * GPU scratch registers helpers function.
1732 */
1733static void si_scratch_init(struct radeon_device *rdev)
1734{
1735 int i;
1736
1737 rdev->scratch.num_reg = 7;
1738 rdev->scratch.reg_base = SCRATCH_REG0;
1739 for (i = 0; i < rdev->scratch.num_reg; i++) {
1740 rdev->scratch.free[i] = true;
1741 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1742 }
1743}
1744
1745void si_fence_ring_emit(struct radeon_device *rdev,
1746 struct radeon_fence *fence)
1747{
1748 struct radeon_ring *ring = &rdev->ring[fence->ring];
1749 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1750
1751 /* flush read cache over gart */
1752 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1753 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1754 radeon_ring_write(ring, 0);
1755 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1756 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1757 PACKET3_TC_ACTION_ENA |
1758 PACKET3_SH_KCACHE_ACTION_ENA |
1759 PACKET3_SH_ICACHE_ACTION_ENA);
1760 radeon_ring_write(ring, 0xFFFFFFFF);
1761 radeon_ring_write(ring, 0);
1762 radeon_ring_write(ring, 10); /* poll interval */
1763 /* EVENT_WRITE_EOP - flush caches, send int */
1764 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1765 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1766 radeon_ring_write(ring, addr & 0xffffffff);
1767 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1768 radeon_ring_write(ring, fence->seq);
1769 radeon_ring_write(ring, 0);
1770}
1771
1772/*
1773 * IB stuff
1774 */
1775void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1776{
876dc9f3 1777 struct radeon_ring *ring = &rdev->ring[ib->ring];
2ece2e8b
AD		 1778 u32 header;
1779
a85a7da4
AD		 1780 if (ib->is_const_ib) {
1781 /* set switch buffer packet before const IB */
1782 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1783 radeon_ring_write(ring, 0);
45df6803 1784
2ece2e8b 1785 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
a85a7da4 1786 } else {
89d35807 1787 u32 next_rptr;
a85a7da4 1788 if (ring->rptr_save_reg) {
89d35807 1789 next_rptr = ring->wptr + 3 + 4 + 8;
a85a7da4
AD		 1790 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 radeon_ring_write(ring, ((ring->rptr_save_reg -
1792 PACKET3_SET_CONFIG_REG_START) >> 2));
1793 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1794 } else if (rdev->wb.enabled) {
1795 next_rptr = ring->wptr + 5 + 4 + 8;
1796 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1797 radeon_ring_write(ring, (1 << 8));
1798 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1799 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1800 radeon_ring_write(ring, next_rptr);
a85a7da4
AD		 1801 }
1802
2ece2e8b 1803 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
a85a7da4 1804 }
2ece2e8b
AD		 1805
1806 radeon_ring_write(ring, header);
1807 radeon_ring_write(ring,
1808#ifdef __BIG_ENDIAN
1809 (2 << 0) |
1810#endif
1811 (ib->gpu_addr & 0xFFFFFFFC));
1812 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4bf3dd92
CK		 1813 radeon_ring_write(ring, ib->length_dw |
1814 (ib->vm ? (ib->vm->id << 24) : 0));
2ece2e8b 1815
a85a7da4
AD		 1816 if (!ib->is_const_ib) {
1817 /* flush read cache over gart for this vmid */
1818 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1819 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 1820 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
a85a7da4
AD		 1821 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1822 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1823 PACKET3_TC_ACTION_ENA |
1824 PACKET3_SH_KCACHE_ACTION_ENA |
1825 PACKET3_SH_ICACHE_ACTION_ENA);
1826 radeon_ring_write(ring, 0xFFFFFFFF);
1827 radeon_ring_write(ring, 0);
1828 radeon_ring_write(ring, 10); /* poll interval */
1829 }
2ece2e8b
AD		 1830}
1831
48c0c902
AD		 1832/*
1833 * CP.
1834 */
1835static void si_cp_enable(struct radeon_device *rdev, bool enable)
1836{
1837 if (enable)
1838 WREG32(CP_ME_CNTL, 0);
1839 else {
1840 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1841 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1842 WREG32(SCRATCH_UMSK, 0);
8c5fd7ef
AD		 1843 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1844 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1845 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
48c0c902
AD		 1846 }
1847 udelay(50);
1848}
1849
1850static int si_cp_load_microcode(struct radeon_device *rdev)
1851{
1852 const __be32 *fw_data;
1853 int i;
1854
1855 if (!rdev->me_fw || !rdev->pfp_fw)
1856 return -EINVAL;
1857
1858 si_cp_enable(rdev, false);
1859
1860 /* PFP */
1861 fw_data = (const __be32 *)rdev->pfp_fw->data;
1862 WREG32(CP_PFP_UCODE_ADDR, 0);
1863 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1864 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1865 WREG32(CP_PFP_UCODE_ADDR, 0);
1866
1867 /* CE */
1868 fw_data = (const __be32 *)rdev->ce_fw->data;
1869 WREG32(CP_CE_UCODE_ADDR, 0);
1870 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1871 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1872 WREG32(CP_CE_UCODE_ADDR, 0);
1873
1874 /* ME */
1875 fw_data = (const __be32 *)rdev->me_fw->data;
1876 WREG32(CP_ME_RAM_WADDR, 0);
1877 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1878 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1879 WREG32(CP_ME_RAM_WADDR, 0);
1880
1881 WREG32(CP_PFP_UCODE_ADDR, 0);
1882 WREG32(CP_CE_UCODE_ADDR, 0);
1883 WREG32(CP_ME_RAM_WADDR, 0);
1884 WREG32(CP_ME_RAM_RADDR, 0);
1885 return 0;
1886}
1887
1888static int si_cp_start(struct radeon_device *rdev)
1889{
1890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1891 int r, i;
1892
1893 r = radeon_ring_lock(rdev, ring, 7 + 4);
1894 if (r) {
1895 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1896 return r;
1897 }
1898 /* init the CP */
1899 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1900 radeon_ring_write(ring, 0x1);
1901 radeon_ring_write(ring, 0x0);
1902 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1903 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1904 radeon_ring_write(ring, 0);
1905 radeon_ring_write(ring, 0);
1906
1907 /* init the CE partitions */
1908 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1909 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1910 radeon_ring_write(ring, 0xc000);
1911 radeon_ring_write(ring, 0xe000);
1912 radeon_ring_unlock_commit(rdev, ring);
1913
1914 si_cp_enable(rdev, true);
1915
1916 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1917 if (r) {
1918 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1919 return r;
1920 }
1921
1922 /* setup clear context state */
1923 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1924 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1925
1926 for (i = 0; i < si_default_size; i++)
1927 radeon_ring_write(ring, si_default_state[i]);
1928
1929 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1930 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1931
1932 /* set clear context state */
1933 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1934 radeon_ring_write(ring, 0);
1935
1936 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1937 radeon_ring_write(ring, 0x00000316);
1938 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1939 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1940
1941 radeon_ring_unlock_commit(rdev, ring);
1942
1943 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1944 ring = &rdev->ring[i];
1945 r = radeon_ring_lock(rdev, ring, 2);
1946
1947 /* clear the compute context state */
1948 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
1949 radeon_ring_write(ring, 0);
1950
1951 radeon_ring_unlock_commit(rdev, ring);
1952 }
1953
1954 return 0;
1955}
1956
1957static void si_cp_fini(struct radeon_device *rdev)
1958{
45df6803 1959 struct radeon_ring *ring;
48c0c902 1960 si_cp_enable(rdev, false);
45df6803
CK		 1961
1962 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1963 radeon_ring_fini(rdev, ring);
1964 radeon_scratch_free(rdev, ring->rptr_save_reg);
1965
1966 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1967 radeon_ring_fini(rdev, ring);
1968 radeon_scratch_free(rdev, ring->rptr_save_reg);
1969
1970 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1971 radeon_ring_fini(rdev, ring);
1972 radeon_scratch_free(rdev, ring->rptr_save_reg);
48c0c902
AD		 1973}
1974
1975static int si_cp_resume(struct radeon_device *rdev)
1976{
1977 struct radeon_ring *ring;
1978 u32 tmp;
1979 u32 rb_bufsz;
1980 int r;
1981
1982 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1983 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1984 SOFT_RESET_PA |
1985 SOFT_RESET_VGT |
1986 SOFT_RESET_SPI |
1987 SOFT_RESET_SX));
1988 RREG32(GRBM_SOFT_RESET);
1989 mdelay(15);
1990 WREG32(GRBM_SOFT_RESET, 0);
1991 RREG32(GRBM_SOFT_RESET);
1992
1993 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1994 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1995
1996 /* Set the write pointer delay */
1997 WREG32(CP_RB_WPTR_DELAY, 0);
1998
1999 WREG32(CP_DEBUG, 0);
2000 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2001
2002 /* ring 0 - compute and gfx */
2003 /* Set ring buffer size */
2004 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2005 rb_bufsz = drm_order(ring->ring_size / 8);
2006 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2007#ifdef __BIG_ENDIAN
2008 tmp |= BUF_SWAP_32BIT;
2009#endif
2010 WREG32(CP_RB0_CNTL, tmp);
2011
2012 /* Initialize the ring buffer's read and write pointers */
2013 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2014 ring->wptr = 0;
2015 WREG32(CP_RB0_WPTR, ring->wptr);
2016
48fc7f7e 2017 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2018 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2019 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2020
2021 if (rdev->wb.enabled)
2022 WREG32(SCRATCH_UMSK, 0xff);
2023 else {
2024 tmp |= RB_NO_UPDATE;
2025 WREG32(SCRATCH_UMSK, 0);
2026 }
2027
2028 mdelay(1);
2029 WREG32(CP_RB0_CNTL, tmp);
2030
2031 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2032
2033 ring->rptr = RREG32(CP_RB0_RPTR);
2034
2035 /* ring1 - compute only */
2036 /* Set ring buffer size */
2037 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2038 rb_bufsz = drm_order(ring->ring_size / 8);
2039 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2040#ifdef __BIG_ENDIAN
2041 tmp |= BUF_SWAP_32BIT;
2042#endif
2043 WREG32(CP_RB1_CNTL, tmp);
2044
2045 /* Initialize the ring buffer's read and write pointers */
2046 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2047 ring->wptr = 0;
2048 WREG32(CP_RB1_WPTR, ring->wptr);
2049
48fc7f7e 2050 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2051 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2052 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2053
2054 mdelay(1);
2055 WREG32(CP_RB1_CNTL, tmp);
2056
2057 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2058
2059 ring->rptr = RREG32(CP_RB1_RPTR);
2060
2061 /* ring2 - compute only */
2062 /* Set ring buffer size */
2063 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2064 rb_bufsz = drm_order(ring->ring_size / 8);
2065 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2066#ifdef __BIG_ENDIAN
2067 tmp |= BUF_SWAP_32BIT;
2068#endif
2069 WREG32(CP_RB2_CNTL, tmp);
2070
2071 /* Initialize the ring buffer's read and write pointers */
2072 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2073 ring->wptr = 0;
2074 WREG32(CP_RB2_WPTR, ring->wptr);
2075
48fc7f7e 2076 /* set the wb address whether it's enabled or not */
48c0c902
AD		 2077 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2078 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2079
2080 mdelay(1);
2081 WREG32(CP_RB2_CNTL, tmp);
2082
2083 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2084
2085 ring->rptr = RREG32(CP_RB2_RPTR);
2086
2087 /* start the rings */
2088 si_cp_start(rdev);
2089 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2090 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2091 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2092 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2093 if (r) {
2094 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2095 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2096 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2097 return r;
2098 }
2099 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2100 if (r) {
2101 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2102 }
2103 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2104 if (r) {
2105 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2106 }
2107
2108 return 0;
2109}
2110
014bb209 2111static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
06bc6df0 2112{
014bb209 2113 u32 reset_mask = 0;
1c534671 2114 u32 tmp;
06bc6df0 2115
014bb209
AD		 2116 /* GRBM_STATUS */
2117 tmp = RREG32(GRBM_STATUS);
2118 if (tmp & (PA_BUSY | SC_BUSY |
2119 BCI_BUSY | SX_BUSY |
2120 TA_BUSY | VGT_BUSY |
2121 DB_BUSY | CB_BUSY |
2122 GDS_BUSY | SPI_BUSY |
2123 IA_BUSY | IA_BUSY_NO_DMA))
2124 reset_mask |= RADEON_RESET_GFX;
2125
2126 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2127 CP_BUSY | CP_COHERENCY_BUSY))
2128 reset_mask |= RADEON_RESET_CP;
2129
2130 if (tmp & GRBM_EE_BUSY)
2131 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2132
2133 /* GRBM_STATUS2 */
2134 tmp = RREG32(GRBM_STATUS2);
2135 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2136 reset_mask |= RADEON_RESET_RLC;
2137
2138 /* DMA_STATUS_REG 0 */
2139 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2140 if (!(tmp & DMA_IDLE))
2141 reset_mask |= RADEON_RESET_DMA;
2142
2143 /* DMA_STATUS_REG 1 */
2144 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2145 if (!(tmp & DMA_IDLE))
2146 reset_mask |= RADEON_RESET_DMA1;
2147
2148 /* SRBM_STATUS2 */
2149 tmp = RREG32(SRBM_STATUS2);
2150 if (tmp & DMA_BUSY)
2151 reset_mask |= RADEON_RESET_DMA;
2152
2153 if (tmp & DMA1_BUSY)
2154 reset_mask |= RADEON_RESET_DMA1;
2155
2156 /* SRBM_STATUS */
2157 tmp = RREG32(SRBM_STATUS);
2158
2159 if (tmp & IH_BUSY)
2160 reset_mask |= RADEON_RESET_IH;
2161
2162 if (tmp & SEM_BUSY)
2163 reset_mask |= RADEON_RESET_SEM;
2164
2165 if (tmp & GRBM_RQ_PENDING)
2166 reset_mask |= RADEON_RESET_GRBM;
2167
2168 if (tmp & VMC_BUSY)
2169 reset_mask |= RADEON_RESET_VMC;
19fc42ed 2170
014bb209
AD		 2171 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2172 MCC_BUSY | MCD_BUSY))
2173 reset_mask |= RADEON_RESET_MC;
2174
2175 if (evergreen_is_display_hung(rdev))
2176 reset_mask |= RADEON_RESET_DISPLAY;
2177
2178 /* VM_L2_STATUS */
2179 tmp = RREG32(VM_L2_STATUS);
2180 if (tmp & L2_BUSY)
2181 reset_mask |= RADEON_RESET_VMC;
2182
2183 return reset_mask;
2184}
2185
2186static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2187{
2188 struct evergreen_mc_save save;
2189 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2190 u32 tmp;
19fc42ed 2191
06bc6df0 2192 if (reset_mask == 0)
014bb209 2193 return;
06bc6df0
AD		 2194
2195 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2196
1c534671 2197 evergreen_print_gpu_status_regs(rdev);
06bc6df0
AD		 2198 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2199 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2200 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2201 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2202
1c534671
AD		 2203 /* Disable CP parsing/prefetching */
2204 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2205
2206 if (reset_mask & RADEON_RESET_DMA) {
2207 /* dma0 */
2208 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2209 tmp &= ~DMA_RB_ENABLE;
2210 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
014bb209
AD		 2211 }
2212 if (reset_mask & RADEON_RESET_DMA1) {
1c534671
AD		 2213 /* dma1 */
2214 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2215 tmp &= ~DMA_RB_ENABLE;
2216 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2217 }
2218
f770d78a
AD		 2219 udelay(50);
2220
2221 evergreen_mc_stop(rdev, &save);
2222 if (evergreen_mc_wait_for_idle(rdev)) {
2223 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2224 }
2225
1c534671
AD		 2226 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2227 grbm_soft_reset = SOFT_RESET_CB |
2228 SOFT_RESET_DB |
2229 SOFT_RESET_GDS |
2230 SOFT_RESET_PA |
2231 SOFT_RESET_SC |
2232 SOFT_RESET_BCI |
2233 SOFT_RESET_SPI |
2234 SOFT_RESET_SX |
2235 SOFT_RESET_TC |
2236 SOFT_RESET_TA |
2237 SOFT_RESET_VGT |
2238 SOFT_RESET_IA;
2239 }
2240
2241 if (reset_mask & RADEON_RESET_CP) {
2242 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2243
2244 srbm_soft_reset |= SOFT_RESET_GRBM;
2245 }
06bc6df0
AD		 2246
2247 if (reset_mask & RADEON_RESET_DMA)
014bb209
AD		 2248 srbm_soft_reset |= SOFT_RESET_DMA;
2249
2250 if (reset_mask & RADEON_RESET_DMA1)
2251 srbm_soft_reset |= SOFT_RESET_DMA1;
2252
2253 if (reset_mask & RADEON_RESET_DISPLAY)
2254 srbm_soft_reset |= SOFT_RESET_DC;
2255
2256 if (reset_mask & RADEON_RESET_RLC)
2257 grbm_soft_reset |= SOFT_RESET_RLC;
2258
2259 if (reset_mask & RADEON_RESET_SEM)
2260 srbm_soft_reset |= SOFT_RESET_SEM;
2261
2262 if (reset_mask & RADEON_RESET_IH)
2263 srbm_soft_reset |= SOFT_RESET_IH;
2264
2265 if (reset_mask & RADEON_RESET_GRBM)
2266 srbm_soft_reset |= SOFT_RESET_GRBM;
2267
2268 if (reset_mask & RADEON_RESET_VMC)
2269 srbm_soft_reset |= SOFT_RESET_VMC;
2270
2271 if (reset_mask & RADEON_RESET_MC)
2272 srbm_soft_reset |= SOFT_RESET_MC;
1c534671
AD		 2273
2274 if (grbm_soft_reset) {
2275 tmp = RREG32(GRBM_SOFT_RESET);
2276 tmp |= grbm_soft_reset;
2277 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2278 WREG32(GRBM_SOFT_RESET, tmp);
2279 tmp = RREG32(GRBM_SOFT_RESET);
2280
2281 udelay(50);
2282
2283 tmp &= ~grbm_soft_reset;
2284 WREG32(GRBM_SOFT_RESET, tmp);
2285 tmp = RREG32(GRBM_SOFT_RESET);
2286 }
2287
2288 if (srbm_soft_reset) {
2289 tmp = RREG32(SRBM_SOFT_RESET);
2290 tmp |= srbm_soft_reset;
2291 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2292 WREG32(SRBM_SOFT_RESET, tmp);
2293 tmp = RREG32(SRBM_SOFT_RESET);
2294
2295 udelay(50);
2296
2297 tmp &= ~srbm_soft_reset;
2298 WREG32(SRBM_SOFT_RESET, tmp);
2299 tmp = RREG32(SRBM_SOFT_RESET);
2300 }
06bc6df0
AD		 2301
2302 /* Wait a little for things to settle down */
2303 udelay(50);
2304
c476dde2 2305 evergreen_mc_resume(rdev, &save);
1c534671
AD		 2306 udelay(50);
2307
1c534671 2308 evergreen_print_gpu_status_regs(rdev);
c476dde2
AD		 2309}
2310
2311int si_asic_reset(struct radeon_device *rdev)
2312{
014bb209
AD		 2313 u32 reset_mask;
2314
2315 reset_mask = si_gpu_check_soft_reset(rdev);
2316
2317 if (reset_mask)
2318 r600_set_bios_scratch_engine_hung(rdev, true);
2319
2320 si_gpu_soft_reset(rdev, reset_mask);
2321
2322 reset_mask = si_gpu_check_soft_reset(rdev);
2323
2324 if (!reset_mask)
2325 r600_set_bios_scratch_engine_hung(rdev, false);
2326
2327 return 0;
c476dde2
AD		 2328}
2329
123bc183
AD		 2330/**
2331 * si_gfx_is_lockup - Check if the GFX engine is locked up
2332 *
2333 * @rdev: radeon_device pointer
2334 * @ring: radeon_ring structure holding ring information
2335 *
2336 * Check if the GFX engine is locked up.
2337 * Returns true if the engine appears to be locked up, false if not.
2338 */
2339bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2340{
2341 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2342
2343 if (!(reset_mask & (RADEON_RESET_GFX |
2344 RADEON_RESET_COMPUTE |
2345 RADEON_RESET_CP))) {
2346 radeon_ring_lockup_update(ring);
2347 return false;
2348 }
2349 /* force CP activities */
2350 radeon_ring_force_activity(rdev, ring);
2351 return radeon_ring_test_lockup(rdev, ring);
2352}
2353
2354/**
2355 * si_dma_is_lockup - Check if the DMA engine is locked up
2356 *
2357 * @rdev: radeon_device pointer
2358 * @ring: radeon_ring structure holding ring information
2359 *
2360 * Check if the async DMA engine is locked up.
2361 * Returns true if the engine appears to be locked up, false if not.
2362 */
2363bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2364{
2365 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2366 u32 mask;
2367
2368 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2369 mask = RADEON_RESET_DMA;
2370 else
2371 mask = RADEON_RESET_DMA1;
2372
2373 if (!(reset_mask & mask)) {
2374 radeon_ring_lockup_update(ring);
2375 return false;
2376 }
2377 /* force ring activities */
2378 radeon_ring_force_activity(rdev, ring);
2379 return radeon_ring_test_lockup(rdev, ring);
2380}
2381
d2800ee5
AD		 2382/* MC */
2383static void si_mc_program(struct radeon_device *rdev)
2384{
2385 struct evergreen_mc_save save;
2386 u32 tmp;
2387 int i, j;
2388
2389 /* Initialize HDP */
2390 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2391 WREG32((0x2c14 + j), 0x00000000);
2392 WREG32((0x2c18 + j), 0x00000000);
2393 WREG32((0x2c1c + j), 0x00000000);
2394 WREG32((0x2c20 + j), 0x00000000);
2395 WREG32((0x2c24 + j), 0x00000000);
2396 }
2397 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2398
2399 evergreen_mc_stop(rdev, &save);
2400 if (radeon_mc_wait_for_idle(rdev)) {
2401 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2402 }
2403 /* Lockout access through VGA aperture*/
2404 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2405 /* Update configuration */
2406 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2407 rdev->mc.vram_start >> 12);
2408 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2409 rdev->mc.vram_end >> 12);
2410 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2411 rdev->vram_scratch.gpu_addr >> 12);
2412 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2413 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2414 WREG32(MC_VM_FB_LOCATION, tmp);
2415 /* XXX double check these! */
2416 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2417 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2418 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2419 WREG32(MC_VM_AGP_BASE, 0);
2420 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2421 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2422 if (radeon_mc_wait_for_idle(rdev)) {
2423 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2424 }
2425 evergreen_mc_resume(rdev, &save);
2426 /* we need to own VRAM, so turn off the VGA renderer here
2427 * to stop it overwriting our objects */
2428 rv515_vga_render_disable(rdev);
2429}
2430
2431/* SI MC address space is 40 bits */
2432static void si_vram_location(struct radeon_device *rdev,
2433 struct radeon_mc *mc, u64 base)
2434{
2435 mc->vram_start = base;
2436 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2437 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2438 mc->real_vram_size = mc->aper_size;
2439 mc->mc_vram_size = mc->aper_size;
2440 }
2441 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2442 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2443 mc->mc_vram_size >> 20, mc->vram_start,
2444 mc->vram_end, mc->real_vram_size >> 20);
2445}
2446
2447static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2448{
2449 u64 size_af, size_bf;
2450
2451 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2452 size_bf = mc->vram_start & ~mc->gtt_base_align;
2453 if (size_bf > size_af) {
2454 if (mc->gtt_size > size_bf) {
2455 dev_warn(rdev->dev, "limiting GTT\n");
2456 mc->gtt_size = size_bf;
2457 }
2458 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2459 } else {
2460 if (mc->gtt_size > size_af) {
2461 dev_warn(rdev->dev, "limiting GTT\n");
2462 mc->gtt_size = size_af;
2463 }
2464 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2465 }
2466 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2467 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2468 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2469}
2470
2471static void si_vram_gtt_location(struct radeon_device *rdev,
2472 struct radeon_mc *mc)
2473{
2474 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2475 /* leave room for at least 1024M GTT */
2476 dev_warn(rdev->dev, "limiting VRAM\n");
2477 mc->real_vram_size = 0xFFC0000000ULL;
2478 mc->mc_vram_size = 0xFFC0000000ULL;
2479 }
2480 si_vram_location(rdev, &rdev->mc, 0);
2481 rdev->mc.gtt_base_align = 0;
2482 si_gtt_location(rdev, mc);
2483}
2484
2485static int si_mc_init(struct radeon_device *rdev)
2486{
2487 u32 tmp;
2488 int chansize, numchan;
2489
2490 /* Get VRAM informations */
2491 rdev->mc.vram_is_ddr = true;
2492 tmp = RREG32(MC_ARB_RAMCFG);
2493 if (tmp & CHANSIZE_OVERRIDE) {
2494 chansize = 16;
2495 } else if (tmp & CHANSIZE_MASK) {
2496 chansize = 64;
2497 } else {
2498 chansize = 32;
2499 }
2500 tmp = RREG32(MC_SHARED_CHMAP);
2501 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2502 case 0:
2503 default:
2504 numchan = 1;
2505 break;
2506 case 1:
2507 numchan = 2;
2508 break;
2509 case 2:
2510 numchan = 4;
2511 break;
2512 case 3:
2513 numchan = 8;
2514 break;
2515 case 4:
2516 numchan = 3;
2517 break;
2518 case 5:
2519 numchan = 6;
2520 break;
2521 case 6:
2522 numchan = 10;
2523 break;
2524 case 7:
2525 numchan = 12;
2526 break;
2527 case 8:
2528 numchan = 16;
2529 break;
2530 }
2531 rdev->mc.vram_width = numchan * chansize;
2532 /* Could aper size report 0 ? */
2533 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2534 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2535 /* size in MB on si */
2536 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2537 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2538 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2539 si_vram_gtt_location(rdev, &rdev->mc);
2540 radeon_update_bandwidth_info(rdev);
2541
2542 return 0;
2543}
2544
2545/*
2546 * GART
2547 */
2548void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2549{
2550 /* flush hdp cache */
2551 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2552
2553 /* bits 0-15 are the VM contexts0-15 */
2554 WREG32(VM_INVALIDATE_REQUEST, 1);
2555}
2556
1109ca09 2557static int si_pcie_gart_enable(struct radeon_device *rdev)
d2800ee5
AD		 2558{
2559 int r, i;
2560
2561 if (rdev->gart.robj == NULL) {
2562 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2563 return -EINVAL;
2564 }
2565 r = radeon_gart_table_vram_pin(rdev);
2566 if (r)
2567 return r;
2568 radeon_gart_restore(rdev);
2569 /* Setup TLB control */
2570 WREG32(MC_VM_MX_L1_TLB_CNTL,
2571 (0xA << 7) |
2572 ENABLE_L1_TLB |
2573 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2574 ENABLE_ADVANCED_DRIVER_MODEL |
2575 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2576 /* Setup L2 cache */
2577 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2578 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2579 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2580 EFFECTIVE_L2_QUEUE_SIZE(7) |
2581 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2582 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2583 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2584 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2585 /* setup context0 */
2586 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2587 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2588 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2589 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2590 (u32)(rdev->dummy_page.addr >> 12));
2591 WREG32(VM_CONTEXT0_CNTL2, 0);
2592 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2593 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2594
2595 WREG32(0x15D4, 0);
2596 WREG32(0x15D8, 0);
2597 WREG32(0x15DC, 0);
2598
2599 /* empty context1-15 */
d2800ee5
AD		 2600 /* set vm size, must be a multiple of 4 */
2601 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
c21b328e 2602 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
23d4f1f2
AD		 2603 /* Assign the pt base to something valid for now; the pts used for
2604 * the VMs are determined by the application and setup and assigned
2605 * on the fly in the vm part of radeon_gart.c
2606 */
d2800ee5
AD		 2607 for (i = 1; i < 16; i++) {
2608 if (i < 8)
2609 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2610 rdev->gart.table_addr >> 12);
2611 else
2612 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2613 rdev->gart.table_addr >> 12);
2614 }
2615
2616 /* enable context1-15 */
2617 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2618 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 2619 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 2620 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 2621 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2622 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2623 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2624 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2625 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2626 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2627 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2628 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2629 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2630 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2631 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2632 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
d2800ee5
AD		 2633
2634 si_pcie_gart_tlb_flush(rdev);
2635 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2636 (unsigned)(rdev->mc.gtt_size >> 20),
2637 (unsigned long long)rdev->gart.table_addr);
2638 rdev->gart.ready = true;
2639 return 0;
2640}
2641
1109ca09 2642static void si_pcie_gart_disable(struct radeon_device *rdev)
d2800ee5
AD		 2643{
2644 /* Disable all tables */
2645 WREG32(VM_CONTEXT0_CNTL, 0);
2646 WREG32(VM_CONTEXT1_CNTL, 0);
2647 /* Setup TLB control */
2648 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2649 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2650 /* Setup L2 cache */
2651 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2652 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2653 EFFECTIVE_L2_QUEUE_SIZE(7) |
2654 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2655 WREG32(VM_L2_CNTL2, 0);
2656 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2657 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2658 radeon_gart_table_vram_unpin(rdev);
2659}
2660
1109ca09 2661static void si_pcie_gart_fini(struct radeon_device *rdev)
d2800ee5
AD		 2662{
2663 si_pcie_gart_disable(rdev);
2664 radeon_gart_table_vram_free(rdev);
2665 radeon_gart_fini(rdev);
2666}
2667
498dd8b3
AD		 2668/* vm parser */
2669static bool si_vm_reg_valid(u32 reg)
2670{
2671 /* context regs are fine */
2672 if (reg >= 0x28000)
2673 return true;
2674
2675 /* check config regs */
2676 switch (reg) {
2677 case GRBM_GFX_INDEX:
f418b88a 2678 case CP_STRMOUT_CNTL:
498dd8b3
AD		 2679 case VGT_VTX_VECT_EJECT_REG:
2680 case VGT_CACHE_INVALIDATION:
2681 case VGT_ESGS_RING_SIZE:
2682 case VGT_GSVS_RING_SIZE:
2683 case VGT_GS_VERTEX_REUSE:
2684 case VGT_PRIMITIVE_TYPE:
2685 case VGT_INDEX_TYPE:
2686 case VGT_NUM_INDICES:
2687 case VGT_NUM_INSTANCES:
2688 case VGT_TF_RING_SIZE:
2689 case VGT_HS_OFFCHIP_PARAM:
2690 case VGT_TF_MEMORY_BASE:
2691 case PA_CL_ENHANCE:
2692 case PA_SU_LINE_STIPPLE_VALUE:
2693 case PA_SC_LINE_STIPPLE_STATE:
2694 case PA_SC_ENHANCE:
2695 case SQC_CACHES:
2696 case SPI_STATIC_THREAD_MGMT_1:
2697 case SPI_STATIC_THREAD_MGMT_2:
2698 case SPI_STATIC_THREAD_MGMT_3:
2699 case SPI_PS_MAX_WAVE_ID:
2700 case SPI_CONFIG_CNTL:
2701 case SPI_CONFIG_CNTL_1:
2702 case TA_CNTL_AUX:
2703 return true;
2704 default:
2705 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2706 return false;
2707 }
2708}
2709
2710static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2711 u32 *ib, struct radeon_cs_packet *pkt)
2712{
2713 switch (pkt->opcode) {
2714 case PACKET3_NOP:
2715 case PACKET3_SET_BASE:
2716 case PACKET3_SET_CE_DE_COUNTERS:
2717 case PACKET3_LOAD_CONST_RAM:
2718 case PACKET3_WRITE_CONST_RAM:
2719 case PACKET3_WRITE_CONST_RAM_OFFSET:
2720 case PACKET3_DUMP_CONST_RAM:
2721 case PACKET3_INCREMENT_CE_COUNTER:
2722 case PACKET3_WAIT_ON_DE_COUNTER:
2723 case PACKET3_CE_WRITE:
2724 break;
2725 default:
2726 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2727 return -EINVAL;
2728 }
2729 return 0;
2730}
2731
2732static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2733 u32 *ib, struct radeon_cs_packet *pkt)
2734{
2735 u32 idx = pkt->idx + 1;
2736 u32 idx_value = ib[idx];
2737 u32 start_reg, end_reg, reg, i;
5aa709be 2738 u32 command, info;
498dd8b3
AD		 2739
2740 switch (pkt->opcode) {
2741 case PACKET3_NOP:
2742 case PACKET3_SET_BASE:
2743 case PACKET3_CLEAR_STATE:
2744 case PACKET3_INDEX_BUFFER_SIZE:
2745 case PACKET3_DISPATCH_DIRECT:
2746 case PACKET3_DISPATCH_INDIRECT:
2747 case PACKET3_ALLOC_GDS:
2748 case PACKET3_WRITE_GDS_RAM:
2749 case PACKET3_ATOMIC_GDS:
2750 case PACKET3_ATOMIC:
2751 case PACKET3_OCCLUSION_QUERY:
2752 case PACKET3_SET_PREDICATION:
2753 case PACKET3_COND_EXEC:
2754 case PACKET3_PRED_EXEC:
2755 case PACKET3_DRAW_INDIRECT:
2756 case PACKET3_DRAW_INDEX_INDIRECT:
2757 case PACKET3_INDEX_BASE:
2758 case PACKET3_DRAW_INDEX_2:
2759 case PACKET3_CONTEXT_CONTROL:
2760 case PACKET3_INDEX_TYPE:
2761 case PACKET3_DRAW_INDIRECT_MULTI:
2762 case PACKET3_DRAW_INDEX_AUTO:
2763 case PACKET3_DRAW_INDEX_IMMD:
2764 case PACKET3_NUM_INSTANCES:
2765 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2766 case PACKET3_STRMOUT_BUFFER_UPDATE:
2767 case PACKET3_DRAW_INDEX_OFFSET_2:
2768 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2769 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2770 case PACKET3_MPEG_INDEX:
2771 case PACKET3_WAIT_REG_MEM:
2772 case PACKET3_MEM_WRITE:
2773 case PACKET3_PFP_SYNC_ME:
2774 case PACKET3_SURFACE_SYNC:
2775 case PACKET3_EVENT_WRITE:
2776 case PACKET3_EVENT_WRITE_EOP:
2777 case PACKET3_EVENT_WRITE_EOS:
2778 case PACKET3_SET_CONTEXT_REG:
2779 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2780 case PACKET3_SET_SH_REG:
2781 case PACKET3_SET_SH_REG_OFFSET:
2782 case PACKET3_INCREMENT_DE_COUNTER:
2783 case PACKET3_WAIT_ON_CE_COUNTER:
2784 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2785 case PACKET3_ME_WRITE:
2786 break;
2787 case PACKET3_COPY_DATA:
2788 if ((idx_value & 0xf00) == 0) {
2789 reg = ib[idx + 3] * 4;
2790 if (!si_vm_reg_valid(reg))
2791 return -EINVAL;
2792 }
2793 break;
2794 case PACKET3_WRITE_DATA:
2795 if ((idx_value & 0xf00) == 0) {
2796 start_reg = ib[idx + 1] * 4;
2797 if (idx_value & 0x10000) {
2798 if (!si_vm_reg_valid(start_reg))
2799 return -EINVAL;
2800 } else {
2801 for (i = 0; i < (pkt->count - 2); i++) {
2802 reg = start_reg + (4 * i);
2803 if (!si_vm_reg_valid(reg))
2804 return -EINVAL;
2805 }
2806 }
2807 }
2808 break;
2809 case PACKET3_COND_WRITE:
2810 if (idx_value & 0x100) {
2811 reg = ib[idx + 5] * 4;
2812 if (!si_vm_reg_valid(reg))
2813 return -EINVAL;
2814 }
2815 break;
2816 case PACKET3_COPY_DW:
2817 if (idx_value & 0x2) {
2818 reg = ib[idx + 3] * 4;
2819 if (!si_vm_reg_valid(reg))
2820 return -EINVAL;
2821 }
2822 break;
2823 case PACKET3_SET_CONFIG_REG:
2824 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2825 end_reg = 4 * pkt->count + start_reg - 4;
2826 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2827 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2828 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2829 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2830 return -EINVAL;
2831 }
2832 for (i = 0; i < pkt->count; i++) {
2833 reg = start_reg + (4 * i);
2834 if (!si_vm_reg_valid(reg))
2835 return -EINVAL;
2836 }
2837 break;
5aa709be
AD		 2838 case PACKET3_CP_DMA:
2839 command = ib[idx + 4];
2840 info = ib[idx + 1];
2841 if (command & PACKET3_CP_DMA_CMD_SAS) {
2842 /* src address space is register */
2843 if (((info & 0x60000000) >> 29) == 0) {
2844 start_reg = idx_value << 2;
2845 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2846 reg = start_reg;
2847 if (!si_vm_reg_valid(reg)) {
2848 DRM_ERROR("CP DMA Bad SRC register\n");
2849 return -EINVAL;
2850 }
2851 } else {
2852 for (i = 0; i < (command & 0x1fffff); i++) {
2853 reg = start_reg + (4 * i);
2854 if (!si_vm_reg_valid(reg)) {
2855 DRM_ERROR("CP DMA Bad SRC register\n");
2856 return -EINVAL;
2857 }
2858 }
2859 }
2860 }
2861 }
2862 if (command & PACKET3_CP_DMA_CMD_DAS) {
2863 /* dst address space is register */
2864 if (((info & 0x00300000) >> 20) == 0) {
2865 start_reg = ib[idx + 2];
2866 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2867 reg = start_reg;
2868 if (!si_vm_reg_valid(reg)) {
2869 DRM_ERROR("CP DMA Bad DST register\n");
2870 return -EINVAL;
2871 }
2872 } else {
2873 for (i = 0; i < (command & 0x1fffff); i++) {
2874 reg = start_reg + (4 * i);
2875 if (!si_vm_reg_valid(reg)) {
2876 DRM_ERROR("CP DMA Bad DST register\n");
2877 return -EINVAL;
2878 }
2879 }
2880 }
2881 }
2882 }
2883 break;
498dd8b3
AD		 2884 default:
2885 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2886 return -EINVAL;
2887 }
2888 return 0;
2889}
2890
2891static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2892 u32 *ib, struct radeon_cs_packet *pkt)
2893{
2894 u32 idx = pkt->idx + 1;
2895 u32 idx_value = ib[idx];
2896 u32 start_reg, reg, i;
2897
2898 switch (pkt->opcode) {
2899 case PACKET3_NOP:
2900 case PACKET3_SET_BASE:
2901 case PACKET3_CLEAR_STATE:
2902 case PACKET3_DISPATCH_DIRECT:
2903 case PACKET3_DISPATCH_INDIRECT:
2904 case PACKET3_ALLOC_GDS:
2905 case PACKET3_WRITE_GDS_RAM:
2906 case PACKET3_ATOMIC_GDS:
2907 case PACKET3_ATOMIC:
2908 case PACKET3_OCCLUSION_QUERY:
2909 case PACKET3_SET_PREDICATION:
2910 case PACKET3_COND_EXEC:
2911 case PACKET3_PRED_EXEC:
2912 case PACKET3_CONTEXT_CONTROL:
2913 case PACKET3_STRMOUT_BUFFER_UPDATE:
2914 case PACKET3_WAIT_REG_MEM:
2915 case PACKET3_MEM_WRITE:
2916 case PACKET3_PFP_SYNC_ME:
2917 case PACKET3_SURFACE_SYNC:
2918 case PACKET3_EVENT_WRITE:
2919 case PACKET3_EVENT_WRITE_EOP:
2920 case PACKET3_EVENT_WRITE_EOS:
2921 case PACKET3_SET_CONTEXT_REG:
2922 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2923 case PACKET3_SET_SH_REG:
2924 case PACKET3_SET_SH_REG_OFFSET:
2925 case PACKET3_INCREMENT_DE_COUNTER:
2926 case PACKET3_WAIT_ON_CE_COUNTER:
2927 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2928 case PACKET3_ME_WRITE:
2929 break;
2930 case PACKET3_COPY_DATA:
2931 if ((idx_value & 0xf00) == 0) {
2932 reg = ib[idx + 3] * 4;
2933 if (!si_vm_reg_valid(reg))
2934 return -EINVAL;
2935 }
2936 break;
2937 case PACKET3_WRITE_DATA:
2938 if ((idx_value & 0xf00) == 0) {
2939 start_reg = ib[idx + 1] * 4;
2940 if (idx_value & 0x10000) {
2941 if (!si_vm_reg_valid(start_reg))
2942 return -EINVAL;
2943 } else {
2944 for (i = 0; i < (pkt->count - 2); i++) {
2945 reg = start_reg + (4 * i);
2946 if (!si_vm_reg_valid(reg))
2947 return -EINVAL;
2948 }
2949 }
2950 }
2951 break;
2952 case PACKET3_COND_WRITE:
2953 if (idx_value & 0x100) {
2954 reg = ib[idx + 5] * 4;
2955 if (!si_vm_reg_valid(reg))
2956 return -EINVAL;
2957 }
2958 break;
2959 case PACKET3_COPY_DW:
2960 if (idx_value & 0x2) {
2961 reg = ib[idx + 3] * 4;
2962 if (!si_vm_reg_valid(reg))
2963 return -EINVAL;
2964 }
2965 break;
2966 default:
2967 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2968 return -EINVAL;
2969 }
2970 return 0;
2971}
2972
2973int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2974{
2975 int ret = 0;
2976 u32 idx = 0;
2977 struct radeon_cs_packet pkt;
2978
2979 do {
2980 pkt.idx = idx;
4e872ae2
IH		 2981 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
2982 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
498dd8b3
AD		 2983 pkt.one_reg_wr = 0;
2984 switch (pkt.type) {
4e872ae2 2985 case RADEON_PACKET_TYPE0:
498dd8b3
AD		 2986 dev_err(rdev->dev, "Packet0 not allowed!\n");
2987 ret = -EINVAL;
2988 break;
4e872ae2 2989 case RADEON_PACKET_TYPE2:
498dd8b3
AD		 2990 idx += 1;
2991 break;
4e872ae2
IH		 2992 case RADEON_PACKET_TYPE3:
2993 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
498dd8b3
AD		 2994 if (ib->is_const_ib)
2995 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2996 else {
876dc9f3 2997 switch (ib->ring) {
498dd8b3
AD		 2998 case RADEON_RING_TYPE_GFX_INDEX:
2999 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
3000 break;
3001 case CAYMAN_RING_TYPE_CP1_INDEX:
3002 case CAYMAN_RING_TYPE_CP2_INDEX:
3003 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
3004 break;
3005 default:
876dc9f3 3006 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
498dd8b3
AD		 3007 ret = -EINVAL;
3008 break;
3009 }
3010 }
3011 idx += pkt.count + 2;
3012 break;
3013 default:
3014 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3015 ret = -EINVAL;
3016 break;
3017 }
3018 if (ret)
3019 break;
3020 } while (idx < ib->length_dw);
3021
3022 return ret;
3023}
3024
d2800ee5
AD		 3025/*
3026 * vm
3027 */
3028int si_vm_init(struct radeon_device *rdev)
3029{
3030 /* number of VMs */
3031 rdev->vm_manager.nvm = 16;
3032 /* base offset of vram pages */
3033 rdev->vm_manager.vram_base_offset = 0;
3034
3035 return 0;
3036}
3037
3038void si_vm_fini(struct radeon_device *rdev)
3039{
3040}
3041
82ffd92b
AD		 3042/**
3043 * si_vm_set_page - update the page tables using the CP
3044 *
3045 * @rdev: radeon_device pointer
43f1214a 3046 * @ib: indirect buffer to fill with commands
82ffd92b
AD		 3047 * @pe: addr of the page entry
3048 * @addr: dst addr to write into pe
3049 * @count: number of page entries to update
3050 * @incr: increase next addr by incr bytes
3051 * @flags: access flags
3052 *
43f1214a 3053 * Update the page tables using the CP (SI).
82ffd92b 3054 */
43f1214a
AD		 3055void si_vm_set_page(struct radeon_device *rdev,
3056 struct radeon_ib *ib,
3057 uint64_t pe,
82ffd92b
AD		 3058 uint64_t addr, unsigned count,
3059 uint32_t incr, uint32_t flags)
d2800ee5 3060{
82ffd92b 3061 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
deab48f1
AD		 3062 uint64_t value;
3063 unsigned ndw;
3064
3065 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
3066 while (count) {
3067 ndw = 2 + count * 2;
3068 if (ndw > 0x3FFE)
3069 ndw = 0x3FFE;
3070
43f1214a
AD		 3071 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
3072 ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
3073 WRITE_DATA_DST_SEL(1));
3074 ib->ptr[ib->length_dw++] = pe;
3075 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
deab48f1
AD		 3076 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3077 if (flags & RADEON_VM_PAGE_SYSTEM) {
3078 value = radeon_vm_map_gart(rdev, addr);
3079 value &= 0xFFFFFFFFFFFFF000ULL;
3080 } else if (flags & RADEON_VM_PAGE_VALID) {
3081 value = addr;
3082 } else {
3083 value = 0;
3084 }
3085 addr += incr;
3086 value |= r600_flags;
43f1214a
AD		 3087 ib->ptr[ib->length_dw++] = value;
3088 ib->ptr[ib->length_dw++] = upper_32_bits(value);
deab48f1
AD		 3089 }
3090 }
3091 } else {
3092 /* DMA */
3093 if (flags & RADEON_VM_PAGE_SYSTEM) {
3094 while (count) {
3095 ndw = count * 2;
3096 if (ndw > 0xFFFFE)
3097 ndw = 0xFFFFE;
3098
3099 /* for non-physically contiguous pages (system) */
43f1214a
AD		 3100 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
3101 ib->ptr[ib->length_dw++] = pe;
3102 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
deab48f1
AD		 3103 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3104 if (flags & RADEON_VM_PAGE_SYSTEM) {
3105 value = radeon_vm_map_gart(rdev, addr);
3106 value &= 0xFFFFFFFFFFFFF000ULL;
3107 } else if (flags & RADEON_VM_PAGE_VALID) {
3108 value = addr;
3109 } else {
3110 value = 0;
3111 }
3112 addr += incr;
3113 value |= r600_flags;
43f1214a
AD		 3114 ib->ptr[ib->length_dw++] = value;
3115 ib->ptr[ib->length_dw++] = upper_32_bits(value);
deab48f1
AD		 3116 }
3117 }
3118 } else {
3119 while (count) {
3120 ndw = count * 2;
3121 if (ndw > 0xFFFFE)
3122 ndw = 0xFFFFE;
3123
3124 if (flags & RADEON_VM_PAGE_VALID)
3125 value = addr;
3126 else
3127 value = 0;
3128 /* for physically contiguous pages (vram) */
43f1214a
AD		 3129 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
3130 ib->ptr[ib->length_dw++] = pe; /* dst addr */
3131 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3132 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
3133 ib->ptr[ib->length_dw++] = 0;
3134 ib->ptr[ib->length_dw++] = value; /* value */
3135 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3136 ib->ptr[ib->length_dw++] = incr; /* increment size */
3137 ib->ptr[ib->length_dw++] = 0;
deab48f1
AD		 3138 pe += ndw * 4;
3139 addr += (ndw / 2) * incr;
3140 count -= ndw / 2;
3141 }
d7025d89 3142 }
43f1214a
AD		 3143 while (ib->length_dw & 0x7)
3144 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);
82ffd92b 3145 }
d2800ee5
AD		 3146}
3147
498522b4 3148void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
d2800ee5 3149{
498522b4 3150 struct radeon_ring *ring = &rdev->ring[ridx];
d2800ee5 3151
ee60e29f 3152 if (vm == NULL)
d2800ee5
AD		 3153 return;
3154
76c44f2c
AD		 3155 /* write new base address */
3156 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3157 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3158 WRITE_DATA_DST_SEL(0)));
3159
ee60e29f 3160 if (vm->id < 8) {
76c44f2c
AD		 3161 radeon_ring_write(ring,
3162 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
ee60e29f 3163 } else {
76c44f2c
AD		 3164 radeon_ring_write(ring,
3165 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
ee60e29f 3166 }
76c44f2c 3167 radeon_ring_write(ring, 0);
fa87e62d 3168 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 3169
d2800ee5 3170 /* flush hdp cache */
76c44f2c
AD		 3171 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3172 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3173 WRITE_DATA_DST_SEL(0)));
3174 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3175 radeon_ring_write(ring, 0);
ee60e29f
CK		 3176 radeon_ring_write(ring, 0x1);
3177
d2800ee5 3178 /* bits 0-15 are the VM contexts0-15 */
76c44f2c
AD		 3179 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3180 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3181 WRITE_DATA_DST_SEL(0)));
3182 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3183 radeon_ring_write(ring, 0);
498522b4 3184 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 3185
3186 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3187 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3188 radeon_ring_write(ring, 0x0);
d2800ee5
AD		 3189}
3190
8c5fd7ef
AD		 3191void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3192{
3193 struct radeon_ring *ring = &rdev->ring[ridx];
3194
3195 if (vm == NULL)
3196 return;
3197
3198 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3199 if (vm->id < 8) {
3200 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3201 } else {
3202 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3203 }
3204 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3205
3206 /* flush hdp cache */
3207 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3208 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3209 radeon_ring_write(ring, 1);
3210
3211 /* bits 0-7 are the VM contexts0-7 */
3212 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3213 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3214 radeon_ring_write(ring, 1 << vm->id);
3215}
3216
347e7592
AD		 3217/*
3218 * RLC
3219 */
c420c745 3220void si_rlc_fini(struct radeon_device *rdev)
347e7592
AD		 3221{
3222 int r;
3223
3224 /* save restore block */
3225 if (rdev->rlc.save_restore_obj) {
3226 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3227 if (unlikely(r != 0))
3228 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3229 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3230 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3231
3232 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3233 rdev->rlc.save_restore_obj = NULL;
3234 }
3235
3236 /* clear state block */
3237 if (rdev->rlc.clear_state_obj) {
3238 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3239 if (unlikely(r != 0))
3240 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3241 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3242 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3243
3244 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3245 rdev->rlc.clear_state_obj = NULL;
3246 }
3247}
3248
c420c745 3249int si_rlc_init(struct radeon_device *rdev)
347e7592
AD		 3250{
3251 int r;
3252
3253 /* save restore block */
3254 if (rdev->rlc.save_restore_obj == NULL) {
3255 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3256 RADEON_GEM_DOMAIN_VRAM, NULL,
3257 &rdev->rlc.save_restore_obj);
347e7592
AD		 3258 if (r) {
3259 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3260 return r;
3261 }
3262 }
3263
3264 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3265 if (unlikely(r != 0)) {
3266 si_rlc_fini(rdev);
3267 return r;
3268 }
3269 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3270 &rdev->rlc.save_restore_gpu_addr);
5273db70 3271 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
347e7592 3272 if (r) {
347e7592
AD		 3273 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3274 si_rlc_fini(rdev);
3275 return r;
3276 }
3277
3278 /* clear state block */
3279 if (rdev->rlc.clear_state_obj == NULL) {
3280 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
40f5cf99
AD		 3281 RADEON_GEM_DOMAIN_VRAM, NULL,
3282 &rdev->rlc.clear_state_obj);
347e7592
AD		 3283 if (r) {
3284 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3285 si_rlc_fini(rdev);
3286 return r;
3287 }
3288 }
3289 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3290 if (unlikely(r != 0)) {
3291 si_rlc_fini(rdev);
3292 return r;
3293 }
3294 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3295 &rdev->rlc.clear_state_gpu_addr);
5273db70 3296 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
347e7592 3297 if (r) {
347e7592
AD		 3298 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3299 si_rlc_fini(rdev);
3300 return r;
3301 }
3302
3303 return 0;
3304}
3305
3306static void si_rlc_stop(struct radeon_device *rdev)
3307{
3308 WREG32(RLC_CNTL, 0);
3309}
3310
3311static void si_rlc_start(struct radeon_device *rdev)
3312{
3313 WREG32(RLC_CNTL, RLC_ENABLE);
3314}
3315
3316static int si_rlc_resume(struct radeon_device *rdev)
3317{
3318 u32 i;
3319 const __be32 *fw_data;
3320
3321 if (!rdev->rlc_fw)
3322 return -EINVAL;
3323
3324 si_rlc_stop(rdev);
3325
3326 WREG32(RLC_RL_BASE, 0);
3327 WREG32(RLC_RL_SIZE, 0);
3328 WREG32(RLC_LB_CNTL, 0);
3329 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3330 WREG32(RLC_LB_CNTR_INIT, 0);
3331
3332 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3333 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3334
3335 WREG32(RLC_MC_CNTL, 0);
3336 WREG32(RLC_UCODE_CNTL, 0);
3337
3338 fw_data = (const __be32 *)rdev->rlc_fw->data;
3339 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3340 WREG32(RLC_UCODE_ADDR, i);
3341 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3342 }
3343 WREG32(RLC_UCODE_ADDR, 0);
3344
3345 si_rlc_start(rdev);
3346
3347 return 0;
3348}
3349
25a857fb
AD		 3350static void si_enable_interrupts(struct radeon_device *rdev)
3351{
3352 u32 ih_cntl = RREG32(IH_CNTL);
3353 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3354
3355 ih_cntl |= ENABLE_INTR;
3356 ih_rb_cntl |= IH_RB_ENABLE;
3357 WREG32(IH_CNTL, ih_cntl);
3358 WREG32(IH_RB_CNTL, ih_rb_cntl);
3359 rdev->ih.enabled = true;
3360}
3361
3362static void si_disable_interrupts(struct radeon_device *rdev)
3363{
3364 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3365 u32 ih_cntl = RREG32(IH_CNTL);
3366
3367 ih_rb_cntl &= ~IH_RB_ENABLE;
3368 ih_cntl &= ~ENABLE_INTR;
3369 WREG32(IH_RB_CNTL, ih_rb_cntl);
3370 WREG32(IH_CNTL, ih_cntl);
3371 /* set rptr, wptr to 0 */
3372 WREG32(IH_RB_RPTR, 0);
3373 WREG32(IH_RB_WPTR, 0);
3374 rdev->ih.enabled = false;
25a857fb
AD		 3375 rdev->ih.rptr = 0;
3376}
3377
3378static void si_disable_interrupt_state(struct radeon_device *rdev)
3379{
3380 u32 tmp;
3381
3382 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3383 WREG32(CP_INT_CNTL_RING1, 0);
3384 WREG32(CP_INT_CNTL_RING2, 0);
8c5fd7ef
AD		 3385 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3386 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3387 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3388 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
25a857fb
AD		 3389 WREG32(GRBM_INT_CNTL, 0);
3390 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3391 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3392 if (rdev->num_crtc >= 4) {
3393 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3394 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3395 }
3396 if (rdev->num_crtc >= 6) {
3397 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3398 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3399 }
3400
3401 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3402 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3403 if (rdev->num_crtc >= 4) {
3404 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3405 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3406 }
3407 if (rdev->num_crtc >= 6) {
3408 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3409 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3410 }
3411
3412 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3413
3414 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3415 WREG32(DC_HPD1_INT_CONTROL, tmp);
3416 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3417 WREG32(DC_HPD2_INT_CONTROL, tmp);
3418 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3419 WREG32(DC_HPD3_INT_CONTROL, tmp);
3420 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3421 WREG32(DC_HPD4_INT_CONTROL, tmp);
3422 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3423 WREG32(DC_HPD5_INT_CONTROL, tmp);
3424 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3425 WREG32(DC_HPD6_INT_CONTROL, tmp);
3426
3427}
3428
3429static int si_irq_init(struct radeon_device *rdev)
3430{
3431 int ret = 0;
3432 int rb_bufsz;
3433 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3434
3435 /* allocate ring */
3436 ret = r600_ih_ring_alloc(rdev);
3437 if (ret)
3438 return ret;
3439
3440 /* disable irqs */
3441 si_disable_interrupts(rdev);
3442
3443 /* init rlc */
3444 ret = si_rlc_resume(rdev);
3445 if (ret) {
3446 r600_ih_ring_fini(rdev);
3447 return ret;
3448 }
3449
3450 /* setup interrupt control */
3451 /* set dummy read address to ring address */
3452 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3453 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3454 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3455 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3456 */
3457 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3458 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3459 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3460 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3461
3462 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3463 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3464
3465 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3466 IH_WPTR_OVERFLOW_CLEAR |
3467 (rb_bufsz << 1));
3468
3469 if (rdev->wb.enabled)
3470 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3471
3472 /* set the writeback address whether it's enabled or not */
3473 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3474 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3475
3476 WREG32(IH_RB_CNTL, ih_rb_cntl);
3477
3478 /* set rptr, wptr to 0 */
3479 WREG32(IH_RB_RPTR, 0);
3480 WREG32(IH_RB_WPTR, 0);
3481
3482 /* Default settings for IH_CNTL (disabled at first) */
3483 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3484 /* RPTR_REARM only works if msi's are enabled */
3485 if (rdev->msi_enabled)
3486 ih_cntl |= RPTR_REARM;
3487 WREG32(IH_CNTL, ih_cntl);
3488
3489 /* force the active interrupt state to all disabled */
3490 si_disable_interrupt_state(rdev);
3491
2099810f
DA		 3492 pci_set_master(rdev->pdev);
3493
25a857fb
AD		 3494 /* enable irqs */
3495 si_enable_interrupts(rdev);
3496
3497 return ret;
3498}
3499
3500int si_irq_set(struct radeon_device *rdev)
3501{
3502 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3503 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3504 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3505 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3506 u32 grbm_int_cntl = 0;
3507 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
8c5fd7ef 3508 u32 dma_cntl, dma_cntl1;
25a857fb
AD		 3509
3510 if (!rdev->irq.installed) {
3511 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3512 return -EINVAL;
3513 }
3514 /* don't enable anything if the ih is disabled */
3515 if (!rdev->ih.enabled) {
3516 si_disable_interrupts(rdev);
3517 /* force the active interrupt state to all disabled */
3518 si_disable_interrupt_state(rdev);
3519 return 0;
3520 }
3521
3522 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3523 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3524 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3525 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3526 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3527 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3528
8c5fd7ef
AD		 3529 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3530 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3531
25a857fb 3532 /* enable CP interrupts on all rings */
736fc37f 3533 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
25a857fb
AD		 3534 DRM_DEBUG("si_irq_set: sw int gfx\n");
3535 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3536 }
736fc37f 3537 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
25a857fb
AD		 3538 DRM_DEBUG("si_irq_set: sw int cp1\n");
3539 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3540 }
736fc37f 3541 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
25a857fb
AD		 3542 DRM_DEBUG("si_irq_set: sw int cp2\n");
3543 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3544 }
8c5fd7ef
AD		 3545 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3546 DRM_DEBUG("si_irq_set: sw int dma\n");
3547 dma_cntl |= TRAP_ENABLE;
3548 }
3549
3550 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3551 DRM_DEBUG("si_irq_set: sw int dma1\n");
3552 dma_cntl1 |= TRAP_ENABLE;
3553 }
25a857fb 3554 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3555 atomic_read(&rdev->irq.pflip[0])) {
25a857fb
AD		 3556 DRM_DEBUG("si_irq_set: vblank 0\n");
3557 crtc1 |= VBLANK_INT_MASK;
3558 }
3559 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3560 atomic_read(&rdev->irq.pflip[1])) {
25a857fb
AD		 3561 DRM_DEBUG("si_irq_set: vblank 1\n");
3562 crtc2 |= VBLANK_INT_MASK;
3563 }
3564 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3565 atomic_read(&rdev->irq.pflip[2])) {
25a857fb
AD		 3566 DRM_DEBUG("si_irq_set: vblank 2\n");
3567 crtc3 |= VBLANK_INT_MASK;
3568 }
3569 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3570 atomic_read(&rdev->irq.pflip[3])) {
25a857fb
AD		 3571 DRM_DEBUG("si_irq_set: vblank 3\n");
3572 crtc4 |= VBLANK_INT_MASK;
3573 }
3574 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3575 atomic_read(&rdev->irq.pflip[4])) {
25a857fb
AD		 3576 DRM_DEBUG("si_irq_set: vblank 4\n");
3577 crtc5 |= VBLANK_INT_MASK;
3578 }
3579 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3580 atomic_read(&rdev->irq.pflip[5])) {
25a857fb
AD		 3581 DRM_DEBUG("si_irq_set: vblank 5\n");
3582 crtc6 |= VBLANK_INT_MASK;
3583 }
3584 if (rdev->irq.hpd[0]) {
3585 DRM_DEBUG("si_irq_set: hpd 1\n");
3586 hpd1 |= DC_HPDx_INT_EN;
3587 }
3588 if (rdev->irq.hpd[1]) {
3589 DRM_DEBUG("si_irq_set: hpd 2\n");
3590 hpd2 |= DC_HPDx_INT_EN;
3591 }
3592 if (rdev->irq.hpd[2]) {
3593 DRM_DEBUG("si_irq_set: hpd 3\n");
3594 hpd3 |= DC_HPDx_INT_EN;
3595 }
3596 if (rdev->irq.hpd[3]) {
3597 DRM_DEBUG("si_irq_set: hpd 4\n");
3598 hpd4 |= DC_HPDx_INT_EN;
3599 }
3600 if (rdev->irq.hpd[4]) {
3601 DRM_DEBUG("si_irq_set: hpd 5\n");
3602 hpd5 |= DC_HPDx_INT_EN;
3603 }
3604 if (rdev->irq.hpd[5]) {
3605 DRM_DEBUG("si_irq_set: hpd 6\n");
3606 hpd6 |= DC_HPDx_INT_EN;
3607 }
25a857fb
AD		 3608
3609 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3610 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3611 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3612
8c5fd7ef
AD		 3613 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3614 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3615
25a857fb
AD		 3616 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3617
3618 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3619 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3620 if (rdev->num_crtc >= 4) {
3621 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3622 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3623 }
3624 if (rdev->num_crtc >= 6) {
3625 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3626 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3627 }
3628
3629 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3630 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3631 if (rdev->num_crtc >= 4) {
3632 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3633 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3634 }
3635 if (rdev->num_crtc >= 6) {
3636 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3637 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3638 }
3639
3640 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3641 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3642 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3643 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3644 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3645 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3646
3647 return 0;
3648}
3649
3650static inline void si_irq_ack(struct radeon_device *rdev)
3651{
3652 u32 tmp;
3653
3654 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3655 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3656 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3657 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3658 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3659 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3660 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3661 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3662 if (rdev->num_crtc >= 4) {
3663 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3664 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3665 }
3666 if (rdev->num_crtc >= 6) {
3667 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3668 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3669 }
3670
3671 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3672 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3673 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3674 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3675 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3676 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3677 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3678 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3679 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3680 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3681 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3682 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3683
3684 if (rdev->num_crtc >= 4) {
3685 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3686 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3687 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3688 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3689 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3690 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3691 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3692 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3693 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3694 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3695 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3696 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3697 }
3698
3699 if (rdev->num_crtc >= 6) {
3700 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3701 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3702 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3703 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3704 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3705 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3706 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3707 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3708 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3709 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3710 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3711 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3712 }
3713
3714 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3715 tmp = RREG32(DC_HPD1_INT_CONTROL);
3716 tmp |= DC_HPDx_INT_ACK;
3717 WREG32(DC_HPD1_INT_CONTROL, tmp);
3718 }
3719 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3720 tmp = RREG32(DC_HPD2_INT_CONTROL);
3721 tmp |= DC_HPDx_INT_ACK;
3722 WREG32(DC_HPD2_INT_CONTROL, tmp);
3723 }
3724 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3725 tmp = RREG32(DC_HPD3_INT_CONTROL);
3726 tmp |= DC_HPDx_INT_ACK;
3727 WREG32(DC_HPD3_INT_CONTROL, tmp);
3728 }
3729 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3730 tmp = RREG32(DC_HPD4_INT_CONTROL);
3731 tmp |= DC_HPDx_INT_ACK;
3732 WREG32(DC_HPD4_INT_CONTROL, tmp);
3733 }
3734 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3735 tmp = RREG32(DC_HPD5_INT_CONTROL);
3736 tmp |= DC_HPDx_INT_ACK;
3737 WREG32(DC_HPD5_INT_CONTROL, tmp);
3738 }
3739 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3740 tmp = RREG32(DC_HPD5_INT_CONTROL);
3741 tmp |= DC_HPDx_INT_ACK;
3742 WREG32(DC_HPD6_INT_CONTROL, tmp);
3743 }
3744}
3745
3746static void si_irq_disable(struct radeon_device *rdev)
3747{
3748 si_disable_interrupts(rdev);
3749 /* Wait and acknowledge irq */
3750 mdelay(1);
3751 si_irq_ack(rdev);
3752 si_disable_interrupt_state(rdev);
3753}
3754
3755static void si_irq_suspend(struct radeon_device *rdev)
3756{
3757 si_irq_disable(rdev);
3758 si_rlc_stop(rdev);
3759}
3760
9b136d51
AD		 3761static void si_irq_fini(struct radeon_device *rdev)
3762{
3763 si_irq_suspend(rdev);
3764 r600_ih_ring_fini(rdev);
3765}
3766
25a857fb
AD		 3767static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3768{
3769 u32 wptr, tmp;
3770
3771 if (rdev->wb.enabled)
3772 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3773 else
3774 wptr = RREG32(IH_RB_WPTR);
3775
3776 if (wptr & RB_OVERFLOW) {
3777 /* When a ring buffer overflow happen start parsing interrupt
3778 * from the last not overwritten vector (wptr + 16). Hopefully
3779 * this should allow us to catchup.
3780 */
3781 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3782 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3783 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3784 tmp = RREG32(IH_RB_CNTL);
3785 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3786 WREG32(IH_RB_CNTL, tmp);
3787 }
3788 return (wptr & rdev->ih.ptr_mask);
3789}
3790
3791/* SI IV Ring
3792 * Each IV ring entry is 128 bits:
3793 * [7:0] - interrupt source id
3794 * [31:8] - reserved
3795 * [59:32] - interrupt source data
3796 * [63:60] - reserved
3797 * [71:64] - RINGID
3798 * [79:72] - VMID
3799 * [127:80] - reserved
3800 */
3801int si_irq_process(struct radeon_device *rdev)
3802{
3803 u32 wptr;
3804 u32 rptr;
3805 u32 src_id, src_data, ring_id;
3806 u32 ring_index;
25a857fb
AD		 3807 bool queue_hotplug = false;
3808
3809 if (!rdev->ih.enabled || rdev->shutdown)
3810 return IRQ_NONE;
3811
3812 wptr = si_get_ih_wptr(rdev);
c20dc369
CK		 3813
3814restart_ih:
3815 /* is somebody else already processing irqs? */
3816 if (atomic_xchg(&rdev->ih.lock, 1))
3817 return IRQ_NONE;
3818
25a857fb
AD		 3819 rptr = rdev->ih.rptr;
3820 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3821
25a857fb
AD		 3822 /* Order reading of wptr vs. reading of IH ring data */
3823 rmb();
3824
3825 /* display interrupts */
3826 si_irq_ack(rdev);
3827
25a857fb
AD		 3828 while (rptr != wptr) {
3829 /* wptr/rptr are in bytes! */
3830 ring_index = rptr / 4;
3831 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3832 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3833 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3834
3835 switch (src_id) {
3836 case 1: /* D1 vblank/vline */
3837 switch (src_data) {
3838 case 0: /* D1 vblank */
3839 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3840 if (rdev->irq.crtc_vblank_int[0]) {
3841 drm_handle_vblank(rdev->ddev, 0);
3842 rdev->pm.vblank_sync = true;
3843 wake_up(&rdev->irq.vblank_queue);
3844 }
736fc37f 3845 if (atomic_read(&rdev->irq.pflip[0]))
25a857fb
AD		 3846 radeon_crtc_handle_flip(rdev, 0);
3847 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3848 DRM_DEBUG("IH: D1 vblank\n");
3849 }
3850 break;
3851 case 1: /* D1 vline */
3852 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3853 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3854 DRM_DEBUG("IH: D1 vline\n");
3855 }
3856 break;
3857 default:
3858 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3859 break;
3860 }
3861 break;
3862 case 2: /* D2 vblank/vline */
3863 switch (src_data) {
3864 case 0: /* D2 vblank */
3865 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3866 if (rdev->irq.crtc_vblank_int[1]) {
3867 drm_handle_vblank(rdev->ddev, 1);
3868 rdev->pm.vblank_sync = true;
3869 wake_up(&rdev->irq.vblank_queue);
3870 }
736fc37f 3871 if (atomic_read(&rdev->irq.pflip[1]))
25a857fb
AD		 3872 radeon_crtc_handle_flip(rdev, 1);
3873 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3874 DRM_DEBUG("IH: D2 vblank\n");
3875 }
3876 break;
3877 case 1: /* D2 vline */
3878 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3879 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3880 DRM_DEBUG("IH: D2 vline\n");
3881 }
3882 break;
3883 default:
3884 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3885 break;
3886 }
3887 break;
3888 case 3: /* D3 vblank/vline */
3889 switch (src_data) {
3890 case 0: /* D3 vblank */
3891 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3892 if (rdev->irq.crtc_vblank_int[2]) {
3893 drm_handle_vblank(rdev->ddev, 2);
3894 rdev->pm.vblank_sync = true;
3895 wake_up(&rdev->irq.vblank_queue);
3896 }
736fc37f 3897 if (atomic_read(&rdev->irq.pflip[2]))
25a857fb
AD		 3898 radeon_crtc_handle_flip(rdev, 2);
3899 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3900 DRM_DEBUG("IH: D3 vblank\n");
3901 }
3902 break;
3903 case 1: /* D3 vline */
3904 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3905 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3906 DRM_DEBUG("IH: D3 vline\n");
3907 }
3908 break;
3909 default:
3910 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3911 break;
3912 }
3913 break;
3914 case 4: /* D4 vblank/vline */
3915 switch (src_data) {
3916 case 0: /* D4 vblank */
3917 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3918 if (rdev->irq.crtc_vblank_int[3]) {
3919 drm_handle_vblank(rdev->ddev, 3);
3920 rdev->pm.vblank_sync = true;
3921 wake_up(&rdev->irq.vblank_queue);
3922 }
736fc37f 3923 if (atomic_read(&rdev->irq.pflip[3]))
25a857fb
AD		 3924 radeon_crtc_handle_flip(rdev, 3);
3925 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3926 DRM_DEBUG("IH: D4 vblank\n");
3927 }
3928 break;
3929 case 1: /* D4 vline */
3930 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3931 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3932 DRM_DEBUG("IH: D4 vline\n");
3933 }
3934 break;
3935 default:
3936 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3937 break;
3938 }
3939 break;
3940 case 5: /* D5 vblank/vline */
3941 switch (src_data) {
3942 case 0: /* D5 vblank */
3943 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3944 if (rdev->irq.crtc_vblank_int[4]) {
3945 drm_handle_vblank(rdev->ddev, 4);
3946 rdev->pm.vblank_sync = true;
3947 wake_up(&rdev->irq.vblank_queue);
3948 }
736fc37f 3949 if (atomic_read(&rdev->irq.pflip[4]))
25a857fb
AD		 3950 radeon_crtc_handle_flip(rdev, 4);
3951 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3952 DRM_DEBUG("IH: D5 vblank\n");
3953 }
3954 break;
3955 case 1: /* D5 vline */
3956 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3957 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3958 DRM_DEBUG("IH: D5 vline\n");
3959 }
3960 break;
3961 default:
3962 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3963 break;
3964 }
3965 break;
3966 case 6: /* D6 vblank/vline */
3967 switch (src_data) {
3968 case 0: /* D6 vblank */
3969 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3970 if (rdev->irq.crtc_vblank_int[5]) {
3971 drm_handle_vblank(rdev->ddev, 5);
3972 rdev->pm.vblank_sync = true;
3973 wake_up(&rdev->irq.vblank_queue);
3974 }
736fc37f 3975 if (atomic_read(&rdev->irq.pflip[5]))
25a857fb
AD		 3976 radeon_crtc_handle_flip(rdev, 5);
3977 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3978 DRM_DEBUG("IH: D6 vblank\n");
3979 }
3980 break;
3981 case 1: /* D6 vline */
3982 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3983 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3984 DRM_DEBUG("IH: D6 vline\n");
3985 }
3986 break;
3987 default:
3988 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3989 break;
3990 }
3991 break;
3992 case 42: /* HPD hotplug */
3993 switch (src_data) {
3994 case 0:
3995 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3996 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3997 queue_hotplug = true;
3998 DRM_DEBUG("IH: HPD1\n");
3999 }
4000 break;
4001 case 1:
4002 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
4003 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
4004 queue_hotplug = true;
4005 DRM_DEBUG("IH: HPD2\n");
4006 }
4007 break;
4008 case 2:
4009 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
4010 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
4011 queue_hotplug = true;
4012 DRM_DEBUG("IH: HPD3\n");
4013 }
4014 break;
4015 case 3:
4016 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
4017 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
4018 queue_hotplug = true;
4019 DRM_DEBUG("IH: HPD4\n");
4020 }
4021 break;
4022 case 4:
4023 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
4024 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
4025 queue_hotplug = true;
4026 DRM_DEBUG("IH: HPD5\n");
4027 }
4028 break;
4029 case 5:
4030 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4031 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
4032 queue_hotplug = true;
4033 DRM_DEBUG("IH: HPD6\n");
4034 }
4035 break;
4036 default:
4037 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4038 break;
4039 }
4040 break;
ae133a11
CK		 4041 case 146:
4042 case 147:
4043 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4044 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4045 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4046 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4047 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4048 /* reset addr and status */
4049 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4050 break;
25a857fb
AD		 4051 case 176: /* RINGID0 CP_INT */
4052 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4053 break;
4054 case 177: /* RINGID1 CP_INT */
4055 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4056 break;
4057 case 178: /* RINGID2 CP_INT */
4058 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4059 break;
4060 case 181: /* CP EOP event */
4061 DRM_DEBUG("IH: CP EOP\n");
4062 switch (ring_id) {
4063 case 0:
4064 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4065 break;
4066 case 1:
4067 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4068 break;
4069 case 2:
4070 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4071 break;
4072 }
4073 break;
8c5fd7ef
AD		 4074 case 224: /* DMA trap event */
4075 DRM_DEBUG("IH: DMA trap\n");
4076 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4077 break;
25a857fb
AD		 4078 case 233: /* GUI IDLE */
4079 DRM_DEBUG("IH: GUI idle\n");
25a857fb 4080 break;
8c5fd7ef
AD		 4081 case 244: /* DMA trap event */
4082 DRM_DEBUG("IH: DMA1 trap\n");
4083 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4084 break;
25a857fb
AD		 4085 default:
4086 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4087 break;
4088 }
4089
4090 /* wptr/rptr are in bytes! */
4091 rptr += 16;
4092 rptr &= rdev->ih.ptr_mask;
4093 }
25a857fb
AD		 4094 if (queue_hotplug)
4095 schedule_work(&rdev->hotplug_work);
4096 rdev->ih.rptr = rptr;
4097 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4098 atomic_set(&rdev->ih.lock, 0);
4099
4100 /* make sure wptr hasn't changed while processing */
4101 wptr = si_get_ih_wptr(rdev);
4102 if (wptr != rptr)
4103 goto restart_ih;
4104
25a857fb
AD		 4105 return IRQ_HANDLED;
4106}
4107
8c5fd7ef
AD		 4108/**
4109 * si_copy_dma - copy pages using the DMA engine
4110 *
4111 * @rdev: radeon_device pointer
4112 * @src_offset: src GPU address
4113 * @dst_offset: dst GPU address
4114 * @num_gpu_pages: number of GPU pages to xfer
4115 * @fence: radeon fence object
4116 *
4117 * Copy GPU paging using the DMA engine (SI).
4118 * Used by the radeon ttm implementation to move pages if
4119 * registered as the asic copy callback.
4120 */
4121int si_copy_dma(struct radeon_device *rdev,
4122 uint64_t src_offset, uint64_t dst_offset,
4123 unsigned num_gpu_pages,
4124 struct radeon_fence **fence)
4125{
4126 struct radeon_semaphore *sem = NULL;
4127 int ring_index = rdev->asic->copy.dma_ring_index;
4128 struct radeon_ring *ring = &rdev->ring[ring_index];
4129 u32 size_in_bytes, cur_size_in_bytes;
4130 int i, num_loops;
4131 int r = 0;
4132
4133 r = radeon_semaphore_create(rdev, &sem);
4134 if (r) {
4135 DRM_ERROR("radeon: moving bo (%d).\n", r);
4136 return r;
4137 }
4138
4139 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4140 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4141 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4142 if (r) {
4143 DRM_ERROR("radeon: moving bo (%d).\n", r);
4144 radeon_semaphore_free(rdev, &sem, NULL);
4145 return r;
4146 }
4147
4148 if (radeon_fence_need_sync(*fence, ring->idx)) {
4149 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4150 ring->idx);
4151 radeon_fence_note_sync(*fence, ring->idx);
4152 } else {
4153 radeon_semaphore_free(rdev, &sem, NULL);
4154 }
4155
4156 for (i = 0; i < num_loops; i++) {
4157 cur_size_in_bytes = size_in_bytes;
4158 if (cur_size_in_bytes > 0xFFFFF)
4159 cur_size_in_bytes = 0xFFFFF;
4160 size_in_bytes -= cur_size_in_bytes;
4161 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4162 radeon_ring_write(ring, dst_offset & 0xffffffff);
4163 radeon_ring_write(ring, src_offset & 0xffffffff);
4164 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4165 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4166 src_offset += cur_size_in_bytes;
4167 dst_offset += cur_size_in_bytes;
4168 }
4169
4170 r = radeon_fence_emit(rdev, fence, ring->idx);
4171 if (r) {
4172 radeon_ring_unlock_undo(rdev, ring);
4173 return r;
4174 }
4175
4176 radeon_ring_unlock_commit(rdev, ring);
4177 radeon_semaphore_free(rdev, &sem, *fence);
4178
4179 return r;
4180}
4181
9b136d51
AD		 4182/*
4183 * startup/shutdown callbacks
4184 */
4185static int si_startup(struct radeon_device *rdev)
4186{
4187 struct radeon_ring *ring;
4188 int r;
4189
4190 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4191 !rdev->rlc_fw || !rdev->mc_fw) {
4192 r = si_init_microcode(rdev);
4193 if (r) {
4194 DRM_ERROR("Failed to load firmware!\n");
4195 return r;
4196 }
4197 }
4198
4199 r = si_mc_load_microcode(rdev);
4200 if (r) {
4201 DRM_ERROR("Failed to load MC firmware!\n");
4202 return r;
4203 }
4204
4205 r = r600_vram_scratch_init(rdev);
4206 if (r)
4207 return r;
4208
4209 si_mc_program(rdev);
4210 r = si_pcie_gart_enable(rdev);
4211 if (r)
4212 return r;
4213 si_gpu_init(rdev);
4214
4215#if 0
4216 r = evergreen_blit_init(rdev);
4217 if (r) {
4218 r600_blit_fini(rdev);
4219 rdev->asic->copy = NULL;
4220 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4221 }
4222#endif
4223 /* allocate rlc buffers */
4224 r = si_rlc_init(rdev);
4225 if (r) {
4226 DRM_ERROR("Failed to init rlc BOs!\n");
4227 return r;
4228 }
4229
4230 /* allocate wb buffer */
4231 r = radeon_wb_init(rdev);
4232 if (r)
4233 return r;
4234
4235 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4236 if (r) {
4237 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4238 return r;
4239 }
4240
4241 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4242 if (r) {
4243 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4244 return r;
4245 }
4246
4247 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4248 if (r) {
4249 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4250 return r;
4251 }
4252
8c5fd7ef
AD		 4253 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4254 if (r) {
4255 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4256 return r;
4257 }
4258
4259 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4260 if (r) {
4261 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4262 return r;
4263 }
4264
9b136d51
AD		 4265 /* Enable IRQ */
4266 r = si_irq_init(rdev);
4267 if (r) {
4268 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4269 radeon_irq_kms_fini(rdev);
4270 return r;
4271 }
4272 si_irq_set(rdev);
4273
4274 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4275 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4276 CP_RB0_RPTR, CP_RB0_WPTR,
4277 0, 0xfffff, RADEON_CP_PACKET2);
4278 if (r)
4279 return r;
4280
4281 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4282 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4283 CP_RB1_RPTR, CP_RB1_WPTR,
4284 0, 0xfffff, RADEON_CP_PACKET2);
4285 if (r)
4286 return r;
4287
4288 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4289 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4290 CP_RB2_RPTR, CP_RB2_WPTR,
4291 0, 0xfffff, RADEON_CP_PACKET2);
4292 if (r)
4293 return r;
4294
8c5fd7ef
AD		 4295 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4296 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4297 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4298 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4299 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4300 if (r)
4301 return r;
4302
4303 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4304 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4305 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4306 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4307 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4308 if (r)
4309 return r;
4310
9b136d51
AD		 4311 r = si_cp_load_microcode(rdev);
4312 if (r)
4313 return r;
4314 r = si_cp_resume(rdev);
4315 if (r)
4316 return r;
4317
8c5fd7ef
AD		 4318 r = cayman_dma_resume(rdev);
4319 if (r)
4320 return r;
4321
2898c348
CK		 4322 r = radeon_ib_pool_init(rdev);
4323 if (r) {
4324 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
9b136d51 4325 return r;
2898c348 4326 }
9b136d51 4327
c6105f24
CK		 4328 r = radeon_vm_manager_init(rdev);
4329 if (r) {
4330 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
9b136d51 4331 return r;
c6105f24 4332 }
9b136d51
AD		 4333
4334 return 0;
4335}
4336
4337int si_resume(struct radeon_device *rdev)
4338{
4339 int r;
4340
4341 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4342 * posting will perform necessary task to bring back GPU into good
4343 * shape.
4344 */
4345 /* post card */
4346 atom_asic_init(rdev->mode_info.atom_context);
4347
4348 rdev->accel_working = true;
4349 r = si_startup(rdev);
4350 if (r) {
4351 DRM_ERROR("si startup failed on resume\n");
4352 rdev->accel_working = false;
4353 return r;
4354 }
4355
4356 return r;
4357
4358}
4359
4360int si_suspend(struct radeon_device *rdev)
4361{
9b136d51 4362 si_cp_enable(rdev, false);
8c5fd7ef 4363 cayman_dma_stop(rdev);
9b136d51
AD		 4364 si_irq_suspend(rdev);
4365 radeon_wb_disable(rdev);
4366 si_pcie_gart_disable(rdev);
4367 return 0;
4368}
4369
4370/* Plan is to move initialization in that function and use
4371 * helper function so that radeon_device_init pretty much
4372 * do nothing more than calling asic specific function. This
4373 * should also allow to remove a bunch of callback function
4374 * like vram_info.
4375 */
4376int si_init(struct radeon_device *rdev)
4377{
4378 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4379 int r;
4380
9b136d51
AD		 4381 /* Read BIOS */
4382 if (!radeon_get_bios(rdev)) {
4383 if (ASIC_IS_AVIVO(rdev))
4384 return -EINVAL;
4385 }
4386 /* Must be an ATOMBIOS */
4387 if (!rdev->is_atom_bios) {
4388 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4389 return -EINVAL;
4390 }
4391 r = radeon_atombios_init(rdev);
4392 if (r)
4393 return r;
4394
4395 /* Post card if necessary */
4396 if (!radeon_card_posted(rdev)) {
4397 if (!rdev->bios) {
4398 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4399 return -EINVAL;
4400 }
4401 DRM_INFO("GPU not posted. posting now...\n");
4402 atom_asic_init(rdev->mode_info.atom_context);
4403 }
4404 /* Initialize scratch registers */
4405 si_scratch_init(rdev);
4406 /* Initialize surface registers */
4407 radeon_surface_init(rdev);
4408 /* Initialize clocks */
4409 radeon_get_clock_info(rdev->ddev);
4410
4411 /* Fence driver */
4412 r = radeon_fence_driver_init(rdev);
4413 if (r)
4414 return r;
4415
4416 /* initialize memory controller */
4417 r = si_mc_init(rdev);
4418 if (r)
4419 return r;
4420 /* Memory manager */
4421 r = radeon_bo_init(rdev);
4422 if (r)
4423 return r;
4424
4425 r = radeon_irq_kms_init(rdev);
4426 if (r)
4427 return r;
4428
4429 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4430 ring->ring_obj = NULL;
4431 r600_ring_init(rdev, ring, 1024 * 1024);
4432
4433 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4434 ring->ring_obj = NULL;
4435 r600_ring_init(rdev, ring, 1024 * 1024);
4436
4437 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4438 ring->ring_obj = NULL;
4439 r600_ring_init(rdev, ring, 1024 * 1024);
4440
8c5fd7ef
AD		 4441 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4442 ring->ring_obj = NULL;
4443 r600_ring_init(rdev, ring, 64 * 1024);
4444
4445 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4446 ring->ring_obj = NULL;
4447 r600_ring_init(rdev, ring, 64 * 1024);
4448
9b136d51
AD		 4449 rdev->ih.ring_obj = NULL;
4450 r600_ih_ring_init(rdev, 64 * 1024);
4451
4452 r = r600_pcie_gart_init(rdev);
4453 if (r)
4454 return r;
4455
9b136d51 4456 rdev->accel_working = true;
9b136d51
AD		 4457 r = si_startup(rdev);
4458 if (r) {
4459 dev_err(rdev->dev, "disabling GPU acceleration\n");
4460 si_cp_fini(rdev);
8c5fd7ef 4461 cayman_dma_fini(rdev);
9b136d51
AD		 4462 si_irq_fini(rdev);
4463 si_rlc_fini(rdev);
4464 radeon_wb_fini(rdev);
2898c348 4465 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4466 radeon_vm_manager_fini(rdev);
4467 radeon_irq_kms_fini(rdev);
4468 si_pcie_gart_fini(rdev);
4469 rdev->accel_working = false;
4470 }
4471
4472 /* Don't start up if the MC ucode is missing.
4473 * The default clocks and voltages before the MC ucode
4474 * is loaded are not suffient for advanced operations.
4475 */
4476 if (!rdev->mc_fw) {
4477 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4478 return -EINVAL;
4479 }
4480
4481 return 0;
4482}
4483
4484void si_fini(struct radeon_device *rdev)
4485{
4486#if 0
4487 r600_blit_fini(rdev);
4488#endif
4489 si_cp_fini(rdev);
8c5fd7ef 4490 cayman_dma_fini(rdev);
9b136d51
AD		 4491 si_irq_fini(rdev);
4492 si_rlc_fini(rdev);
4493 radeon_wb_fini(rdev);
4494 radeon_vm_manager_fini(rdev);
2898c348 4495 radeon_ib_pool_fini(rdev);
9b136d51
AD		 4496 radeon_irq_kms_fini(rdev);
4497 si_pcie_gart_fini(rdev);
4498 r600_vram_scratch_fini(rdev);
4499 radeon_gem_fini(rdev);
9b136d51
AD		 4500 radeon_fence_driver_fini(rdev);
4501 radeon_bo_fini(rdev);
4502 radeon_atombios_fini(rdev);
4503 kfree(rdev->bios);
4504 rdev->bios = NULL;
4505}
4506
6759a0a7
MO		 4507/**
4508 * si_get_gpu_clock - return GPU clock counter snapshot
4509 *
4510 * @rdev: radeon_device pointer
4511 *
4512 * Fetches a GPU clock counter snapshot (SI).
4513 * Returns the 64 bit clock counter snapshot.
4514 */
4515uint64_t si_get_gpu_clock(struct radeon_device *rdev)
4516{
4517 uint64_t clock;
4518
4519 mutex_lock(&rdev->gpu_clock_mutex);
4520 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4521 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4522 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4523 mutex_unlock(&rdev->gpu_clock_mutex);
4524 return clock;
4525}
Linux 6.x block layer and io_uring tree(s)