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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
29 | #include <drm/drmP.h> | |
30 | #include "radeon_reg.h" | |
31 | #include "radeon.h" | |
32 | ||
33 | /* rs400,rs480 depends on : */ | |
34 | void r100_hdp_reset(struct radeon_device *rdev); | |
35 | void r100_mc_disable_clients(struct radeon_device *rdev); | |
36 | int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
37 | void r420_pipes_init(struct radeon_device *rdev); | |
38 | ||
39 | /* This files gather functions specifics to : | |
40 | * rs400,rs480 | |
41 | * | |
42 | * Some of these functions might be used by newer ASICs. | |
43 | */ | |
44 | void rs400_gpu_init(struct radeon_device *rdev); | |
45 | int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); | |
46 | ||
47 | ||
48 | /* | |
49 | * GART functions. | |
50 | */ | |
51 | void rs400_gart_adjust_size(struct radeon_device *rdev) | |
52 | { | |
53 | /* Check gart size */ | |
54 | switch (rdev->mc.gtt_size/(1024*1024)) { | |
55 | case 32: | |
56 | case 64: | |
57 | case 128: | |
58 | case 256: | |
59 | case 512: | |
60 | case 1024: | |
61 | case 2048: | |
62 | break; | |
63 | default: | |
64 | DRM_ERROR("Unable to use IGP GART size %uM\n", | |
65 | rdev->mc.gtt_size >> 20); | |
66 | DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); | |
67 | DRM_ERROR("Forcing to 32M GART size\n"); | |
68 | rdev->mc.gtt_size = 32 * 1024 * 1024; | |
69 | return; | |
70 | } | |
71 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
72 | /* FIXME: RS400 & RS480 seems to have issue with GART size | |
73 | * if 4G of system memory (needs more testing) */ | |
74 | rdev->mc.gtt_size = 32 * 1024 * 1024; | |
75 | DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); | |
76 | } | |
77 | } | |
78 | ||
79 | void rs400_gart_tlb_flush(struct radeon_device *rdev) | |
80 | { | |
81 | uint32_t tmp; | |
82 | unsigned int timeout = rdev->usec_timeout; | |
83 | ||
84 | WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); | |
85 | do { | |
86 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); | |
87 | if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) | |
88 | break; | |
89 | DRM_UDELAY(1); | |
90 | timeout--; | |
91 | } while (timeout > 0); | |
92 | WREG32_MC(RS480_GART_CACHE_CNTRL, 0); | |
93 | } | |
94 | ||
95 | int rs400_gart_enable(struct radeon_device *rdev) | |
96 | { | |
97 | uint32_t size_reg; | |
98 | uint32_t tmp; | |
99 | int r; | |
100 | ||
101 | /* Initialize common gart structure */ | |
102 | r = radeon_gart_init(rdev); | |
103 | if (r) { | |
104 | return r; | |
105 | } | |
106 | if (rs400_debugfs_pcie_gart_info_init(rdev)) { | |
107 | DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); | |
108 | } | |
109 | ||
110 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); | |
111 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; | |
112 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); | |
113 | /* Check gart size */ | |
114 | switch(rdev->mc.gtt_size / (1024 * 1024)) { | |
115 | case 32: | |
116 | size_reg = RS480_VA_SIZE_32MB; | |
117 | break; | |
118 | case 64: | |
119 | size_reg = RS480_VA_SIZE_64MB; | |
120 | break; | |
121 | case 128: | |
122 | size_reg = RS480_VA_SIZE_128MB; | |
123 | break; | |
124 | case 256: | |
125 | size_reg = RS480_VA_SIZE_256MB; | |
126 | break; | |
127 | case 512: | |
128 | size_reg = RS480_VA_SIZE_512MB; | |
129 | break; | |
130 | case 1024: | |
131 | size_reg = RS480_VA_SIZE_1GB; | |
132 | break; | |
133 | case 2048: | |
134 | size_reg = RS480_VA_SIZE_2GB; | |
135 | break; | |
136 | default: | |
137 | return -EINVAL; | |
138 | } | |
139 | if (rdev->gart.table.ram.ptr == NULL) { | |
140 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; | |
141 | r = radeon_gart_table_ram_alloc(rdev); | |
142 | if (r) { | |
143 | return r; | |
144 | } | |
145 | } | |
146 | /* It should be fine to program it to max value */ | |
147 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { | |
148 | WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); | |
149 | WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); | |
150 | } else { | |
151 | WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); | |
152 | WREG32(RS480_AGP_BASE_2, 0); | |
153 | } | |
154 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; | |
155 | tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16); | |
156 | tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16); | |
157 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { | |
158 | WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); | |
159 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; | |
160 | WREG32(RADEON_BUS_CNTL, tmp); | |
161 | } else { | |
162 | WREG32(RADEON_MC_AGP_LOCATION, tmp); | |
163 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
164 | WREG32(RADEON_BUS_CNTL, tmp); | |
165 | } | |
166 | /* Table should be in 32bits address space so ignore bits above. */ | |
ed10f95d DA |
167 | tmp = (u32)rdev->gart.table_addr & 0xfffff000; |
168 | tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; | |
169 | ||
771fe6b9 JG |
170 | WREG32_MC(RS480_GART_BASE, tmp); |
171 | /* TODO: more tweaking here */ | |
172 | WREG32_MC(RS480_GART_FEATURE_ID, | |
173 | (RS480_TLB_ENABLE | | |
174 | RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); | |
175 | /* Disable snooping */ | |
176 | WREG32_MC(RS480_AGP_MODE_CNTL, | |
177 | (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); | |
178 | /* Disable AGP mode */ | |
179 | /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, | |
180 | * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ | |
181 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { | |
182 | WREG32_MC(RS480_MC_MISC_CNTL, | |
183 | (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); | |
184 | } else { | |
185 | WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); | |
186 | } | |
187 | /* Enable gart */ | |
188 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); | |
189 | rs400_gart_tlb_flush(rdev); | |
190 | rdev->gart.ready = true; | |
191 | return 0; | |
192 | } | |
193 | ||
194 | void rs400_gart_disable(struct radeon_device *rdev) | |
195 | { | |
196 | uint32_t tmp; | |
197 | ||
198 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); | |
199 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; | |
200 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); | |
201 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); | |
202 | } | |
203 | ||
204 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
205 | { | |
ed10f95d DA |
206 | uint32_t entry; |
207 | ||
771fe6b9 JG |
208 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
209 | return -EINVAL; | |
210 | } | |
ed10f95d DA |
211 | |
212 | entry = (lower_32_bits(addr) & PAGE_MASK) | | |
213 | ((upper_32_bits(addr) & 0xff) << 4) | | |
214 | 0xc; | |
215 | entry = cpu_to_le32(entry); | |
216 | rdev->gart.table.ram.ptr[i] = entry; | |
771fe6b9 JG |
217 | return 0; |
218 | } | |
219 | ||
220 | ||
221 | /* | |
222 | * MC functions. | |
223 | */ | |
224 | int rs400_mc_init(struct radeon_device *rdev) | |
225 | { | |
226 | uint32_t tmp; | |
227 | int r; | |
228 | ||
229 | if (r100_debugfs_rbbm_init(rdev)) { | |
230 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
231 | } | |
232 | ||
233 | rs400_gpu_init(rdev); | |
234 | rs400_gart_disable(rdev); | |
235 | rdev->mc.gtt_location = rdev->mc.vram_size; | |
236 | rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); | |
237 | rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); | |
771fe6b9 JG |
238 | r = radeon_mc_setup(rdev); |
239 | if (r) { | |
240 | return r; | |
241 | } | |
242 | ||
243 | r100_mc_disable_clients(rdev); | |
244 | if (r300_mc_wait_for_idle(rdev)) { | |
245 | printk(KERN_WARNING "Failed to wait MC idle while " | |
246 | "programming pipes. Bad things might happen.\n"); | |
247 | } | |
248 | ||
249 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | |
250 | tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); | |
251 | tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); | |
252 | WREG32(RADEON_MC_FB_LOCATION, tmp); | |
253 | tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS; | |
254 | WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); | |
255 | (void)RREG32(RADEON_HOST_PATH_CNTL); | |
256 | WREG32(RADEON_HOST_PATH_CNTL, tmp); | |
257 | (void)RREG32(RADEON_HOST_PATH_CNTL); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | void rs400_mc_fini(struct radeon_device *rdev) | |
262 | { | |
263 | rs400_gart_disable(rdev); | |
264 | radeon_gart_table_ram_free(rdev); | |
265 | radeon_gart_fini(rdev); | |
266 | } | |
267 | ||
268 | ||
269 | /* | |
270 | * Global GPU functions | |
271 | */ | |
272 | void rs400_errata(struct radeon_device *rdev) | |
273 | { | |
274 | rdev->pll_errata = 0; | |
275 | } | |
276 | ||
277 | void rs400_gpu_init(struct radeon_device *rdev) | |
278 | { | |
279 | /* FIXME: HDP same place on rs400 ? */ | |
280 | r100_hdp_reset(rdev); | |
281 | /* FIXME: is this correct ? */ | |
282 | r420_pipes_init(rdev); | |
283 | if (r300_mc_wait_for_idle(rdev)) { | |
284 | printk(KERN_WARNING "Failed to wait MC idle while " | |
285 | "programming pipes. Bad things might happen.\n"); | |
286 | } | |
287 | } | |
288 | ||
289 | ||
290 | /* | |
291 | * VRAM info. | |
292 | */ | |
293 | void rs400_vram_info(struct radeon_device *rdev) | |
294 | { | |
295 | uint32_t tom; | |
296 | ||
297 | rs400_gart_adjust_size(rdev); | |
298 | /* DDR for all card after R300 & IGP */ | |
299 | rdev->mc.vram_is_ddr = true; | |
300 | rdev->mc.vram_width = 128; | |
301 | ||
302 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | |
303 | tom = RREG32(RADEON_NB_TOM); | |
304 | rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); | |
305 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | |
306 | ||
3e43d821 DA |
307 | /* RS480 IGPs don't seem to translate to main RAM, they |
308 | * just reserve and scan out of it. So setting VRAM location | |
309 | * to say 0, will actually trash the OS. */ | |
310 | rdev->mc.vram_location = (tom & 0xffff) << 16; | |
771fe6b9 JG |
311 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
312 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
313 | } | |
314 | ||
315 | ||
316 | /* | |
317 | * Indirect registers accessor | |
318 | */ | |
319 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) | |
320 | { | |
321 | uint32_t r; | |
322 | ||
323 | WREG32(RS480_NB_MC_INDEX, reg & 0xff); | |
324 | r = RREG32(RS480_NB_MC_DATA); | |
325 | WREG32(RS480_NB_MC_INDEX, 0xff); | |
326 | return r; | |
327 | } | |
328 | ||
329 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
330 | { | |
331 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); | |
332 | WREG32(RS480_NB_MC_DATA, (v)); | |
333 | WREG32(RS480_NB_MC_INDEX, 0xff); | |
334 | } | |
335 | ||
336 | ||
337 | /* | |
338 | * Debugfs info | |
339 | */ | |
340 | #if defined(CONFIG_DEBUG_FS) | |
341 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) | |
342 | { | |
343 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
344 | struct drm_device *dev = node->minor->dev; | |
345 | struct radeon_device *rdev = dev->dev_private; | |
346 | uint32_t tmp; | |
347 | ||
348 | tmp = RREG32(RADEON_HOST_PATH_CNTL); | |
349 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); | |
350 | tmp = RREG32(RADEON_BUS_CNTL); | |
351 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); | |
352 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); | |
353 | seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); | |
354 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { | |
355 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); | |
356 | seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); | |
357 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); | |
358 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); | |
359 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); | |
360 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); | |
361 | tmp = RREG32_MC(0x100); | |
362 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); | |
363 | tmp = RREG32(0x134); | |
364 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); | |
365 | } else { | |
366 | tmp = RREG32(RADEON_AGP_BASE); | |
367 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); | |
368 | tmp = RREG32(RS480_AGP_BASE_2); | |
369 | seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); | |
370 | tmp = RREG32(RADEON_MC_AGP_LOCATION); | |
371 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); | |
372 | } | |
373 | tmp = RREG32_MC(RS480_GART_BASE); | |
374 | seq_printf(m, "GART_BASE 0x%08x\n", tmp); | |
375 | tmp = RREG32_MC(RS480_GART_FEATURE_ID); | |
376 | seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); | |
377 | tmp = RREG32_MC(RS480_AGP_MODE_CNTL); | |
378 | seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); | |
379 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); | |
380 | seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); | |
381 | tmp = RREG32_MC(0x5F); | |
382 | seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); | |
383 | tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); | |
384 | seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); | |
385 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); | |
386 | seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); | |
387 | tmp = RREG32_MC(0x3B); | |
388 | seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); | |
389 | tmp = RREG32_MC(0x3C); | |
390 | seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); | |
391 | tmp = RREG32_MC(0x30); | |
392 | seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); | |
393 | tmp = RREG32_MC(0x31); | |
394 | seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); | |
395 | tmp = RREG32_MC(0x32); | |
396 | seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); | |
397 | tmp = RREG32_MC(0x33); | |
398 | seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); | |
399 | tmp = RREG32_MC(0x34); | |
400 | seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); | |
401 | tmp = RREG32_MC(0x35); | |
402 | seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); | |
403 | tmp = RREG32_MC(0x36); | |
404 | seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); | |
405 | tmp = RREG32_MC(0x37); | |
406 | seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static struct drm_info_list rs400_gart_info_list[] = { | |
411 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, | |
412 | }; | |
413 | #endif | |
414 | ||
415 | int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) | |
416 | { | |
417 | #if defined(CONFIG_DEBUG_FS) | |
418 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); | |
419 | #else | |
420 | return 0; | |
421 | #endif | |
422 | } |