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drm/radeon/kms: fix panel scaling adjusted mode setup
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
771fe6b9
JG		 37#include <linux/i2c.h>
38#include <linux/i2c-id.h>
39#include <linux/i2c-algo-bit.h>
c93bb85b
JG		 40#include "radeon_fixed.h"
41
42struct radeon_device;
771fe6b9
JG		 43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
771fe6b9
JG		 49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
d79766fa 65 TV_STD_PAL_N,
771fe6b9
JG		 66};
67
9b9fe724
AD		 68/* radeon gpio-based i2c
69 * 1. "mask" reg and bits
70 * grabs the gpio pins for software use
71 * 0=not held 1=held
72 * 2. "a" reg and bits
73 * output pin value
74 * 0=low 1=high
75 * 3. "en" reg and bits
76 * sets the pin direction
77 * 0=input 1=output
78 * 4. "y" reg and bits
79 * input pin value
80 * 0=low 1=high
81 */
771fe6b9
JG		 82struct radeon_i2c_bus_rec {
83 bool valid;
6a93cb25
AD		 84 /* id used by atom */
85 uint8_t i2c_id;
bcc1c2a1
AD		 86 /* id used by atom */
87 uint8_t hpd_id;
6a93cb25
AD		 88 /* can be used with hw i2c engine */
89 bool hw_capable;
90 /* uses multi-media i2c engine */
91 bool mm_i2c;
92 /* regs and bits */
771fe6b9
JG		 93 uint32_t mask_clk_reg;
94 uint32_t mask_data_reg;
95 uint32_t a_clk_reg;
96 uint32_t a_data_reg;
9b9fe724
AD		 97 uint32_t en_clk_reg;
98 uint32_t en_data_reg;
99 uint32_t y_clk_reg;
100 uint32_t y_data_reg;
771fe6b9
JG		 101 uint32_t mask_clk_mask;
102 uint32_t mask_data_mask;
771fe6b9
JG		 103 uint32_t a_clk_mask;
104 uint32_t a_data_mask;
9b9fe724
AD		 105 uint32_t en_clk_mask;
106 uint32_t en_data_mask;
107 uint32_t y_clk_mask;
108 uint32_t y_data_mask;
771fe6b9
JG		 109};
110
111struct radeon_tmds_pll {
112 uint32_t freq;
113 uint32_t value;
114};
115
116#define RADEON_MAX_BIOS_CONNECTOR 16
117
7c27f87d 118/* pll flags */
771fe6b9
JG		 119#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
120#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
121#define RADEON_PLL_USE_REF_DIV (1 << 2)
122#define RADEON_PLL_LEGACY (1 << 3)
123#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
124#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
125#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
126#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
127#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
128#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
129#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 130#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 131#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 132#define RADEON_PLL_IS_LCD (1 << 13)
771fe6b9 133
7c27f87d
AD		 134/* pll algo */
135enum radeon_pll_algo {
136 PLL_ALGO_LEGACY,
383be5d1 137 PLL_ALGO_NEW
7c27f87d
AD		 138};
139
771fe6b9 140struct radeon_pll {
fc10332b
AD		 141 /* reference frequency */
142 uint32_t reference_freq;
143
144 /* fixed dividers */
145 uint32_t reference_div;
146 uint32_t post_div;
147
148 /* pll in/out limits */
771fe6b9
JG		 149 uint32_t pll_in_min;
150 uint32_t pll_in_max;
151 uint32_t pll_out_min;
152 uint32_t pll_out_max;
86cb2bbf
AD		 153 uint32_t lcd_pll_out_min;
154 uint32_t lcd_pll_out_max;
fc10332b 155 uint32_t best_vco;
771fe6b9 156
fc10332b 157 /* divider limits */
771fe6b9
JG		 158 uint32_t min_ref_div;
159 uint32_t max_ref_div;
160 uint32_t min_post_div;
161 uint32_t max_post_div;
162 uint32_t min_feedback_div;
163 uint32_t max_feedback_div;
164 uint32_t min_frac_feedback_div;
165 uint32_t max_frac_feedback_div;
fc10332b
AD		 166
167 /* flags for the current clock */
168 uint32_t flags;
169
170 /* pll id */
171 uint32_t id;
7c27f87d
AD		 172 /* pll algo */
173 enum radeon_pll_algo algo;
771fe6b9
JG		 174};
175
176struct radeon_i2c_chan {
771fe6b9 177 struct i2c_adapter adapter;
746c1aa4
DA		 178 struct drm_device *dev;
179 union {
ac1aade6 180 struct i2c_algo_bit_data bit;
746c1aa4 181 struct i2c_algo_dp_aux_data dp;
746c1aa4 182 } algo;
771fe6b9
JG		 183 struct radeon_i2c_bus_rec rec;
184};
185
186/* mostly for macs, but really any system without connector tables */
187enum radeon_connector_table {
188 CT_NONE,
189 CT_GENERIC,
190 CT_IBOOK,
191 CT_POWERBOOK_EXTERNAL,
192 CT_POWERBOOK_INTERNAL,
193 CT_POWERBOOK_VGA,
194 CT_MINI_EXTERNAL,
195 CT_MINI_INTERNAL,
196 CT_IMAC_G5_ISIGHT,
197 CT_EMAC,
198};
199
fcec570b
AD		 200enum radeon_dvo_chip {
201 DVO_SIL164,
202 DVO_SIL1178,
203};
204
771fe6b9
JG		 205struct radeon_mode_info {
206 struct atom_context *atom_context;
61c4b24b 207 struct card_info *atom_card_info;
771fe6b9
JG		 208 enum radeon_connector_table connector_table;
209 bool mode_config_initialized;
bcc1c2a1 210 struct radeon_crtc *crtcs[6];
445282db
DA		 211 /* DVI-I properties */
212 struct drm_property *coherent_mode_property;
213 /* DAC enable load detect */
214 struct drm_property *load_detect_property;
215 /* TV standard load detect */
216 struct drm_property *tv_std_property;
217 /* legacy TMDS PLL detect */
218 struct drm_property *tmds_pll_property;
3c537889
AD		 219 /* hardcoded DFP edid from BIOS */
220 struct edid *bios_hardcoded_edid;
c93bb85b
JG		 221};
222
4ce001ab
DA		 223#define MAX_H_CODE_TIMING_LEN 32
224#define MAX_V_CODE_TIMING_LEN 32
225
226/* need to store these as reading
227 back code tables is excessive */
228struct radeon_tv_regs {
229 uint32_t tv_uv_adr;
230 uint32_t timing_cntl;
231 uint32_t hrestart;
232 uint32_t vrestart;
233 uint32_t frestart;
234 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
235 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
236};
237
771fe6b9
JG		 238struct radeon_crtc {
239 struct drm_crtc base;
240 int crtc_id;
241 u16 lut_r[256], lut_g[256], lut_b[256];
242 bool enabled;
243 bool can_tile;
244 uint32_t crtc_offset;
771fe6b9
JG		 245 struct drm_gem_object *cursor_bo;
246 uint64_t cursor_addr;
247 int cursor_width;
248 int cursor_height;
4162338a 249 uint32_t legacy_display_base_addr;
c836e862 250 uint32_t legacy_cursor_offset;
c93bb85b 251 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 252 fixed20_12 vsc;
253 fixed20_12 hsc;
de2103e4 254 struct drm_display_mode native_mode;
bcc1c2a1 255 int pll_id;
771fe6b9
JG		 256};
257
258struct radeon_encoder_primary_dac {
259 /* legacy primary dac */
260 uint32_t ps2_pdac_adj;
261};
262
263struct radeon_encoder_lvds {
264 /* legacy lvds */
265 uint16_t panel_vcc_delay;
266 uint8_t panel_pwr_delay;
267 uint8_t panel_digon_delay;
268 uint8_t panel_blon_delay;
269 uint16_t panel_ref_divider;
270 uint8_t panel_post_divider;
271 uint16_t panel_fb_divider;
272 bool use_bios_dividers;
273 uint32_t lvds_gen_cntl;
274 /* panel mode */
de2103e4 275 struct drm_display_mode native_mode;
771fe6b9
JG		 276};
277
278struct radeon_encoder_tv_dac {
279 /* legacy tv dac */
280 uint32_t ps2_tvdac_adj;
281 uint32_t ntsc_tvdac_adj;
282 uint32_t pal_tvdac_adj;
283
4ce001ab
DA		 284 int h_pos;
285 int v_pos;
286 int h_size;
287 int supported_tv_stds;
288 bool tv_on;
771fe6b9 289 enum radeon_tv_std tv_std;
4ce001ab 290 struct radeon_tv_regs tv;
771fe6b9
JG		 291};
292
293struct radeon_encoder_int_tmds {
294 /* legacy int tmds */
295 struct radeon_tmds_pll tmds_pll[4];
296};
297
fcec570b
AD		 298struct radeon_encoder_ext_tmds {
299 /* tmds over dvo */
300 struct radeon_i2c_chan *i2c_bus;
301 uint8_t slave_addr;
302 enum radeon_dvo_chip dvo_chip;
303};
304
ebbe1cb9
AD		 305/* spread spectrum */
306struct radeon_atom_ss {
307 uint16_t percentage;
308 uint8_t type;
309 uint8_t step;
310 uint8_t delay;
311 uint8_t range;
312 uint8_t refdiv;
313};
314
771fe6b9
JG		 315struct radeon_encoder_atom_dig {
316 /* atom dig */
317 bool coherent_mode;
f28cf339 318 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
771fe6b9
JG		 319 /* atom lvds */
320 uint32_t lvds_misc;
321 uint16_t panel_pwr_delay;
7c27f87d 322 enum radeon_pll_algo pll_algo;
ebbe1cb9 323 struct radeon_atom_ss *ss;
771fe6b9 324 /* panel mode */
de2103e4 325 struct drm_display_mode native_mode;
771fe6b9
JG		 326};
327
4ce001ab
DA		 328struct radeon_encoder_atom_dac {
329 enum radeon_tv_std tv_std;
330};
331
771fe6b9
JG		 332struct radeon_encoder {
333 struct drm_encoder base;
334 uint32_t encoder_id;
335 uint32_t devices;
4ce001ab 336 uint32_t active_device;
771fe6b9
JG		 337 uint32_t flags;
338 uint32_t pixel_clock;
339 enum radeon_rmx_type rmx_type;
de2103e4 340 struct drm_display_mode native_mode;
771fe6b9 341 void *enc_priv;
dafc3bd5 342 int hdmi_offset;
808032ee 343 int hdmi_config_offset;
dafc3bd5
CK		 344 int hdmi_audio_workaround;
345 int hdmi_buffer_status;
771fe6b9
JG		 346};
347
348struct radeon_connector_atom_dig {
349 uint32_t igp_lane_info;
350 bool linkb;
4143e919 351 /* displayport */
746c1aa4 352 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 353 u8 dpcd[8];
4143e919 354 u8 dp_sink_type;
5801ead6
AD		 355 int dp_clock;
356 int dp_lane_count;
771fe6b9
JG		 357};
358
eed45b30
AD		 359struct radeon_gpio_rec {
360 bool valid;
361 u8 id;
362 u32 reg;
363 u32 mask;
364};
365
366enum radeon_hpd_id {
367 RADEON_HPD_NONE = 0,
368 RADEON_HPD_1,
369 RADEON_HPD_2,
370 RADEON_HPD_3,
371 RADEON_HPD_4,
372 RADEON_HPD_5,
373 RADEON_HPD_6,
374};
375
376struct radeon_hpd {
377 enum radeon_hpd_id hpd;
378 u8 plugged_state;
379 struct radeon_gpio_rec gpio;
380};
381
771fe6b9
JG		 382struct radeon_connector {
383 struct drm_connector base;
384 uint32_t connector_id;
385 uint32_t devices;
386 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 387 /* some systems have a an hdmi and vga port with a shared ddc line */
388 bool shared_ddc;
4ce001ab
DA		 389 bool use_digital;
390 /* we need to mind the EDID between detect
391 and get modes due to analog/digital/tvencoder */
392 struct edid *edid;
771fe6b9 393 void *con_priv;
445282db 394 bool dac_load_detect;
b75fad06 395 uint16_t connector_object_id;
eed45b30 396 struct radeon_hpd hpd;
771fe6b9
JG		 397};
398
399struct radeon_framebuffer {
400 struct drm_framebuffer base;
401 struct drm_gem_object *obj;
402};
403
d79766fa
AD		 404extern enum radeon_tv_std
405radeon_combios_get_tv_info(struct radeon_device *rdev);
406extern enum radeon_tv_std
407radeon_atombios_get_tv_info(struct radeon_device *rdev);
408
d4877cf2
AD		 409extern void radeon_connector_hotplug(struct drm_connector *connector);
410extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 411extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
412 struct drm_display_mode *mode);
413extern void radeon_dp_set_link_config(struct drm_connector *connector,
414 struct drm_display_mode *mode);
415extern void dp_link_train(struct drm_encoder *encoder,
416 struct drm_connector *connector);
4143e919 417extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 418extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
bcc1c2a1 419extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
5801ead6
AD		 420extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
421 int action, uint8_t lane_num,
422 uint8_t lane_set);
746c1aa4
DA		 423extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
424 uint8_t write_byte, uint8_t *read_byte);
425
426extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 427 struct radeon_i2c_bus_rec *rec,
428 const char *name);
771fe6b9
JG		 429extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
430 struct radeon_i2c_bus_rec *rec,
431 const char *name);
432extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 433extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
434 u8 slave_addr,
435 u8 addr,
436 u8 *val);
437extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
438 u8 slave_addr,
439 u8 addr,
440 u8 val);
771fe6b9
JG		 441extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
442extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
443
444extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
445
446extern void radeon_compute_pll(struct radeon_pll *pll,
447 uint64_t freq,
448 uint32_t *dot_clock_p,
449 uint32_t *fb_div_p,
450 uint32_t *frac_fb_div_p,
451 uint32_t *ref_div_p,
fc10332b 452 uint32_t *post_div_p);
771fe6b9 453
1f3b6a45
DA		 454extern void radeon_setup_encoder_clones(struct drm_device *dev);
455
771fe6b9
JG		 456struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
457struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
458struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
459struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
460struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
461extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 462extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 463extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 464extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 465
466extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
467extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
468 struct drm_framebuffer *old_fb);
469extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
470 struct drm_display_mode *mode,
471 struct drm_display_mode *adjusted_mode,
472 int x, int y,
473 struct drm_framebuffer *old_fb);
474extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
475
476extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
477 struct drm_framebuffer *old_fb);
771fe6b9
JG		 478
479extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
480 struct drm_file *file_priv,
481 uint32_t handle,
482 uint32_t width,
483 uint32_t height);
484extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
485 int x, int y);
486
3c537889
AD		 487extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
488extern struct edid *
489radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 490extern bool radeon_atom_get_clock_info(struct drm_device *dev);
491extern bool radeon_combios_get_clock_info(struct drm_device *dev);
492extern struct radeon_encoder_atom_dig *
493radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 494extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
495 struct radeon_encoder_int_tmds *tmds);
496extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
497 struct radeon_encoder_int_tmds *tmds);
498extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
499 struct radeon_encoder_int_tmds *tmds);
500extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
501 struct radeon_encoder_ext_tmds *tmds);
502extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
503 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 504extern struct radeon_encoder_primary_dac *
505radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
506extern struct radeon_encoder_tv_dac *
507radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 508extern struct radeon_encoder_lvds *
509radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 510extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
511extern struct radeon_encoder_tv_dac *
512radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
513extern struct radeon_encoder_primary_dac *
514radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 515extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
516extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 517extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
518extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
519extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
520extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 521extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
522extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 523extern void
524radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
525extern void
526radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
527extern void
528radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
529extern void
530radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
531extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
532 u16 blue, int regno);
b8c00ac5
DA		 533extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
534 u16 *blue, int regno);
771fe6b9
JG		 535struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
536 struct drm_mode_fb_cmd *mode_cmd,
537 struct drm_gem_object *obj);
538
539int radeonfb_probe(struct drm_device *dev);
540
541int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
542bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
543bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
544void radeon_atombios_init_crtc(struct drm_device *dev,
545 struct radeon_crtc *radeon_crtc);
546void radeon_legacy_init_crtc(struct drm_device *dev,
547 struct radeon_crtc *radeon_crtc);
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JG		 548
549void radeon_get_clock_info(struct drm_device *dev);
550
551extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
552extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
553
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JG		 554void radeon_enc_destroy(struct drm_encoder *encoder);
555void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
556void radeon_combios_asic_init(struct drm_device *dev);
557extern int radeon_static_clocks_init(struct drm_device *dev);
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JG		 558bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
559 struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode);
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AD		 561void radeon_panel_mode_fixup(struct drm_encoder *encoder,
562 struct drm_display_mode *adjusted_mode);
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DA		 563void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
564
565/* legacy tv */
566void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
567 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
568 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
569void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
570 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
571 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
572void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
573 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
574 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
575void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
576 struct drm_display_mode *mode,
577 struct drm_display_mode *adjusted_mode);
771fe6b9 578#endif
Linux 6.x block layer and io_uring tree(s)