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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
b516a9ef 28#include <drm/drm_fb_helper.h>
771fe6b9 29#include <drm/radeon_drm.h>
68adac5e 30#include <drm/drm_fixed.h>
771fe6b9 31#include "radeon.h"
4ce001ab 32#include "atom.h"
771fe6b9 33
6b02af1c
AD		 34static void radeon_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode)
36{
37 struct drm_device *dev = crtc->dev;
38 struct radeon_device *rdev = dev->dev_private;
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40
41 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
43 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
44}
45
c93bb85b 46static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
310a82c8 47 struct drm_display_mode *mode)
c93bb85b
JG		 48{
49 struct drm_device *dev = crtc->dev;
50 struct radeon_device *rdev = dev->dev_private;
51 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
52 int xres = mode->hdisplay;
53 int yres = mode->vdisplay;
54 bool hscale = true, vscale = true;
55 int hsync_wid;
56 int vsync_wid;
57 int hsync_start;
58 int blank_width;
59 u32 scale, inc, crtc_more_cntl;
60 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
61 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
62 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
de2103e4 63 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
c93bb85b
JG		 64
65 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
66 (RADEON_VERT_STRETCH_RESERVED |
67 RADEON_VERT_AUTO_RATIO_INC);
68 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
69 (RADEON_HORZ_FP_LOOP_STRETCH |
70 RADEON_HORZ_AUTO_RATIO_INC);
71
72 crtc_more_cntl = 0;
73 if ((rdev->family == CHIP_RS100) ||
74 (rdev->family == CHIP_RS200)) {
75 /* This is to workaround the asic bug for RMX, some versions
76 of BIOS dosen't have this register initialized correctly. */
77 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
78 }
79
80
81 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
82 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
83
84 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
85 if (!hsync_wid)
86 hsync_wid = 1;
87 hsync_start = mode->crtc_hsync_start - 8;
88
89 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
90 | ((hsync_wid & 0x3f) << 16)
91 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
92 ? RADEON_CRTC_H_SYNC_POL
93 : 0));
94
95 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
96 | ((mode->crtc_vdisplay - 1) << 16));
97
98 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
99 if (!vsync_wid)
100 vsync_wid = 1;
101
102 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
103 | ((vsync_wid & 0x1f) << 16)
104 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
105 ? RADEON_CRTC_V_SYNC_POL
106 : 0));
107
108 fp_horz_vert_active = 0;
109
de2103e4
AD		 110 if (native_mode->hdisplay == 0 ||
111 native_mode->vdisplay == 0) {
c93bb85b
JG		 112 hscale = false;
113 vscale = false;
114 } else {
de2103e4
AD		 115 if (xres > native_mode->hdisplay)
116 xres = native_mode->hdisplay;
117 if (yres > native_mode->vdisplay)
118 yres = native_mode->vdisplay;
c93bb85b 119
de2103e4 120 if (xres == native_mode->hdisplay)
c93bb85b 121 hscale = false;
de2103e4 122 if (yres == native_mode->vdisplay)
c93bb85b
JG		 123 vscale = false;
124 }
125
126 switch (radeon_crtc->rmx_type) {
127 case RMX_FULL:
128 case RMX_ASPECT:
129 if (!hscale)
130 fp_horz_stretch |= ((xres/8-1) << 16);
131 else {
132 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
133 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
de2103e4 134 / native_mode->hdisplay + 1;
c93bb85b
JG		 135 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
136 RADEON_HORZ_STRETCH_BLEND |
137 RADEON_HORZ_STRETCH_ENABLE |
de2103e4 138 ((native_mode->hdisplay/8-1) << 16));
c93bb85b
JG		 139 }
140
141 if (!vscale)
142 fp_vert_stretch |= ((yres-1) << 12);
143 else {
144 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
145 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
de2103e4 146 / native_mode->vdisplay + 1;
c93bb85b
JG		 147 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
148 RADEON_VERT_STRETCH_ENABLE |
149 RADEON_VERT_STRETCH_BLEND |
de2103e4 150 ((native_mode->vdisplay-1) << 12));
c93bb85b
JG		 151 }
152 break;
153 case RMX_CENTER:
154 fp_horz_stretch |= ((xres/8-1) << 16);
155 fp_vert_stretch |= ((yres-1) << 12);
156
157 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
158 RADEON_CRTC_AUTO_VERT_CENTER_EN);
159
160 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
161 if (blank_width > 110)
162 blank_width = 110;
163
164 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
165 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
166
167 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
168 if (!hsync_wid)
169 hsync_wid = 1;
170
171 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
172 | ((hsync_wid & 0x3f) << 16)
173 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
174 ? RADEON_CRTC_H_SYNC_POL
175 : 0));
176
177 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
178 | ((mode->crtc_vdisplay - 1) << 16));
179
180 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
181 if (!vsync_wid)
182 vsync_wid = 1;
183
184 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
185 | ((vsync_wid & 0x1f) << 16)
186 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
187 ? RADEON_CRTC_V_SYNC_POL
188 : 0)));
189
de2103e4
AD		 190 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
191 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
c93bb85b
JG		 192 break;
193 case RMX_OFF:
194 default:
195 fp_horz_stretch |= ((xres/8-1) << 16);
196 fp_vert_stretch |= ((yres-1) << 12);
197 break;
198 }
199
200 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
201 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
202 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
203 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
204 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
205 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
206 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
207 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
208}
209
771fe6b9
JG		 210static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
211{
212 struct radeon_device *rdev = dev->dev_private;
213 int i = 0;
214
215 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
216 the cause yet, but this workaround will mask the problem for now.
217 Other chips usually will pass at the very first test, so the
218 workaround shouldn't have any effect on them. */
219 for (i = 0;
220 (i < 10000 &&
221 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
222 i++);
223}
224
225static void radeon_pll_write_update(struct drm_device *dev)
226{
227 struct radeon_device *rdev = dev->dev_private;
228
229 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
230
231 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
232 RADEON_PPLL_ATOMIC_UPDATE_W,
233 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
234}
235
236static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
237{
238 struct radeon_device *rdev = dev->dev_private;
239 int i = 0;
240
241
242 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
243 the cause yet, but this workaround will mask the problem for now.
244 Other chips usually will pass at the very first test, so the
245 workaround shouldn't have any effect on them. */
246 for (i = 0;
247 (i < 10000 &&
248 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
249 i++);
250}
251
252static void radeon_pll2_write_update(struct drm_device *dev)
253{
254 struct radeon_device *rdev = dev->dev_private;
255
256 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
257
258 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
259 RADEON_P2PLL_ATOMIC_UPDATE_W,
260 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
261}
262
263static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
264 uint16_t fb_div)
265{
266 unsigned int vcoFreq;
267
268 if (!ref_div)
269 return 1;
270
0537398b 271 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
771fe6b9
JG		 272
273 /*
274 * This is horribly crude: the VCO frequency range is divided into
275 * 3 parts, each part having a fixed PLL gain value.
276 */
277 if (vcoFreq >= 30000)
278 /*
279 * [300..max] MHz : 7
280 */
281 return 7;
282 else if (vcoFreq >= 18000)
283 /*
284 * [180..300) MHz : 4
285 */
286 return 4;
287 else
288 /*
289 * [0..180) MHz : 1
290 */
291 return 1;
292}
293
1109ca09 294static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
771fe6b9
JG		 295{
296 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
297 struct drm_device *dev = crtc->dev;
298 struct radeon_device *rdev = dev->dev_private;
f8c4d701 299 uint32_t crtc_ext_cntl = 0;
771fe6b9
JG		 300 uint32_t mask;
301
302 if (radeon_crtc->crtc_id)
8de21525 303 mask = (RADEON_CRTC2_DISP_DIS |
771fe6b9
JG		 304 RADEON_CRTC2_VSYNC_DIS |
305 RADEON_CRTC2_HSYNC_DIS |
306 RADEON_CRTC2_DISP_REQ_EN_B);
307 else
308 mask = (RADEON_CRTC_DISPLAY_DIS |
309 RADEON_CRTC_VSYNC_DIS |
310 RADEON_CRTC_HSYNC_DIS);
311
f8c4d701
EE		 312 /*
313 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
314 * Therefore it is set in the DAC DMPS function.
315 * This is different for GPU's with a single CRTC but a primary and a
316 * TV DAC: here it controls the single CRTC no matter where it is
317 * routed. Therefore we set it here.
318 */
319 if (rdev->flags & RADEON_SINGLE_CRTC)
320 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
321
771fe6b9
JG		 322 switch (mode) {
323 case DRM_MODE_DPMS_ON:
d7311171
AD		 324 radeon_crtc->enabled = true;
325 /* adjust pm to dpms changes BEFORE enabling crtcs */
326 radeon_pm_compute_clocks(rdev);
771fe6b9 327 if (radeon_crtc->crtc_id)
8de21525 328 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
771fe6b9
JG		 329 else {
330 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
331 RADEON_CRTC_DISP_REQ_EN_B));
f8c4d701 332 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
771fe6b9 333 }
777e3cbc 334 drm_vblank_on(dev, radeon_crtc->crtc_id);
7ed220d7 335 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 336 break;
337 case DRM_MODE_DPMS_STANDBY:
338 case DRM_MODE_DPMS_SUSPEND:
339 case DRM_MODE_DPMS_OFF:
777e3cbc 340 drm_vblank_off(dev, radeon_crtc->crtc_id);
771fe6b9 341 if (radeon_crtc->crtc_id)
8de21525 342 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
771fe6b9
JG		 343 else {
344 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
345 RADEON_CRTC_DISP_REQ_EN_B));
f8c4d701 346 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
771fe6b9 347 }
a48b9b4e 348 radeon_crtc->enabled = false;
d7311171
AD		 349 /* adjust pm to dpms changes AFTER disabling crtcs */
350 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 351 break;
352 }
771fe6b9
JG		 353}
354
771fe6b9
JG		 355int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
356 struct drm_framebuffer *old_fb)
4dd19b0d
CB		 357{
358 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
359}
360
361int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
362 struct drm_framebuffer *fb,
21c74a8e 363 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 364{
365 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
366}
367
368int radeon_crtc_do_set_base(struct drm_crtc *crtc,
369 struct drm_framebuffer *fb,
370 int x, int y, int atomic)
771fe6b9
JG		 371{
372 struct drm_device *dev = crtc->dev;
373 struct radeon_device *rdev = dev->dev_private;
374 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
375 struct radeon_framebuffer *radeon_fb;
4dd19b0d 376 struct drm_framebuffer *target_fb;
771fe6b9 377 struct drm_gem_object *obj;
4c788679 378 struct radeon_bo *rbo;
771fe6b9
JG		 379 uint64_t base;
380 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
381 uint32_t crtc_pitch, pitch_pixels;
e024e110 382 uint32_t tiling_flags;
41456df2
DA		 383 int format;
384 uint32_t gen_cntl_reg, gen_cntl_val;
4c788679 385 int r;
771fe6b9 386
d9fdaafb 387 DRM_DEBUG_KMS("\n");
2de3b484 388 /* no fb bound */
f4510a27 389 if (!atomic && !crtc->primary->fb) {
d9fdaafb 390 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 391 return 0;
392 }
771fe6b9 393
4dd19b0d
CB		 394 if (atomic) {
395 radeon_fb = to_radeon_framebuffer(fb);
396 target_fb = fb;
397 }
398 else {
f4510a27
MR		 399 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
400 target_fb = crtc->primary->fb;
4dd19b0d 401 }
771fe6b9 402
4dd19b0d 403 switch (target_fb->bits_per_pixel) {
41456df2
DA		 404 case 8:
405 format = 2;
406 break;
407 case 15: /* 555 */
408 format = 3;
409 break;
410 case 16: /* 565 */
411 format = 4;
412 break;
413 case 24: /* RGB */
414 format = 5;
415 break;
416 case 32: /* xRGB */
417 format = 6;
418 break;
419 default:
420 return false;
421 }
422
4c788679 423 /* Pin framebuffer & get tilling informations */
771fe6b9 424 obj = radeon_fb->obj;
7e4d15d9 425 rbo = gem_to_radeon_bo(obj);
97b6ff6b 426retry:
4c788679
JG		 427 r = radeon_bo_reserve(rbo, false);
428 if (unlikely(r != 0))
429 return r;
0349af70
MD		 430 /* Only 27 bit offset for legacy CRTC */
431 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
432 &base);
4c788679
JG		 433 if (unlikely(r != 0)) {
434 radeon_bo_unreserve(rbo);
97b6ff6b
JG		 435
436 /* On old GPU like RN50 with little vram pining can fails because
437 * current fb is taking all space needed. So instead of unpining
438 * the old buffer after pining the new one, first unpin old one
439 * and then retry pining new one.
440 *
441 * As only master can set mode only master can pin and it is
442 * unlikely the master client will race with itself especialy
443 * on those old gpu with single crtc.
444 *
445 * We don't shutdown the display controller because new buffer
446 * will end up in same spot.
447 */
f4510a27 448 if (!atomic && fb && fb != crtc->primary->fb) {
97b6ff6b
JG		 449 struct radeon_bo *old_rbo;
450 unsigned long nsize, osize;
451
452 old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj);
453 osize = radeon_bo_size(old_rbo);
454 nsize = radeon_bo_size(rbo);
455 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
456 radeon_bo_unpin(old_rbo);
457 radeon_bo_unreserve(old_rbo);
458 fb = NULL;
459 goto retry;
460 }
461 }
771fe6b9
JG		 462 return -EINVAL;
463 }
4c788679
JG		 464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
465 radeon_bo_unreserve(rbo);
466 if (tiling_flags & RADEON_TILING_MICRO)
467 DRM_ERROR("trying to scanout microtiled buffer\n");
468
4162338a
DA		 469 /* if scanout was in GTT this really wouldn't work */
470 /* crtc offset is from display base addr not FB location */
d594e46a 471 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
4162338a
DA		 472
473 base -= radeon_crtc->legacy_display_base_addr;
474
771fe6b9
JG		 475 crtc_offset_cntl = 0;
476
01f2c773 477 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
4dd19b0d
CB		 478 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) +
479 ((target_fb->bits_per_pixel * 8) - 1)) /
480 (target_fb->bits_per_pixel * 8));
771fe6b9
JG		 481 crtc_pitch |= crtc_pitch << 16;
482
c640e8ca 483 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
e024e110 484 if (tiling_flags & RADEON_TILING_MACRO) {
771fe6b9
JG		 485 if (ASIC_IS_R300(rdev))
486 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
487 R300_CRTC_MICRO_TILE_BUFFER_DIS |
488 R300_CRTC_MACRO_TILE_EN);
489 else
490 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
491 } else {
492 if (ASIC_IS_R300(rdev))
493 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
494 R300_CRTC_MICRO_TILE_BUFFER_DIS |
495 R300_CRTC_MACRO_TILE_EN);
496 else
497 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
498 }
499
e024e110 500 if (tiling_flags & RADEON_TILING_MACRO) {
771fe6b9
JG		 501 if (ASIC_IS_R300(rdev)) {
502 crtc_tile_x0_y0 = x | (y << 16);
503 base &= ~0x7ff;
504 } else {
4dd19b0d 505 int byteshift = target_fb->bits_per_pixel >> 4;
e024e110 506 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
771fe6b9
JG		 507 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
508 crtc_offset_cntl |= (y % 16);
509 }
510 } else {
511 int offset = y * pitch_pixels + x;
4dd19b0d 512 switch (target_fb->bits_per_pixel) {
41456df2
DA		 513 case 8:
514 offset *= 1;
515 break;
771fe6b9
JG		 516 case 15:
517 case 16:
518 offset *= 2;
519 break;
520 case 24:
521 offset *= 3;
522 break;
523 case 32:
524 offset *= 4;
525 break;
526 default:
527 return false;
528 }
529 base += offset;
530 }
531
532 base &= ~7;
533
41456df2
DA		 534 if (radeon_crtc->crtc_id == 1)
535 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
536 else
537 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
538
539 gen_cntl_val = RREG32(gen_cntl_reg);
540 gen_cntl_val &= ~(0xf << 8);
541 gen_cntl_val |= (format << 8);
c640e8ca 542 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
41456df2
DA		 543 WREG32(gen_cntl_reg, gen_cntl_val);
544
771fe6b9
JG		 545 crtc_offset = (u32)base;
546
4162338a 547 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
771fe6b9
JG		 548
549 if (ASIC_IS_R300(rdev)) {
550 if (radeon_crtc->crtc_id)
551 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
552 else
553 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
554 }
555 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
556 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
557 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
558
f4510a27 559 if (!atomic && fb && fb != crtc->primary->fb) {
4dd19b0d 560 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 561 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 562 r = radeon_bo_reserve(rbo, false);
563 if (unlikely(r != 0))
564 return r;
565 radeon_bo_unpin(rbo);
566 radeon_bo_unreserve(rbo);
771fe6b9 567 }
f30f37de
MD		 568
569 /* Bytes per pixel may have changed */
570 radeon_bandwidth_update(rdev);
571
771fe6b9
JG		 572 return 0;
573}
574
575static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
576{
577 struct drm_device *dev = crtc->dev;
578 struct radeon_device *rdev = dev->dev_private;
579 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
4ce001ab 580 struct drm_encoder *encoder;
771fe6b9
JG		 581 int format;
582 int hsync_start;
583 int hsync_wid;
584 int vsync_wid;
585 uint32_t crtc_h_total_disp;
586 uint32_t crtc_h_sync_strt_wid;
587 uint32_t crtc_v_total_disp;
588 uint32_t crtc_v_sync_strt_wid;
4ce001ab 589 bool is_tv = false;
771fe6b9 590
d9fdaafb 591 DRM_DEBUG_KMS("\n");
4ce001ab
DA		 592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
593 if (encoder->crtc == crtc) {
594 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
595 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
596 is_tv = true;
597 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
598 break;
599 }
600 }
601 }
771fe6b9 602
f4510a27 603 switch (crtc->primary->fb->bits_per_pixel) {
41456df2
DA		 604 case 8:
605 format = 2;
606 break;
771fe6b9
JG		 607 case 15: /* 555 */
608 format = 3;
609 break;
610 case 16: /* 565 */
611 format = 4;
612 break;
613 case 24: /* RGB */
614 format = 5;
615 break;
616 case 32: /* xRGB */
617 format = 6;
618 break;
619 default:
620 return false;
621 }
622
623 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
624 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
625
626 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
627 if (!hsync_wid)
628 hsync_wid = 1;
629 hsync_start = mode->crtc_hsync_start - 8;
630
631 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
632 | ((hsync_wid & 0x3f) << 16)
633 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
634 ? RADEON_CRTC_H_SYNC_POL
635 : 0));
636
637 /* This works for double scan mode. */
638 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
639 | ((mode->crtc_vdisplay - 1) << 16));
640
641 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
642 if (!vsync_wid)
643 vsync_wid = 1;
644
645 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
646 | ((vsync_wid & 0x1f) << 16)
647 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
648 ? RADEON_CRTC_V_SYNC_POL
649 : 0));
650
771fe6b9
JG		 651 if (radeon_crtc->crtc_id) {
652 uint32_t crtc2_gen_cntl;
653 uint32_t disp2_merge_cntl;
654
ee2215f0
JG		 655 /* if TV DAC is enabled for another crtc and keep it enabled */
656 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
771fe6b9
JG		 657 crtc2_gen_cntl |= ((format << 8)
658 | RADEON_CRTC2_VSYNC_DIS
659 | RADEON_CRTC2_HSYNC_DIS
660 | RADEON_CRTC2_DISP_DIS
661 | RADEON_CRTC2_DISP_REQ_EN_B
662 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
663 ? RADEON_CRTC2_DBL_SCAN_EN
664 : 0)
665 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
666 ? RADEON_CRTC2_CSYNC_EN
667 : 0)
668 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
669 ? RADEON_CRTC2_INTERLACE_EN
670 : 0));
671
d805f50a
AD		 672 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
673 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
674 crtc2_gen_cntl |= RADEON_CRTC2_EN;
675
771fe6b9
JG		 676 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
677 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
678
679 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
680 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1b4d7d75
AD		 681
682 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
683 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
771fe6b9
JG		 684 } else {
685 uint32_t crtc_gen_cntl;
686 uint32_t crtc_ext_cntl;
687 uint32_t disp_merge_cntl;
688
ee2215f0
JG		 689 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
690 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
771fe6b9
JG		 691 | (format << 8)
692 | RADEON_CRTC_DISP_REQ_EN_B
693 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
694 ? RADEON_CRTC_DBL_SCAN_EN
695 : 0)
696 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
697 ? RADEON_CRTC_CSYNC_EN
698 : 0)
699 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
700 ? RADEON_CRTC_INTERLACE_EN
701 : 0));
702
d805f50a
AD		 703 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
704 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
705 crtc_gen_cntl |= RADEON_CRTC_EN;
706
771fe6b9
JG		 707 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
708 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
709 RADEON_CRTC_VSYNC_DIS |
710 RADEON_CRTC_HSYNC_DIS |
711 RADEON_CRTC_DISPLAY_DIS);
712
713 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
714 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
715
716 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
717 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
718 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
719 }
720
4ce001ab
DA		 721 if (is_tv)
722 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
723 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
724 &crtc_v_sync_strt_wid);
725
771fe6b9
JG		 726 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
727 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
728 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
729 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
730
731 return true;
732}
733
734static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
735{
736 struct drm_device *dev = crtc->dev;
737 struct radeon_device *rdev = dev->dev_private;
738 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
739 struct drm_encoder *encoder;
740 uint32_t feedback_div = 0;
741 uint32_t frac_fb_div = 0;
742 uint32_t reference_div = 0;
743 uint32_t post_divider = 0;
744 uint32_t freq = 0;
745 uint8_t pll_gain;
771fe6b9
JG		 746 bool use_bios_divs = false;
747 /* PLL registers */
748 uint32_t pll_ref_div = 0;
749 uint32_t pll_fb_post_div = 0;
750 uint32_t htotal_cntl = 0;
4ce001ab 751 bool is_tv = false;
771fe6b9
JG		 752 struct radeon_pll *pll;
753
754 struct {
755 int divider;
756 int bitvalue;
757 } *post_div, post_divs[] = {
758 /* From RAGE 128 VR/RAGE 128 GL Register
759 * Reference Manual (Technical Reference
760 * Manual P/N RRG-G04100-C Rev. 0.04), page
761 * 3-17 (PLL_DIV_[3:0]).
762 */
763 { 1, 0 }, /* VCLK_SRC */
764 { 2, 1 }, /* VCLK_SRC/2 */
765 { 4, 2 }, /* VCLK_SRC/4 */
766 { 8, 3 }, /* VCLK_SRC/8 */
767 { 3, 4 }, /* VCLK_SRC/3 */
768 { 16, 5 }, /* VCLK_SRC/16 */
769 { 6, 6 }, /* VCLK_SRC/6 */
770 { 12, 7 }, /* VCLK_SRC/12 */
771 { 0, 0 }
772 };
773
774 if (radeon_crtc->crtc_id)
775 pll = &rdev->clock.p2pll;
776 else
777 pll = &rdev->clock.p1pll;
778
fc10332b 779 pll->flags = RADEON_PLL_LEGACY;
771fe6b9 780
5480f727
DA		 781 if (mode->clock > 200000) /* range limits??? */
782 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
783 else
784 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
785
771fe6b9
JG		 786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
787 if (encoder->crtc == crtc) {
4ce001ab
DA		 788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
789
790 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
791 is_tv = true;
792 break;
793 }
794
771fe6b9 795 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 796 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
771fe6b9 797 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
4c4f5413
AD		 798 if (!rdev->is_atom_bios) {
799 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
800 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
801 if (lvds) {
802 if (lvds->use_bios_dividers) {
803 pll_ref_div = lvds->panel_ref_divider;
804 pll_fb_post_div = (lvds->panel_fb_divider |
805 (lvds->panel_post_divider << 16));
806 htotal_cntl = 0;
807 use_bios_divs = true;
808 }
771fe6b9
JG		 809 }
810 }
fc10332b 811 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9
JG		 812 }
813 }
814 }
815
d9fdaafb 816 DRM_DEBUG_KMS("\n");
771fe6b9
JG		 817
818 if (!use_bios_divs) {
f523f74e
AD		 819 radeon_compute_pll_legacy(pll, mode->clock,
820 &freq, &feedback_div, &frac_fb_div,
821 &reference_div, &post_divider);
771fe6b9
JG		 822
823 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
824 if (post_div->divider == post_divider)
825 break;
826 }
827
828 if (!post_div->divider)
829 post_div = &post_divs[0];
830
d9fdaafb 831 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
771fe6b9
JG		 832 (unsigned)freq,
833 feedback_div,
834 reference_div,
835 post_divider);
836
837 pll_ref_div = reference_div;
838#if defined(__powerpc__) && (0) /* TODO */
839 /* apparently programming this otherwise causes a hang??? */
840 if (info->MacModel == RADEON_MAC_IBOOK)
841 pll_fb_post_div = 0x000600ad;
842 else
843#endif
844 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
845
846 htotal_cntl = mode->htotal & 0x7;
847
848 }
849
850 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
851 pll_ref_div & 0x3ff,
852 pll_fb_post_div & 0x7ff);
853
854 if (radeon_crtc->crtc_id) {
855 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
856 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
857 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
858
4ce001ab
DA		 859 if (is_tv) {
860 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
861 &pll_ref_div, &pll_fb_post_div,
862 &pixclks_cntl);
863 }
864
771fe6b9
JG		 865 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
866 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
867 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
868
869 WREG32_PLL_P(RADEON_P2PLL_CNTL,
870 RADEON_P2PLL_RESET
871 | RADEON_P2PLL_ATOMIC_UPDATE_EN
872 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
873 ~(RADEON_P2PLL_RESET
874 | RADEON_P2PLL_ATOMIC_UPDATE_EN
875 | RADEON_P2PLL_PVG_MASK));
876
877 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
878 pll_ref_div,
879 ~RADEON_P2PLL_REF_DIV_MASK);
880
881 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
882 pll_fb_post_div,
883 ~RADEON_P2PLL_FB0_DIV_MASK);
884
885 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
886 pll_fb_post_div,
887 ~RADEON_P2PLL_POST0_DIV_MASK);
888
889 radeon_pll2_write_update(dev);
890 radeon_pll2_wait_for_read_update_complete(dev);
891
892 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
893
894 WREG32_PLL_P(RADEON_P2PLL_CNTL,
895 0,
896 ~(RADEON_P2PLL_RESET
897 | RADEON_P2PLL_SLEEP
898 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
899
d9fdaafb 900 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
771fe6b9
JG		 901 (unsigned)pll_ref_div,
902 (unsigned)pll_fb_post_div,
903 (unsigned)htotal_cntl,
904 RREG32_PLL(RADEON_P2PLL_CNTL));
d9fdaafb 905 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
771fe6b9
JG		 906 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
907 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
908 (unsigned)((pll_fb_post_div &
909 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
910
911 mdelay(50); /* Let the clock to lock */
912
913 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
914 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
915 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
916
917 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
918 } else {
4ce001ab
DA		 919 uint32_t pixclks_cntl;
920
921
922 if (is_tv) {
923 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
924 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
925 &pll_fb_post_div, &pixclks_cntl);
926 }
927
771fe6b9 928 if (rdev->flags & RADEON_IS_MOBILITY) {
83e61f71 929 /* A temporal workaround for the occasional blanking on certain laptop panels.
771fe6b9
JG		 930 This appears to related to the PLL divider registers (fail to lock?).
931 It occurs even when all dividers are the same with their old settings.
932 In this case we really don't need to fiddle with PLL registers.
933 By doing this we can avoid the blanking problem with some panels.
934 */
935 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
936 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
937 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
938 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
939 RADEON_PLL_DIV_SEL,
940 ~(RADEON_PLL_DIV_SEL));
941 r100_pll_errata_after_index(rdev);
942 return;
943 }
944 }
945
946 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
947 RADEON_VCLK_SRC_SEL_CPUCLK,
948 ~(RADEON_VCLK_SRC_SEL_MASK));
949 WREG32_PLL_P(RADEON_PPLL_CNTL,
950 RADEON_PPLL_RESET
951 | RADEON_PPLL_ATOMIC_UPDATE_EN
952 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
953 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
954 ~(RADEON_PPLL_RESET
955 | RADEON_PPLL_ATOMIC_UPDATE_EN
956 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
957 | RADEON_PPLL_PVG_MASK));
958
959 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
960 RADEON_PLL_DIV_SEL,
961 ~(RADEON_PLL_DIV_SEL));
962 r100_pll_errata_after_index(rdev);
963
964 if (ASIC_IS_R300(rdev) ||
965 (rdev->family == CHIP_RS300) ||
966 (rdev->family == CHIP_RS400) ||
967 (rdev->family == CHIP_RS480)) {
968 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
969 /* When restoring console mode, use saved PPLL_REF_DIV
970 * setting.
971 */
972 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
973 pll_ref_div,
974 0);
975 } else {
976 /* R300 uses ref_div_acc field as real ref divider */
977 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
978 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
979 ~R300_PPLL_REF_DIV_ACC_MASK);
980 }
981 } else
982 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
983 pll_ref_div,
984 ~RADEON_PPLL_REF_DIV_MASK);
985
986 WREG32_PLL_P(RADEON_PPLL_DIV_3,
987 pll_fb_post_div,
988 ~RADEON_PPLL_FB3_DIV_MASK);
989
990 WREG32_PLL_P(RADEON_PPLL_DIV_3,
991 pll_fb_post_div,
992 ~RADEON_PPLL_POST3_DIV_MASK);
993
994 radeon_pll_write_update(dev);
995 radeon_pll_wait_for_read_update_complete(dev);
996
997 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
998
999 WREG32_PLL_P(RADEON_PPLL_CNTL,
1000 0,
1001 ~(RADEON_PPLL_RESET
1002 | RADEON_PPLL_SLEEP
1003 | RADEON_PPLL_ATOMIC_UPDATE_EN
1004 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1005
d9fdaafb 1006 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
771fe6b9
JG		 1007 pll_ref_div,
1008 pll_fb_post_div,
1009 (unsigned)htotal_cntl,
1010 RREG32_PLL(RADEON_PPLL_CNTL));
d9fdaafb 1011 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
771fe6b9
JG		 1012 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1013 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1014 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1015
1016 mdelay(50); /* Let the clock to lock */
1017
1018 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1019 RADEON_VCLK_SRC_SEL_PPLLCLK,
1020 ~(RADEON_VCLK_SRC_SEL_MASK));
1021
4ce001ab
DA		 1022 if (is_tv)
1023 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
771fe6b9
JG		 1024 }
1025}
1026
1027static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1028 const struct drm_display_mode *mode,
771fe6b9
JG		 1029 struct drm_display_mode *adjusted_mode)
1030{
c93bb85b
JG		 1031 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1032 return false;
771fe6b9
JG		 1033 return true;
1034}
1035
1036static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1037 struct drm_display_mode *mode,
1038 struct drm_display_mode *adjusted_mode,
1039 int x, int y, struct drm_framebuffer *old_fb)
1040{
c93bb85b 1041 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 1042
1043 /* TODO TV */
771fe6b9
JG		 1044 radeon_crtc_set_base(crtc, x, y, old_fb);
1045 radeon_set_crtc_timing(crtc, adjusted_mode);
1046 radeon_set_pll(crtc, adjusted_mode);
6b02af1c 1047 radeon_overscan_setup(crtc, adjusted_mode);
c93bb85b 1048 if (radeon_crtc->crtc_id == 0) {
310a82c8 1049 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
c93bb85b
JG		 1050 } else {
1051 if (radeon_crtc->rmx_type != RMX_OFF) {
1052 /* FIXME: only first crtc has rmx what should we
1053 * do ?
1054 */
1055 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1056 }
1057 }
6d3759fa 1058 radeon_cursor_reset(crtc);
771fe6b9
JG		 1059 return 0;
1060}
1061
1062static void radeon_crtc_prepare(struct drm_crtc *crtc)
1063{
ec51efa9
PO		 1064 struct drm_device *dev = crtc->dev;
1065 struct drm_crtc *crtci;
1066
1067 /*
1068 * The hardware wedges sometimes if you reconfigure one CRTC
1069 * whilst another is running (see fdo bug #24611).
1070 */
1071 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1072 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1073}
1074
1075static void radeon_crtc_commit(struct drm_crtc *crtc)
1076{
ec51efa9
PO		 1077 struct drm_device *dev = crtc->dev;
1078 struct drm_crtc *crtci;
1079
1080 /*
1081 * Reenable the CRTCs that should be running.
1082 */
1083 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1084 if (crtci->enabled)
1085 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1086 }
771fe6b9
JG		 1087}
1088
520a8718
IH		 1089static void radeon_crtc_disable(struct drm_crtc *crtc)
1090{
1091 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
f4510a27 1092 if (crtc->primary->fb) {
520a8718
IH		 1093 int r;
1094 struct radeon_framebuffer *radeon_fb;
1095 struct radeon_bo *rbo;
1096
f4510a27 1097 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
520a8718
IH		 1098 rbo = gem_to_radeon_bo(radeon_fb->obj);
1099 r = radeon_bo_reserve(rbo, false);
1100 if (unlikely(r))
1101 DRM_ERROR("failed to reserve rbo before unpin\n");
1102 else {
1103 radeon_bo_unpin(rbo);
1104 radeon_bo_unreserve(rbo);
1105 }
1106 }
1107}
1108
771fe6b9
JG		 1109static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1110 .dpms = radeon_crtc_dpms,
1111 .mode_fixup = radeon_crtc_mode_fixup,
1112 .mode_set = radeon_crtc_mode_set,
1113 .mode_set_base = radeon_crtc_set_base,
4dd19b0d 1114 .mode_set_base_atomic = radeon_crtc_set_base_atomic,
771fe6b9
JG		 1115 .prepare = radeon_crtc_prepare,
1116 .commit = radeon_crtc_commit,
068143d3 1117 .load_lut = radeon_crtc_load_lut,
520a8718 1118 .disable = radeon_crtc_disable
771fe6b9
JG		 1119};
1120
1121
1122void radeon_legacy_init_crtc(struct drm_device *dev,
1123 struct radeon_crtc *radeon_crtc)
1124{
1125 if (radeon_crtc->crtc_id == 1)
1126 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1127 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1128}
Linux 6.x block layer and io_uring tree(s)