Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
27 | #include "drmP.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon_reg.h" | |
30 | #include "radeon.h" | |
31 | ||
32 | void r100_cs_dump_packet(struct radeon_cs_parser *p, | |
33 | struct radeon_cs_packet *pkt); | |
34 | ||
35 | int radeon_cs_parser_relocs(struct radeon_cs_parser *p) | |
36 | { | |
37 | struct drm_device *ddev = p->rdev->ddev; | |
38 | struct radeon_cs_chunk *chunk; | |
39 | unsigned i, j; | |
40 | bool duplicate; | |
41 | ||
42 | if (p->chunk_relocs_idx == -1) { | |
43 | return 0; | |
44 | } | |
45 | chunk = &p->chunks[p->chunk_relocs_idx]; | |
46 | /* FIXME: we assume that each relocs use 4 dwords */ | |
47 | p->nrelocs = chunk->length_dw / 4; | |
48 | p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); | |
49 | if (p->relocs_ptr == NULL) { | |
50 | return -ENOMEM; | |
51 | } | |
52 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); | |
53 | if (p->relocs == NULL) { | |
54 | return -ENOMEM; | |
55 | } | |
56 | for (i = 0; i < p->nrelocs; i++) { | |
57 | struct drm_radeon_cs_reloc *r; | |
58 | ||
59 | duplicate = false; | |
60 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; | |
16557f1e | 61 | for (j = 0; j < i; j++) { |
771fe6b9 JG |
62 | if (r->handle == p->relocs[j].handle) { |
63 | p->relocs_ptr[i] = &p->relocs[j]; | |
64 | duplicate = true; | |
65 | break; | |
66 | } | |
67 | } | |
68 | if (!duplicate) { | |
69 | p->relocs[i].gobj = drm_gem_object_lookup(ddev, | |
70 | p->filp, | |
71 | r->handle); | |
72 | if (p->relocs[i].gobj == NULL) { | |
73 | DRM_ERROR("gem object lookup failed 0x%x\n", | |
74 | r->handle); | |
bf79cb91 | 75 | return -ENOENT; |
771fe6b9 JG |
76 | } |
77 | p->relocs_ptr[i] = &p->relocs[i]; | |
7e4d15d9 | 78 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); |
4c788679 | 79 | p->relocs[i].lobj.bo = p->relocs[i].robj; |
771fe6b9 | 80 | p->relocs[i].lobj.wdomain = r->write_domain; |
147666fb TH |
81 | p->relocs[i].lobj.rdomain = r->read_domains; |
82 | p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; | |
771fe6b9 JG |
83 | p->relocs[i].handle = r->handle; |
84 | p->relocs[i].flags = r->flags; | |
4c788679 | 85 | radeon_bo_list_add_object(&p->relocs[i].lobj, |
147666fb | 86 | &p->validated); |
93504fce | 87 | |
16557f1e CK |
88 | } else |
89 | p->relocs[i].handle = 0; | |
771fe6b9 | 90 | } |
94429bb6 | 91 | return radeon_bo_list_validate(&p->validated); |
771fe6b9 JG |
92 | } |
93 | ||
721604a1 JG |
94 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
95 | { | |
96 | p->priority = priority; | |
97 | ||
98 | switch (ring) { | |
99 | default: | |
100 | DRM_ERROR("unknown ring id: %d\n", ring); | |
101 | return -EINVAL; | |
102 | case RADEON_CS_RING_GFX: | |
103 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
104 | break; | |
105 | case RADEON_CS_RING_COMPUTE: | |
106 | /* for now */ | |
107 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
108 | break; | |
109 | } | |
110 | return 0; | |
111 | } | |
112 | ||
93504fce CK |
113 | static int radeon_cs_sync_rings(struct radeon_cs_parser *p) |
114 | { | |
cdac5504 | 115 | bool sync_to_ring[RADEON_NUM_RINGS] = { }; |
93504fce CK |
116 | int i, r; |
117 | ||
cdac5504 CK |
118 | for (i = 0; i < p->nrelocs; i++) { |
119 | if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj) | |
120 | continue; | |
121 | ||
122 | if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) { | |
123 | struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj; | |
124 | if (!radeon_fence_signaled(fence)) { | |
125 | sync_to_ring[fence->ring] = true; | |
126 | } | |
127 | } | |
128 | } | |
129 | ||
93504fce CK |
130 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
131 | /* no need to sync to our own or unused rings */ | |
cdac5504 | 132 | if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready) |
93504fce CK |
133 | continue; |
134 | ||
135 | if (!p->ib->fence->semaphore) { | |
136 | r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore); | |
137 | if (r) | |
138 | return r; | |
139 | } | |
140 | ||
141 | r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3); | |
142 | if (r) | |
143 | return r; | |
144 | radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore); | |
145 | radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]); | |
146 | ||
147 | r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3); | |
148 | if (r) | |
149 | return r; | |
150 | radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore); | |
151 | radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]); | |
152 | } | |
153 | return 0; | |
154 | } | |
155 | ||
771fe6b9 JG |
156 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
157 | { | |
158 | struct drm_radeon_cs *cs = data; | |
159 | uint64_t *chunk_array_ptr; | |
721604a1 JG |
160 | unsigned size, i; |
161 | u32 ring = RADEON_CS_RING_GFX; | |
162 | s32 priority = 0; | |
771fe6b9 JG |
163 | |
164 | if (!cs->num_chunks) { | |
165 | return 0; | |
166 | } | |
167 | /* get chunks */ | |
168 | INIT_LIST_HEAD(&p->validated); | |
169 | p->idx = 0; | |
170 | p->chunk_ib_idx = -1; | |
171 | p->chunk_relocs_idx = -1; | |
721604a1 | 172 | p->chunk_flags_idx = -1; |
771fe6b9 JG |
173 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
174 | if (p->chunks_array == NULL) { | |
175 | return -ENOMEM; | |
176 | } | |
177 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); | |
178 | if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, | |
179 | sizeof(uint64_t)*cs->num_chunks)) { | |
180 | return -EFAULT; | |
181 | } | |
721604a1 | 182 | p->cs_flags = 0; |
771fe6b9 JG |
183 | p->nchunks = cs->num_chunks; |
184 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); | |
185 | if (p->chunks == NULL) { | |
186 | return -ENOMEM; | |
187 | } | |
188 | for (i = 0; i < p->nchunks; i++) { | |
189 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; | |
190 | struct drm_radeon_cs_chunk user_chunk; | |
191 | uint32_t __user *cdata; | |
192 | ||
193 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; | |
194 | if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, | |
195 | sizeof(struct drm_radeon_cs_chunk))) { | |
196 | return -EFAULT; | |
197 | } | |
5176fdc4 DA |
198 | p->chunks[i].length_dw = user_chunk.length_dw; |
199 | p->chunks[i].kdata = NULL; | |
771fe6b9 | 200 | p->chunks[i].chunk_id = user_chunk.chunk_id; |
5176fdc4 | 201 | |
771fe6b9 JG |
202 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { |
203 | p->chunk_relocs_idx = i; | |
204 | } | |
205 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | |
206 | p->chunk_ib_idx = i; | |
5176fdc4 DA |
207 | /* zero length IB isn't useful */ |
208 | if (p->chunks[i].length_dw == 0) | |
209 | return -EINVAL; | |
771fe6b9 | 210 | } |
721604a1 JG |
211 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
212 | p->chunk_flags_idx = i; | |
213 | /* zero length flags aren't useful */ | |
214 | if (p->chunks[i].length_dw == 0) | |
215 | return -EINVAL; | |
e70f224c | 216 | } |
5176fdc4 | 217 | |
771fe6b9 | 218 | p->chunks[i].length_dw = user_chunk.length_dw; |
513bcb46 | 219 | p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; |
771fe6b9 | 220 | |
513bcb46 | 221 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; |
721604a1 JG |
222 | if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || |
223 | (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { | |
513bcb46 DA |
224 | size = p->chunks[i].length_dw * sizeof(uint32_t); |
225 | p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); | |
226 | if (p->chunks[i].kdata == NULL) { | |
227 | return -ENOMEM; | |
228 | } | |
229 | if (DRM_COPY_FROM_USER(p->chunks[i].kdata, | |
230 | p->chunks[i].user_ptr, size)) { | |
231 | return -EFAULT; | |
232 | } | |
e70f224c | 233 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
721604a1 JG |
234 | p->cs_flags = p->chunks[i].kdata[0]; |
235 | if (p->chunks[i].length_dw > 1) | |
236 | ring = p->chunks[i].kdata[1]; | |
237 | if (p->chunks[i].length_dw > 2) | |
238 | priority = (s32)p->chunks[i].kdata[2]; | |
e70f224c | 239 | } |
771fe6b9 JG |
240 | } |
241 | } | |
721604a1 JG |
242 | |
243 | if ((p->cs_flags & RADEON_CS_USE_VM) && | |
67e915e4 AD |
244 | !p->rdev->vm_manager.enabled) { |
245 | DRM_ERROR("VM not active on asic!\n"); | |
771fe6b9 JG |
246 | return -EINVAL; |
247 | } | |
e70f224c | 248 | |
f48bb04a | 249 | if (radeon_cs_get_ring(p, ring, priority)) |
721604a1 | 250 | return -EINVAL; |
721604a1 JG |
251 | |
252 | ||
253 | /* deal with non-vm */ | |
254 | if ((p->chunk_ib_idx != -1) && | |
255 | ((p->cs_flags & RADEON_CS_USE_VM) == 0) && | |
256 | (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { | |
257 | if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { | |
258 | DRM_ERROR("cs IB too big: %d\n", | |
259 | p->chunks[p->chunk_ib_idx].length_dw); | |
260 | return -EINVAL; | |
261 | } | |
262 | p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
263 | p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
264 | if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || | |
f48bb04a | 265 | p->chunks[p->chunk_ib_idx].kpage[1] == NULL) |
721604a1 | 266 | return -ENOMEM; |
721604a1 JG |
267 | p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; |
268 | p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; | |
269 | p->chunks[p->chunk_ib_idx].last_copied_page = -1; | |
270 | p->chunks[p->chunk_ib_idx].last_page_index = | |
271 | ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; | |
272 | } | |
273 | ||
771fe6b9 JG |
274 | return 0; |
275 | } | |
276 | ||
277 | /** | |
278 | * cs_parser_fini() - clean parser states | |
279 | * @parser: parser structure holding parsing context. | |
280 | * @error: error number | |
281 | * | |
282 | * If error is set than unvalidate buffer, otherwise just free memory | |
283 | * used by parsing context. | |
284 | **/ | |
285 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) | |
286 | { | |
287 | unsigned i; | |
288 | ||
147666fb TH |
289 | |
290 | if (!error && parser->ib) | |
291 | ttm_eu_fence_buffer_objects(&parser->validated, | |
292 | parser->ib->fence); | |
293 | else | |
294 | ttm_eu_backoff_reservation(&parser->validated); | |
295 | ||
fcbc451b PN |
296 | if (parser->relocs != NULL) { |
297 | for (i = 0; i < parser->nrelocs; i++) { | |
298 | if (parser->relocs[i].gobj) | |
299 | drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); | |
300 | } | |
771fe6b9 | 301 | } |
48e113e5 | 302 | kfree(parser->track); |
771fe6b9 JG |
303 | kfree(parser->relocs); |
304 | kfree(parser->relocs_ptr); | |
305 | for (i = 0; i < parser->nchunks; i++) { | |
306 | kfree(parser->chunks[i].kdata); | |
513bcb46 DA |
307 | kfree(parser->chunks[i].kpage[0]); |
308 | kfree(parser->chunks[i].kpage[1]); | |
771fe6b9 JG |
309 | } |
310 | kfree(parser->chunks); | |
311 | kfree(parser->chunks_array); | |
312 | radeon_ib_free(parser->rdev, &parser->ib); | |
313 | } | |
314 | ||
721604a1 JG |
315 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
316 | struct radeon_cs_parser *parser) | |
317 | { | |
318 | struct radeon_cs_chunk *ib_chunk; | |
319 | int r; | |
320 | ||
321 | if (parser->chunk_ib_idx == -1) | |
322 | return 0; | |
323 | ||
324 | if (parser->cs_flags & RADEON_CS_USE_VM) | |
325 | return 0; | |
326 | ||
327 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
328 | /* Copy the packet into the IB, the parser will read from the | |
329 | * input memory (cached) and write to the IB (which can be | |
330 | * uncached). | |
331 | */ | |
332 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
333 | ib_chunk->length_dw * 4); | |
334 | if (r) { | |
335 | DRM_ERROR("Failed to get ib !\n"); | |
336 | return r; | |
337 | } | |
338 | parser->ib->length_dw = ib_chunk->length_dw; | |
eb0c19c5 | 339 | r = radeon_cs_parse(rdev, parser->ring, parser); |
721604a1 JG |
340 | if (r || parser->parser_error) { |
341 | DRM_ERROR("Invalid command stream !\n"); | |
342 | return r; | |
343 | } | |
344 | r = radeon_cs_finish_pages(parser); | |
345 | if (r) { | |
346 | DRM_ERROR("Invalid command stream !\n"); | |
347 | return r; | |
348 | } | |
93504fce CK |
349 | r = radeon_cs_sync_rings(parser); |
350 | if (r) { | |
351 | DRM_ERROR("Failed to synchronize rings !\n"); | |
352 | } | |
721604a1 JG |
353 | parser->ib->vm_id = 0; |
354 | r = radeon_ib_schedule(rdev, parser->ib); | |
355 | if (r) { | |
356 | DRM_ERROR("Failed to schedule IB !\n"); | |
357 | } | |
358 | return 0; | |
359 | } | |
360 | ||
361 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, | |
362 | struct radeon_vm *vm) | |
363 | { | |
364 | struct radeon_bo_list *lobj; | |
365 | struct radeon_bo *bo; | |
366 | int r; | |
367 | ||
368 | list_for_each_entry(lobj, &parser->validated, tv.head) { | |
369 | bo = lobj->bo; | |
370 | r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); | |
371 | if (r) { | |
372 | return r; | |
373 | } | |
374 | } | |
375 | return 0; | |
376 | } | |
377 | ||
378 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |
379 | struct radeon_cs_parser *parser) | |
380 | { | |
381 | struct radeon_cs_chunk *ib_chunk; | |
382 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; | |
383 | struct radeon_vm *vm = &fpriv->vm; | |
384 | int r; | |
385 | ||
386 | if (parser->chunk_ib_idx == -1) | |
387 | return 0; | |
388 | ||
389 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) | |
390 | return 0; | |
391 | ||
392 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
393 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
394 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); | |
395 | return -EINVAL; | |
396 | } | |
397 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
398 | ib_chunk->length_dw * 4); | |
399 | if (r) { | |
400 | DRM_ERROR("Failed to get ib !\n"); | |
401 | return r; | |
402 | } | |
403 | parser->ib->length_dw = ib_chunk->length_dw; | |
404 | /* Copy the packet into the IB */ | |
405 | if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr, | |
406 | ib_chunk->length_dw * 4)) { | |
407 | return -EFAULT; | |
408 | } | |
409 | r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib); | |
410 | if (r) { | |
411 | return r; | |
412 | } | |
413 | ||
414 | mutex_lock(&vm->mutex); | |
415 | r = radeon_vm_bind(rdev, vm); | |
416 | if (r) { | |
417 | goto out; | |
418 | } | |
419 | r = radeon_bo_vm_update_pte(parser, vm); | |
420 | if (r) { | |
421 | goto out; | |
422 | } | |
93504fce CK |
423 | r = radeon_cs_sync_rings(parser); |
424 | if (r) { | |
425 | DRM_ERROR("Failed to synchronize rings !\n"); | |
426 | } | |
721604a1 JG |
427 | parser->ib->vm_id = vm->id; |
428 | /* ib pool is bind at 0 in virtual address space to gpu_addr is the | |
429 | * offset inside the pool bo | |
430 | */ | |
431 | parser->ib->gpu_addr = parser->ib->sa_bo.offset; | |
432 | r = radeon_ib_schedule(rdev, parser->ib); | |
433 | out: | |
434 | if (!r) { | |
435 | if (vm->fence) { | |
436 | radeon_fence_unref(&vm->fence); | |
437 | } | |
438 | vm->fence = radeon_fence_ref(parser->ib->fence); | |
439 | } | |
440 | mutex_unlock(&fpriv->vm.mutex); | |
441 | return r; | |
442 | } | |
443 | ||
771fe6b9 JG |
444 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
445 | { | |
446 | struct radeon_device *rdev = dev->dev_private; | |
447 | struct radeon_cs_parser parser; | |
771fe6b9 JG |
448 | int r; |
449 | ||
7a1619b9 | 450 | radeon_mutex_lock(&rdev->cs_mutex); |
6b7746e8 JG |
451 | if (!rdev->accel_working) { |
452 | radeon_mutex_unlock(&rdev->cs_mutex); | |
453 | return -EBUSY; | |
454 | } | |
771fe6b9 JG |
455 | /* initialize parser */ |
456 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
457 | parser.filp = filp; | |
458 | parser.rdev = rdev; | |
c8c15ff1 | 459 | parser.dev = rdev->dev; |
428c6e36 | 460 | parser.family = rdev->family; |
771fe6b9 JG |
461 | r = radeon_cs_parser_init(&parser, data); |
462 | if (r) { | |
463 | DRM_ERROR("Failed to initialize parser !\n"); | |
464 | radeon_cs_parser_fini(&parser, r); | |
7a1619b9 | 465 | radeon_mutex_unlock(&rdev->cs_mutex); |
771fe6b9 JG |
466 | return r; |
467 | } | |
771fe6b9 JG |
468 | r = radeon_cs_parser_relocs(&parser); |
469 | if (r) { | |
97f23b3d DA |
470 | if (r != -ERESTARTSYS) |
471 | DRM_ERROR("Failed to parse relocation %d!\n", r); | |
771fe6b9 | 472 | radeon_cs_parser_fini(&parser, r); |
7a1619b9 | 473 | radeon_mutex_unlock(&rdev->cs_mutex); |
771fe6b9 JG |
474 | return r; |
475 | } | |
721604a1 | 476 | r = radeon_cs_ib_chunk(rdev, &parser); |
771fe6b9 | 477 | if (r) { |
721604a1 | 478 | goto out; |
771fe6b9 | 479 | } |
721604a1 | 480 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
771fe6b9 | 481 | if (r) { |
721604a1 | 482 | goto out; |
771fe6b9 | 483 | } |
721604a1 | 484 | out: |
771fe6b9 | 485 | radeon_cs_parser_fini(&parser, r); |
7a1619b9 | 486 | radeon_mutex_unlock(&rdev->cs_mutex); |
771fe6b9 JG |
487 | return r; |
488 | } | |
513bcb46 DA |
489 | |
490 | int radeon_cs_finish_pages(struct radeon_cs_parser *p) | |
491 | { | |
492 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
493 | int i; | |
494 | int size = PAGE_SIZE; | |
495 | ||
496 | for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { | |
497 | if (i == ibc->last_page_index) { | |
498 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
499 | if (size == 0) | |
500 | size = PAGE_SIZE; | |
501 | } | |
502 | ||
503 | if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), | |
504 | ibc->user_ptr + (i * PAGE_SIZE), | |
505 | size)) | |
506 | return -EFAULT; | |
507 | } | |
508 | return 0; | |
509 | } | |
510 | ||
511 | int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) | |
512 | { | |
513 | int new_page; | |
513bcb46 DA |
514 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
515 | int i; | |
516 | int size = PAGE_SIZE; | |
517 | ||
c5e617e2 | 518 | for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { |
513bcb46 DA |
519 | if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), |
520 | ibc->user_ptr + (i * PAGE_SIZE), | |
521 | PAGE_SIZE)) { | |
522 | p->parser_error = -EFAULT; | |
523 | return 0; | |
524 | } | |
525 | } | |
526 | ||
527 | new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; | |
528 | ||
529 | if (pg_idx == ibc->last_page_index) { | |
530 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
531 | if (size == 0) | |
532 | size = PAGE_SIZE; | |
533 | } | |
534 | ||
535 | if (DRM_COPY_FROM_USER(ibc->kpage[new_page], | |
536 | ibc->user_ptr + (pg_idx * PAGE_SIZE), | |
537 | size)) { | |
538 | p->parser_error = -EFAULT; | |
539 | return 0; | |
540 | } | |
541 | ||
542 | /* copy to IB here */ | |
543 | memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); | |
544 | ||
545 | ibc->last_copied_page = pg_idx; | |
546 | ibc->kpage_idx[new_page] = pg_idx; | |
547 | ||
548 | return new_page; | |
549 | } |