[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_cs.c

/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
{
	struct drm_device *ddev = p->rdev->ddev;
	struct radeon_cs_chunk *chunk;
	unsigned i, j;
	bool duplicate;

	if (p->chunk_relocs_idx == -1) {
		return 0;
	}
	chunk = &p->chunks[p->chunk_relocs_idx];
	/* FIXME: we assume that each relocs use 4 dwords */
	p->nrelocs = chunk->length_dw / 4;
	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	if (p->relocs_ptr == NULL) {
		return -ENOMEM;
	}
	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	if (p->relocs == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nrelocs; i++) {
		struct drm_radeon_cs_reloc *r;

		duplicate = false;
		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
		for (j = 0; j < i; j++) {
			if (r->handle == p->relocs[j].handle) {
				p->relocs_ptr[i] = &p->relocs[j];
				duplicate = true;
				break;
			}
		}
		if (!duplicate) {
			p->relocs[i].gobj = drm_gem_object_lookup(ddev,
								  p->filp,
								  r->handle);
			if (p->relocs[i].gobj == NULL) {
				DRM_ERROR("gem object lookup failed 0x%x\n",
					  r->handle);
				return -ENOENT;
			}
			p->relocs_ptr[i] = &p->relocs[i];
			p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
			p->relocs[i].lobj.bo = p->relocs[i].robj;
			p->relocs[i].lobj.wdomain = r->write_domain;
			p->relocs[i].lobj.rdomain = r->read_domains;
			p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
			p->relocs[i].handle = r->handle;
			p->relocs[i].flags = r->flags;
			radeon_bo_list_add_object(&p->relocs[i].lobj,
						  &p->validated);

		} else
			p->relocs[i].handle = 0;
	}
	return radeon_bo_list_validate(&p->validated);
}

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
{
	p->priority = priority;

	switch (ring) {
	default:
		DRM_ERROR("unknown ring id: %d\n", ring);
		return -EINVAL;
	case RADEON_CS_RING_GFX:
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	case RADEON_CS_RING_COMPUTE:
		if (p->rdev->family >= CHIP_TAHITI) {
			if (p->priority > 0)
				p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
			else
				p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
		} else
			p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	}
	return 0;
}

static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
{
	int i;

	for (i = 0; i < p->nrelocs; i++) {
		struct radeon_fence *a, *b;

		if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
			continue;

		a = p->relocs[i].robj->tbo.sync_obj;
		b = p->ib.sync_to[a->ring];
		p->ib.sync_to[a->ring] = radeon_fence_later(a, b);
	}
}

/* XXX: note that this is called from the legacy UMS CS ioctl as well */
int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
{
	struct drm_radeon_cs *cs = data;
	uint64_t *chunk_array_ptr;
	unsigned size, i;
	u32 ring = RADEON_CS_RING_GFX;
	s32 priority = 0;

	if (!cs->num_chunks) {
		return 0;
	}
	/* get chunks */
	INIT_LIST_HEAD(&p->validated);
	p->idx = 0;
	p->ib.sa_bo = NULL;
	p->ib.semaphore = NULL;
	p->const_ib.sa_bo = NULL;
	p->const_ib.semaphore = NULL;
	p->chunk_ib_idx = -1;
	p->chunk_relocs_idx = -1;
	p->chunk_flags_idx = -1;
	p->chunk_const_ib_idx = -1;
	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (p->chunks_array == NULL) {
		return -ENOMEM;
	}
	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
			       sizeof(uint64_t)*cs->num_chunks)) {
		return -EFAULT;
	}
	p->cs_flags = 0;
	p->nchunks = cs->num_chunks;
	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	if (p->chunks == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nchunks; i++) {
		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
		struct drm_radeon_cs_chunk user_chunk;
		uint32_t __user *cdata;

		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
		if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
				       sizeof(struct drm_radeon_cs_chunk))) {
			return -EFAULT;
		}
		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].kdata = NULL;
		p->chunks[i].chunk_id = user_chunk.chunk_id;

		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
			p->chunk_relocs_idx = i;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
			p->chunk_ib_idx = i;
			/* zero length IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
			p->chunk_const_ib_idx = i;
			/* zero length CONST IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
			p->chunk_flags_idx = i;
			/* zero length flags aren't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}

		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
		if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
		    (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
			size = p->chunks[i].length_dw * sizeof(uint32_t);
			p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
			if (p->chunks[i].kdata == NULL) {
				return -ENOMEM;
			}
			if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
					       p->chunks[i].user_ptr, size)) {
				return -EFAULT;
			}
			if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
				p->cs_flags = p->chunks[i].kdata[0];
				if (p->chunks[i].length_dw > 1)
					ring = p->chunks[i].kdata[1];
				if (p->chunks[i].length_dw > 2)
					priority = (s32)p->chunks[i].kdata[2];
			}
		}
	}

	/* these are KMS only */
	if (p->rdev) {
		if ((p->cs_flags & RADEON_CS_USE_VM) &&
		    !p->rdev->vm_manager.enabled) {
			DRM_ERROR("VM not active on asic!\n");
			return -EINVAL;
		}

		/* we only support VM on SI+ */
		if ((p->rdev->family >= CHIP_TAHITI) &&
		    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
			DRM_ERROR("VM required on SI+!\n");
			return -EINVAL;
		}

		if (radeon_cs_get_ring(p, ring, priority))
			return -EINVAL;
	}

	/* deal with non-vm */
	if ((p->chunk_ib_idx != -1) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	    (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
		if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
			DRM_ERROR("cs IB too big: %d\n",
				  p->chunks[p->chunk_ib_idx].length_dw);
			return -EINVAL;
		}
		if ((p->rdev->flags & RADEON_IS_AGP)) {
			p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
			    p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
				kfree(p->chunks[i].kpage[0]);
				kfree(p->chunks[i].kpage[1]);
				return -ENOMEM;
			}
		}
		p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
		p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
		p->chunks[p->chunk_ib_idx].last_copied_page = -1;
		p->chunks[p->chunk_ib_idx].last_page_index =
			((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	}

	return 0;
}

/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
{
	unsigned i;

	if (!error)
		ttm_eu_fence_buffer_objects(&parser->validated,
					    parser->ib.fence);
	else
		ttm_eu_backoff_reservation(&parser->validated);

	if (parser->relocs != NULL) {
		for (i = 0; i < parser->nrelocs; i++) {
			if (parser->relocs[i].gobj)
				drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
		}
	}
	kfree(parser->track);
	kfree(parser->relocs);
	kfree(parser->relocs_ptr);
	for (i = 0; i < parser->nchunks; i++) {
		kfree(parser->chunks[i].kdata);
		if ((parser->rdev->flags & RADEON_IS_AGP)) {
			kfree(parser->chunks[i].kpage[0]);
			kfree(parser->chunks[i].kpage[1]);
		}
	}
	kfree(parser->chunks);
	kfree(parser->chunks_array);
	radeon_ib_free(parser->rdev, &parser->ib);
	radeon_ib_free(parser->rdev, &parser->const_ib);
}

static int radeon_cs_ib_chunk(struct radeon_device *rdev,
			      struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if (parser->cs_flags & RADEON_CS_USE_VM)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	/* Copy the packet into the IB, the parser will read from the
	 * input memory (cached) and write to the IB (which can be
	 * uncached).
	 */
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib.length_dw = ib_chunk->length_dw;
	r = radeon_cs_parse(rdev, parser->ring, parser);
	if (r || parser->parser_error) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_finish_pages(parser);
	if (r) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	radeon_cs_sync_rings(parser);
	parser->ib.vm_id = 0;
	r = radeon_ib_schedule(rdev, &parser->ib);
	if (r) {
		DRM_ERROR("Failed to schedule IB !\n");
	}
	return r;
}

static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
				   struct radeon_vm *vm)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	list_for_each_entry(lobj, &parser->validated, tv.head) {
		bo = lobj->bo;
		r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
		if (r) {
			return r;
		}
	}
	return 0;
}

static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
				 struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
		return 0;

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
		if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
			DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
			return -EINVAL;
		}
		r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
				   ib_chunk->length_dw * 4);
		if (r) {
			DRM_ERROR("Failed to get const ib !\n");
			return r;
		}
		parser->const_ib.is_const_ib = true;
		parser->const_ib.length_dw = ib_chunk->length_dw;
		/* Copy the packet into the IB */
		if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
				       ib_chunk->length_dw * 4)) {
			return -EFAULT;
		}
		r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
		if (r) {
			return r;
		}
	}

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
		DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
		return -EINVAL;
	}
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib.length_dw = ib_chunk->length_dw;
	/* Copy the packet into the IB */
	if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
			       ib_chunk->length_dw * 4)) {
		return -EFAULT;
	}
	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
	if (r) {
		return r;
	}

	mutex_lock(&rdev->vm_manager.lock);
	mutex_lock(&vm->mutex);
	r = radeon_vm_bind(rdev, vm);
	if (r) {
		goto out;
	}
	r = radeon_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
	}
	radeon_cs_sync_rings(parser);

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		parser->const_ib.vm_id = vm->id;
		/* ib pool is bind at 0 in virtual address space to gpu_addr is the
		 * offset inside the pool bo
		 */
		parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
		r = radeon_ib_schedule(rdev, &parser->const_ib);
		if (r)
			goto out;
	}

	parser->ib.vm_id = vm->id;
	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	 * offset inside the pool bo
	 */
	parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
	parser->ib.is_const_ib = false;
	r = radeon_ib_schedule(rdev, &parser->ib);
out:
	if (!r) {
		if (vm->fence) {
			radeon_fence_unref(&vm->fence);
		}
		vm->fence = radeon_fence_ref(parser->ib.fence);
	}
	mutex_unlock(&vm->mutex);
	mutex_unlock(&rdev->vm_manager.lock);
	return r;
}

static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
{
	if (r == -EDEADLK) {
		r = radeon_gpu_reset(rdev);
		if (!r)
			r = -EAGAIN;
	}
	return r;
}

int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_cs_parser parser;
	int r;

	down_read(&rdev->exclusive_lock);
	if (!rdev->accel_working) {
		up_read(&rdev->exclusive_lock);
		return -EBUSY;
	}
	/* initialize parser */
	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	parser.filp = filp;
	parser.rdev = rdev;
	parser.dev = rdev->dev;
	parser.family = rdev->family;
	r = radeon_cs_parser_init(&parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		radeon_cs_parser_fini(&parser, r);
		up_read(&rdev->exclusive_lock);
		r = radeon_cs_handle_lockup(rdev, r);
		return r;
	}
	r = radeon_cs_parser_relocs(&parser);
	if (r) {
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to parse relocation %d!\n", r);
		radeon_cs_parser_fini(&parser, r);
		up_read(&rdev->exclusive_lock);
		r = radeon_cs_handle_lockup(rdev, r);
		return r;
	}
	r = radeon_cs_ib_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
	r = radeon_cs_ib_vm_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
out:
	radeon_cs_parser_fini(&parser, r);
	up_read(&rdev->exclusive_lock);
	r = radeon_cs_handle_lockup(rdev, r);
	return r;
}

int radeon_cs_finish_pages(struct radeon_cs_parser *p)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
		if (i == ibc->last_page_index) {
			size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
		}
		
		if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       size))
			return -EFAULT;
	}
	return 0;
}

static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
{
	int new_page;
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;
	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;

	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
		if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       PAGE_SIZE)) {
			p->parser_error = -EFAULT;
			return 0;
		}
	}

	if (pg_idx == ibc->last_page_index) {
		size = (ibc->length_dw * 4) % PAGE_SIZE;
		if (size == 0)
			size = PAGE_SIZE;
	}

	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	if (copy1)
		ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));

	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
			       ibc->user_ptr + (pg_idx * PAGE_SIZE),
			       size)) {
		p->parser_error = -EFAULT;
		return 0;
	}

	/* copy to IB for non single case */
	if (!copy1)
		memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);

	ibc->last_copied_page = pg_idx;
	ibc->kpage_idx[new_page] = pg_idx;

	return new_page;
}

u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	u32 pg_idx, pg_offset;
	u32 idx_value = 0;
	int new_page;

	pg_idx = (idx * 4) / PAGE_SIZE;
	pg_offset = (idx * 4) % PAGE_SIZE;

	if (ibc->kpage_idx[0] == pg_idx)
		return ibc->kpage[0][pg_offset/4];
	if (ibc->kpage_idx[1] == pg_idx)
		return ibc->kpage[1][pg_offset/4];

	new_page = radeon_cs_update_pages(p, pg_idx);
	if (new_page < 0) {
		p->parser_error = new_page;
		return 0;
	}

	idx_value = ibc->kpage[new_page][pg_offset/4];
	return idx_value;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Jerome Glisse <glisse@freedesktop.org>
	26	*/
	27	#include "drmP.h"
	28	#include "radeon_drm.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
	32	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	33	struct radeon_cs_packet *pkt);
	34
	35	int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
	36	{
	37	struct drm_device *ddev = p->rdev->ddev;
	38	struct radeon_cs_chunk *chunk;
	39	unsigned i, j;
	40	bool duplicate;
	41
	42	if (p->chunk_relocs_idx == -1) {
	43	return 0;
	44	}
	45	chunk = &p->chunks[p->chunk_relocs_idx];
	46	/* FIXME: we assume that each relocs use 4 dwords */
	47	p->nrelocs = chunk->length_dw / 4;
	48	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	49	if (p->relocs_ptr == NULL) {
	50	return -ENOMEM;
	51	}
	52	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	53	if (p->relocs == NULL) {
	54	return -ENOMEM;
	55	}
	56	for (i = 0; i < p->nrelocs; i++) {
	57	struct drm_radeon_cs_reloc *r;
	58
	59	duplicate = false;
	60	r = (struct drm_radeon_cs_reloc )&chunk->kdata[i4];
16557f1e	61	for (j = 0; j < i; j++) {
771fe6b9 JG	62	if (r->handle == p->relocs[j].handle) {
	63	p->relocs_ptr[i] = &p->relocs[j];
	64	duplicate = true;
	65	break;
	66	}
	67	}
	68	if (!duplicate) {
	69	p->relocs[i].gobj = drm_gem_object_lookup(ddev,
	70	p->filp,
	71	r->handle);
	72	if (p->relocs[i].gobj == NULL) {
	73	DRM_ERROR("gem object lookup failed 0x%x\n",
	74	r->handle);
bf79cb91	75	return -ENOENT;
771fe6b9 JG	76	}
771fe6b9 JG	77	p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9	78	p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679	79	p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9	80	p->relocs[i].lobj.wdomain = r->write_domain;
147666fb TH	81	p->relocs[i].lobj.rdomain = r->read_domains;
147666fb TH	82	p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9 JG	83	p->relocs[i].handle = r->handle;
771fe6b9 JG	84	p->relocs[i].flags = r->flags;
4c788679	85	radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb	86	&p->validated);
93504fce	87
16557f1e CK	88	} else
16557f1e CK	89	p->relocs[i].handle = 0;
771fe6b9	90	}
94429bb6	91	return radeon_bo_list_validate(&p->validated);
771fe6b9 JG	92	}
771fe6b9 JG	93
721604a1 JG	94	static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
	95	{
	96	p->priority = priority;
	97
	98	switch (ring) {
	99	default:
	100	DRM_ERROR("unknown ring id: %d\n", ring);
	101	return -EINVAL;
	102	case RADEON_CS_RING_GFX:
	103	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	104	break;
	105	case RADEON_CS_RING_COMPUTE:
8d5ef7b1 AD	106	if (p->rdev->family >= CHIP_TAHITI) {
	107	if (p->priority > 0)
	108	p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
	109	else
	110	p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
	111	} else
	112	p->ring = RADEON_RING_TYPE_GFX_INDEX;
721604a1 JG	113	break;
	114	}
	115	return 0;
	116	}
	117
220907d9	118	static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
93504fce	119	{
220907d9	120	int i;
93504fce	121
cdac5504	122	for (i = 0; i < p->nrelocs; i++) {
220907d9	123	struct radeon_fence a, b;
133f4cb3	124
cdac5504 CK	125	if (!p->relocs[i].robj \|\| !p->relocs[i].robj->tbo.sync_obj)
	126	continue;
	127
220907d9 CK	128	a = p->relocs[i].robj->tbo.sync_obj;
	129	b = p->ib.sync_to[a->ring];
	130	p->ib.sync_to[a->ring] = radeon_fence_later(a, b);
8f676c4c	131	}
93504fce CK	132	}
93504fce CK	133
9b00147d	134	/* XXX: note that this is called from the legacy UMS CS ioctl as well */
771fe6b9 JG	135	int radeon_cs_parser_init(struct radeon_cs_parser p, void data)
	136	{
	137	struct drm_radeon_cs *cs = data;
	138	uint64_t *chunk_array_ptr;
721604a1 JG	139	unsigned size, i;
	140	u32 ring = RADEON_CS_RING_GFX;
	141	s32 priority = 0;
771fe6b9 JG	142
	143	if (!cs->num_chunks) {
	144	return 0;
	145	}
	146	/* get chunks */
	147	INIT_LIST_HEAD(&p->validated);
	148	p->idx = 0;
f2e39221 JG	149	p->ib.sa_bo = NULL;
	150	p->ib.semaphore = NULL;
	151	p->const_ib.sa_bo = NULL;
	152	p->const_ib.semaphore = NULL;
771fe6b9 JG	153	p->chunk_ib_idx = -1;
771fe6b9 JG	154	p->chunk_relocs_idx = -1;
721604a1	155	p->chunk_flags_idx = -1;
dfcf5f36	156	p->chunk_const_ib_idx = -1;
771fe6b9 JG	157	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	158	if (p->chunks_array == NULL) {
	159	return -ENOMEM;
	160	}
	161	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	162	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
	163	sizeof(uint64_t)*cs->num_chunks)) {
	164	return -EFAULT;
	165	}
721604a1	166	p->cs_flags = 0;
771fe6b9 JG	167	p->nchunks = cs->num_chunks;
	168	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	169	if (p->chunks == NULL) {
	170	return -ENOMEM;
	171	}
	172	for (i = 0; i < p->nchunks; i++) {
	173	struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
	174	struct drm_radeon_cs_chunk user_chunk;
	175	uint32_t __user *cdata;
	176
	177	chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
	178	if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
	179	sizeof(struct drm_radeon_cs_chunk))) {
	180	return -EFAULT;
	181	}
5176fdc4 DA	182	p->chunks[i].length_dw = user_chunk.length_dw;
5176fdc4 DA	183	p->chunks[i].kdata = NULL;
771fe6b9	184	p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4	185
771fe6b9 JG	186	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
	187	p->chunk_relocs_idx = i;
	188	}
	189	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
	190	p->chunk_ib_idx = i;
5176fdc4 DA	191	/* zero length IB isn't useful */
	192	if (p->chunks[i].length_dw == 0)
	193	return -EINVAL;
771fe6b9	194	}
dfcf5f36 AD	195	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
	196	p->chunk_const_ib_idx = i;
	197	/* zero length CONST IB isn't useful */
	198	if (p->chunks[i].length_dw == 0)
	199	return -EINVAL;
	200	}
721604a1 JG	201	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
	202	p->chunk_flags_idx = i;
	203	/* zero length flags aren't useful */
	204	if (p->chunks[i].length_dw == 0)
	205	return -EINVAL;
e70f224c	206	}
5176fdc4	207
771fe6b9	208	p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46	209	p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9	210
513bcb46	211	cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1 JG	212	if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) \|\|
721604a1 JG	213	(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46 DA	214	size = p->chunks[i].length_dw * sizeof(uint32_t);
	215	p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
	216	if (p->chunks[i].kdata == NULL) {
	217	return -ENOMEM;
	218	}
	219	if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
	220	p->chunks[i].user_ptr, size)) {
	221	return -EFAULT;
	222	}
e70f224c	223	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1 JG	224	p->cs_flags = p->chunks[i].kdata[0];
	225	if (p->chunks[i].length_dw > 1)
	226	ring = p->chunks[i].kdata[1];
	227	if (p->chunks[i].length_dw > 2)
	228	priority = (s32)p->chunks[i].kdata[2];
e70f224c	229	}
771fe6b9 JG	230	}
771fe6b9 JG	231	}
721604a1	232
9b00147d AD	233	/* these are KMS only */
	234	if (p->rdev) {
	235	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	236	!p->rdev->vm_manager.enabled) {
	237	DRM_ERROR("VM not active on asic!\n");
	238	return -EINVAL;
	239	}
1b5475db	240
9b00147d AD	241	/* we only support VM on SI+ */
	242	if ((p->rdev->family >= CHIP_TAHITI) &&
	243	((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
	244	DRM_ERROR("VM required on SI+!\n");
	245	return -EINVAL;
	246	}
721604a1	247
9b00147d AD	248	if (radeon_cs_get_ring(p, ring, priority))
	249	return -EINVAL;
	250	}
721604a1 JG	251
	252	/* deal with non-vm */
	253	if ((p->chunk_ib_idx != -1) &&
	254	((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	255	(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
	256	if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
	257	DRM_ERROR("cs IB too big: %d\n",
	258	p->chunks[p->chunk_ib_idx].length_dw);
	259	return -EINVAL;
	260	}
6a7068b4 DA	261	if ((p->rdev->flags & RADEON_IS_AGP)) {
	262	p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	263	p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	264	if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL \|\|
	265	p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
	266	kfree(p->chunks[i].kpage[0]);
	267	kfree(p->chunks[i].kpage[1]);
	268	return -ENOMEM;
	269	}
	270	}
721604a1 JG	271	p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
	272	p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
	273	p->chunks[p->chunk_ib_idx].last_copied_page = -1;
	274	p->chunks[p->chunk_ib_idx].last_page_index =
	275	((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	276	}
	277
771fe6b9 JG	278	return 0;
	279	}
	280
	281	/**
	282	* cs_parser_fini() - clean parser states
	283	* @parser: parser structure holding parsing context.
	284	* @error: error number
	285	*
	286	* If error is set than unvalidate buffer, otherwise just free memory
	287	* used by parsing context.
	288	**/
	289	static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
	290	{
	291	unsigned i;
	292
f2e39221	293	if (!error)
147666fb	294	ttm_eu_fence_buffer_objects(&parser->validated,
f2e39221	295	parser->ib.fence);
147666fb TH	296	else
	297	ttm_eu_backoff_reservation(&parser->validated);
	298
fcbc451b PN	299	if (parser->relocs != NULL) {
	300	for (i = 0; i < parser->nrelocs; i++) {
	301	if (parser->relocs[i].gobj)
	302	drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
	303	}
771fe6b9	304	}
48e113e5	305	kfree(parser->track);
771fe6b9 JG	306	kfree(parser->relocs);
	307	kfree(parser->relocs_ptr);
	308	for (i = 0; i < parser->nchunks; i++) {
	309	kfree(parser->chunks[i].kdata);
6a7068b4 DA	310	if ((parser->rdev->flags & RADEON_IS_AGP)) {
	311	kfree(parser->chunks[i].kpage[0]);
	312	kfree(parser->chunks[i].kpage[1]);
	313	}
771fe6b9 JG	314	}
	315	kfree(parser->chunks);
	316	kfree(parser->chunks_array);
	317	radeon_ib_free(parser->rdev, &parser->ib);
f2e39221	318	radeon_ib_free(parser->rdev, &parser->const_ib);
771fe6b9 JG	319	}
771fe6b9 JG	320
721604a1 JG	321	static int radeon_cs_ib_chunk(struct radeon_device *rdev,
	322	struct radeon_cs_parser *parser)
	323	{
	324	struct radeon_cs_chunk *ib_chunk;
	325	int r;
	326
	327	if (parser->chunk_ib_idx == -1)
	328	return 0;
	329
	330	if (parser->cs_flags & RADEON_CS_USE_VM)
	331	return 0;
	332
	333	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	334	/* Copy the packet into the IB, the parser will read from the
	335	* input memory (cached) and write to the IB (which can be
	336	* uncached).
	337	*/
	338	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	339	ib_chunk->length_dw * 4);
	340	if (r) {
	341	DRM_ERROR("Failed to get ib !\n");
	342	return r;
	343	}
f2e39221	344	parser->ib.length_dw = ib_chunk->length_dw;
eb0c19c5	345	r = radeon_cs_parse(rdev, parser->ring, parser);
721604a1 JG	346	if (r \|\| parser->parser_error) {
	347	DRM_ERROR("Invalid command stream !\n");
	348	return r;
	349	}
	350	r = radeon_cs_finish_pages(parser);
	351	if (r) {
	352	DRM_ERROR("Invalid command stream !\n");
	353	return r;
	354	}
220907d9	355	radeon_cs_sync_rings(parser);
f2e39221 JG	356	parser->ib.vm_id = 0;
f2e39221 JG	357	r = radeon_ib_schedule(rdev, &parser->ib);
721604a1 JG	358	if (r) {
	359	DRM_ERROR("Failed to schedule IB !\n");
	360	}
93bf888c	361	return r;
721604a1 JG	362	}
	363
	364	static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
	365	struct radeon_vm *vm)
	366	{
	367	struct radeon_bo_list *lobj;
	368	struct radeon_bo *bo;
	369	int r;
	370
	371	list_for_each_entry(lobj, &parser->validated, tv.head) {
	372	bo = lobj->bo;
	373	r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
	374	if (r) {
	375	return r;
	376	}
	377	}
	378	return 0;
	379	}
	380
	381	static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
	382	struct radeon_cs_parser *parser)
	383	{
	384	struct radeon_cs_chunk *ib_chunk;
	385	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	386	struct radeon_vm *vm = &fpriv->vm;
	387	int r;
	388
	389	if (parser->chunk_ib_idx == -1)
	390	return 0;
	391
	392	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
	393	return 0;
	394
dfcf5f36 AD	395	if ((rdev->family >= CHIP_TAHITI) &&
	396	(parser->chunk_const_ib_idx != -1)) {
	397	ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
	398	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	399	DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
	400	return -EINVAL;
	401	}
	402	r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
	403	ib_chunk->length_dw * 4);
	404	if (r) {
	405	DRM_ERROR("Failed to get const ib !\n");
	406	return r;
	407	}
f2e39221 JG	408	parser->const_ib.is_const_ib = true;
f2e39221 JG	409	parser->const_ib.length_dw = ib_chunk->length_dw;
dfcf5f36	410	/* Copy the packet into the IB */
f2e39221	411	if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
dfcf5f36 AD	412	ib_chunk->length_dw * 4)) {
	413	return -EFAULT;
	414	}
f2e39221	415	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
dfcf5f36 AD	416	if (r) {
	417	return r;
	418	}
	419	}
	420
721604a1 JG	421	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	422	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	423	DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
	424	return -EINVAL;
	425	}
	426	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	427	ib_chunk->length_dw * 4);
	428	if (r) {
	429	DRM_ERROR("Failed to get ib !\n");
	430	return r;
	431	}
f2e39221	432	parser->ib.length_dw = ib_chunk->length_dw;
721604a1	433	/* Copy the packet into the IB */
f2e39221	434	if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
721604a1 JG	435	ib_chunk->length_dw * 4)) {
	436	return -EFAULT;
	437	}
f2e39221	438	r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
721604a1 JG	439	if (r) {
	440	return r;
	441	}
	442
36ff39c4	443	mutex_lock(&rdev->vm_manager.lock);
721604a1 JG	444	mutex_lock(&vm->mutex);
	445	r = radeon_vm_bind(rdev, vm);
	446	if (r) {
	447	goto out;
	448	}
	449	r = radeon_bo_vm_update_pte(parser, vm);
	450	if (r) {
	451	goto out;
	452	}
220907d9	453	radeon_cs_sync_rings(parser);
dfcf5f36 AD	454
	455	if ((rdev->family >= CHIP_TAHITI) &&
	456	(parser->chunk_const_ib_idx != -1)) {
f2e39221	457	parser->const_ib.vm_id = vm->id;
dfcf5f36 AD	458	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	459	* offset inside the pool bo
	460	*/
f2e39221 JG	461	parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
f2e39221 JG	462	r = radeon_ib_schedule(rdev, &parser->const_ib);
dfcf5f36 AD	463	if (r)
	464	goto out;
	465	}
	466
f2e39221	467	parser->ib.vm_id = vm->id;
721604a1 JG	468	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	469	* offset inside the pool bo
	470	*/
f2e39221 JG	471	parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
	472	parser->ib.is_const_ib = false;
	473	r = radeon_ib_schedule(rdev, &parser->ib);
721604a1 JG	474	out:
	475	if (!r) {
	476	if (vm->fence) {
	477	radeon_fence_unref(&vm->fence);
	478	}
f2e39221	479	vm->fence = radeon_fence_ref(parser->ib.fence);
721604a1	480	}
36ff39c4 CK	481	mutex_unlock(&vm->mutex);
36ff39c4 CK	482	mutex_unlock(&rdev->vm_manager.lock);
721604a1 JG	483	return r;
	484	}
	485
6c6f4783 CK	486	static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
	487	{
	488	if (r == -EDEADLK) {
	489	r = radeon_gpu_reset(rdev);
	490	if (!r)
	491	r = -EAGAIN;
	492	}
	493	return r;
	494	}
	495
771fe6b9 JG	496	int radeon_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	497	{
	498	struct radeon_device *rdev = dev->dev_private;
	499	struct radeon_cs_parser parser;
771fe6b9 JG	500	int r;
771fe6b9 JG	501
dee53e7f	502	down_read(&rdev->exclusive_lock);
6b7746e8	503	if (!rdev->accel_working) {
dee53e7f	504	up_read(&rdev->exclusive_lock);
6b7746e8 JG	505	return -EBUSY;
6b7746e8 JG	506	}
771fe6b9 JG	507	/* initialize parser */
	508	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	509	parser.filp = filp;
	510	parser.rdev = rdev;
c8c15ff1	511	parser.dev = rdev->dev;
428c6e36	512	parser.family = rdev->family;
771fe6b9 JG	513	r = radeon_cs_parser_init(&parser, data);
	514	if (r) {
	515	DRM_ERROR("Failed to initialize parser !\n");
	516	radeon_cs_parser_fini(&parser, r);
dee53e7f	517	up_read(&rdev->exclusive_lock);
6c6f4783	518	r = radeon_cs_handle_lockup(rdev, r);
771fe6b9 JG	519	return r;
771fe6b9 JG	520	}
771fe6b9 JG	521	r = radeon_cs_parser_relocs(&parser);
771fe6b9 JG	522	if (r) {
97f23b3d DA	523	if (r != -ERESTARTSYS)
97f23b3d DA	524	DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9	525	radeon_cs_parser_fini(&parser, r);
dee53e7f	526	up_read(&rdev->exclusive_lock);
6c6f4783	527	r = radeon_cs_handle_lockup(rdev, r);
771fe6b9 JG	528	return r;
771fe6b9 JG	529	}
721604a1	530	r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9	531	if (r) {
721604a1	532	goto out;
771fe6b9	533	}
721604a1	534	r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9	535	if (r) {
721604a1	536	goto out;
771fe6b9	537	}
721604a1	538	out:
771fe6b9	539	radeon_cs_parser_fini(&parser, r);
dee53e7f	540	up_read(&rdev->exclusive_lock);
6c6f4783	541	r = radeon_cs_handle_lockup(rdev, r);
771fe6b9 JG	542	return r;
771fe6b9 JG	543	}
513bcb46 DA	544
	545	int radeon_cs_finish_pages(struct radeon_cs_parser *p)
	546	{
	547	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	548	int i;
	549	int size = PAGE_SIZE;
	550
	551	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
	552	if (i == ibc->last_page_index) {
	553	size = (ibc->length_dw * 4) % PAGE_SIZE;
	554	if (size == 0)
	555	size = PAGE_SIZE;
	556	}
	557
f2e39221	558	if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
513bcb46 DA	559	ibc->user_ptr + (i * PAGE_SIZE),
	560	size))
	561	return -EFAULT;
	562	}
	563	return 0;
	564	}
	565
c4c7f314	566	static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
513bcb46 DA	567	{
513bcb46 DA	568	int new_page;
513bcb46 DA	569	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	570	int i;
	571	int size = PAGE_SIZE;
6a7068b4	572	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
513bcb46	573
c5e617e2	574	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
f2e39221	575	if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
513bcb46 DA	576	ibc->user_ptr + (i * PAGE_SIZE),
	577	PAGE_SIZE)) {
	578	p->parser_error = -EFAULT;
	579	return 0;
	580	}
	581	}
	582
513bcb46 DA	583	if (pg_idx == ibc->last_page_index) {
513bcb46 DA	584	size = (ibc->length_dw * 4) % PAGE_SIZE;
6a7068b4 DA	585	if (size == 0)
6a7068b4 DA	586	size = PAGE_SIZE;
513bcb46 DA	587	}
513bcb46 DA	588
6a7068b4 DA	589	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
6a7068b4 DA	590	if (copy1)
f2e39221	591	ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
6a7068b4	592
513bcb46 DA	593	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
	594	ibc->user_ptr + (pg_idx * PAGE_SIZE),
	595	size)) {
	596	p->parser_error = -EFAULT;
	597	return 0;
	598	}
	599
6a7068b4 DA	600	/* copy to IB for non single case */
6a7068b4 DA	601	if (!copy1)
f2e39221	602	memcpy((void )(p->ib.ptr+(pg_idx(PAGE_SIZE/4))), ibc->kpage[new_page], size);
513bcb46 DA	603
	604	ibc->last_copied_page = pg_idx;
	605	ibc->kpage_idx[new_page] = pg_idx;
	606
	607	return new_page;
	608	}
c4c7f314 DA	609
	610	u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
	611	{
	612	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	613	u32 pg_idx, pg_offset;
	614	u32 idx_value = 0;
	615	int new_page;
	616
	617	pg_idx = (idx * 4) / PAGE_SIZE;
	618	pg_offset = (idx * 4) % PAGE_SIZE;
	619
	620	if (ibc->kpage_idx[0] == pg_idx)
	621	return ibc->kpage[0][pg_offset/4];
	622	if (ibc->kpage_idx[1] == pg_idx)
	623	return ibc->kpage[1][pg_offset/4];
	624
	625	new_page = radeon_cs_update_pages(p, pg_idx);
	626	if (new_page < 0) {
	627	p->parser_error = new_page;
	628	return 0;
	629	}
	630
	631	idx_value = ibc->kpage[new_page][pg_offset/4];
	632	return idx_value;
	633	}