[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_cs.c

/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
{
	struct drm_device *ddev = p->rdev->ddev;
	struct radeon_cs_chunk *chunk;
	unsigned i, j;
	bool duplicate;

	if (p->chunk_relocs_idx == -1) {
		return 0;
	}
	chunk = &p->chunks[p->chunk_relocs_idx];
	/* FIXME: we assume that each relocs use 4 dwords */
	p->nrelocs = chunk->length_dw / 4;
	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	if (p->relocs_ptr == NULL) {
		return -ENOMEM;
	}
	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	if (p->relocs == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nrelocs; i++) {
		struct drm_radeon_cs_reloc *r;

		duplicate = false;
		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
		for (j = 0; j < i; j++) {
			if (r->handle == p->relocs[j].handle) {
				p->relocs_ptr[i] = &p->relocs[j];
				duplicate = true;
				break;
			}
		}
		if (!duplicate) {
			p->relocs[i].gobj = drm_gem_object_lookup(ddev,
								  p->filp,
								  r->handle);
			if (p->relocs[i].gobj == NULL) {
				DRM_ERROR("gem object lookup failed 0x%x\n",
					  r->handle);
				return -ENOENT;
			}
			p->relocs_ptr[i] = &p->relocs[i];
			p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
			p->relocs[i].lobj.bo = p->relocs[i].robj;
			p->relocs[i].lobj.wdomain = r->write_domain;
			p->relocs[i].lobj.rdomain = r->read_domains;
			p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
			p->relocs[i].handle = r->handle;
			p->relocs[i].flags = r->flags;
			radeon_bo_list_add_object(&p->relocs[i].lobj,
						  &p->validated);

		} else
			p->relocs[i].handle = 0;
	}
	return radeon_bo_list_validate(&p->validated);
}

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
{
	p->priority = priority;

	switch (ring) {
	default:
		DRM_ERROR("unknown ring id: %d\n", ring);
		return -EINVAL;
	case RADEON_CS_RING_GFX:
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	case RADEON_CS_RING_COMPUTE:
		if (p->rdev->family >= CHIP_TAHITI) {
			if (p->priority > 0)
				p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
			else
				p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
		} else
			p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	}
	return 0;
}

static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
{
	bool sync_to_ring[RADEON_NUM_RINGS] = { };
	bool need_sync = false;
	int i, r;

	for (i = 0; i < p->nrelocs; i++) {
		if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
			continue;

		if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
			struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
			if (fence->ring != p->ring && !radeon_fence_signaled(fence)) {
				sync_to_ring[fence->ring] = true;
				need_sync = true;
			}
		}
	}

	if (!need_sync) {
		return 0;
	}

	r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
	if (r) {
		return r;
	}

	return radeon_semaphore_sync_rings(p->rdev, p->ib->fence->semaphore,
					   sync_to_ring, p->ring);
}

int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
{
	struct drm_radeon_cs *cs = data;
	uint64_t *chunk_array_ptr;
	unsigned size, i;
	u32 ring = RADEON_CS_RING_GFX;
	s32 priority = 0;

	if (!cs->num_chunks) {
		return 0;
	}
	/* get chunks */
	INIT_LIST_HEAD(&p->validated);
	p->idx = 0;
	p->chunk_ib_idx = -1;
	p->chunk_relocs_idx = -1;
	p->chunk_flags_idx = -1;
	p->chunk_const_ib_idx = -1;
	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (p->chunks_array == NULL) {
		return -ENOMEM;
	}
	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
			       sizeof(uint64_t)*cs->num_chunks)) {
		return -EFAULT;
	}
	p->cs_flags = 0;
	p->nchunks = cs->num_chunks;
	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	if (p->chunks == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nchunks; i++) {
		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
		struct drm_radeon_cs_chunk user_chunk;
		uint32_t __user *cdata;

		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
		if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
				       sizeof(struct drm_radeon_cs_chunk))) {
			return -EFAULT;
		}
		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].kdata = NULL;
		p->chunks[i].chunk_id = user_chunk.chunk_id;

		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
			p->chunk_relocs_idx = i;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
			p->chunk_ib_idx = i;
			/* zero length IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
			p->chunk_const_ib_idx = i;
			/* zero length CONST IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
			p->chunk_flags_idx = i;
			/* zero length flags aren't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}

		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
		if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
		    (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
			size = p->chunks[i].length_dw * sizeof(uint32_t);
			p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
			if (p->chunks[i].kdata == NULL) {
				return -ENOMEM;
			}
			if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
					       p->chunks[i].user_ptr, size)) {
				return -EFAULT;
			}
			if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
				p->cs_flags = p->chunks[i].kdata[0];
				if (p->chunks[i].length_dw > 1)
					ring = p->chunks[i].kdata[1];
				if (p->chunks[i].length_dw > 2)
					priority = (s32)p->chunks[i].kdata[2];
			}
		}
	}

	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	    !p->rdev->vm_manager.enabled) {
		DRM_ERROR("VM not active on asic!\n");
		return -EINVAL;
	}

	/* we only support VM on SI+ */
	if ((p->rdev->family >= CHIP_TAHITI) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
		DRM_ERROR("VM required on SI+!\n");
		return -EINVAL;
	}

	if (radeon_cs_get_ring(p, ring, priority))
		return -EINVAL;


	/* deal with non-vm */
	if ((p->chunk_ib_idx != -1) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	    (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
		if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
			DRM_ERROR("cs IB too big: %d\n",
				  p->chunks[p->chunk_ib_idx].length_dw);
			return -EINVAL;
		}
		if ((p->rdev->flags & RADEON_IS_AGP)) {
			p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
			    p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
				kfree(p->chunks[i].kpage[0]);
				kfree(p->chunks[i].kpage[1]);
				return -ENOMEM;
			}
		}
		p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
		p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
		p->chunks[p->chunk_ib_idx].last_copied_page = -1;
		p->chunks[p->chunk_ib_idx].last_page_index =
			((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	}

	return 0;
}

/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
{
	unsigned i;


	if (!error && parser->ib)
		ttm_eu_fence_buffer_objects(&parser->validated,
					    parser->ib->fence);
	else
		ttm_eu_backoff_reservation(&parser->validated);

	if (parser->relocs != NULL) {
		for (i = 0; i < parser->nrelocs; i++) {
			if (parser->relocs[i].gobj)
				drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
		}
	}
	kfree(parser->track);
	kfree(parser->relocs);
	kfree(parser->relocs_ptr);
	for (i = 0; i < parser->nchunks; i++) {
		kfree(parser->chunks[i].kdata);
		if ((parser->rdev->flags & RADEON_IS_AGP)) {
			kfree(parser->chunks[i].kpage[0]);
			kfree(parser->chunks[i].kpage[1]);
		}
	}
	kfree(parser->chunks);
	kfree(parser->chunks_array);
	radeon_ib_free(parser->rdev, &parser->ib);
}

static int radeon_cs_ib_chunk(struct radeon_device *rdev,
			      struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if (parser->cs_flags & RADEON_CS_USE_VM)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	/* Copy the packet into the IB, the parser will read from the
	 * input memory (cached) and write to the IB (which can be
	 * uncached).
	 */
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	r = radeon_cs_parse(rdev, parser->ring, parser);
	if (r || parser->parser_error) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_finish_pages(parser);
	if (r) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}
	parser->ib->vm_id = 0;
	r = radeon_ib_schedule(rdev, parser->ib);
	if (r) {
		DRM_ERROR("Failed to schedule IB !\n");
	}
	return 0;
}

static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
				   struct radeon_vm *vm)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	list_for_each_entry(lobj, &parser->validated, tv.head) {
		bo = lobj->bo;
		r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
		if (r) {
			return r;
		}
	}
	return 0;
}

static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
				 struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
		return 0;

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
		if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
			DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
			return -EINVAL;
		}
		r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
				   ib_chunk->length_dw * 4);
		if (r) {
			DRM_ERROR("Failed to get const ib !\n");
			return r;
		}
		parser->const_ib->is_const_ib = true;
		parser->const_ib->length_dw = ib_chunk->length_dw;
		/* Copy the packet into the IB */
		if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
				       ib_chunk->length_dw * 4)) {
			return -EFAULT;
		}
		r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
		if (r) {
			return r;
		}
	}

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
		DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
		return -EINVAL;
	}
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	/* Copy the packet into the IB */
	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
			       ib_chunk->length_dw * 4)) {
		return -EFAULT;
	}
	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	if (r) {
		return r;
	}

	mutex_lock(&vm->mutex);
	r = radeon_vm_bind(rdev, vm);
	if (r) {
		goto out;
	}
	r = radeon_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		parser->const_ib->vm_id = vm->id;
		/* ib pool is bind at 0 in virtual address space to gpu_addr is the
		 * offset inside the pool bo
		 */
		parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
		r = radeon_ib_schedule(rdev, parser->const_ib);
		if (r)
			goto out;
	}

	parser->ib->vm_id = vm->id;
	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	 * offset inside the pool bo
	 */
	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
	parser->ib->is_const_ib = false;
	r = radeon_ib_schedule(rdev, parser->ib);
out:
	if (!r) {
		if (vm->fence) {
			radeon_fence_unref(&vm->fence);
		}
		vm->fence = radeon_fence_ref(parser->ib->fence);
	}
	mutex_unlock(&fpriv->vm.mutex);
	return r;
}

int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_cs_parser parser;
	int r;

	radeon_mutex_lock(&rdev->cs_mutex);
	if (!rdev->accel_working) {
		radeon_mutex_unlock(&rdev->cs_mutex);
		return -EBUSY;
	}
	/* initialize parser */
	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	parser.filp = filp;
	parser.rdev = rdev;
	parser.dev = rdev->dev;
	parser.family = rdev->family;
	r = radeon_cs_parser_init(&parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_parser_relocs(&parser);
	if (r) {
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to parse relocation %d!\n", r);
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_ib_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
	r = radeon_cs_ib_vm_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
out:
	radeon_cs_parser_fini(&parser, r);
	radeon_mutex_unlock(&rdev->cs_mutex);
	return r;
}

int radeon_cs_finish_pages(struct radeon_cs_parser *p)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
		if (i == ibc->last_page_index) {
			size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
		}
		
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       size))
			return -EFAULT;
	}
	return 0;
}

int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
{
	int new_page;
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;
	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;

	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       PAGE_SIZE)) {
			p->parser_error = -EFAULT;
			return 0;
		}
	}

	if (pg_idx == ibc->last_page_index) {
		size = (ibc->length_dw * 4) % PAGE_SIZE;
		if (size == 0)
			size = PAGE_SIZE;
	}

	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	if (copy1)
		ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));

	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
			       ibc->user_ptr + (pg_idx * PAGE_SIZE),
			       size)) {
		p->parser_error = -EFAULT;
		return 0;
	}

	/* copy to IB for non single case */
	if (!copy1)
		memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);

	ibc->last_copied_page = pg_idx;
	ibc->kpage_idx[new_page] = pg_idx;

	return new_page;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Jerome Glisse <glisse@freedesktop.org>
	26	*/
	27	#include "drmP.h"
	28	#include "radeon_drm.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
	32	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	33	struct radeon_cs_packet *pkt);
	34
	35	int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
	36	{
	37	struct drm_device *ddev = p->rdev->ddev;
	38	struct radeon_cs_chunk *chunk;
	39	unsigned i, j;
	40	bool duplicate;
	41
	42	if (p->chunk_relocs_idx == -1) {
	43	return 0;
	44	}
	45	chunk = &p->chunks[p->chunk_relocs_idx];
	46	/* FIXME: we assume that each relocs use 4 dwords */
	47	p->nrelocs = chunk->length_dw / 4;
	48	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	49	if (p->relocs_ptr == NULL) {
	50	return -ENOMEM;
	51	}
	52	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	53	if (p->relocs == NULL) {
	54	return -ENOMEM;
	55	}
	56	for (i = 0; i < p->nrelocs; i++) {
	57	struct drm_radeon_cs_reloc *r;
	58
	59	duplicate = false;
	60	r = (struct drm_radeon_cs_reloc )&chunk->kdata[i4];
16557f1e	61	for (j = 0; j < i; j++) {
771fe6b9 JG	62	if (r->handle == p->relocs[j].handle) {
	63	p->relocs_ptr[i] = &p->relocs[j];
	64	duplicate = true;
	65	break;
	66	}
	67	}
	68	if (!duplicate) {
	69	p->relocs[i].gobj = drm_gem_object_lookup(ddev,
	70	p->filp,
	71	r->handle);
	72	if (p->relocs[i].gobj == NULL) {
	73	DRM_ERROR("gem object lookup failed 0x%x\n",
	74	r->handle);
bf79cb91	75	return -ENOENT;
771fe6b9 JG	76	}
771fe6b9 JG	77	p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9	78	p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679	79	p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9	80	p->relocs[i].lobj.wdomain = r->write_domain;
147666fb TH	81	p->relocs[i].lobj.rdomain = r->read_domains;
147666fb TH	82	p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9 JG	83	p->relocs[i].handle = r->handle;
771fe6b9 JG	84	p->relocs[i].flags = r->flags;
4c788679	85	radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb	86	&p->validated);
93504fce	87
16557f1e CK	88	} else
16557f1e CK	89	p->relocs[i].handle = 0;
771fe6b9	90	}
94429bb6	91	return radeon_bo_list_validate(&p->validated);
771fe6b9 JG	92	}
771fe6b9 JG	93
721604a1 JG	94	static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
	95	{
	96	p->priority = priority;
	97
	98	switch (ring) {
	99	default:
	100	DRM_ERROR("unknown ring id: %d\n", ring);
	101	return -EINVAL;
	102	case RADEON_CS_RING_GFX:
	103	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	104	break;
	105	case RADEON_CS_RING_COMPUTE:
8d5ef7b1 AD	106	if (p->rdev->family >= CHIP_TAHITI) {
	107	if (p->priority > 0)
	108	p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
	109	else
	110	p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
	111	} else
	112	p->ring = RADEON_RING_TYPE_GFX_INDEX;
721604a1 JG	113	break;
	114	}
	115	return 0;
	116	}
	117
93504fce CK	118	static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
93504fce CK	119	{
cdac5504	120	bool sync_to_ring[RADEON_NUM_RINGS] = { };
8f676c4c	121	bool need_sync = false;
93504fce CK	122	int i, r;
93504fce CK	123
cdac5504 CK	124	for (i = 0; i < p->nrelocs; i++) {
	125	if (!p->relocs[i].robj \|\| !p->relocs[i].robj->tbo.sync_obj)
	126	continue;
	127
	128	if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
	129	struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
8f676c4c	130	if (fence->ring != p->ring && !radeon_fence_signaled(fence)) {
cdac5504	131	sync_to_ring[fence->ring] = true;
8f676c4c	132	need_sync = true;
cdac5504 CK	133	}
	134	}
	135	}
	136
8f676c4c CK	137	if (!need_sync) {
	138	return 0;
	139	}
93504fce	140
8f676c4c CK	141	r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
	142	if (r) {
	143	return r;
93504fce	144	}
8f676c4c CK	145
	146	return radeon_semaphore_sync_rings(p->rdev, p->ib->fence->semaphore,
	147	sync_to_ring, p->ring);
93504fce CK	148	}
93504fce CK	149
771fe6b9 JG	150	int radeon_cs_parser_init(struct radeon_cs_parser p, void data)
	151	{
	152	struct drm_radeon_cs *cs = data;
	153	uint64_t *chunk_array_ptr;
721604a1 JG	154	unsigned size, i;
	155	u32 ring = RADEON_CS_RING_GFX;
	156	s32 priority = 0;
771fe6b9 JG	157
	158	if (!cs->num_chunks) {
	159	return 0;
	160	}
	161	/* get chunks */
	162	INIT_LIST_HEAD(&p->validated);
	163	p->idx = 0;
	164	p->chunk_ib_idx = -1;
	165	p->chunk_relocs_idx = -1;
721604a1	166	p->chunk_flags_idx = -1;
dfcf5f36	167	p->chunk_const_ib_idx = -1;
771fe6b9 JG	168	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	169	if (p->chunks_array == NULL) {
	170	return -ENOMEM;
	171	}
	172	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	173	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
	174	sizeof(uint64_t)*cs->num_chunks)) {
	175	return -EFAULT;
	176	}
721604a1	177	p->cs_flags = 0;
771fe6b9 JG	178	p->nchunks = cs->num_chunks;
	179	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	180	if (p->chunks == NULL) {
	181	return -ENOMEM;
	182	}
	183	for (i = 0; i < p->nchunks; i++) {
	184	struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
	185	struct drm_radeon_cs_chunk user_chunk;
	186	uint32_t __user *cdata;
	187
	188	chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
	189	if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
	190	sizeof(struct drm_radeon_cs_chunk))) {
	191	return -EFAULT;
	192	}
5176fdc4 DA	193	p->chunks[i].length_dw = user_chunk.length_dw;
5176fdc4 DA	194	p->chunks[i].kdata = NULL;
771fe6b9	195	p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4	196
771fe6b9 JG	197	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
	198	p->chunk_relocs_idx = i;
	199	}
	200	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
	201	p->chunk_ib_idx = i;
5176fdc4 DA	202	/* zero length IB isn't useful */
	203	if (p->chunks[i].length_dw == 0)
	204	return -EINVAL;
771fe6b9	205	}
dfcf5f36 AD	206	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
	207	p->chunk_const_ib_idx = i;
	208	/* zero length CONST IB isn't useful */
	209	if (p->chunks[i].length_dw == 0)
	210	return -EINVAL;
	211	}
721604a1 JG	212	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
	213	p->chunk_flags_idx = i;
	214	/* zero length flags aren't useful */
	215	if (p->chunks[i].length_dw == 0)
	216	return -EINVAL;
e70f224c	217	}
5176fdc4	218
771fe6b9	219	p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46	220	p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9	221
513bcb46	222	cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1 JG	223	if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) \|\|
721604a1 JG	224	(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46 DA	225	size = p->chunks[i].length_dw * sizeof(uint32_t);
	226	p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
	227	if (p->chunks[i].kdata == NULL) {
	228	return -ENOMEM;
	229	}
	230	if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
	231	p->chunks[i].user_ptr, size)) {
	232	return -EFAULT;
	233	}
e70f224c	234	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1 JG	235	p->cs_flags = p->chunks[i].kdata[0];
	236	if (p->chunks[i].length_dw > 1)
	237	ring = p->chunks[i].kdata[1];
	238	if (p->chunks[i].length_dw > 2)
	239	priority = (s32)p->chunks[i].kdata[2];
e70f224c	240	}
771fe6b9 JG	241	}
771fe6b9 JG	242	}
721604a1 JG	243
721604a1 JG	244	if ((p->cs_flags & RADEON_CS_USE_VM) &&
67e915e4 AD	245	!p->rdev->vm_manager.enabled) {
67e915e4 AD	246	DRM_ERROR("VM not active on asic!\n");
771fe6b9 JG	247	return -EINVAL;
771fe6b9 JG	248	}
e70f224c	249
1b5475db AD	250	/* we only support VM on SI+ */
	251	if ((p->rdev->family >= CHIP_TAHITI) &&
	252	((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
	253	DRM_ERROR("VM required on SI+!\n");
	254	return -EINVAL;
	255	}
	256
f48bb04a	257	if (radeon_cs_get_ring(p, ring, priority))
721604a1	258	return -EINVAL;
721604a1 JG	259
	260
	261	/* deal with non-vm */
	262	if ((p->chunk_ib_idx != -1) &&
	263	((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	264	(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
	265	if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
	266	DRM_ERROR("cs IB too big: %d\n",
	267	p->chunks[p->chunk_ib_idx].length_dw);
	268	return -EINVAL;
	269	}
6a7068b4 DA	270	if ((p->rdev->flags & RADEON_IS_AGP)) {
	271	p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	272	p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	273	if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL \|\|
	274	p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
	275	kfree(p->chunks[i].kpage[0]);
	276	kfree(p->chunks[i].kpage[1]);
	277	return -ENOMEM;
	278	}
	279	}
721604a1 JG	280	p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
	281	p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
	282	p->chunks[p->chunk_ib_idx].last_copied_page = -1;
	283	p->chunks[p->chunk_ib_idx].last_page_index =
	284	((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	285	}
	286
771fe6b9 JG	287	return 0;
	288	}
	289
	290	/**
	291	* cs_parser_fini() - clean parser states
	292	* @parser: parser structure holding parsing context.
	293	* @error: error number
	294	*
	295	* If error is set than unvalidate buffer, otherwise just free memory
	296	* used by parsing context.
	297	**/
	298	static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
	299	{
	300	unsigned i;
	301
147666fb TH	302
	303	if (!error && parser->ib)
	304	ttm_eu_fence_buffer_objects(&parser->validated,
	305	parser->ib->fence);
	306	else
	307	ttm_eu_backoff_reservation(&parser->validated);
	308
fcbc451b PN	309	if (parser->relocs != NULL) {
	310	for (i = 0; i < parser->nrelocs; i++) {
	311	if (parser->relocs[i].gobj)
	312	drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
	313	}
771fe6b9	314	}
48e113e5	315	kfree(parser->track);
771fe6b9 JG	316	kfree(parser->relocs);
	317	kfree(parser->relocs_ptr);
	318	for (i = 0; i < parser->nchunks; i++) {
	319	kfree(parser->chunks[i].kdata);
6a7068b4 DA	320	if ((parser->rdev->flags & RADEON_IS_AGP)) {
	321	kfree(parser->chunks[i].kpage[0]);
	322	kfree(parser->chunks[i].kpage[1]);
	323	}
771fe6b9 JG	324	}
	325	kfree(parser->chunks);
	326	kfree(parser->chunks_array);
	327	radeon_ib_free(parser->rdev, &parser->ib);
	328	}
	329
721604a1 JG	330	static int radeon_cs_ib_chunk(struct radeon_device *rdev,
	331	struct radeon_cs_parser *parser)
	332	{
	333	struct radeon_cs_chunk *ib_chunk;
	334	int r;
	335
	336	if (parser->chunk_ib_idx == -1)
	337	return 0;
	338
	339	if (parser->cs_flags & RADEON_CS_USE_VM)
	340	return 0;
	341
	342	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	343	/* Copy the packet into the IB, the parser will read from the
	344	* input memory (cached) and write to the IB (which can be
	345	* uncached).
	346	*/
	347	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	348	ib_chunk->length_dw * 4);
	349	if (r) {
	350	DRM_ERROR("Failed to get ib !\n");
	351	return r;
	352	}
	353	parser->ib->length_dw = ib_chunk->length_dw;
eb0c19c5	354	r = radeon_cs_parse(rdev, parser->ring, parser);
721604a1 JG	355	if (r \|\| parser->parser_error) {
	356	DRM_ERROR("Invalid command stream !\n");
	357	return r;
	358	}
	359	r = radeon_cs_finish_pages(parser);
	360	if (r) {
	361	DRM_ERROR("Invalid command stream !\n");
	362	return r;
	363	}
93504fce CK	364	r = radeon_cs_sync_rings(parser);
	365	if (r) {
	366	DRM_ERROR("Failed to synchronize rings !\n");
	367	}
721604a1 JG	368	parser->ib->vm_id = 0;
	369	r = radeon_ib_schedule(rdev, parser->ib);
	370	if (r) {
	371	DRM_ERROR("Failed to schedule IB !\n");
	372	}
	373	return 0;
	374	}
	375
	376	static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
	377	struct radeon_vm *vm)
	378	{
	379	struct radeon_bo_list *lobj;
	380	struct radeon_bo *bo;
	381	int r;
	382
	383	list_for_each_entry(lobj, &parser->validated, tv.head) {
	384	bo = lobj->bo;
	385	r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
	386	if (r) {
	387	return r;
	388	}
	389	}
	390	return 0;
	391	}
	392
	393	static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
	394	struct radeon_cs_parser *parser)
	395	{
	396	struct radeon_cs_chunk *ib_chunk;
	397	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	398	struct radeon_vm *vm = &fpriv->vm;
	399	int r;
	400
	401	if (parser->chunk_ib_idx == -1)
	402	return 0;
	403
	404	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
	405	return 0;
	406
dfcf5f36 AD	407	if ((rdev->family >= CHIP_TAHITI) &&
	408	(parser->chunk_const_ib_idx != -1)) {
	409	ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
	410	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	411	DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
	412	return -EINVAL;
	413	}
	414	r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
	415	ib_chunk->length_dw * 4);
	416	if (r) {
	417	DRM_ERROR("Failed to get const ib !\n");
	418	return r;
	419	}
	420	parser->const_ib->is_const_ib = true;
	421	parser->const_ib->length_dw = ib_chunk->length_dw;
	422	/* Copy the packet into the IB */
	423	if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
	424	ib_chunk->length_dw * 4)) {
	425	return -EFAULT;
	426	}
	427	r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
	428	if (r) {
	429	return r;
	430	}
	431	}
	432
721604a1 JG	433	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	434	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	435	DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
	436	return -EINVAL;
	437	}
	438	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	439	ib_chunk->length_dw * 4);
	440	if (r) {
	441	DRM_ERROR("Failed to get ib !\n");
	442	return r;
	443	}
	444	parser->ib->length_dw = ib_chunk->length_dw;
	445	/* Copy the packet into the IB */
	446	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
	447	ib_chunk->length_dw * 4)) {
	448	return -EFAULT;
	449	}
	450	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	451	if (r) {
	452	return r;
	453	}
	454
	455	mutex_lock(&vm->mutex);
	456	r = radeon_vm_bind(rdev, vm);
	457	if (r) {
	458	goto out;
	459	}
	460	r = radeon_bo_vm_update_pte(parser, vm);
	461	if (r) {
	462	goto out;
	463	}
93504fce CK	464	r = radeon_cs_sync_rings(parser);
	465	if (r) {
	466	DRM_ERROR("Failed to synchronize rings !\n");
	467	}
dfcf5f36 AD	468
	469	if ((rdev->family >= CHIP_TAHITI) &&
	470	(parser->chunk_const_ib_idx != -1)) {
	471	parser->const_ib->vm_id = vm->id;
	472	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	473	* offset inside the pool bo
	474	*/
	475	parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
	476	r = radeon_ib_schedule(rdev, parser->const_ib);
	477	if (r)
	478	goto out;
	479	}
	480
721604a1 JG	481	parser->ib->vm_id = vm->id;
	482	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	483	* offset inside the pool bo
	484	*/
	485	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
dfcf5f36	486	parser->ib->is_const_ib = false;
721604a1 JG	487	r = radeon_ib_schedule(rdev, parser->ib);
	488	out:
	489	if (!r) {
	490	if (vm->fence) {
	491	radeon_fence_unref(&vm->fence);
	492	}
	493	vm->fence = radeon_fence_ref(parser->ib->fence);
	494	}
	495	mutex_unlock(&fpriv->vm.mutex);
	496	return r;
	497	}
	498
771fe6b9 JG	499	int radeon_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	500	{
	501	struct radeon_device *rdev = dev->dev_private;
	502	struct radeon_cs_parser parser;
771fe6b9 JG	503	int r;
771fe6b9 JG	504
7a1619b9	505	radeon_mutex_lock(&rdev->cs_mutex);
6b7746e8 JG	506	if (!rdev->accel_working) {
	507	radeon_mutex_unlock(&rdev->cs_mutex);
	508	return -EBUSY;
	509	}
771fe6b9 JG	510	/* initialize parser */
	511	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	512	parser.filp = filp;
	513	parser.rdev = rdev;
c8c15ff1	514	parser.dev = rdev->dev;
428c6e36	515	parser.family = rdev->family;
771fe6b9 JG	516	r = radeon_cs_parser_init(&parser, data);
	517	if (r) {
	518	DRM_ERROR("Failed to initialize parser !\n");
	519	radeon_cs_parser_fini(&parser, r);
7a1619b9	520	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	521	return r;
771fe6b9 JG	522	}
771fe6b9 JG	523	r = radeon_cs_parser_relocs(&parser);
771fe6b9 JG	524	if (r) {
97f23b3d DA	525	if (r != -ERESTARTSYS)
97f23b3d DA	526	DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9	527	radeon_cs_parser_fini(&parser, r);
7a1619b9	528	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	529	return r;
771fe6b9 JG	530	}
721604a1	531	r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9	532	if (r) {
721604a1	533	goto out;
771fe6b9	534	}
721604a1	535	r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9	536	if (r) {
721604a1	537	goto out;
771fe6b9	538	}
721604a1	539	out:
771fe6b9	540	radeon_cs_parser_fini(&parser, r);
7a1619b9	541	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	542	return r;
771fe6b9 JG	543	}
513bcb46 DA	544
	545	int radeon_cs_finish_pages(struct radeon_cs_parser *p)
	546	{
	547	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	548	int i;
	549	int size = PAGE_SIZE;
	550
	551	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
	552	if (i == ibc->last_page_index) {
	553	size = (ibc->length_dw * 4) % PAGE_SIZE;
	554	if (size == 0)
	555	size = PAGE_SIZE;
	556	}
	557
	558	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	559	ibc->user_ptr + (i * PAGE_SIZE),
	560	size))
	561	return -EFAULT;
	562	}
	563	return 0;
	564	}
	565
	566	int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
	567	{
	568	int new_page;
513bcb46 DA	569	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	570	int i;
	571	int size = PAGE_SIZE;
6a7068b4	572	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
513bcb46	573
c5e617e2	574	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
513bcb46 DA	575	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	576	ibc->user_ptr + (i * PAGE_SIZE),
	577	PAGE_SIZE)) {
	578	p->parser_error = -EFAULT;
	579	return 0;
	580	}
	581	}
	582
513bcb46 DA	583	if (pg_idx == ibc->last_page_index) {
513bcb46 DA	584	size = (ibc->length_dw * 4) % PAGE_SIZE;
6a7068b4 DA	585	if (size == 0)
6a7068b4 DA	586	size = PAGE_SIZE;
513bcb46 DA	587	}
513bcb46 DA	588
6a7068b4 DA	589	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	590	if (copy1)
	591	ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));
	592
513bcb46 DA	593	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
	594	ibc->user_ptr + (pg_idx * PAGE_SIZE),
	595	size)) {
	596	p->parser_error = -EFAULT;
	597	return 0;
	598	}
	599
6a7068b4 DA	600	/* copy to IB for non single case */
	601	if (!copy1)
	602	memcpy((void )(p->ib->ptr+(pg_idx(PAGE_SIZE/4))), ibc->kpage[new_page], size);
513bcb46 DA	603
	604	ibc->last_copied_page = pg_idx;
	605	ibc->kpage_idx[new_page] = pg_idx;
	606
	607	return new_page;
	608	}