drm/radeon/kms: no need to align IB like this
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_cs.c
CommitLineData
771fe6b9
JG
1/*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon_reg.h"
30#include "radeon.h"
31
32void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
34
35int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
36{
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
39 unsigned i, j;
40 bool duplicate;
41
42 if (p->chunk_relocs_idx == -1) {
43 return 0;
44 }
45 chunk = &p->chunks[p->chunk_relocs_idx];
46 /* FIXME: we assume that each relocs use 4 dwords */
47 p->nrelocs = chunk->length_dw / 4;
48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
49 if (p->relocs_ptr == NULL) {
50 return -ENOMEM;
51 }
52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
53 if (p->relocs == NULL) {
54 return -ENOMEM;
55 }
56 for (i = 0; i < p->nrelocs; i++) {
57 struct drm_radeon_cs_reloc *r;
58
59 duplicate = false;
60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
16557f1e 61 for (j = 0; j < i; j++) {
771fe6b9
JG
62 if (r->handle == p->relocs[j].handle) {
63 p->relocs_ptr[i] = &p->relocs[j];
64 duplicate = true;
65 break;
66 }
67 }
68 if (!duplicate) {
69 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
70 p->filp,
71 r->handle);
72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n",
74 r->handle);
bf79cb91 75 return -ENOENT;
771fe6b9
JG
76 }
77 p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9 78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679 79 p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9 80 p->relocs[i].lobj.wdomain = r->write_domain;
147666fb
TH
81 p->relocs[i].lobj.rdomain = r->read_domains;
82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9
JG
83 p->relocs[i].handle = r->handle;
84 p->relocs[i].flags = r->flags;
4c788679 85 radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb 86 &p->validated);
93504fce 87
16557f1e
CK
88 } else
89 p->relocs[i].handle = 0;
771fe6b9 90 }
94429bb6 91 return radeon_bo_list_validate(&p->validated);
771fe6b9
JG
92}
93
721604a1
JG
94static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
95{
96 p->priority = priority;
97
98 switch (ring) {
99 default:
100 DRM_ERROR("unknown ring id: %d\n", ring);
101 return -EINVAL;
102 case RADEON_CS_RING_GFX:
103 p->ring = RADEON_RING_TYPE_GFX_INDEX;
104 break;
105 case RADEON_CS_RING_COMPUTE:
106 /* for now */
107 p->ring = RADEON_RING_TYPE_GFX_INDEX;
108 break;
109 }
110 return 0;
111}
112
93504fce
CK
113static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
114{
cdac5504 115 bool sync_to_ring[RADEON_NUM_RINGS] = { };
93504fce
CK
116 int i, r;
117
cdac5504
CK
118 for (i = 0; i < p->nrelocs; i++) {
119 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
120 continue;
121
122 if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
123 struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
124 if (!radeon_fence_signaled(fence)) {
125 sync_to_ring[fence->ring] = true;
126 }
127 }
128 }
129
93504fce
CK
130 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
131 /* no need to sync to our own or unused rings */
cdac5504 132 if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
93504fce
CK
133 continue;
134
135 if (!p->ib->fence->semaphore) {
136 r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
137 if (r)
138 return r;
139 }
140
141 r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
142 if (r)
143 return r;
144 radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
145 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
146
147 r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
148 if (r)
149 return r;
150 radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
151 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
152 }
153 return 0;
154}
155
771fe6b9
JG
156int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
157{
158 struct drm_radeon_cs *cs = data;
159 uint64_t *chunk_array_ptr;
721604a1
JG
160 unsigned size, i;
161 u32 ring = RADEON_CS_RING_GFX;
162 s32 priority = 0;
771fe6b9
JG
163
164 if (!cs->num_chunks) {
165 return 0;
166 }
167 /* get chunks */
168 INIT_LIST_HEAD(&p->validated);
169 p->idx = 0;
170 p->chunk_ib_idx = -1;
171 p->chunk_relocs_idx = -1;
721604a1 172 p->chunk_flags_idx = -1;
771fe6b9
JG
173 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
174 if (p->chunks_array == NULL) {
175 return -ENOMEM;
176 }
177 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
178 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
179 sizeof(uint64_t)*cs->num_chunks)) {
180 return -EFAULT;
181 }
721604a1 182 p->cs_flags = 0;
771fe6b9
JG
183 p->nchunks = cs->num_chunks;
184 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
185 if (p->chunks == NULL) {
186 return -ENOMEM;
187 }
188 for (i = 0; i < p->nchunks; i++) {
189 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
190 struct drm_radeon_cs_chunk user_chunk;
191 uint32_t __user *cdata;
192
193 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
194 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
195 sizeof(struct drm_radeon_cs_chunk))) {
196 return -EFAULT;
197 }
5176fdc4
DA
198 p->chunks[i].length_dw = user_chunk.length_dw;
199 p->chunks[i].kdata = NULL;
771fe6b9 200 p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4 201
771fe6b9
JG
202 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
203 p->chunk_relocs_idx = i;
204 }
205 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
206 p->chunk_ib_idx = i;
5176fdc4
DA
207 /* zero length IB isn't useful */
208 if (p->chunks[i].length_dw == 0)
209 return -EINVAL;
771fe6b9 210 }
721604a1
JG
211 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
212 p->chunk_flags_idx = i;
213 /* zero length flags aren't useful */
214 if (p->chunks[i].length_dw == 0)
215 return -EINVAL;
e70f224c 216 }
5176fdc4 217
771fe6b9 218 p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46 219 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9 220
513bcb46 221 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1
JG
222 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
223 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46
DA
224 size = p->chunks[i].length_dw * sizeof(uint32_t);
225 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
226 if (p->chunks[i].kdata == NULL) {
227 return -ENOMEM;
228 }
229 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
230 p->chunks[i].user_ptr, size)) {
231 return -EFAULT;
232 }
e70f224c 233 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1
JG
234 p->cs_flags = p->chunks[i].kdata[0];
235 if (p->chunks[i].length_dw > 1)
236 ring = p->chunks[i].kdata[1];
237 if (p->chunks[i].length_dw > 2)
238 priority = (s32)p->chunks[i].kdata[2];
e70f224c 239 }
771fe6b9
JG
240 }
241 }
721604a1
JG
242
243 if ((p->cs_flags & RADEON_CS_USE_VM) &&
67e915e4
AD
244 !p->rdev->vm_manager.enabled) {
245 DRM_ERROR("VM not active on asic!\n");
721604a1
JG
246 if (p->chunk_relocs_idx != -1)
247 kfree(p->chunks[p->chunk_relocs_idx].kdata);
248 if (p->chunk_flags_idx != -1)
249 kfree(p->chunks[p->chunk_flags_idx].kdata);
771fe6b9
JG
250 return -EINVAL;
251 }
e70f224c 252
721604a1
JG
253 if (radeon_cs_get_ring(p, ring, priority)) {
254 if (p->chunk_relocs_idx != -1)
255 kfree(p->chunks[p->chunk_relocs_idx].kdata);
256 if (p->chunk_flags_idx != -1)
257 kfree(p->chunks[p->chunk_flags_idx].kdata);
258 return -EINVAL;
259 }
260
261
262 /* deal with non-vm */
263 if ((p->chunk_ib_idx != -1) &&
264 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
265 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
266 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
267 DRM_ERROR("cs IB too big: %d\n",
268 p->chunks[p->chunk_ib_idx].length_dw);
269 return -EINVAL;
270 }
271 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
272 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
273 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
274 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
275 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
276 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
277 return -ENOMEM;
278 }
279 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
280 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
281 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
282 p->chunks[p->chunk_ib_idx].last_page_index =
283 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
284 }
285
771fe6b9
JG
286 return 0;
287}
288
289/**
290 * cs_parser_fini() - clean parser states
291 * @parser: parser structure holding parsing context.
292 * @error: error number
293 *
294 * If error is set than unvalidate buffer, otherwise just free memory
295 * used by parsing context.
296 **/
297static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
298{
299 unsigned i;
300
147666fb
TH
301
302 if (!error && parser->ib)
303 ttm_eu_fence_buffer_objects(&parser->validated,
304 parser->ib->fence);
305 else
306 ttm_eu_backoff_reservation(&parser->validated);
307
fcbc451b
PN
308 if (parser->relocs != NULL) {
309 for (i = 0; i < parser->nrelocs; i++) {
310 if (parser->relocs[i].gobj)
311 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
312 }
771fe6b9 313 }
48e113e5 314 kfree(parser->track);
771fe6b9
JG
315 kfree(parser->relocs);
316 kfree(parser->relocs_ptr);
317 for (i = 0; i < parser->nchunks; i++) {
318 kfree(parser->chunks[i].kdata);
513bcb46
DA
319 kfree(parser->chunks[i].kpage[0]);
320 kfree(parser->chunks[i].kpage[1]);
771fe6b9
JG
321 }
322 kfree(parser->chunks);
323 kfree(parser->chunks_array);
324 radeon_ib_free(parser->rdev, &parser->ib);
325}
326
721604a1
JG
327static int radeon_cs_ib_chunk(struct radeon_device *rdev,
328 struct radeon_cs_parser *parser)
329{
330 struct radeon_cs_chunk *ib_chunk;
331 int r;
332
333 if (parser->chunk_ib_idx == -1)
334 return 0;
335
336 if (parser->cs_flags & RADEON_CS_USE_VM)
337 return 0;
338
339 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
340 /* Copy the packet into the IB, the parser will read from the
341 * input memory (cached) and write to the IB (which can be
342 * uncached).
343 */
344 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
345 ib_chunk->length_dw * 4);
346 if (r) {
347 DRM_ERROR("Failed to get ib !\n");
348 return r;
349 }
350 parser->ib->length_dw = ib_chunk->length_dw;
351 r = radeon_cs_parse(parser);
352 if (r || parser->parser_error) {
353 DRM_ERROR("Invalid command stream !\n");
354 return r;
355 }
356 r = radeon_cs_finish_pages(parser);
357 if (r) {
358 DRM_ERROR("Invalid command stream !\n");
359 return r;
360 }
93504fce
CK
361 r = radeon_cs_sync_rings(parser);
362 if (r) {
363 DRM_ERROR("Failed to synchronize rings !\n");
364 }
721604a1
JG
365 parser->ib->vm_id = 0;
366 r = radeon_ib_schedule(rdev, parser->ib);
367 if (r) {
368 DRM_ERROR("Failed to schedule IB !\n");
369 }
370 return 0;
371}
372
373static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
374 struct radeon_vm *vm)
375{
376 struct radeon_bo_list *lobj;
377 struct radeon_bo *bo;
378 int r;
379
380 list_for_each_entry(lobj, &parser->validated, tv.head) {
381 bo = lobj->bo;
382 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
383 if (r) {
384 return r;
385 }
386 }
387 return 0;
388}
389
390static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
391 struct radeon_cs_parser *parser)
392{
393 struct radeon_cs_chunk *ib_chunk;
394 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
395 struct radeon_vm *vm = &fpriv->vm;
396 int r;
397
398 if (parser->chunk_ib_idx == -1)
399 return 0;
400
401 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
402 return 0;
403
404 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
405 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
406 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
407 return -EINVAL;
408 }
409 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
410 ib_chunk->length_dw * 4);
411 if (r) {
412 DRM_ERROR("Failed to get ib !\n");
413 return r;
414 }
415 parser->ib->length_dw = ib_chunk->length_dw;
416 /* Copy the packet into the IB */
417 if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
418 ib_chunk->length_dw * 4)) {
419 return -EFAULT;
420 }
421 r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
422 if (r) {
423 return r;
424 }
425
426 mutex_lock(&vm->mutex);
427 r = radeon_vm_bind(rdev, vm);
428 if (r) {
429 goto out;
430 }
431 r = radeon_bo_vm_update_pte(parser, vm);
432 if (r) {
433 goto out;
434 }
93504fce
CK
435 r = radeon_cs_sync_rings(parser);
436 if (r) {
437 DRM_ERROR("Failed to synchronize rings !\n");
438 }
721604a1
JG
439 parser->ib->vm_id = vm->id;
440 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
441 * offset inside the pool bo
442 */
443 parser->ib->gpu_addr = parser->ib->sa_bo.offset;
444 r = radeon_ib_schedule(rdev, parser->ib);
445out:
446 if (!r) {
447 if (vm->fence) {
448 radeon_fence_unref(&vm->fence);
449 }
450 vm->fence = radeon_fence_ref(parser->ib->fence);
451 }
452 mutex_unlock(&fpriv->vm.mutex);
453 return r;
454}
455
771fe6b9
JG
456int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
457{
458 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_cs_parser parser;
771fe6b9
JG
460 int r;
461
7a1619b9 462 radeon_mutex_lock(&rdev->cs_mutex);
771fe6b9
JG
463 /* initialize parser */
464 memset(&parser, 0, sizeof(struct radeon_cs_parser));
465 parser.filp = filp;
466 parser.rdev = rdev;
c8c15ff1 467 parser.dev = rdev->dev;
428c6e36 468 parser.family = rdev->family;
771fe6b9
JG
469 r = radeon_cs_parser_init(&parser, data);
470 if (r) {
471 DRM_ERROR("Failed to initialize parser !\n");
472 radeon_cs_parser_fini(&parser, r);
7a1619b9 473 radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9
JG
474 return r;
475 }
771fe6b9
JG
476 r = radeon_cs_parser_relocs(&parser);
477 if (r) {
97f23b3d
DA
478 if (r != -ERESTARTSYS)
479 DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9 480 radeon_cs_parser_fini(&parser, r);
7a1619b9 481 radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9
JG
482 return r;
483 }
721604a1 484 r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9 485 if (r) {
721604a1 486 goto out;
771fe6b9 487 }
721604a1 488 r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9 489 if (r) {
721604a1 490 goto out;
771fe6b9 491 }
721604a1 492out:
771fe6b9 493 radeon_cs_parser_fini(&parser, r);
7a1619b9 494 radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9
JG
495 return r;
496}
513bcb46
DA
497
498int radeon_cs_finish_pages(struct radeon_cs_parser *p)
499{
500 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
501 int i;
502 int size = PAGE_SIZE;
503
504 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
505 if (i == ibc->last_page_index) {
506 size = (ibc->length_dw * 4) % PAGE_SIZE;
507 if (size == 0)
508 size = PAGE_SIZE;
509 }
510
511 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
512 ibc->user_ptr + (i * PAGE_SIZE),
513 size))
514 return -EFAULT;
515 }
516 return 0;
517}
518
519int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
520{
521 int new_page;
513bcb46
DA
522 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
523 int i;
524 int size = PAGE_SIZE;
525
c5e617e2 526 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
513bcb46
DA
527 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
528 ibc->user_ptr + (i * PAGE_SIZE),
529 PAGE_SIZE)) {
530 p->parser_error = -EFAULT;
531 return 0;
532 }
533 }
534
535 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
536
537 if (pg_idx == ibc->last_page_index) {
538 size = (ibc->length_dw * 4) % PAGE_SIZE;
539 if (size == 0)
540 size = PAGE_SIZE;
541 }
542
543 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
544 ibc->user_ptr + (pg_idx * PAGE_SIZE),
545 size)) {
546 p->parser_error = -EFAULT;
547 return 0;
548 }
549
550 /* copy to IB here */
551 memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
552
553 ibc->last_copied_page = pg_idx;
554 ibc->kpage_idx[new_page] = pg_idx;
555
556 return new_page;
557}