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Merge branches 'topic/slob/cleanups', 'topic/slob/fixes', 'topic/slub/core', 'topic...
[linux-block.git] / drivers / gpu / drm / radeon / radeon_cp.c
CommitLineData
f26c473c
DA		 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
1da177e4
LT		 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
45e51905 5 * Copyright 2007 Advanced Micro Devices, Inc.
1da177e4
LT		 6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32#include "drmP.h"
33#include "drm.h"
7c1c2871 34#include "drm_sarea.h"
1da177e4
LT		 35#include "radeon_drm.h"
36#include "radeon_drv.h"
414ed537 37#include "r300_reg.h"
1da177e4 38
9f18409e
AD		 39#include "radeon_microcode.h"
40
1da177e4
LT		 41#define RADEON_FIFO_DEBUG 0
42
84b1fd10 43static int radeon_do_cleanup_cp(struct drm_device * dev);
54f961a6 44static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
1da177e4 45
45e51905 46static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
3d5e2c13
DA		 47{
48 u32 ret;
49 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
50 ret = RADEON_READ(R520_MC_IND_DATA);
51 RADEON_WRITE(R520_MC_IND_INDEX, 0);
52 return ret;
53}
54
45e51905
AD		 55static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
56{
57 u32 ret;
58 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
59 ret = RADEON_READ(RS480_NB_MC_DATA);
60 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
61 return ret;
62}
63
60f92683
MC		 64static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
65{
45e51905 66 u32 ret;
60f92683 67 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
45e51905
AD		 68 ret = RADEON_READ(RS690_MC_DATA);
69 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
70 return ret;
71}
72
73static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
74{
f0738e92
AD		 75 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
76 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
45e51905
AD		 77 return RS690_READ_MCIND(dev_priv, addr);
78 else
79 return RS480_READ_MCIND(dev_priv, addr);
60f92683
MC		 80}
81
3d5e2c13
DA		 82u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
83{
84
85 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 86 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
f0738e92
AD		 87 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
88 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
60f92683 89 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
3d5e2c13 90 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 91 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
3d5e2c13
DA		 92 else
93 return RADEON_READ(RADEON_MC_FB_LOCATION);
94}
95
96static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
97{
98 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 99 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
f0738e92
AD		 100 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
101 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
60f92683 102 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
3d5e2c13 103 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 104 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
3d5e2c13
DA		 105 else
106 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
107}
108
109static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
110{
111 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
45e51905 112 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
f0738e92
AD		 113 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
114 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
60f92683 115 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
3d5e2c13 116 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
45e51905 117 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
3d5e2c13
DA		 118 else
119 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
120}
121
70b13d51
DA		 122static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
123{
124 u32 agp_base_hi = upper_32_bits(agp_base);
125 u32 agp_base_lo = agp_base & 0xffffffff;
126
127 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
128 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
f0738e92
AD		 130 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
131 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
70b13d51
DA		 132 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
133 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
134 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
135 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
136 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
b2ceddfa
AD		 137 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
138 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
5cfb6956 139 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
b2ceddfa 140 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
70b13d51
DA		 141 } else {
142 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
143 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
144 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
145 }
146}
147
84b1fd10 148static int RADEON_READ_PLL(struct drm_device * dev, int addr)
1da177e4
LT		 149{
150 drm_radeon_private_t *dev_priv = dev->dev_private;
151
152 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
153 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
154}
155
3d5e2c13 156static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
ea98a92f
DA		 157{
158 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
159 return RADEON_READ(RADEON_PCIE_DATA);
160}
161
1da177e4 162#if RADEON_FIFO_DEBUG
b5e89ed5 163static void radeon_status(drm_radeon_private_t * dev_priv)
1da177e4 164{
bf9d8929 165 printk("%s:\n", __func__);
b5e89ed5
DA		 166 printk("RBBM_STATUS = 0x%08x\n",
167 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
168 printk("CP_RB_RTPR = 0x%08x\n",
169 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
170 printk("CP_RB_WTPR = 0x%08x\n",
171 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
172 printk("AIC_CNTL = 0x%08x\n",
173 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
174 printk("AIC_STAT = 0x%08x\n",
175 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
176 printk("AIC_PT_BASE = 0x%08x\n",
177 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
178 printk("TLB_ADDR = 0x%08x\n",
179 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
180 printk("TLB_DATA = 0x%08x\n",
181 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
1da177e4
LT		 182}
183#endif
184
1da177e4
LT		 185/* ================================================================
186 * Engine, FIFO control
187 */
188
b5e89ed5 189static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
1da177e4
LT		 190{
191 u32 tmp;
192 int i;
193
194 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
195
259434ac
AD		 196 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
197 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
198 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
199 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
200
201 for (i = 0; i < dev_priv->usec_timeout; i++) {
202 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
203 & RADEON_RB3D_DC_BUSY)) {
204 return 0;
205 }
206 DRM_UDELAY(1);
207 }
208 } else {
54f961a6
JG		 209 /* don't flush or purge cache here or lockup */
210 return 0;
1da177e4
LT		 211 }
212
213#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 214 DRM_ERROR("failed!\n");
215 radeon_status(dev_priv);
1da177e4 216#endif
20caafa6 217 return -EBUSY;
1da177e4
LT		 218}
219
b5e89ed5 220static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
1da177e4
LT		 221{
222 int i;
223
224 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
225
b5e89ed5
DA		 226 for (i = 0; i < dev_priv->usec_timeout; i++) {
227 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
228 & RADEON_RBBM_FIFOCNT_MASK);
229 if (slots >= entries)
230 return 0;
231 DRM_UDELAY(1);
1da177e4 232 }
6c7be298 233 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
54f961a6
JG		 234 RADEON_READ(RADEON_RBBM_STATUS),
235 RADEON_READ(R300_VAP_CNTL_STATUS));
1da177e4
LT		 236
237#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 238 DRM_ERROR("failed!\n");
239 radeon_status(dev_priv);
1da177e4 240#endif
20caafa6 241 return -EBUSY;
1da177e4
LT		 242}
243
b5e89ed5 244static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 245{
246 int i, ret;
247
248 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
249
b5e89ed5
DA		 250 ret = radeon_do_wait_for_fifo(dev_priv, 64);
251 if (ret)
252 return ret;
1da177e4 253
b5e89ed5
DA		 254 for (i = 0; i < dev_priv->usec_timeout; i++) {
255 if (!(RADEON_READ(RADEON_RBBM_STATUS)
256 & RADEON_RBBM_ACTIVE)) {
257 radeon_do_pixcache_flush(dev_priv);
1da177e4
LT		 258 return 0;
259 }
b5e89ed5 260 DRM_UDELAY(1);
1da177e4 261 }
6c7be298 262 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
54f961a6
JG		 263 RADEON_READ(RADEON_RBBM_STATUS),
264 RADEON_READ(R300_VAP_CNTL_STATUS));
1da177e4
LT		 265
266#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 267 DRM_ERROR("failed!\n");
268 radeon_status(dev_priv);
1da177e4 269#endif
20caafa6 270 return -EBUSY;
1da177e4
LT		 271}
272
5b92c404
AD		 273static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
274{
275 uint32_t gb_tile_config, gb_pipe_sel = 0;
276
277 /* RS4xx/RS6xx/R4xx/R5xx */
278 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
279 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
280 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
281 } else {
282 /* R3xx */
283 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
284 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
285 dev_priv->num_gb_pipes = 2;
286 } else {
287 /* R3Vxx */
288 dev_priv->num_gb_pipes = 1;
289 }
290 }
291 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
292
293 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
294
295 switch (dev_priv->num_gb_pipes) {
296 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
297 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
298 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
299 default:
300 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
301 }
302
303 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
304 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
305 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
306 }
307 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
308 radeon_do_wait_for_idle(dev_priv);
309 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
310 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
311 R300_DC_AUTOFLUSH_ENABLE |
312 R300_DC_DC_DISABLE_IGNORE_PE));
313
314
315}
316
1da177e4
LT		 317/* ================================================================
318 * CP control, initialization
319 */
320
321/* Load the microcode for the CP */
b5e89ed5 322static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1da177e4
LT		 323{
324 int i;
b5e89ed5 325 DRM_DEBUG("\n");
1da177e4 326
b5e89ed5 327 radeon_do_wait_for_idle(dev_priv);
1da177e4 328
b5e89ed5 329 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
9f18409e
AD		 330 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
331 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
335 DRM_INFO("Loading R100 Microcode\n");
336 for (i = 0; i < 256; i++) {
337 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
338 R100_cp_microcode[i][1]);
339 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
340 R100_cp_microcode[i][0]);
341 }
342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
343 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
1da177e4 346 DRM_INFO("Loading R200 Microcode\n");
b5e89ed5
DA		 347 for (i = 0; i < 256; i++) {
348 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
349 R200_cp_microcode[i][1]);
350 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
351 R200_cp_microcode[i][0]);
1da177e4 352 }
9f18409e
AD		 353 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
b2ceddfa 357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
45e51905 358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
1da177e4 359 DRM_INFO("Loading R300 Microcode\n");
b5e89ed5
DA		 360 for (i = 0; i < 256; i++) {
361 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
362 R300_cp_microcode[i][1]);
363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
364 R300_cp_microcode[i][0]);
1da177e4 365 }
9f18409e 366 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
edc6f389 367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
9f18409e
AD		 368 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
369 DRM_INFO("Loading R400 Microcode\n");
370 for (i = 0; i < 256; i++) {
371 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
372 R420_cp_microcode[i][1]);
373 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
374 R420_cp_microcode[i][0]);
375 }
f0738e92
AD		 376 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
377 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
378 DRM_INFO("Loading RS690/RS740 Microcode\n");
9f18409e
AD		 379 for (i = 0; i < 256; i++) {
380 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
381 RS690_cp_microcode[i][1]);
382 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
383 RS690_cp_microcode[i][0]);
384 }
385 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
390 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
391 DRM_INFO("Loading R500 Microcode\n");
b5e89ed5
DA		 392 for (i = 0; i < 256; i++) {
393 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
9f18409e 394 R520_cp_microcode[i][1]);
b5e89ed5 395 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
9f18409e 396 R520_cp_microcode[i][0]);
1da177e4
LT		 397 }
398 }
399}
400
401/* Flush any pending commands to the CP. This should only be used just
402 * prior to a wait for idle, as it informs the engine that the command
403 * stream is ending.
404 */
b5e89ed5 405static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1da177e4 406{
b5e89ed5 407 DRM_DEBUG("\n");
1da177e4
LT		 408#if 0
409 u32 tmp;
410
b5e89ed5
DA		 411 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
412 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1da177e4
LT		 413#endif
414}
415
416/* Wait for the CP to go idle.
417 */
b5e89ed5 418int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1da177e4
LT		 419{
420 RING_LOCALS;
b5e89ed5 421 DRM_DEBUG("\n");
1da177e4 422
b5e89ed5 423 BEGIN_RING(6);
1da177e4
LT		 424
425 RADEON_PURGE_CACHE();
426 RADEON_PURGE_ZCACHE();
427 RADEON_WAIT_UNTIL_IDLE();
428
429 ADVANCE_RING();
430 COMMIT_RING();
431
b5e89ed5 432 return radeon_do_wait_for_idle(dev_priv);
1da177e4
LT		 433}
434
435/* Start the Command Processor.
436 */
b5e89ed5 437static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1da177e4
LT		 438{
439 RING_LOCALS;
b5e89ed5 440 DRM_DEBUG("\n");
1da177e4 441
b5e89ed5 442 radeon_do_wait_for_idle(dev_priv);
1da177e4 443
b5e89ed5 444 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1da177e4
LT		 445
446 dev_priv->cp_running = 1;
447
54f961a6
JG		 448 BEGIN_RING(8);
449 /* isync can only be written through cp on r5xx write it here */
450 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
451 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
452 RADEON_ISYNC_ANY3D_IDLE2D |
453 RADEON_ISYNC_WAIT_IDLEGUI |
454 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1da177e4
LT		 455 RADEON_PURGE_CACHE();
456 RADEON_PURGE_ZCACHE();
457 RADEON_WAIT_UNTIL_IDLE();
1da177e4
LT		 458 ADVANCE_RING();
459 COMMIT_RING();
54f961a6
JG		 460
461 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
1da177e4
LT		 462}
463
464/* Reset the Command Processor. This will not flush any pending
465 * commands, so you must wait for the CP command stream to complete
466 * before calling this routine.
467 */
b5e89ed5 468static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1da177e4
LT		 469{
470 u32 cur_read_ptr;
b5e89ed5 471 DRM_DEBUG("\n");
1da177e4 472
b5e89ed5
DA		 473 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
474 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
475 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 476 dev_priv->ring.tail = cur_read_ptr;
477}
478
479/* Stop the Command Processor. This will not flush any pending
480 * commands, so you must flush the command stream and wait for the CP
481 * to go idle before calling this routine.
482 */
b5e89ed5 483static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1da177e4 484{
b5e89ed5 485 DRM_DEBUG("\n");
1da177e4 486
b5e89ed5 487 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1da177e4
LT		 488
489 dev_priv->cp_running = 0;
490}
491
492/* Reset the engine. This will stop the CP if it is running.
493 */
84b1fd10 494static int radeon_do_engine_reset(struct drm_device * dev)
1da177e4
LT		 495{
496 drm_radeon_private_t *dev_priv = dev->dev_private;
d396db32 497 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
b5e89ed5 498 DRM_DEBUG("\n");
1da177e4 499
b5e89ed5
DA		 500 radeon_do_pixcache_flush(dev_priv);
501
d396db32
AD		 502 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
503 /* may need something similar for newer chips */
3d5e2c13
DA		 504 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
505 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
506
507 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
508 RADEON_FORCEON_MCLKA |
509 RADEON_FORCEON_MCLKB |
510 RADEON_FORCEON_YCLKA |
511 RADEON_FORCEON_YCLKB |
512 RADEON_FORCEON_MC |
513 RADEON_FORCEON_AIC));
d396db32 514 }
3d5e2c13 515
d396db32
AD		 516 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
517
518 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
519 RADEON_SOFT_RESET_CP |
520 RADEON_SOFT_RESET_HI |
521 RADEON_SOFT_RESET_SE |
522 RADEON_SOFT_RESET_RE |
523 RADEON_SOFT_RESET_PP |
524 RADEON_SOFT_RESET_E2 |
525 RADEON_SOFT_RESET_RB));
526 RADEON_READ(RADEON_RBBM_SOFT_RESET);
527 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
528 ~(RADEON_SOFT_RESET_CP |
529 RADEON_SOFT_RESET_HI |
530 RADEON_SOFT_RESET_SE |
531 RADEON_SOFT_RESET_RE |
532 RADEON_SOFT_RESET_PP |
533 RADEON_SOFT_RESET_E2 |
534 RADEON_SOFT_RESET_RB)));
535 RADEON_READ(RADEON_RBBM_SOFT_RESET);
536
537 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
3d5e2c13
DA		 538 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
539 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
540 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
541 }
1da177e4 542
5b92c404
AD		 543 /* setup the raster pipes */
544 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
545 radeon_init_pipes(dev_priv);
546
1da177e4 547 /* Reset the CP ring */
b5e89ed5 548 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 549
550 /* The CP is no longer running after an engine reset */
551 dev_priv->cp_running = 0;
552
553 /* Reset any pending vertex, indirect buffers */
b5e89ed5 554 radeon_freelist_reset(dev);
1da177e4
LT		 555
556 return 0;
557}
558
84b1fd10 559static void radeon_cp_init_ring_buffer(struct drm_device * dev,
3d16118d 560 drm_radeon_private_t *dev_priv,
561 struct drm_file *file_priv)
1da177e4 562{
3d16118d 563 struct drm_radeon_master_private *master_priv;
1da177e4
LT		 564 u32 ring_start, cur_read_ptr;
565 u32 tmp;
bc5f4523 566
d5ea702f
DA		 567 /* Initialize the memory controller. With new memory map, the fb location
568 * is not changed, it should have been properly initialized already. Part
569 * of the problem is that the code below is bogus, assuming the GART is
570 * always appended to the fb which is not necessarily the case
571 */
572 if (!dev_priv->new_memmap)
3d5e2c13 573 radeon_write_fb_location(dev_priv,
d5ea702f
DA		 574 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
575 | (dev_priv->fb_location >> 16));
1da177e4
LT		 576
577#if __OS_HAS_AGP
54a56ac5 578 if (dev_priv->flags & RADEON_IS_AGP) {
70b13d51
DA		 579 radeon_write_agp_base(dev_priv, dev->agp->base);
580
3d5e2c13 581 radeon_write_agp_location(dev_priv,
b5e89ed5
DA		 582 (((dev_priv->gart_vm_start - 1 +
583 dev_priv->gart_size) & 0xffff0000) |
584 (dev_priv->gart_vm_start >> 16)));
1da177e4
LT		 585
586 ring_start = (dev_priv->cp_ring->offset
587 - dev->agp->base
588 + dev_priv->gart_vm_start);
b0917bd9 589 } else
1da177e4
LT		 590#endif
591 ring_start = (dev_priv->cp_ring->offset
b0917bd9 592 - (unsigned long)dev->sg->virtual
1da177e4
LT		 593 + dev_priv->gart_vm_start);
594
b5e89ed5 595 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1da177e4
LT		 596
597 /* Set the write pointer delay */
b5e89ed5 598 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1da177e4
LT		 599
600 /* Initialize the ring buffer's read and write pointers */
b5e89ed5
DA		 601 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
602 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
603 SET_RING_HEAD(dev_priv, cur_read_ptr);
1da177e4
LT		 604 dev_priv->ring.tail = cur_read_ptr;
605
606#if __OS_HAS_AGP
54a56ac5 607 if (dev_priv->flags & RADEON_IS_AGP) {
b5e89ed5
DA		 608 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
609 dev_priv->ring_rptr->offset
610 - dev->agp->base + dev_priv->gart_vm_start);
1da177e4
LT		 611 } else
612#endif
613 {
55910517 614 struct drm_sg_mem *entry = dev->sg;
1da177e4
LT		 615 unsigned long tmp_ofs, page_ofs;
616
b0917bd9
IK		 617 tmp_ofs = dev_priv->ring_rptr->offset -
618 (unsigned long)dev->sg->virtual;
1da177e4
LT		 619 page_ofs = tmp_ofs >> PAGE_SHIFT;
620
b5e89ed5
DA		 621 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
622 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
623 (unsigned long)entry->busaddr[page_ofs],
624 entry->handle + tmp_ofs);
1da177e4
LT		 625 }
626
d5ea702f
DA		 627 /* Set ring buffer size */
628#ifdef __BIG_ENDIAN
629 RADEON_WRITE(RADEON_CP_RB_CNTL,
576cc458
RS		 630 RADEON_BUF_SWAP_32BIT |
631 (dev_priv->ring.fetch_size_l2ow << 18) |
632 (dev_priv->ring.rptr_update_l2qw << 8) |
633 dev_priv->ring.size_l2qw);
d5ea702f 634#else
576cc458
RS		 635 RADEON_WRITE(RADEON_CP_RB_CNTL,
636 (dev_priv->ring.fetch_size_l2ow << 18) |
637 (dev_priv->ring.rptr_update_l2qw << 8) |
638 dev_priv->ring.size_l2qw);
d5ea702f
DA		 639#endif
640
d5ea702f 641
1da177e4
LT		 642 /* Initialize the scratch register pointer. This will cause
643 * the scratch register values to be written out to memory
644 * whenever they are updated.
645 *
646 * We simply put this behind the ring read pointer, this works
647 * with PCI GART as well as (whatever kind of) AGP GART
648 */
b5e89ed5
DA		 649 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
650 + RADEON_SCRATCH_REG_OFFSET);
1da177e4
LT		 651
652 dev_priv->scratch = ((__volatile__ u32 *)
653 dev_priv->ring_rptr->handle +
654 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
655
b5e89ed5 656 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1da177e4 657
d5ea702f 658 /* Turn on bus mastering */
4e270e9b 659 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
edc6f389 660 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
4e270e9b
AD		 661 /* rs600/rs690/rs740 */
662 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
edc6f389 663 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
4e270e9b
AD		 664 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
665 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
666 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
667 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
668 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
edc6f389
AD		 669 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
670 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
671 } /* PCIE cards appears to not need this */
1da177e4 672
7c1c2871
DA		 673 dev_priv->scratch[0] = 0;
674 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
1da177e4 675
7c1c2871
DA		 676 dev_priv->scratch[1] = 0;
677 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
1da177e4 678
7c1c2871
DA		 679 dev_priv->scratch[2] = 0;
680 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
1da177e4 681
3d16118d 682 /* reset sarea copies of these */
683 master_priv = file_priv->master->driver_priv;
684 if (master_priv->sarea_priv) {
685 master_priv->sarea_priv->last_frame = 0;
686 master_priv->sarea_priv->last_dispatch = 0;
687 master_priv->sarea_priv->last_clear = 0;
688 }
689
b5e89ed5 690 radeon_do_wait_for_idle(dev_priv);
1da177e4 691
1da177e4 692 /* Sync everything up */
b5e89ed5
DA		 693 RADEON_WRITE(RADEON_ISYNC_CNTL,
694 (RADEON_ISYNC_ANY2D_IDLE3D |
695 RADEON_ISYNC_ANY3D_IDLE2D |
696 RADEON_ISYNC_WAIT_IDLEGUI |
697 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
d5ea702f
DA		 698
699}
700
701static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
702{
703 u32 tmp;
704
6b79d521
DA		 705 /* Start with assuming that writeback doesn't work */
706 dev_priv->writeback_works = 0;
707
d5ea702f
DA		 708 /* Writeback doesn't seem to work everywhere, test it here and possibly
709 * enable it if it appears to work
710 */
711 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
712 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
713
714 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
715 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
716 0xdeadbeef)
717 break;
718 DRM_UDELAY(1);
719 }
720
721 if (tmp < dev_priv->usec_timeout) {
722 dev_priv->writeback_works = 1;
723 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
724 } else {
725 dev_priv->writeback_works = 0;
726 DRM_INFO("writeback test failed\n");
727 }
728 if (radeon_no_wb == 1) {
729 dev_priv->writeback_works = 0;
730 DRM_INFO("writeback forced off\n");
731 }
ae1b1a48
MD		 732
733 if (!dev_priv->writeback_works) {
734 /* Disable writeback to avoid unnecessary bus master transfer */
735 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
736 RADEON_RB_NO_UPDATE);
737 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
738 }
1da177e4
LT		 739}
740
f2b04cd2
DA		 741/* Enable or disable IGP GART on the chip */
742static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
60f92683
MC		 743{
744 u32 temp;
745
746 if (on) {
45e51905 747 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
60f92683
MC		 748 dev_priv->gart_vm_start,
749 (long)dev_priv->gart_info.bus_addr,
750 dev_priv->gart_size);
751
45e51905 752 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
f0738e92
AD		 753 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
754 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
45e51905
AD		 755 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
756 RS690_BLOCK_GFX_D3_EN));
757 else
758 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
60f92683 759
45e51905
AD		 760 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
761 RS480_VA_SIZE_32MB));
60f92683 762
45e51905
AD		 763 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
764 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
765 RS480_TLB_ENABLE |
766 RS480_GTW_LAC_EN |
767 RS480_1LEVEL_GART));
60f92683 768
fa0d71b9
DA		 769 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
770 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
45e51905
AD		 771 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
772
773 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
774 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
775 RS480_REQ_TYPE_SNOOP_DIS));
776
5cfb6956 777 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
3722bfc6 778
60f92683
MC		 779 dev_priv->gart_size = 32*1024*1024;
780 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
781 0xffff0000) | (dev_priv->gart_vm_start >> 16));
782
45e51905 783 radeon_write_agp_location(dev_priv, temp);
60f92683 784
45e51905
AD		 785 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
786 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
787 RS480_VA_SIZE_32MB));
60f92683
MC		 788
789 do {
45e51905
AD		 790 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
791 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
60f92683
MC		 792 break;
793 DRM_UDELAY(1);
794 } while (1);
795
45e51905
AD		 796 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
797 RS480_GART_CACHE_INVALIDATE);
2735977b 798
60f92683 799 do {
45e51905
AD		 800 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
801 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
60f92683
MC		 802 break;
803 DRM_UDELAY(1);
804 } while (1);
805
45e51905 806 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
60f92683 807 } else {
45e51905 808 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
60f92683
MC		 809 }
810}
811
ea98a92f
DA		 812static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
813{
814 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
815 if (on) {
816
817 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
b5e89ed5
DA		 818 dev_priv->gart_vm_start,
819 (long)dev_priv->gart_info.bus_addr,
ea98a92f 820 dev_priv->gart_size);
b5e89ed5
DA		 821 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
822 dev_priv->gart_vm_start);
823 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
824 dev_priv->gart_info.bus_addr);
825 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
826 dev_priv->gart_vm_start);
827 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
828 dev_priv->gart_vm_start +
829 dev_priv->gart_size - 1);
830
3d5e2c13 831 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
b5e89ed5
DA		 832
833 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
834 RADEON_PCIE_TX_GART_EN);
ea98a92f 835 } else {
b5e89ed5
DA		 836 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
837 tmp & ~RADEON_PCIE_TX_GART_EN);
ea98a92f 838 }
1da177e4
LT		 839}
840
841/* Enable or disable PCI GART on the chip */
b5e89ed5 842static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1da177e4 843{
d985c108 844 u32 tmp;
1da177e4 845
45e51905 846 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
f0738e92 847 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
45e51905 848 (dev_priv->flags & RADEON_IS_IGPGART)) {
f2b04cd2
DA		 849 radeon_set_igpgart(dev_priv, on);
850 return;
851 }
852
54a56ac5 853 if (dev_priv->flags & RADEON_IS_PCIE) {
ea98a92f
DA		 854 radeon_set_pciegart(dev_priv, on);
855 return;
856 }
1da177e4 857
bc5f4523 858 tmp = RADEON_READ(RADEON_AIC_CNTL);
d985c108 859
b5e89ed5
DA		 860 if (on) {
861 RADEON_WRITE(RADEON_AIC_CNTL,
862 tmp | RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 863
864 /* set PCI GART page-table base address
865 */
ea98a92f 866 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1da177e4
LT		 867
868 /* set address range for PCI address translate
869 */
b5e89ed5
DA		 870 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
871 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
872 + dev_priv->gart_size - 1);
1da177e4
LT		 873
874 /* Turn off AGP aperture -- is this required for PCI GART?
875 */
3d5e2c13 876 radeon_write_agp_location(dev_priv, 0xffffffc0);
b5e89ed5 877 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1da177e4 878 } else {
b5e89ed5
DA		 879 RADEON_WRITE(RADEON_AIC_CNTL,
880 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1da177e4
LT		 881 }
882}
883
7c1c2871
DA		 884static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
885 struct drm_file *file_priv)
1da177e4 886{
d985c108 887 drm_radeon_private_t *dev_priv = dev->dev_private;
7c1c2871 888 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
d985c108 889
b5e89ed5 890 DRM_DEBUG("\n");
1da177e4 891
f3dd5c37 892 /* if we require new memory map but we don't have it fail */
54a56ac5 893 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
b15ec368 894 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
f3dd5c37 895 radeon_do_cleanup_cp(dev);
20caafa6 896 return -EINVAL;
f3dd5c37
DA		 897 }
898
54a56ac5 899 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
d985c108 900 DRM_DEBUG("Forcing AGP card to PCI mode\n");
54a56ac5
DA		 901 dev_priv->flags &= ~RADEON_IS_AGP;
902 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
b15ec368
DA		 903 && !init->is_pci) {
904 DRM_DEBUG("Restoring AGP flag\n");
54a56ac5 905 dev_priv->flags |= RADEON_IS_AGP;
d985c108 906 }
1da177e4 907
54a56ac5 908 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
b5e89ed5 909 DRM_ERROR("PCI GART memory not allocated!\n");
1da177e4 910 radeon_do_cleanup_cp(dev);
20caafa6 911 return -EINVAL;
1da177e4
LT		 912 }
913
914 dev_priv->usec_timeout = init->usec_timeout;
b5e89ed5
DA		 915 if (dev_priv->usec_timeout < 1 ||
916 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
917 DRM_DEBUG("TIMEOUT problem!\n");
1da177e4 918 radeon_do_cleanup_cp(dev);
20caafa6 919 return -EINVAL;
1da177e4
LT		 920 }
921
ddbee333
DA		 922 /* Enable vblank on CRTC1 for older X servers
923 */
924 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
925
d985c108 926 switch(init->func) {
1da177e4 927 case RADEON_INIT_R200_CP:
b5e89ed5 928 dev_priv->microcode_version = UCODE_R200;
1da177e4
LT		 929 break;
930 case RADEON_INIT_R300_CP:
b5e89ed5 931 dev_priv->microcode_version = UCODE_R300;
1da177e4
LT		 932 break;
933 default:
b5e89ed5 934 dev_priv->microcode_version = UCODE_R100;
1da177e4 935 }
b5e89ed5 936
1da177e4
LT		 937 dev_priv->do_boxes = 0;
938 dev_priv->cp_mode = init->cp_mode;
939
940 /* We don't support anything other than bus-mastering ring mode,
941 * but the ring can be in either AGP or PCI space for the ring
942 * read pointer.
943 */
b5e89ed5
DA		 944 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
945 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
946 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1da177e4 947 radeon_do_cleanup_cp(dev);
20caafa6 948 return -EINVAL;
1da177e4
LT		 949 }
950
b5e89ed5 951 switch (init->fb_bpp) {
1da177e4
LT		 952 case 16:
953 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
954 break;
955 case 32:
956 default:
957 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
958 break;
959 }
b5e89ed5
DA		 960 dev_priv->front_offset = init->front_offset;
961 dev_priv->front_pitch = init->front_pitch;
962 dev_priv->back_offset = init->back_offset;
963 dev_priv->back_pitch = init->back_pitch;
1da177e4 964
b5e89ed5 965 switch (init->depth_bpp) {
1da177e4
LT		 966 case 16:
967 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
968 break;
969 case 32:
970 default:
971 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
972 break;
973 }
b5e89ed5
DA		 974 dev_priv->depth_offset = init->depth_offset;
975 dev_priv->depth_pitch = init->depth_pitch;
1da177e4
LT		 976
977 /* Hardware state for depth clears. Remove this if/when we no
978 * longer clear the depth buffer with a 3D rectangle. Hard-code
979 * all values to prevent unwanted 3D state from slipping through
980 * and screwing with the clear operation.
981 */
982 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
983 (dev_priv->color_fmt << 10) |
b5e89ed5
DA		 984 (dev_priv->microcode_version ==
985 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1da177e4 986
b5e89ed5
DA		 987 dev_priv->depth_clear.rb3d_zstencilcntl =
988 (dev_priv->depth_fmt |
989 RADEON_Z_TEST_ALWAYS |
990 RADEON_STENCIL_TEST_ALWAYS |
991 RADEON_STENCIL_S_FAIL_REPLACE |
992 RADEON_STENCIL_ZPASS_REPLACE |
993 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1da177e4
LT		 994
995 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
996 RADEON_BFACE_SOLID |
997 RADEON_FFACE_SOLID |
998 RADEON_FLAT_SHADE_VTX_LAST |
999 RADEON_DIFFUSE_SHADE_FLAT |
1000 RADEON_ALPHA_SHADE_FLAT |
1001 RADEON_SPECULAR_SHADE_FLAT |
1002 RADEON_FOG_SHADE_FLAT |
1003 RADEON_VTX_PIX_CENTER_OGL |
1004 RADEON_ROUND_MODE_TRUNC |
1005 RADEON_ROUND_PREC_8TH_PIX);
1006
1da177e4 1007
1da177e4
LT		 1008 dev_priv->ring_offset = init->ring_offset;
1009 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1010 dev_priv->buffers_offset = init->buffers_offset;
1011 dev_priv->gart_textures_offset = init->gart_textures_offset;
b5e89ed5 1012
7c1c2871
DA		 1013 master_priv->sarea = drm_getsarea(dev);
1014 if (!master_priv->sarea) {
1da177e4 1015 DRM_ERROR("could not find sarea!\n");
1da177e4 1016 radeon_do_cleanup_cp(dev);
20caafa6 1017 return -EINVAL;
1da177e4
LT		 1018 }
1019
1da177e4 1020 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
b5e89ed5 1021 if (!dev_priv->cp_ring) {
1da177e4 1022 DRM_ERROR("could not find cp ring region!\n");
1da177e4 1023 radeon_do_cleanup_cp(dev);
20caafa6 1024 return -EINVAL;
1da177e4
LT		 1025 }
1026 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
b5e89ed5 1027 if (!dev_priv->ring_rptr) {
1da177e4 1028 DRM_ERROR("could not find ring read pointer!\n");
1da177e4 1029 radeon_do_cleanup_cp(dev);
20caafa6 1030 return -EINVAL;
1da177e4 1031 }
d1f2b55a 1032 dev->agp_buffer_token = init->buffers_offset;
1da177e4 1033 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
b5e89ed5 1034 if (!dev->agp_buffer_map) {
1da177e4 1035 DRM_ERROR("could not find dma buffer region!\n");
1da177e4 1036 radeon_do_cleanup_cp(dev);
20caafa6 1037 return -EINVAL;
1da177e4
LT		 1038 }
1039
b5e89ed5
DA		 1040 if (init->gart_textures_offset) {
1041 dev_priv->gart_textures =
1042 drm_core_findmap(dev, init->gart_textures_offset);
1043 if (!dev_priv->gart_textures) {
1da177e4 1044 DRM_ERROR("could not find GART texture region!\n");
1da177e4 1045 radeon_do_cleanup_cp(dev);
20caafa6 1046 return -EINVAL;
1da177e4
LT		 1047 }
1048 }
1049
1da177e4 1050#if __OS_HAS_AGP
54a56ac5 1051 if (dev_priv->flags & RADEON_IS_AGP) {
9b8d5a12
DA		 1052 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1053 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1054 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
b5e89ed5
DA		 1055 if (!dev_priv->cp_ring->handle ||
1056 !dev_priv->ring_rptr->handle ||
1057 !dev->agp_buffer_map->handle) {
1da177e4 1058 DRM_ERROR("could not find ioremap agp regions!\n");
1da177e4 1059 radeon_do_cleanup_cp(dev);
20caafa6 1060 return -EINVAL;
1da177e4
LT		 1061 }
1062 } else
1063#endif
1064 {
b5e89ed5 1065 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1da177e4 1066 dev_priv->ring_rptr->handle =
b5e89ed5
DA		 1067 (void *)dev_priv->ring_rptr->offset;
1068 dev->agp_buffer_map->handle =
1069 (void *)dev->agp_buffer_map->offset;
1070
1071 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1072 dev_priv->cp_ring->handle);
1073 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1074 dev_priv->ring_rptr->handle);
1075 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1076 dev->agp_buffer_map->handle);
1da177e4
LT		 1077 }
1078
3d5e2c13 1079 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
bc5f4523 1080 dev_priv->fb_size =
3d5e2c13 1081 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
d5ea702f 1082 - dev_priv->fb_location;
1da177e4 1083
b5e89ed5
DA		 1084 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1085 ((dev_priv->front_offset
1086 + dev_priv->fb_location) >> 10));
1da177e4 1087
b5e89ed5
DA		 1088 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1089 ((dev_priv->back_offset
1090 + dev_priv->fb_location) >> 10));
1da177e4 1091
b5e89ed5
DA		 1092 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1093 ((dev_priv->depth_offset
1094 + dev_priv->fb_location) >> 10));
1da177e4
LT		 1095
1096 dev_priv->gart_size = init->gart_size;
d5ea702f
DA		 1097
1098 /* New let's set the memory map ... */
1099 if (dev_priv->new_memmap) {
1100 u32 base = 0;
1101
1102 DRM_INFO("Setting GART location based on new memory map\n");
1103
1104 /* If using AGP, try to locate the AGP aperture at the same
1105 * location in the card and on the bus, though we have to
1106 * align it down.
1107 */
1108#if __OS_HAS_AGP
54a56ac5 1109 if (dev_priv->flags & RADEON_IS_AGP) {
d5ea702f
DA		 1110 base = dev->agp->base;
1111 /* Check if valid */
80b2c386
MD		 1112 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1113 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
d5ea702f
DA		 1114 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1115 dev->agp->base);
1116 base = 0;
1117 }
1118 }
1119#endif
1120 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1121 if (base == 0) {
1122 base = dev_priv->fb_location + dev_priv->fb_size;
80b2c386
MD		 1123 if (base < dev_priv->fb_location ||
1124 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
d5ea702f
DA		 1125 base = dev_priv->fb_location
1126 - dev_priv->gart_size;
bc5f4523 1127 }
d5ea702f
DA		 1128 dev_priv->gart_vm_start = base & 0xffc00000u;
1129 if (dev_priv->gart_vm_start != base)
1130 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1131 base, dev_priv->gart_vm_start);
1132 } else {
1133 DRM_INFO("Setting GART location based on old memory map\n");
1134 dev_priv->gart_vm_start = dev_priv->fb_location +
1135 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1136 }
1da177e4
LT		 1137
1138#if __OS_HAS_AGP
54a56ac5 1139 if (dev_priv->flags & RADEON_IS_AGP)
1da177e4 1140 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b5e89ed5
DA		 1141 - dev->agp->base
1142 + dev_priv->gart_vm_start);
1da177e4
LT		 1143 else
1144#endif
1145 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
b0917bd9
IK		 1146 - (unsigned long)dev->sg->virtual
1147 + dev_priv->gart_vm_start);
1da177e4 1148
b5e89ed5
DA		 1149 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1150 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1151 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1152 dev_priv->gart_buffers_offset);
1da177e4 1153
b5e89ed5
DA		 1154 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1155 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1da177e4
LT		 1156 + init->ring_size / sizeof(u32));
1157 dev_priv->ring.size = init->ring_size;
b5e89ed5 1158 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1da177e4 1159
576cc458
RS		 1160 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1161 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1162
1163 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1164 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
b5e89ed5 1165 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1da177e4
LT		 1166
1167 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1168
1169#if __OS_HAS_AGP
54a56ac5 1170 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1171 /* Turn off PCI GART */
b5e89ed5 1172 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1173 } else
1174#endif
1175 {
b05c2385 1176 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
ea98a92f 1177 /* if we have an offset set from userspace */
f2b04cd2 1178 if (dev_priv->pcigart_offset_set) {
b5e89ed5
DA		 1179 dev_priv->gart_info.bus_addr =
1180 dev_priv->pcigart_offset + dev_priv->fb_location;
f26c473c 1181 dev_priv->gart_info.mapping.offset =
7fc86860 1182 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
f26c473c 1183 dev_priv->gart_info.mapping.size =
f2b04cd2 1184 dev_priv->gart_info.table_size;
f26c473c 1185
242e3df8 1186 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
b5e89ed5 1187 dev_priv->gart_info.addr =
f26c473c 1188 dev_priv->gart_info.mapping.handle;
b5e89ed5 1189
f2b04cd2
DA		 1190 if (dev_priv->flags & RADEON_IS_PCIE)
1191 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1192 else
1193 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1194 dev_priv->gart_info.gart_table_location =
1195 DRM_ATI_GART_FB;
1196
f26c473c 1197 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
b5e89ed5
DA		 1198 dev_priv->gart_info.addr,
1199 dev_priv->pcigart_offset);
1200 } else {
f2b04cd2
DA		 1201 if (dev_priv->flags & RADEON_IS_IGPGART)
1202 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1203 else
1204 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
b5e89ed5
DA		 1205 dev_priv->gart_info.gart_table_location =
1206 DRM_ATI_GART_MAIN;
f26c473c
DA		 1207 dev_priv->gart_info.addr = NULL;
1208 dev_priv->gart_info.bus_addr = 0;
54a56ac5 1209 if (dev_priv->flags & RADEON_IS_PCIE) {
b5e89ed5
DA		 1210 DRM_ERROR
1211 ("Cannot use PCI Express without GART in FB memory\n");
ea98a92f 1212 radeon_do_cleanup_cp(dev);
20caafa6 1213 return -EINVAL;
ea98a92f
DA		 1214 }
1215 }
1216
1217 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
b5e89ed5 1218 DRM_ERROR("failed to init PCI GART!\n");
1da177e4 1219 radeon_do_cleanup_cp(dev);
20caafa6 1220 return -ENOMEM;
1da177e4
LT		 1221 }
1222
1223 /* Turn on PCI GART */
b5e89ed5 1224 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1225 }
1226
b5e89ed5 1227 radeon_cp_load_microcode(dev_priv);
3d16118d 1228 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1da177e4
LT		 1229
1230 dev_priv->last_buf = 0;
1231
b5e89ed5 1232 radeon_do_engine_reset(dev);
d5ea702f 1233 radeon_test_writeback(dev_priv);
1da177e4
LT		 1234
1235 return 0;
1236}
1237
84b1fd10 1238static int radeon_do_cleanup_cp(struct drm_device * dev)
1da177e4
LT		 1239{
1240 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1241 DRM_DEBUG("\n");
1da177e4
LT		 1242
1243 /* Make sure interrupts are disabled here because the uninstall ioctl
1244 * may not have been called from userspace and after dev_private
1245 * is freed, it's too late.
1246 */
b5e89ed5
DA		 1247 if (dev->irq_enabled)
1248 drm_irq_uninstall(dev);
1da177e4
LT		 1249
1250#if __OS_HAS_AGP
54a56ac5 1251 if (dev_priv->flags & RADEON_IS_AGP) {
d985c108 1252 if (dev_priv->cp_ring != NULL) {
b5e89ed5 1253 drm_core_ioremapfree(dev_priv->cp_ring, dev);
d985c108
DA		 1254 dev_priv->cp_ring = NULL;
1255 }
1256 if (dev_priv->ring_rptr != NULL) {
b5e89ed5 1257 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
d985c108
DA		 1258 dev_priv->ring_rptr = NULL;
1259 }
b5e89ed5
DA		 1260 if (dev->agp_buffer_map != NULL) {
1261 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1da177e4
LT		 1262 dev->agp_buffer_map = NULL;
1263 }
1264 } else
1265#endif
1266 {
d985c108
DA		 1267
1268 if (dev_priv->gart_info.bus_addr) {
1269 /* Turn off PCI GART */
1270 radeon_set_pcigart(dev_priv, 0);
ea98a92f
DA		 1271 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1272 DRM_ERROR("failed to cleanup PCI GART!\n");
d985c108 1273 }
b5e89ed5 1274
d985c108
DA		 1275 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1276 {
f26c473c 1277 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
f2b04cd2 1278 dev_priv->gart_info.addr = 0;
ea98a92f 1279 }
1da177e4 1280 }
1da177e4
LT		 1281 /* only clear to the start of flags */
1282 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1283
1284 return 0;
1285}
1286
b5e89ed5
DA		 1287/* This code will reinit the Radeon CP hardware after a resume from disc.
1288 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1da177e4
LT		 1289 * here we make sure that all Radeon hardware initialisation is re-done without
1290 * affecting running applications.
1291 *
1292 * Charl P. Botha <http://cpbotha.net>
1293 */
3d16118d 1294static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1da177e4
LT		 1295{
1296 drm_radeon_private_t *dev_priv = dev->dev_private;
1297
b5e89ed5
DA		 1298 if (!dev_priv) {
1299 DRM_ERROR("Called with no initialization\n");
20caafa6 1300 return -EINVAL;
1da177e4
LT		 1301 }
1302
1303 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1304
1305#if __OS_HAS_AGP
54a56ac5 1306 if (dev_priv->flags & RADEON_IS_AGP) {
1da177e4 1307 /* Turn off PCI GART */
b5e89ed5 1308 radeon_set_pcigart(dev_priv, 0);
1da177e4
LT		 1309 } else
1310#endif
1311 {
1312 /* Turn on PCI GART */
b5e89ed5 1313 radeon_set_pcigart(dev_priv, 1);
1da177e4
LT		 1314 }
1315
b5e89ed5 1316 radeon_cp_load_microcode(dev_priv);
3d16118d 1317 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1da177e4 1318
b5e89ed5 1319 radeon_do_engine_reset(dev);
0a3e67a4 1320 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1da177e4
LT		 1321
1322 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1323
1324 return 0;
1325}
1326
c153f45f 1327int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1328{
c153f45f 1329 drm_radeon_init_t *init = data;
1da177e4 1330
6c340eac 1331 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1332
c153f45f 1333 if (init->func == RADEON_INIT_R300_CP)
3d5e2c13 1334 r300_init_reg_flags(dev);
414ed537 1335
c153f45f 1336 switch (init->func) {
1da177e4
LT		 1337 case RADEON_INIT_CP:
1338 case RADEON_INIT_R200_CP:
1339 case RADEON_INIT_R300_CP:
7c1c2871 1340 return radeon_do_init_cp(dev, init, file_priv);
1da177e4 1341 case RADEON_CLEANUP_CP:
b5e89ed5 1342 return radeon_do_cleanup_cp(dev);
1da177e4
LT		 1343 }
1344
20caafa6 1345 return -EINVAL;
1da177e4
LT		 1346}
1347
c153f45f 1348int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1349{
1da177e4 1350 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1351 DRM_DEBUG("\n");
1da177e4 1352
6c340eac 1353 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1354
b5e89ed5 1355 if (dev_priv->cp_running) {
3e684eae 1356 DRM_DEBUG("while CP running\n");
1da177e4
LT		 1357 return 0;
1358 }
b5e89ed5 1359 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
3e684eae
MN		 1360 DRM_DEBUG("called with bogus CP mode (%d)\n",
1361 dev_priv->cp_mode);
1da177e4
LT		 1362 return 0;
1363 }
1364
b5e89ed5 1365 radeon_do_cp_start(dev_priv);
1da177e4
LT		 1366
1367 return 0;
1368}
1369
1370/* Stop the CP. The engine must have been idled before calling this
1371 * routine.
1372 */
c153f45f 1373int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1374{
1da177e4 1375 drm_radeon_private_t *dev_priv = dev->dev_private;
c153f45f 1376 drm_radeon_cp_stop_t *stop = data;
1da177e4 1377 int ret;
b5e89ed5 1378 DRM_DEBUG("\n");
1da177e4 1379
6c340eac 1380 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1381
1da177e4
LT		 1382 if (!dev_priv->cp_running)
1383 return 0;
1384
1385 /* Flush any pending CP commands. This ensures any outstanding
1386 * commands are exectuted by the engine before we turn it off.
1387 */
c153f45f 1388 if (stop->flush) {
b5e89ed5 1389 radeon_do_cp_flush(dev_priv);
1da177e4
LT		 1390 }
1391
1392 /* If we fail to make the engine go idle, we return an error
1393 * code so that the DRM ioctl wrapper can try again.
1394 */
c153f45f 1395 if (stop->idle) {
b5e89ed5
DA		 1396 ret = radeon_do_cp_idle(dev_priv);
1397 if (ret)
1398 return ret;
1da177e4
LT		 1399 }
1400
1401 /* Finally, we can turn off the CP. If the engine isn't idle,
1402 * we will get some dropped triangles as they won't be fully
1403 * rendered before the CP is shut down.
1404 */
b5e89ed5 1405 radeon_do_cp_stop(dev_priv);
1da177e4
LT		 1406
1407 /* Reset the engine */
b5e89ed5 1408 radeon_do_engine_reset(dev);
1da177e4
LT		 1409
1410 return 0;
1411}
1412
84b1fd10 1413void radeon_do_release(struct drm_device * dev)
1da177e4
LT		 1414{
1415 drm_radeon_private_t *dev_priv = dev->dev_private;
1416 int i, ret;
1417
1418 if (dev_priv) {
1419 if (dev_priv->cp_running) {
1420 /* Stop the cp */
b5e89ed5 1421 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1da177e4
LT		 1422 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1423#ifdef __linux__
1424 schedule();
1425#else
1426 tsleep(&ret, PZERO, "rdnrel", 1);
1427#endif
1428 }
b5e89ed5
DA		 1429 radeon_do_cp_stop(dev_priv);
1430 radeon_do_engine_reset(dev);
1da177e4
LT		 1431 }
1432
1433 /* Disable *all* interrupts */
1434 if (dev_priv->mmio) /* remove this after permanent addmaps */
b5e89ed5 1435 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1da177e4 1436
b5e89ed5 1437 if (dev_priv->mmio) { /* remove all surfaces */
1da177e4 1438 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
b5e89ed5
DA		 1439 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1440 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1441 16 * i, 0);
1442 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1443 16 * i, 0);
1da177e4
LT		 1444 }
1445 }
1446
1447 /* Free memory heap structures */
b5e89ed5
DA		 1448 radeon_mem_takedown(&(dev_priv->gart_heap));
1449 radeon_mem_takedown(&(dev_priv->fb_heap));
1da177e4
LT		 1450
1451 /* deallocate kernel resources */
b5e89ed5 1452 radeon_do_cleanup_cp(dev);
1da177e4
LT		 1453 }
1454}
1455
1456/* Just reset the CP ring. Called as part of an X Server engine reset.
1457 */
c153f45f 1458int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1459{
1da177e4 1460 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1461 DRM_DEBUG("\n");
1da177e4 1462
6c340eac 1463 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1464
b5e89ed5 1465 if (!dev_priv) {
3e684eae 1466 DRM_DEBUG("called before init done\n");
20caafa6 1467 return -EINVAL;
1da177e4
LT		 1468 }
1469
b5e89ed5 1470 radeon_do_cp_reset(dev_priv);
1da177e4
LT		 1471
1472 /* The CP is no longer running after an engine reset */
1473 dev_priv->cp_running = 0;
1474
1475 return 0;
1476}
1477
c153f45f 1478int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1479{
1da177e4 1480 drm_radeon_private_t *dev_priv = dev->dev_private;
b5e89ed5 1481 DRM_DEBUG("\n");
1da177e4 1482
6c340eac 1483 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1484
b5e89ed5 1485 return radeon_do_cp_idle(dev_priv);
1da177e4
LT		 1486}
1487
1488/* Added by Charl P. Botha to call radeon_do_resume_cp().
1489 */
c153f45f 1490int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1491{
3d16118d 1492 return radeon_do_resume_cp(dev, file_priv);
1da177e4
LT		 1493}
1494
c153f45f 1495int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1496{
b5e89ed5 1497 DRM_DEBUG("\n");
1da177e4 1498
6c340eac 1499 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1500
b5e89ed5 1501 return radeon_do_engine_reset(dev);
1da177e4
LT		 1502}
1503
1da177e4
LT		 1504/* ================================================================
1505 * Fullscreen mode
1506 */
1507
1508/* KW: Deprecated to say the least:
1509 */
c153f45f 1510int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4
LT		 1511{
1512 return 0;
1513}
1514
1da177e4
LT		 1515/* ================================================================
1516 * Freelist management
1517 */
1518
1519/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1520 * bufs until freelist code is used. Note this hides a problem with
1521 * the scratch register * (used to keep track of last buffer
1522 * completed) being written to before * the last buffer has actually
b5e89ed5 1523 * completed rendering.
1da177e4
LT		 1524 *
1525 * KW: It's also a good way to find free buffers quickly.
1526 *
1527 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1528 * sleep. However, bugs in older versions of radeon_accel.c mean that
1529 * we essentially have to do this, else old clients will break.
b5e89ed5 1530 *
1da177e4
LT		 1531 * However, it does leave open a potential deadlock where all the
1532 * buffers are held by other clients, which can't release them because
b5e89ed5 1533 * they can't get the lock.
1da177e4
LT		 1534 */
1535
056219e2 1536struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 1537{
cdd55a29 1538 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1539 drm_radeon_private_t *dev_priv = dev->dev_private;
1540 drm_radeon_buf_priv_t *buf_priv;
056219e2 1541 struct drm_buf *buf;
1da177e4
LT		 1542 int i, t;
1543 int start;
1544
b5e89ed5 1545 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1546 dev_priv->last_buf = 0;
1547
1548 start = dev_priv->last_buf;
1549
b5e89ed5
DA		 1550 for (t = 0; t < dev_priv->usec_timeout; t++) {
1551 u32 done_age = GET_SCRATCH(1);
1552 DRM_DEBUG("done_age = %d\n", done_age);
1553 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1554 buf = dma->buflist[i];
1555 buf_priv = buf->dev_private;
6c340eac
EA		 1556 if (buf->file_priv == NULL || (buf->pending &&
1557 buf_priv->age <=
1558 done_age)) {
1da177e4
LT		 1559 dev_priv->stats.requested_bufs++;
1560 buf->pending = 0;
1561 return buf;
1562 }
1563 start = 0;
1564 }
1565
1566 if (t) {
b5e89ed5 1567 DRM_UDELAY(1);
1da177e4
LT		 1568 dev_priv->stats.freelist_loops++;
1569 }
1570 }
1571
b5e89ed5 1572 DRM_DEBUG("returning NULL!\n");
1da177e4
LT		 1573 return NULL;
1574}
b5e89ed5 1575
1da177e4 1576#if 0
056219e2 1577struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1da177e4 1578{
cdd55a29 1579 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1580 drm_radeon_private_t *dev_priv = dev->dev_private;
1581 drm_radeon_buf_priv_t *buf_priv;
056219e2 1582 struct drm_buf *buf;
1da177e4
LT		 1583 int i, t;
1584 int start;
1585 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1586
b5e89ed5 1587 if (++dev_priv->last_buf >= dma->buf_count)
1da177e4
LT		 1588 dev_priv->last_buf = 0;
1589
1590 start = dev_priv->last_buf;
1591 dev_priv->stats.freelist_loops++;
b5e89ed5
DA		 1592
1593 for (t = 0; t < 2; t++) {
1594 for (i = start; i < dma->buf_count; i++) {
1da177e4
LT		 1595 buf = dma->buflist[i];
1596 buf_priv = buf->dev_private;
6c340eac
EA		 1597 if (buf->file_priv == 0 || (buf->pending &&
1598 buf_priv->age <=
1599 done_age)) {
1da177e4
LT		 1600 dev_priv->stats.requested_bufs++;
1601 buf->pending = 0;
1602 return buf;
1603 }
1604 }
1605 start = 0;
1606 }
1607
1608 return NULL;
1609}
1610#endif
1611
84b1fd10 1612void radeon_freelist_reset(struct drm_device * dev)
1da177e4 1613{
cdd55a29 1614 struct drm_device_dma *dma = dev->dma;
1da177e4
LT		 1615 drm_radeon_private_t *dev_priv = dev->dev_private;
1616 int i;
1617
1618 dev_priv->last_buf = 0;
b5e89ed5 1619 for (i = 0; i < dma->buf_count; i++) {
056219e2 1620 struct drm_buf *buf = dma->buflist[i];
1da177e4
LT		 1621 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1622 buf_priv->age = 0;
1623 }
1624}
1625
1da177e4
LT		 1626/* ================================================================
1627 * CP command submission
1628 */
1629
b5e89ed5 1630int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1da177e4
LT		 1631{
1632 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1633 int i;
b5e89ed5 1634 u32 last_head = GET_RING_HEAD(dev_priv);
1da177e4 1635
b5e89ed5
DA		 1636 for (i = 0; i < dev_priv->usec_timeout; i++) {
1637 u32 head = GET_RING_HEAD(dev_priv);
1da177e4
LT		 1638
1639 ring->space = (head - ring->tail) * sizeof(u32);
b5e89ed5 1640 if (ring->space <= 0)
1da177e4 1641 ring->space += ring->size;
b5e89ed5 1642 if (ring->space > n)
1da177e4 1643 return 0;
b5e89ed5 1644
1da177e4
LT		 1645 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1646
1647 if (head != last_head)
1648 i = 0;
1649 last_head = head;
1650
b5e89ed5 1651 DRM_UDELAY(1);
1da177e4
LT		 1652 }
1653
1654 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1655#if RADEON_FIFO_DEBUG
b5e89ed5
DA		 1656 radeon_status(dev_priv);
1657 DRM_ERROR("failed!\n");
1da177e4 1658#endif
20caafa6 1659 return -EBUSY;
1da177e4
LT		 1660}
1661
6c340eac
EA		 1662static int radeon_cp_get_buffers(struct drm_device *dev,
1663 struct drm_file *file_priv,
c60ce623 1664 struct drm_dma * d)
1da177e4
LT		 1665{
1666 int i;
056219e2 1667 struct drm_buf *buf;
1da177e4 1668
b5e89ed5
DA		 1669 for (i = d->granted_count; i < d->request_count; i++) {
1670 buf = radeon_freelist_get(dev);
1671 if (!buf)
20caafa6 1672 return -EBUSY; /* NOTE: broken client */
1da177e4 1673
6c340eac 1674 buf->file_priv = file_priv;
1da177e4 1675
b5e89ed5
DA		 1676 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1677 sizeof(buf->idx)))
20caafa6 1678 return -EFAULT;
b5e89ed5
DA		 1679 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1680 sizeof(buf->total)))
20caafa6 1681 return -EFAULT;
1da177e4
LT		 1682
1683 d->granted_count++;
1684 }
1685 return 0;
1686}
1687
c153f45f 1688int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1da177e4 1689{
cdd55a29 1690 struct drm_device_dma *dma = dev->dma;
1da177e4 1691 int ret = 0;
c153f45f 1692 struct drm_dma *d = data;
1da177e4 1693
6c340eac 1694 LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 1695
1da177e4
LT		 1696 /* Please don't send us buffers.
1697 */
c153f45f 1698 if (d->send_count != 0) {
b5e89ed5 1699 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
c153f45f 1700 DRM_CURRENTPID, d->send_count);
20caafa6 1701 return -EINVAL;
1da177e4
LT		 1702 }
1703
1704 /* We'll send you buffers.
1705 */
c153f45f 1706 if (d->request_count < 0 || d->request_count > dma->buf_count) {
b5e89ed5 1707 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
c153f45f 1708 DRM_CURRENTPID, d->request_count, dma->buf_count);
20caafa6 1709 return -EINVAL;
1da177e4
LT		 1710 }
1711
c153f45f 1712 d->granted_count = 0;
1da177e4 1713
c153f45f
EA		 1714 if (d->request_count) {
1715 ret = radeon_cp_get_buffers(dev, file_priv, d);
1da177e4
LT		 1716 }
1717
1da177e4
LT		 1718 return ret;
1719}
1720
22eae947 1721int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1da177e4
LT		 1722{
1723 drm_radeon_private_t *dev_priv;
1724 int ret = 0;
1725
1726 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1727 if (dev_priv == NULL)
20caafa6 1728 return -ENOMEM;
1da177e4
LT		 1729
1730 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1731 dev->dev_private = (void *)dev_priv;
1732 dev_priv->flags = flags;
1733
54a56ac5 1734 switch (flags & RADEON_FAMILY_MASK) {
1da177e4
LT		 1735 case CHIP_R100:
1736 case CHIP_RV200:
1737 case CHIP_R200:
1738 case CHIP_R300:
b15ec368 1739 case CHIP_R350:
414ed537 1740 case CHIP_R420:
edc6f389 1741 case CHIP_R423:
b15ec368 1742 case CHIP_RV410:
3d5e2c13
DA		 1743 case CHIP_RV515:
1744 case CHIP_R520:
1745 case CHIP_RV570:
1746 case CHIP_R580:
54a56ac5 1747 dev_priv->flags |= RADEON_HAS_HIERZ;
1da177e4
LT		 1748 break;
1749 default:
b5e89ed5 1750 /* all other chips have no hierarchical z buffer */
1da177e4
LT		 1751 break;
1752 }
414ed537
DA		 1753
1754 if (drm_device_is_agp(dev))
54a56ac5 1755 dev_priv->flags |= RADEON_IS_AGP;
b15ec368 1756 else if (drm_device_is_pcie(dev))
54a56ac5 1757 dev_priv->flags |= RADEON_IS_PCIE;
b15ec368 1758 else
54a56ac5 1759 dev_priv->flags |= RADEON_IS_PCI;
ea98a92f 1760
78538bf1
DA		 1761 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1762 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1763 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1764 if (ret != 0)
1765 return ret;
1766
52440211
KP		 1767 ret = drm_vblank_init(dev, 2);
1768 if (ret) {
1769 radeon_driver_unload(dev);
1770 return ret;
1771 }
1772
414ed537 1773 DRM_DEBUG("%s card detected\n",
54a56ac5 1774 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1da177e4
LT		 1775 return ret;
1776}
1777
7c1c2871
DA		 1778int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1779{
1780 struct drm_radeon_master_private *master_priv;
1781 unsigned long sareapage;
1782 int ret;
1783
1784 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1785 if (!master_priv)
1786 return -ENOMEM;
1787
1788 /* prebuild the SAREA */
bdf539ad 1789 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
7c1c2871
DA		 1790 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1791 &master_priv->sarea);
1792 if (ret) {
1793 DRM_ERROR("SAREA setup failed\n");
1794 return ret;
1795 }
1796 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1797 master_priv->sarea_priv->pfCurrentPage = 0;
1798
1799 master->driver_priv = master_priv;
1800 return 0;
1801}
1802
1803void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1804{
1805 struct drm_radeon_master_private *master_priv = master->driver_priv;
1806
1807 if (!master_priv)
1808 return;
1809
1810 if (master_priv->sarea_priv &&
1811 master_priv->sarea_priv->pfCurrentPage != 0)
1812 radeon_cp_dispatch_flip(dev, master);
1813
1814 master_priv->sarea_priv = NULL;
1815 if (master_priv->sarea)
4e74f36d 1816 drm_rmmap_locked(dev, master_priv->sarea);
7c1c2871
DA		 1817
1818 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1819
1820 master->driver_priv = NULL;
1821}
1822
22eae947
DA		 1823/* Create mappings for registers and framebuffer so userland doesn't necessarily
1824 * have to find them.
1825 */
1826int radeon_driver_firstopen(struct drm_device *dev)
836cf046
DA		 1827{
1828 int ret;
1829 drm_local_map_t *map;
1830 drm_radeon_private_t *dev_priv = dev->dev_private;
1831
f2b04cd2
DA		 1832 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1833
7fc86860
DA		 1834 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1835 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
836cf046
DA		 1836 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1837 _DRM_WRITE_COMBINING, &map);
1838 if (ret != 0)
1839 return ret;
1840
1841 return 0;
1842}
1843
22eae947 1844int radeon_driver_unload(struct drm_device *dev)
1da177e4
LT		 1845{
1846 drm_radeon_private_t *dev_priv = dev->dev_private;
1847
1848 DRM_DEBUG("\n");
78538bf1
DA		 1849
1850 drm_rmmap(dev, dev_priv->mmio);
1851
1da177e4
LT		 1852 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1853
1854 dev->dev_private = NULL;
1855 return 0;
1856}
Linux 6.x block layer and io_uring tree(s)