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drm/radeon: assign pin in detect
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_audio.c
CommitLineData
bfc1f97d
SG		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Slava Grigorev <slava.grigorev@amd.com>
23 */
24
64424d6e 25#include <linux/gcd.h>
bfc1f97d 26#include <drm/drmP.h>
1a626b68 27#include <drm/drm_crtc.h>
bfc1f97d 28#include "radeon.h"
1a626b68
SG		 29#include "atom.h"
30#include "radeon_audio.h"
bfc1f97d
SG		 31
32void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
33 u8 enable_mask);
8bf59820
SG		 34void dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
35 u8 enable_mask);
bfc1f97d
SG		 36void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
37 u8 enable_mask);
1a626b68
SG		 38u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);
39void dce6_endpoint_wreg(struct radeon_device *rdev,
40 u32 offset, u32 reg, u32 v);
070a2e63
AD		 41void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
42 struct cea_sad *sads, int sad_count);
43void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
44 struct cea_sad *sads, int sad_count);
45void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
46 struct cea_sad *sads, int sad_count);
00a9d4bc
SG		 47void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
48 u8 *sadb, int sad_count);
49void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
50 u8 *sadb, int sad_count);
51void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
52 u8 *sadb, int sad_count);
53void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
54 u8 *sadb, int sad_count);
55void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
56 u8 *sadb, int sad_count);
57void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
58 u8 *sadb, int sad_count);
87654f87
SG		 59void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
60 struct drm_connector *connector, struct drm_display_mode *mode);
61void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
62 struct drm_connector *connector, struct drm_display_mode *mode);
3cdde027
SG		 63struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev);
64struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev);
88252d77 65void dce6_afmt_select_pin(struct drm_encoder *encoder);
a85d682a
SG		 66void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
67 struct radeon_crtc *crtc, unsigned int clock);
68void dce3_2_audio_set_dto(struct radeon_device *rdev,
69 struct radeon_crtc *crtc, unsigned int clock);
70void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
71 struct radeon_crtc *crtc, unsigned int clock);
72void dce4_dp_audio_set_dto(struct radeon_device *rdev,
73 struct radeon_crtc *crtc, unsigned int clock);
74void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
75 struct radeon_crtc *crtc, unsigned int clock);
76void dce6_dp_audio_set_dto(struct radeon_device *rdev,
77 struct radeon_crtc *crtc, unsigned int clock);
baa7d8e4 78void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
96ea7afb 79 unsigned char *buffer, size_t size);
baa7d8e4 80void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
96ea7afb 81 unsigned char *buffer, size_t size);
64424d6e
SG		 82void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
83 const struct radeon_hdmi_acr *acr);
84void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
85 const struct radeon_hdmi_acr *acr);
86void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
87 const struct radeon_hdmi_acr *acr);
930a9785
AD		 88void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset);
89void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);
be273e58
SG		 90void dce4_hdmi_set_color_depth(struct drm_encoder *encoder,
91 u32 offset, int bpc);
1852c9a0
SG		 92void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset);
93void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset);
94void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);
3be2e7d0
SG		 95void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
96void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
97void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
6e72376d
SG		 98static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder,
99 struct drm_display_mode *mode);
e55bca26
SG		 100static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
101 struct drm_display_mode *mode);
6f945693
SG		 102void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
103void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
add7d759
AD		 104void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);
105void dce6_dp_enable(struct drm_encoder *encoder, bool enable);
bfc1f97d
SG		 106
107static const u32 pin_offsets[7] =
108{
109 (0x5e00 - 0x5e00),
110 (0x5e18 - 0x5e00),
111 (0x5e30 - 0x5e00),
112 (0x5e48 - 0x5e00),
113 (0x5e60 - 0x5e00),
114 (0x5e78 - 0x5e00),
115 (0x5e90 - 0x5e00),
116};
117
1a626b68
SG		 118static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
119{
120 return RREG32(reg);
121}
122
123static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset,
124 u32 reg, u32 v)
125{
126 WREG32(reg, v);
127}
128
a85d682a
SG		 129static struct radeon_audio_basic_funcs r600_funcs = {
130 .endpoint_rreg = radeon_audio_rreg,
131 .endpoint_wreg = radeon_audio_wreg,
132 .enable = r600_audio_enable,
133};
134
1a626b68
SG		 135static struct radeon_audio_basic_funcs dce32_funcs = {
136 .endpoint_rreg = radeon_audio_rreg,
137 .endpoint_wreg = radeon_audio_wreg,
8bf59820 138 .enable = r600_audio_enable,
1a626b68
SG		 139};
140
141static struct radeon_audio_basic_funcs dce4_funcs = {
142 .endpoint_rreg = radeon_audio_rreg,
143 .endpoint_wreg = radeon_audio_wreg,
8bf59820 144 .enable = dce4_audio_enable,
1a626b68
SG		 145};
146
147static struct radeon_audio_basic_funcs dce6_funcs = {
148 .endpoint_rreg = dce6_endpoint_rreg,
149 .endpoint_wreg = dce6_endpoint_wreg,
8bf59820 150 .enable = dce6_audio_enable,
1a626b68
SG		 151};
152
a85d682a
SG		 153static struct radeon_audio_funcs r600_hdmi_funcs = {
154 .get_pin = r600_audio_get_pin,
155 .set_dto = r600_hdmi_audio_set_dto,
64424d6e 156 .update_acr = r600_hdmi_update_acr,
930a9785 157 .set_vbi_packet = r600_set_vbi_packet,
baa7d8e4 158 .set_avi_packet = r600_set_avi_packet,
1852c9a0 159 .set_audio_packet = r600_set_audio_packet,
3be2e7d0 160 .set_mute = r600_set_mute,
6e72376d 161 .mode_set = radeon_audio_hdmi_mode_set,
6f945693 162 .dpms = r600_hdmi_enable,
a85d682a
SG		 163};
164
070a2e63 165static struct radeon_audio_funcs dce32_hdmi_funcs = {
3cdde027 166 .get_pin = r600_audio_get_pin,
070a2e63 167 .write_sad_regs = dce3_2_afmt_write_sad_regs,
00a9d4bc 168 .write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation,
a85d682a 169 .set_dto = dce3_2_audio_set_dto,
64424d6e 170 .update_acr = dce3_2_hdmi_update_acr,
930a9785 171 .set_vbi_packet = r600_set_vbi_packet,
baa7d8e4 172 .set_avi_packet = r600_set_avi_packet,
1852c9a0 173 .set_audio_packet = dce3_2_set_audio_packet,
3be2e7d0 174 .set_mute = dce3_2_set_mute,
6e72376d 175 .mode_set = radeon_audio_hdmi_mode_set,
6f945693 176 .dpms = r600_hdmi_enable,
070a2e63
AD		 177};
178
179static struct radeon_audio_funcs dce32_dp_funcs = {
3cdde027 180 .get_pin = r600_audio_get_pin,
070a2e63 181 .write_sad_regs = dce3_2_afmt_write_sad_regs,
00a9d4bc 182 .write_speaker_allocation = dce3_2_afmt_dp_write_speaker_allocation,
a85d682a 183 .set_dto = dce3_2_audio_set_dto,
baa7d8e4 184 .set_avi_packet = r600_set_avi_packet,
e55bca26 185 .set_audio_packet = dce3_2_set_audio_packet,
070a2e63
AD		 186};
187
188static struct radeon_audio_funcs dce4_hdmi_funcs = {
3cdde027 189 .get_pin = r600_audio_get_pin,
070a2e63 190 .write_sad_regs = evergreen_hdmi_write_sad_regs,
00a9d4bc 191 .write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation,
87654f87 192 .write_latency_fields = dce4_afmt_write_latency_fields,
a85d682a 193 .set_dto = dce4_hdmi_audio_set_dto,
64424d6e 194 .update_acr = evergreen_hdmi_update_acr,
930a9785 195 .set_vbi_packet = dce4_set_vbi_packet,
be273e58 196 .set_color_depth = dce4_hdmi_set_color_depth,
baa7d8e4 197 .set_avi_packet = evergreen_set_avi_packet,
1852c9a0 198 .set_audio_packet = dce4_set_audio_packet,
3be2e7d0 199 .set_mute = dce4_set_mute,
6e72376d 200 .mode_set = radeon_audio_hdmi_mode_set,
6f945693 201 .dpms = evergreen_hdmi_enable,
070a2e63
AD		 202};
203
204static struct radeon_audio_funcs dce4_dp_funcs = {
3cdde027 205 .get_pin = r600_audio_get_pin,
070a2e63 206 .write_sad_regs = evergreen_hdmi_write_sad_regs,
00a9d4bc 207 .write_speaker_allocation = dce4_afmt_dp_write_speaker_allocation,
87654f87 208 .write_latency_fields = dce4_afmt_write_latency_fields,
a85d682a 209 .set_dto = dce4_dp_audio_set_dto,
baa7d8e4 210 .set_avi_packet = evergreen_set_avi_packet,
e55bca26
SG		 211 .set_audio_packet = dce4_set_audio_packet,
212 .mode_set = radeon_audio_dp_mode_set,
add7d759 213 .dpms = evergreen_dp_enable,
070a2e63
AD		 214};
215
216static struct radeon_audio_funcs dce6_hdmi_funcs = {
88252d77 217 .select_pin = dce6_afmt_select_pin,
3cdde027 218 .get_pin = dce6_audio_get_pin,
070a2e63 219 .write_sad_regs = dce6_afmt_write_sad_regs,
00a9d4bc 220 .write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation,
87654f87 221 .write_latency_fields = dce6_afmt_write_latency_fields,
a85d682a 222 .set_dto = dce6_hdmi_audio_set_dto,
64424d6e 223 .update_acr = evergreen_hdmi_update_acr,
930a9785 224 .set_vbi_packet = dce4_set_vbi_packet,
be273e58 225 .set_color_depth = dce4_hdmi_set_color_depth,
baa7d8e4 226 .set_avi_packet = evergreen_set_avi_packet,
1852c9a0 227 .set_audio_packet = dce4_set_audio_packet,
3be2e7d0 228 .set_mute = dce4_set_mute,
6e72376d 229 .mode_set = radeon_audio_hdmi_mode_set,
6f945693 230 .dpms = evergreen_hdmi_enable,
070a2e63
AD		 231};
232
233static struct radeon_audio_funcs dce6_dp_funcs = {
88252d77 234 .select_pin = dce6_afmt_select_pin,
3cdde027 235 .get_pin = dce6_audio_get_pin,
070a2e63 236 .write_sad_regs = dce6_afmt_write_sad_regs,
00a9d4bc 237 .write_speaker_allocation = dce6_afmt_dp_write_speaker_allocation,
87654f87 238 .write_latency_fields = dce6_afmt_write_latency_fields,
a85d682a 239 .set_dto = dce6_dp_audio_set_dto,
baa7d8e4 240 .set_avi_packet = evergreen_set_avi_packet,
e55bca26
SG		 241 .set_audio_packet = dce4_set_audio_packet,
242 .mode_set = radeon_audio_dp_mode_set,
add7d759 243 .dpms = dce6_dp_enable,
070a2e63
AD		 244};
245
1a626b68
SG		 246static void radeon_audio_interface_init(struct radeon_device *rdev)
247{
248 if (ASIC_IS_DCE6(rdev)) {
249 rdev->audio.funcs = &dce6_funcs;
070a2e63
AD		 250 rdev->audio.hdmi_funcs = &dce6_hdmi_funcs;
251 rdev->audio.dp_funcs = &dce6_dp_funcs;
1a626b68
SG		 252 } else if (ASIC_IS_DCE4(rdev)) {
253 rdev->audio.funcs = &dce4_funcs;
070a2e63
AD		 254 rdev->audio.hdmi_funcs = &dce4_hdmi_funcs;
255 rdev->audio.dp_funcs = &dce4_dp_funcs;
a85d682a 256 } else if (ASIC_IS_DCE32(rdev)) {
1a626b68 257 rdev->audio.funcs = &dce32_funcs;
070a2e63
AD		 258 rdev->audio.hdmi_funcs = &dce32_hdmi_funcs;
259 rdev->audio.dp_funcs = &dce32_dp_funcs;
a85d682a
SG		 260 } else {
261 rdev->audio.funcs = &r600_funcs;
262 rdev->audio.hdmi_funcs = &r600_hdmi_funcs;
263 rdev->audio.dp_funcs = 0;
1a626b68
SG		 264 }
265}
266
bfc1f97d
SG		 267static int radeon_audio_chipset_supported(struct radeon_device *rdev)
268{
269 return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev);
270}
271
272int radeon_audio_init(struct radeon_device *rdev)
273{
274 int i;
275
276 if (!radeon_audio || !radeon_audio_chipset_supported(rdev))
277 return 0;
278
279 rdev->audio.enabled = true;
280
281 if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
282 rdev->audio.num_pins = 3;
283 else if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */
284 rdev->audio.num_pins = 7;
285 else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */
286 rdev->audio.num_pins = 7;
287 else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */
288 rdev->audio.num_pins = 2;
289 else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */
290 rdev->audio.num_pins = 6;
291 else if (ASIC_IS_DCE6(rdev)) /* SI: 6 streams, 6 endpoints */
292 rdev->audio.num_pins = 6;
293 else
294 rdev->audio.num_pins = 1;
295
296 for (i = 0; i < rdev->audio.num_pins; i++) {
297 rdev->audio.pin[i].channels = -1;
298 rdev->audio.pin[i].rate = -1;
299 rdev->audio.pin[i].bits_per_sample = -1;
300 rdev->audio.pin[i].status_bits = 0;
301 rdev->audio.pin[i].category_code = 0;
302 rdev->audio.pin[i].connected = false;
303 rdev->audio.pin[i].offset = pin_offsets[i];
304 rdev->audio.pin[i].id = i;
1a626b68
SG		 305 }
306
307 radeon_audio_interface_init(rdev);
308
309 /* disable audio. it will be set up later */
310 for (i = 0; i < rdev->audio.num_pins; i++)
8bf59820 311 radeon_audio_enable(rdev, &rdev->audio.pin[i], false);
1a626b68
SG		 312
313 return 0;
314}
315
1a626b68
SG		 316u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
317{
318 if (rdev->audio.funcs->endpoint_rreg)
319 return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg);
bfc1f97d
SG		 320
321 return 0;
322}
1a626b68
SG		 323
324void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset,
325 u32 reg, u32 v)
326{
327 if (rdev->audio.funcs->endpoint_wreg)
328 rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);
329}
070a2e63 330
6e72376d 331static void radeon_audio_write_sad_regs(struct drm_encoder *encoder)
070a2e63
AD		 332{
333 struct radeon_encoder *radeon_encoder;
334 struct drm_connector *connector;
335 struct radeon_connector *radeon_connector = NULL;
336 struct cea_sad *sads;
337 int sad_count;
338
339 list_for_each_entry(connector,
340 &encoder->dev->mode_config.connector_list, head) {
341 if (connector->encoder == encoder) {
342 radeon_connector = to_radeon_connector(connector);
343 break;
344 }
345 }
346
347 if (!radeon_connector) {
348 DRM_ERROR("Couldn't find encoder's connector\n");
349 return;
350 }
351
352 sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads);
353 if (sad_count <= 0) {
354 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
355 return;
356 }
357 BUG_ON(!sads);
358
359 radeon_encoder = to_radeon_encoder(encoder);
360
361 if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs)
362 radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count);
363
364 kfree(sads);
365}
00a9d4bc 366
6e72376d 367static void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder)
00a9d4bc
SG		 368{
369 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f4c6c081
AD		 370 struct drm_connector *connector;
371 struct radeon_connector *radeon_connector = NULL;
372 u8 *sadb = NULL;
373 int sad_count;
00a9d4bc 374
f4c6c081
AD		 375 list_for_each_entry(connector,
376 &encoder->dev->mode_config.connector_list, head) {
377 if (connector->encoder == encoder) {
378 radeon_connector = to_radeon_connector(connector);
379 break;
380 }
381 }
382
383 if (!radeon_connector) {
384 DRM_ERROR("Couldn't find encoder's connector\n");
385 return;
386 }
387
388 sad_count = drm_edid_to_speaker_allocation(
00a9d4bc 389 radeon_connector_edid(connector), &sadb);
f4c6c081
AD		 390 if (sad_count < 0) {
391 DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n",
392 sad_count);
393 sad_count = 0;
394 }
00a9d4bc
SG		 395
396 if (radeon_encoder->audio && radeon_encoder->audio->write_speaker_allocation)
397 radeon_encoder->audio->write_speaker_allocation(encoder, sadb, sad_count);
398
f4c6c081 399 kfree(sadb);
00a9d4bc 400}
87654f87 401
6e72376d 402static void radeon_audio_write_latency_fields(struct drm_encoder *encoder,
87654f87
SG		 403 struct drm_display_mode *mode)
404{
405 struct radeon_encoder *radeon_encoder;
406 struct drm_connector *connector;
407 struct radeon_connector *radeon_connector = 0;
408
409 list_for_each_entry(connector,
410 &encoder->dev->mode_config.connector_list, head) {
411 if (connector->encoder == encoder) {
412 radeon_connector = to_radeon_connector(connector);
413 break;
414 }
415 }
416
417 if (!radeon_connector) {
418 DRM_ERROR("Couldn't find encoder's connector\n");
419 return;
420 }
421
422 radeon_encoder = to_radeon_encoder(encoder);
423
424 if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields)
425 radeon_encoder->audio->write_latency_fields(encoder, connector, mode);
426}
3cdde027
SG		 427
428struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder *encoder)
429{
430 struct radeon_device *rdev = encoder->dev->dev_private;
431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
432
433 if (radeon_encoder->audio && radeon_encoder->audio->get_pin)
434 return radeon_encoder->audio->get_pin(rdev);
435
436 return NULL;
437}
88252d77 438
6e72376d 439static void radeon_audio_select_pin(struct drm_encoder *encoder)
88252d77
SG		 440{
441 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
442
443 if (radeon_encoder->audio && radeon_encoder->audio->select_pin)
444 radeon_encoder->audio->select_pin(encoder);
445}
8bf59820
SG		 446
447void radeon_audio_enable(struct radeon_device *rdev,
448 struct r600_audio_pin *pin, u8 enable_mask)
449{
450 if (rdev->audio.funcs->enable)
451 rdev->audio.funcs->enable(rdev, pin, enable_mask);
452}
7991d665 453
ccd4be7e 454void radeon_audio_detect(struct drm_connector *connector,
d3c34d2c 455 enum drm_connector_status status)
ccd4be7e
SG		 456{
457 struct radeon_device *rdev;
458 struct radeon_encoder *radeon_encoder;
459 struct radeon_encoder_atom_dig *dig;
460
461 if (!connector || !connector->encoder)
462 return;
463
464 rdev = connector->encoder->dev->dev_private;
465 radeon_encoder = to_radeon_encoder(connector->encoder);
466 dig = radeon_encoder->enc_priv;
467
468 if (status == connector_status_connected) {
469 struct radeon_connector *radeon_connector;
470 int sink_type;
471
472 if (!drm_detect_monitor_audio(radeon_connector_edid(connector))) {
308de41b 473 radeon_encoder->audio = NULL;
ccd4be7e
SG		 474 return;
475 }
476
477 radeon_connector = to_radeon_connector(connector);
478 sink_type = radeon_dp_getsinktype(radeon_connector);
479
480 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
481 sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
482 radeon_encoder->audio = rdev->audio.dp_funcs;
483 else
484 radeon_encoder->audio = rdev->audio.hdmi_funcs;
485
d3c34d2c 486 dig->afmt->pin = radeon_audio_get_pin(connector->encoder);
ccd4be7e
SG		 487 radeon_audio_write_speaker_allocation(connector->encoder);
488 radeon_audio_write_sad_regs(connector->encoder);
489 if (connector->encoder->crtc)
490 radeon_audio_write_latency_fields(connector->encoder,
491 &connector->encoder->crtc->mode);
492 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
493 } else {
494 radeon_audio_enable(rdev, dig->afmt->pin, 0);
d3c34d2c 495 dig->afmt->pin = NULL;
ccd4be7e
SG		 496 }
497}
498
7991d665
SG		 499void radeon_audio_fini(struct radeon_device *rdev)
500{
501 int i;
502
503 if (!rdev->audio.enabled)
504 return;
505
506 for (i = 0; i < rdev->audio.num_pins; i++)
507 radeon_audio_enable(rdev, &rdev->audio.pin[i], false);
508
509 rdev->audio.enabled = false;
510}
a85d682a 511
6e72376d 512static void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock)
a85d682a
SG		 513{
514 struct radeon_device *rdev = encoder->dev->dev_private;
515 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
516 struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc);
517
518 if (radeon_encoder->audio && radeon_encoder->audio->set_dto)
519 radeon_encoder->audio->set_dto(rdev, crtc, clock);
520}
96ea7afb 521
6e72376d 522static int radeon_audio_set_avi_packet(struct drm_encoder *encoder,
baa7d8e4 523 struct drm_display_mode *mode)
96ea7afb 524{
f4c6c081 525 struct radeon_device *rdev = encoder->dev->dev_private;
96ea7afb
SG		 526 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
527 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
baa7d8e4
SG		 528 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
529 struct hdmi_avi_infoframe frame;
530 int err;
531
532 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
533 if (err < 0) {
534 DRM_ERROR("failed to setup AVI infoframe: %d\n", err);
535 return err;
536 }
537
538 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
539 if (err < 0) {
540 DRM_ERROR("failed to pack AVI infoframe: %d\n", err);
541 return err;
542 }
543
544 if (dig && dig->afmt &&
545 radeon_encoder->audio && radeon_encoder->audio->set_avi_packet)
546 radeon_encoder->audio->set_avi_packet(rdev, dig->afmt->offset,
547 buffer, sizeof(buffer));
96ea7afb 548
baa7d8e4 549 return 0;
96ea7afb 550}
64424d6e
SG		 551
552/*
553 * calculate CTS and N values if they are not found in the table
554 */
555static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq)
556{
557 int n, cts;
558 unsigned long div, mul;
559
560 /* Safe, but overly large values */
561 n = 128 * freq;
562 cts = clock * 1000;
563
564 /* Smallest valid fraction */
565 div = gcd(n, cts);
566
567 n /= div;
568 cts /= div;
569
570 /*
571 * The optimal N is 128*freq/1000. Calculate the closest larger
572 * value that doesn't truncate any bits.
573 */
574 mul = ((128*freq/1000) + (n-1))/n;
575
576 n *= mul;
577 cts *= mul;
578
579 /* Check that we are in spec (not always possible) */
580 if (n < (128*freq/1500))
581 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
582 if (n > (128*freq/300))
583 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
584
585 *N = n;
586 *CTS = cts;
587
588 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
589 *N, *CTS, freq);
590}
591
592static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock)
593{
594 static struct radeon_hdmi_acr res;
595 u8 i;
596
597 static const struct radeon_hdmi_acr hdmi_predefined_acr[] = {
598 /* 32kHz 44.1kHz 48kHz */
599 /* Clock N CTS N CTS N CTS */
600 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
601 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
602 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
603 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
604 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
605 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
606 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
607 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
608 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
609 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
610 };
611
612 /* Precalculated values for common clocks */
613 for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++)
614 if (hdmi_predefined_acr[i].clock == clock)
615 return &hdmi_predefined_acr[i];
616
617 /* And odd clocks get manually calculated */
618 radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
619 radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
620 radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
621
622 return &res;
623}
624
625/*
626 * update the N and CTS parameters for a given pixel clock rate
627 */
6e72376d 628static void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock)
64424d6e 629{
f4c6c081
AD		 630 const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock);
631 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
64424d6e
SG		 633
634 if (!dig || !dig->afmt)
635 return;
636
637 if (radeon_encoder->audio && radeon_encoder->audio->update_acr)
638 radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr);
639}
930a9785 640
6e72376d 641static void radeon_audio_set_vbi_packet(struct drm_encoder *encoder)
930a9785 642{
f4c6c081
AD		 643 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
644 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
930a9785
AD		 645
646 if (!dig || !dig->afmt)
647 return;
648
649 if (radeon_encoder->audio && radeon_encoder->audio->set_vbi_packet)
650 radeon_encoder->audio->set_vbi_packet(encoder, dig->afmt->offset);
651}
be273e58 652
6e72376d 653static void radeon_hdmi_set_color_depth(struct drm_encoder *encoder)
be273e58
SG		 654{
655 int bpc = 8;
656 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
657 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
658
659 if (!dig || !dig->afmt)
660 return;
661
662 if (encoder->crtc) {
663 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
664 bpc = radeon_crtc->bpc;
665 }
666
667 if (radeon_encoder->audio && radeon_encoder->audio->set_color_depth)
668 radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc);
669}
1852c9a0 670
6e72376d 671static void radeon_audio_set_audio_packet(struct drm_encoder *encoder)
1852c9a0 672{
f4c6c081
AD		 673 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
674 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1852c9a0
SG		 675
676 if (!dig || !dig->afmt)
677 return;
678
679 if (radeon_encoder->audio && radeon_encoder->audio->set_audio_packet)
680 radeon_encoder->audio->set_audio_packet(encoder, dig->afmt->offset);
681}
3be2e7d0 682
6e72376d 683static void radeon_audio_set_mute(struct drm_encoder *encoder, bool mute)
3be2e7d0 684{
f4c6c081
AD		 685 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
686 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3be2e7d0
SG		 687
688 if (!dig || !dig->afmt)
689 return;
690
691 if (radeon_encoder->audio && radeon_encoder->audio->set_mute)
692 radeon_encoder->audio->set_mute(encoder, dig->afmt->offset, mute);
693}
6e72376d
SG		 694
695/*
696 * update the info frames with the data from the current display mode
697 */
698static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder,
699 struct drm_display_mode *mode)
700{
f4c6c081 701 struct radeon_device *rdev = encoder->dev->dev_private;
6e72376d
SG		 702 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
703 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
704
705 if (!dig || !dig->afmt)
706 return;
707
708 /* disable audio prior to setting up hw */
6e72376d
SG		 709 radeon_audio_enable(rdev, dig->afmt->pin, 0);
710
711 radeon_audio_set_dto(encoder, mode->clock);
712 radeon_audio_set_vbi_packet(encoder);
713 radeon_hdmi_set_color_depth(encoder);
714 radeon_audio_set_mute(encoder, false);
715 radeon_audio_update_acr(encoder, mode->clock);
6e72376d
SG		 716 radeon_audio_set_audio_packet(encoder);
717 radeon_audio_select_pin(encoder);
6e72376d
SG		 718
719 if (radeon_audio_set_avi_packet(encoder, mode) < 0)
720 return;
721
722 /* enable audio after to setting up hw */
723 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
724}
725
e55bca26
SG		 726static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
727 struct drm_display_mode *mode)
728{
729 struct drm_device *dev = encoder->dev;
730 struct radeon_device *rdev = dev->dev_private;
731 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
732 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
733
734 if (!dig || !dig->afmt)
735 return;
736
737 /* disable audio prior to setting up hw */
e55bca26
SG		 738 radeon_audio_enable(rdev, dig->afmt->pin, 0);
739
740 radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10);
741 radeon_audio_set_audio_packet(encoder);
742 radeon_audio_select_pin(encoder);
743
744 if (radeon_audio_set_avi_packet(encoder, mode) < 0)
745 return;
746
747 /* enable audio after to setting up hw */
748 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
749}
750
6e72376d
SG		 751void radeon_audio_mode_set(struct drm_encoder *encoder,
752 struct drm_display_mode *mode)
753{
754 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
755
756 if (radeon_encoder->audio && radeon_encoder->audio->mode_set)
757 radeon_encoder->audio->mode_set(encoder, mode);
758}
6f945693
SG		 759
760void radeon_audio_dpms(struct drm_encoder *encoder, int mode)
761{
762 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
763
764 if (radeon_encoder->audio && radeon_encoder->audio->dpms)
765 radeon_encoder->audio->dpms(encoder, mode == DRM_MODE_DPMS_ON);
766}
Linux 6.x block layer and io_uring tree(s)