projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 3ce0a23d JG |
1 | /* |
| 2 | * Copyright 2009 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2009 Red Hat Inc. | |
| 4 | * | |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 6 | * copy of this software and associated documentation files (the "Software"), | |
| 7 | * to deal in the Software without restriction, including without limitation | |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 10 | * Software is furnished to do so, subject to the following conditions: | |
| 11 | * | |
| 12 | * The above copyright notice and this permission notice shall be included in | |
| 13 | * all copies or substantial portions of the Software. | |
| 14 | * | |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 22 | * | |
| 23 | * Authors: Dave Airlie | |
| 24 | * Alex Deucher | |
| 25 | * Jerome Glisse | |
| 26 | */ | |
| 27 | #ifndef R600D_H | |
| 28 | #define R600D_H | |
| 29 | ||
| 30 | #define CP_PACKET2 0x80000000 | |
| 31 | #define PACKET2_PAD_SHIFT 0 | |
| 32 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
| 33 | ||
| 34 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
| 35 | ||
| 36 | #define R6XX_MAX_SH_GPRS 256 | |
| 37 | #define R6XX_MAX_TEMP_GPRS 16 | |
| 38 | #define R6XX_MAX_SH_THREADS 256 | |
| 39 | #define R6XX_MAX_SH_STACK_ENTRIES 4096 | |
| 40 | #define R6XX_MAX_BACKENDS 8 | |
| 41 | #define R6XX_MAX_BACKENDS_MASK 0xff | |
| 42 | #define R6XX_MAX_SIMDS 8 | |
| 43 | #define R6XX_MAX_SIMDS_MASK 0xff | |
| 44 | #define R6XX_MAX_PIPES 8 | |
| 45 | #define R6XX_MAX_PIPES_MASK 0xff | |
| 46 | ||
| 47 | /* PTE flags */ | |
| 48 | #define PTE_VALID (1 << 0) | |
| 49 | #define PTE_SYSTEM (1 << 1) | |
| 50 | #define PTE_SNOOPED (1 << 2) | |
| 51 | #define PTE_READABLE (1 << 5) | |
| 52 | #define PTE_WRITEABLE (1 << 6) | |
| 53 | ||
| 54 | /* Registers */ | |
| 55 | #define ARB_POP 0x2418 | |
| 56 | #define ENABLE_TC128 (1 << 30) | |
| 57 | #define ARB_GDEC_RD_CNTL 0x246C | |
| 58 | ||
| 59 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 | |
| 60 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
| 61 | #define BACKEND_DISABLE(x) ((x) << 16) | |
| 62 | ||
| 63 | #define CB_COLOR0_BASE 0x28040 | |
| 64 | #define CB_COLOR1_BASE 0x28044 | |
| 65 | #define CB_COLOR2_BASE 0x28048 | |
| 66 | #define CB_COLOR3_BASE 0x2804C | |
| 67 | #define CB_COLOR4_BASE 0x28050 | |
| 68 | #define CB_COLOR5_BASE 0x28054 | |
| 69 | #define CB_COLOR6_BASE 0x28058 | |
| 70 | #define CB_COLOR7_BASE 0x2805C | |
| 71 | #define CB_COLOR7_FRAG 0x280FC | |
| 72 | ||
| 73 | #define CB_COLOR0_SIZE 0x28060 | |
| 74 | #define CB_COLOR0_VIEW 0x28080 | |
| 75 | #define CB_COLOR0_INFO 0x280a0 | |
| 76 | #define CB_COLOR0_TILE 0x280c0 | |
| 77 | #define CB_COLOR0_FRAG 0x280e0 | |
| 78 | #define CB_COLOR0_MASK 0x28100 | |
| 79 | ||
| 80 | #define CONFIG_MEMSIZE 0x5428 | |
| 81 | #define CP_STAT 0x8680 | |
| 82 | #define CP_COHER_BASE 0x85F8 | |
| 83 | #define CP_DEBUG 0xC1FC | |
| 84 | #define R_0086D8_CP_ME_CNTL 0x86D8 | |
| 85 | #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) | |
| 86 | #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) | |
| 87 | #define CP_ME_RAM_DATA 0xC160 | |
| 88 | #define CP_ME_RAM_RADDR 0xC158 | |
| 89 | #define CP_ME_RAM_WADDR 0xC15C | |
| 90 | #define CP_MEQ_THRESHOLDS 0x8764 | |
| 91 | #define MEQ_END(x) ((x) << 16) | |
| 92 | #define ROQ_END(x) ((x) << 24) | |
| 93 | #define CP_PERFMON_CNTL 0x87FC | |
| 94 | #define CP_PFP_UCODE_ADDR 0xC150 | |
| 95 | #define CP_PFP_UCODE_DATA 0xC154 | |
| 96 | #define CP_QUEUE_THRESHOLDS 0x8760 | |
| 97 | #define ROQ_IB1_START(x) ((x) << 0) | |
| 98 | #define ROQ_IB2_START(x) ((x) << 8) | |
| 99 | #define CP_RB_BASE 0xC100 | |
| 100 | #define CP_RB_CNTL 0xC104 | |
| 101 | #define RB_BUFSZ(x) ((x)<<0) | |
| 102 | #define RB_BLKSZ(x) ((x)<<8) | |
| 103 | #define RB_NO_UPDATE (1<<27) | |
| 104 | #define RB_RPTR_WR_ENA (1<<31) | |
| 105 | #define BUF_SWAP_32BIT (2 << 16) | |
| 106 | #define CP_RB_RPTR 0x8700 | |
| 107 | #define CP_RB_RPTR_ADDR 0xC10C | |
| 108 | #define CP_RB_RPTR_ADDR_HI 0xC110 | |
| 109 | #define CP_RB_RPTR_WR 0xC108 | |
| 110 | #define CP_RB_WPTR 0xC114 | |
| 111 | #define CP_RB_WPTR_ADDR 0xC118 | |
| 112 | #define CP_RB_WPTR_ADDR_HI 0xC11C | |
| 113 | #define CP_RB_WPTR_DELAY 0x8704 | |
| 114 | #define CP_ROQ_IB1_STAT 0x8784 | |
| 115 | #define CP_ROQ_IB2_STAT 0x8788 | |
| 116 | #define CP_SEM_WAIT_TIMER 0x85BC | |
| 117 | ||
| 118 | #define DB_DEBUG 0x9830 | |
| 119 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) | |
| 120 | #define DB_DEPTH_BASE 0x2800C | |
| 121 | #define DB_WATERMARKS 0x9838 | |
| 122 | #define DEPTH_FREE(x) ((x) << 0) | |
| 123 | #define DEPTH_FLUSH(x) ((x) << 5) | |
| 124 | #define DEPTH_PENDING_FREE(x) ((x) << 15) | |
| 125 | #define DEPTH_CACHELINE_FREE(x) ((x) << 20) | |
| 126 | ||
| 127 | #define DCP_TILING_CONFIG 0x6CA0 | |
| 128 | #define PIPE_TILING(x) ((x) << 1) | |
| 129 | #define BANK_TILING(x) ((x) << 4) | |
| 130 | #define GROUP_SIZE(x) ((x) << 6) | |
| 131 | #define ROW_TILING(x) ((x) << 8) | |
| 132 | #define BANK_SWAPS(x) ((x) << 11) | |
| 133 | #define SAMPLE_SPLIT(x) ((x) << 14) | |
| 134 | #define BACKEND_MAP(x) ((x) << 16) | |
| 135 | ||
| 136 | #define GB_TILING_CONFIG 0x98F0 | |
| 137 | ||
| 138 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 | |
| 139 | #define INACTIVE_QD_PIPES(x) ((x) << 8) | |
| 140 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 | |
| 141 | #define INACTIVE_SIMDS(x) ((x) << 16) | |
| 142 | #define INACTIVE_SIMDS_MASK 0x00FF0000 | |
| 143 | ||
| 144 | #define SQ_CONFIG 0x8c00 | |
| 145 | # define VC_ENABLE (1 << 0) | |
| 146 | # define EXPORT_SRC_C (1 << 1) | |
| 147 | # define DX9_CONSTS (1 << 2) | |
| 148 | # define ALU_INST_PREFER_VECTOR (1 << 3) | |
| 149 | # define DX10_CLAMP (1 << 4) | |
| 150 | # define CLAUSE_SEQ_PRIO(x) ((x) << 8) | |
| 151 | # define PS_PRIO(x) ((x) << 24) | |
| 152 | # define VS_PRIO(x) ((x) << 26) | |
| 153 | # define GS_PRIO(x) ((x) << 28) | |
| 154 | # define ES_PRIO(x) ((x) << 30) | |
| 155 | #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 | |
| 156 | # define NUM_PS_GPRS(x) ((x) << 0) | |
| 157 | # define NUM_VS_GPRS(x) ((x) << 16) | |
| 158 | # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | |
| 159 | #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 | |
| 160 | # define NUM_GS_GPRS(x) ((x) << 0) | |
| 161 | # define NUM_ES_GPRS(x) ((x) << 16) | |
| 162 | #define SQ_THREAD_RESOURCE_MGMT 0x8c0c | |
| 163 | # define NUM_PS_THREADS(x) ((x) << 0) | |
| 164 | # define NUM_VS_THREADS(x) ((x) << 8) | |
| 165 | # define NUM_GS_THREADS(x) ((x) << 16) | |
| 166 | # define NUM_ES_THREADS(x) ((x) << 24) | |
| 167 | #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 | |
| 168 | # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) | |
| 169 | # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) | |
| 170 | #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 | |
| 171 | # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) | |
| 172 | # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) | |
| 173 | ||
| 174 | #define GRBM_CNTL 0x8000 | |
| 175 | # define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
| 176 | #define GRBM_STATUS 0x8010 | |
| 177 | #define CMDFIFO_AVAIL_MASK 0x0000001F | |
| 178 | #define GUI_ACTIVE (1<<31) | |
| 179 | #define GRBM_STATUS2 0x8014 | |
| 180 | #define GRBM_SOFT_RESET 0x8020 | |
| 181 | #define SOFT_RESET_CP (1<<0) | |
| 182 | ||
| 183 | #define HDP_HOST_PATH_CNTL 0x2C00 | |
| 184 | #define HDP_NONSURFACE_BASE 0x2C04 | |
| 185 | #define HDP_NONSURFACE_INFO 0x2C08 | |
| 186 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
| 187 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 | |
| 188 | #define HDP_TILING_CONFIG 0x2F3C | |
| 189 | ||
| 190 | #define MC_VM_AGP_TOP 0x2184 | |
| 191 | #define MC_VM_AGP_BOT 0x2188 | |
| 192 | #define MC_VM_AGP_BASE 0x218C | |
| 193 | #define MC_VM_FB_LOCATION 0x2180 | |
| 194 | #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C | |
| 195 | #define ENABLE_L1_TLB (1 << 0) | |
| 196 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
| 197 | #define ENABLE_L1_STRICT_ORDERING (1 << 2) | |
| 198 | #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 | |
| 199 | #define SYSTEM_ACCESS_MODE_SHIFT 6 | |
| 200 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) | |
| 201 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) | |
| 202 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) | |
| 203 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) | |
| 204 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) | |
| 205 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) | |
| 206 | #define ENABLE_SEMAPHORE_MODE (1 << 10) | |
| 207 | #define ENABLE_WAIT_L2_QUERY (1 << 11) | |
| 208 | #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) | |
| 209 | #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 | |
| 210 | #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 | |
| 211 | #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) | |
| 212 | #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 | |
| 213 | #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 | |
| 214 | #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 | |
| 215 | #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC | |
| 216 | #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 | |
| 217 | #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 | |
| 218 | #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C | |
| 219 | #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 | |
| 220 | #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 | |
| 221 | #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 | |
| 222 | #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 | |
| 223 | #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 | |
| 224 | #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C | |
| 225 | #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 | |
| 226 | #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 | |
| 227 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 | |
| 228 | #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF | |
| 229 | #define LOGICAL_PAGE_NUMBER_SHIFT 0 | |
| 230 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 | |
| 231 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 | |
| 232 | ||
| 233 | #define PA_CL_ENHANCE 0x8A14 | |
| 234 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
| 235 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
| 236 | #define PA_SC_AA_CONFIG 0x28C04 | |
| 237 | #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 | |
| 238 | #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 | |
| 239 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 | |
| 240 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C | |
| 241 | #define S0_X(x) ((x) << 0) | |
| 242 | #define S0_Y(x) ((x) << 4) | |
| 243 | #define S1_X(x) ((x) << 8) | |
| 244 | #define S1_Y(x) ((x) << 12) | |
| 245 | #define S2_X(x) ((x) << 16) | |
| 246 | #define S2_Y(x) ((x) << 20) | |
| 247 | #define S3_X(x) ((x) << 24) | |
| 248 | #define S3_Y(x) ((x) << 28) | |
| 249 | #define S4_X(x) ((x) << 0) | |
| 250 | #define S4_Y(x) ((x) << 4) | |
| 251 | #define S5_X(x) ((x) << 8) | |
| 252 | #define S5_Y(x) ((x) << 12) | |
| 253 | #define S6_X(x) ((x) << 16) | |
| 254 | #define S6_Y(x) ((x) << 20) | |
| 255 | #define S7_X(x) ((x) << 24) | |
| 256 | #define S7_Y(x) ((x) << 28) | |
| 257 | #define PA_SC_CLIPRECT_RULE 0x2820c | |
| 258 | #define PA_SC_ENHANCE 0x8BF0 | |
| 259 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | |
| 260 | #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) | |
| 261 | #define PA_SC_LINE_STIPPLE 0x28A0C | |
| 262 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 | |
| 263 | #define PA_SC_MODE_CNTL 0x28A4C | |
| 264 | #define PA_SC_MULTI_CHIP_CNTL 0x8B20 | |
| 265 | ||
| 266 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 | |
| 267 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 | |
| 268 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 | |
| 269 | ||
| 270 | #define PCIE_PORT_INDEX 0x0038 | |
| 271 | #define PCIE_PORT_DATA 0x003C | |
| 272 | ||
| 273 | #define RAMCFG 0x2408 | |
| 274 | #define NOOFBANK_SHIFT 0 | |
| 275 | #define NOOFBANK_MASK 0x00000001 | |
| 276 | #define NOOFRANK_SHIFT 1 | |
| 277 | #define NOOFRANK_MASK 0x00000002 | |
| 278 | #define NOOFROWS_SHIFT 2 | |
| 279 | #define NOOFROWS_MASK 0x0000001C | |
| 280 | #define NOOFCOLS_SHIFT 5 | |
| 281 | #define NOOFCOLS_MASK 0x00000060 | |
| 282 | #define CHANSIZE_SHIFT 7 | |
| 283 | #define CHANSIZE_MASK 0x00000080 | |
| 284 | #define BURSTLENGTH_SHIFT 8 | |
| 285 | #define BURSTLENGTH_MASK 0x00000100 | |
| 286 | #define CHANSIZE_OVERRIDE (1 << 10) | |
| 287 | ||
| 288 | #define SCRATCH_REG0 0x8500 | |
| 289 | #define SCRATCH_REG1 0x8504 | |
| 290 | #define SCRATCH_REG2 0x8508 | |
| 291 | #define SCRATCH_REG3 0x850C | |
| 292 | #define SCRATCH_REG4 0x8510 | |
| 293 | #define SCRATCH_REG5 0x8514 | |
| 294 | #define SCRATCH_REG6 0x8518 | |
| 295 | #define SCRATCH_REG7 0x851C | |
| 296 | #define SCRATCH_UMSK 0x8540 | |
| 297 | #define SCRATCH_ADDR 0x8544 | |
| 298 | ||
| 299 | #define SPI_CONFIG_CNTL 0x9100 | |
| 300 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) | |
| 301 | #define DISABLE_INTERP_1 (1 << 5) | |
| 302 | #define SPI_CONFIG_CNTL_1 0x913C | |
| 303 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
| 304 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
| 305 | #define SPI_INPUT_Z 0x286D8 | |
| 306 | #define SPI_PS_IN_CONTROL_0 0x286CC | |
| 307 | #define NUM_INTERP(x) ((x)<<0) | |
| 308 | #define POSITION_ENA (1<<8) | |
| 309 | #define POSITION_CENTROID (1<<9) | |
| 310 | #define POSITION_ADDR(x) ((x)<<10) | |
| 311 | #define PARAM_GEN(x) ((x)<<15) | |
| 312 | #define PARAM_GEN_ADDR(x) ((x)<<19) | |
| 313 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) | |
| 314 | #define PERSP_GRADIENT_ENA (1<<28) | |
| 315 | #define LINEAR_GRADIENT_ENA (1<<29) | |
| 316 | #define POSITION_SAMPLE (1<<30) | |
| 317 | #define BARYC_AT_SAMPLE_ENA (1<<31) | |
| 318 | #define SPI_PS_IN_CONTROL_1 0x286D0 | |
| 319 | #define GEN_INDEX_PIX (1<<0) | |
| 320 | #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) | |
| 321 | #define FRONT_FACE_ENA (1<<8) | |
| 322 | #define FRONT_FACE_CHAN(x) ((x)<<9) | |
| 323 | #define FRONT_FACE_ALL_BITS (1<<11) | |
| 324 | #define FRONT_FACE_ADDR(x) ((x)<<12) | |
| 325 | #define FOG_ADDR(x) ((x)<<17) | |
| 326 | #define FIXED_PT_POSITION_ENA (1<<24) | |
| 327 | #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) | |
| 328 | ||
| 329 | #define SQ_MS_FIFO_SIZES 0x8CF0 | |
| 330 | #define CACHE_FIFO_SIZE(x) ((x) << 0) | |
| 331 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) | |
| 332 | #define DONE_FIFO_HIWATER(x) ((x) << 16) | |
| 333 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | |
| 334 | #define SQ_PGM_START_ES 0x28880 | |
| 335 | #define SQ_PGM_START_FS 0x28894 | |
| 336 | #define SQ_PGM_START_GS 0x2886C | |
| 337 | #define SQ_PGM_START_PS 0x28840 | |
| 338 | #define SQ_PGM_RESOURCES_PS 0x28850 | |
| 339 | #define SQ_PGM_EXPORTS_PS 0x28854 | |
| 340 | #define SQ_PGM_CF_OFFSET_PS 0x288cc | |
| 341 | #define SQ_PGM_START_VS 0x28858 | |
| 342 | #define SQ_PGM_RESOURCES_VS 0x28868 | |
| 343 | #define SQ_PGM_CF_OFFSET_VS 0x288d0 | |
| 344 | #define SQ_VTX_CONSTANT_WORD6_0 0x38018 | |
| 345 | #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) | |
| 346 | #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) | |
| 347 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 | |
| 348 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 | |
| 349 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 | |
| 350 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 | |
| 351 | ||
| 352 | ||
| 353 | #define SX_MISC 0x28350 | |
| 354 | #define SX_DEBUG_1 0x9054 | |
| 355 | #define SMX_EVENT_RELEASE (1 << 0) | |
| 356 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | |
| 357 | ||
| 358 | #define TA_CNTL_AUX 0x9508 | |
| 359 | #define DISABLE_CUBE_WRAP (1 << 0) | |
| 360 | #define DISABLE_CUBE_ANISO (1 << 1) | |
| 361 | #define SYNC_GRADIENT (1 << 24) | |
| 362 | #define SYNC_WALKER (1 << 25) | |
| 363 | #define SYNC_ALIGNER (1 << 26) | |
| 364 | #define BILINEAR_PRECISION_6_BIT (0 << 31) | |
| 365 | #define BILINEAR_PRECISION_8_BIT (1 << 31) | |
| 366 | ||
| 367 | #define TC_CNTL 0x9608 | |
| 368 | #define TC_L2_SIZE(x) ((x)<<5) | |
| 369 | #define L2_DISABLE_LATE_HIT (1<<9) | |
| 370 | ||
| 371 | ||
| 372 | #define VGT_CACHE_INVALIDATION 0x88C4 | |
| 373 | #define CACHE_INVALIDATION(x) ((x)<<0) | |
| 374 | #define VC_ONLY 0 | |
| 375 | #define TC_ONLY 1 | |
| 376 | #define VC_AND_TC 2 | |
| 377 | #define VGT_DMA_BASE 0x287E8 | |
| 378 | #define VGT_DMA_BASE_HI 0x287E4 | |
| 379 | #define VGT_ES_PER_GS 0x88CC | |
| 380 | #define VGT_GS_PER_ES 0x88C8 | |
| 381 | #define VGT_GS_PER_VS 0x88E8 | |
| 382 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
| 383 | #define VGT_PRIMITIVE_TYPE 0x8958 | |
| 384 | #define VGT_NUM_INSTANCES 0x8974 | |
| 385 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C | |
| 386 | #define DEALLOC_DIST_MASK 0x0000007F | |
| 387 | #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 | |
| 388 | #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 | |
| 389 | #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 | |
| 390 | #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c | |
| 391 | #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 | |
| 392 | #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 | |
| 393 | #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c | |
| 394 | #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 | |
| 395 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 | |
| 396 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 | |
| 397 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 | |
| 398 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 | |
| 399 | #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC | |
| 400 | #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC | |
| 401 | #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC | |
| 402 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C | |
| 403 | #define VGT_STRMOUT_EN 0x28AB0 | |
| 404 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 | |
| 405 | #define VTX_REUSE_DEPTH_MASK 0x000000FF | |
| 406 | #define VGT_EVENT_INITIATOR 0x28a90 | |
| 407 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) | |
| 408 | ||
| 409 | #define VM_CONTEXT0_CNTL 0x1410 | |
| 410 | #define ENABLE_CONTEXT (1 << 0) | |
| 411 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
| 412 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) | |
| 413 | #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 | |
| 414 | #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 | |
| 415 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 | |
| 416 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 | |
| 417 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 | |
| 418 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 | |
| 419 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 | |
| 420 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) | |
| 421 | #define RESPONSE_TYPE_MASK 0x000000F0 | |
| 422 | #define RESPONSE_TYPE_SHIFT 4 | |
| 423 | #define VM_L2_CNTL 0x1400 | |
| 424 | #define ENABLE_L2_CACHE (1 << 0) | |
| 425 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
| 426 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
| 427 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) | |
| 428 | #define VM_L2_CNTL2 0x1404 | |
| 429 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
| 430 | #define INVALIDATE_L2_CACHE (1 << 1) | |
| 431 | #define VM_L2_CNTL3 0x1408 | |
| 432 | #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) | |
| 433 | #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) | |
| 434 | #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) | |
| 435 | #define VM_L2_STATUS 0x140C | |
| 436 | #define L2_BUSY (1 << 0) | |
| 437 | ||
| 438 | #define WAIT_UNTIL 0x8040 | |
| 439 | #define WAIT_2D_IDLE_bit (1 << 14) | |
| 440 | #define WAIT_3D_IDLE_bit (1 << 15) | |
| 441 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) | |
| 442 | #define WAIT_3D_IDLECLEAN_bit (1 << 17) | |
| 443 | ||
| 444 | ||
| 445 | ||
| 446 | /* | |
| 447 | * PM4 | |
| 448 | */ | |
| 449 | #define PACKET_TYPE0 0 | |
| 450 | #define PACKET_TYPE1 1 | |
| 451 | #define PACKET_TYPE2 2 | |
| 452 | #define PACKET_TYPE3 3 | |
| 453 | ||
| 454 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) | |
| 455 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) | |
| 456 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) | |
| 457 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | |
| 458 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ | |
| 459 | (((reg) >> 2) & 0xFFFF) | \ | |
| 460 | ((n) & 0x3FFF) << 16) | |
| 461 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ | |
| 462 | (((op) & 0xFF) << 8) | \ | |
| 463 | ((n) & 0x3FFF) << 16) | |
| 464 | ||
| 465 | /* Packet 3 types */ | |
| 466 | #define PACKET3_NOP 0x10 | |
| 467 | #define PACKET3_INDIRECT_BUFFER_END 0x17 | |
| 468 | #define PACKET3_SET_PREDICATION 0x20 | |
| 469 | #define PACKET3_REG_RMW 0x21 | |
| 470 | #define PACKET3_COND_EXEC 0x22 | |
| 471 | #define PACKET3_PRED_EXEC 0x23 | |
| 472 | #define PACKET3_START_3D_CMDBUF 0x24 | |
| 473 | #define PACKET3_DRAW_INDEX_2 0x27 | |
| 474 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
| 475 | #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 | |
| 476 | #define PACKET3_INDEX_TYPE 0x2A | |
| 477 | #define PACKET3_DRAW_INDEX 0x2B | |
| 478 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
| 479 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | |
| 480 | #define PACKET3_NUM_INSTANCES 0x2F | |
| 481 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
| 482 | #define PACKET3_INDIRECT_BUFFER_MP 0x38 | |
| 483 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
| 484 | #define PACKET3_MPEG_INDEX 0x3A | |
| 485 | #define PACKET3_WAIT_REG_MEM 0x3C | |
| 486 | #define PACKET3_MEM_WRITE 0x3D | |
| 487 | #define PACKET3_INDIRECT_BUFFER 0x32 | |
| 488 | #define PACKET3_CP_INTERRUPT 0x40 | |
| 489 | #define PACKET3_SURFACE_SYNC 0x43 | |
| 490 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
| 491 | # define PACKET3_TC_ACTION_ENA (1 << 23) | |
| 492 | # define PACKET3_VC_ACTION_ENA (1 << 24) | |
| 493 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
| 494 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
| 495 | # define PACKET3_SH_ACTION_ENA (1 << 27) | |
| 496 | # define PACKET3_SMX_ACTION_ENA (1 << 28) | |
| 497 | #define PACKET3_ME_INITIALIZE 0x44 | |
| 498 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | |
| 499 | #define PACKET3_COND_WRITE 0x45 | |
| 500 | #define PACKET3_EVENT_WRITE 0x46 | |
| 501 | #define PACKET3_EVENT_WRITE_EOP 0x47 | |
| 502 | #define PACKET3_ONE_REG_WRITE 0x57 | |
| 503 | #define PACKET3_SET_CONFIG_REG 0x68 | |
| 504 | #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 | |
| 505 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 | |
| 506 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
| 507 | #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 | |
| 508 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
| 509 | #define PACKET3_SET_ALU_CONST 0x6A | |
| 510 | #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 | |
| 511 | #define PACKET3_SET_ALU_CONST_END 0x00032000 | |
| 512 | #define PACKET3_SET_BOOL_CONST 0x6B | |
| 513 | #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 | |
| 514 | #define PACKET3_SET_BOOL_CONST_END 0x00040000 | |
| 515 | #define PACKET3_SET_LOOP_CONST 0x6C | |
| 516 | #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 | |
| 517 | #define PACKET3_SET_LOOP_CONST_END 0x0003e380 | |
| 518 | #define PACKET3_SET_RESOURCE 0x6D | |
| 519 | #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 | |
| 520 | #define PACKET3_SET_RESOURCE_END 0x0003c000 | |
| 521 | #define PACKET3_SET_SAMPLER 0x6E | |
| 522 | #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 | |
| 523 | #define PACKET3_SET_SAMPLER_END 0x0003cff0 | |
| 524 | #define PACKET3_SET_CTL_CONST 0x6F | |
| 525 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 | |
| 526 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 | |
| 527 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 | |
| 528 | ||
| 529 | ||
| 530 | #define R_008020_GRBM_SOFT_RESET 0x8020 | |
| 531 | #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) | |
| 532 | #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) | |
| 533 | #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) | |
| 534 | #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) | |
| 535 | #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) | |
| 536 | #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) | |
| 537 | #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) | |
| 538 | #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) | |
| 539 | #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) | |
| 540 | #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) | |
| 541 | #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) | |
| 542 | #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) | |
| 543 | #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) | |
| 544 | #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) | |
| 545 | #define R_008010_GRBM_STATUS 0x8010 | |
| 546 | #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) | |
| 547 | #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) | |
| 548 | #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) | |
| 549 | #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) | |
| 550 | #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) | |
| 551 | #define S_008010_VC_BUSY(x) (((x) & 1) << 11) | |
| 552 | #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) | |
| 553 | #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) | |
| 554 | #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) | |
| 555 | #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) | |
| 556 | #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) | |
| 557 | #define S_008010_TC_BUSY(x) (((x) & 1) << 19) | |
| 558 | #define S_008010_SX_BUSY(x) (((x) & 1) << 20) | |
| 559 | #define S_008010_SH_BUSY(x) (((x) & 1) << 21) | |
| 560 | #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) | |
| 561 | #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) | |
| 562 | #define S_008010_SC_BUSY(x) (((x) & 1) << 24) | |
| 563 | #define S_008010_PA_BUSY(x) (((x) & 1) << 25) | |
| 564 | #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) | |
| 565 | #define S_008010_CR_BUSY(x) (((x) & 1) << 27) | |
| 566 | #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) | |
| 567 | #define S_008010_CP_BUSY(x) (((x) & 1) << 29) | |
| 568 | #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) | |
| 569 | #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) | |
| 570 | #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) | |
| 571 | #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) | |
| 572 | #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) | |
| 573 | #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) | |
| 574 | #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) | |
| 575 | #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) | |
| 576 | #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) | |
| 577 | #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) | |
| 578 | #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) | |
| 579 | #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) | |
| 580 | #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) | |
| 581 | #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) | |
| 582 | #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) | |
| 583 | #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) | |
| 584 | #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) | |
| 585 | #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) | |
| 586 | #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) | |
| 587 | #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) | |
| 588 | #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) | |
| 589 | #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) | |
| 590 | #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) | |
| 591 | #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) | |
| 592 | #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) | |
| 593 | #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) | |
| 594 | #define R_008014_GRBM_STATUS2 0x8014 | |
| 595 | #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) | |
| 596 | #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) | |
| 597 | #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) | |
| 598 | #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) | |
| 599 | #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) | |
| 600 | #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) | |
| 601 | #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) | |
| 602 | #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) | |
| 603 | #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) | |
| 604 | #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) | |
| 605 | #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) | |
| 606 | #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) | |
| 607 | #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) | |
| 608 | #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) | |
| 609 | #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) | |
| 610 | #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) | |
| 611 | #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) | |
| 612 | #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) | |
| 613 | #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) | |
| 614 | #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) | |
| 615 | #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) | |
| 616 | #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) | |
| 617 | #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) | |
| 618 | #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) | |
| 619 | #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) | |
| 620 | #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) | |
| 621 | #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) | |
| 622 | #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) | |
| 623 | #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) | |
| 624 | #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) | |
| 625 | #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) | |
| 626 | #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) | |
| 627 | #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) | |
| 628 | #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) | |
| 629 | #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) | |
| 630 | #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) | |
| 631 | #define R_000E50_SRBM_STATUS 0x0E50 | |
| 632 | #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) | |
| 633 | #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) | |
| 634 | #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) | |
| 635 | #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) | |
| 636 | #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) | |
| 637 | #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) | |
| 638 | #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) | |
| 639 | #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) | |
| 640 | #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) | |
| 641 | #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) | |
| 642 | #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) | |
| 643 | #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) | |
| 644 | #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) | |
| 645 | #define R_000E60_SRBM_SOFT_RESET 0x0E60 | |
| 646 | #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) | |
| 647 | #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) | |
| 648 | #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) | |
| 649 | #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) | |
| 650 | #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) | |
| 651 | #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) | |
| 652 | #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) | |
| 653 | #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) | |
| 654 | #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) | |
| 655 | #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) | |
| 656 | #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) | |
| 657 | #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) | |
| 658 | #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) | |
| 659 | #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) | |
| 660 | ||
| 661 | #endif |