[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600_hdmi.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Christian König.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#include <linux/hdmi.h>
#include <linux/gcd.h>

#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_asic.h"
#include "radeon_audio.h"
#include "r600.h"
#include "r600d.h"
#include "atom.h"

/*
 * HDMI color format
 */
enum r600_hdmi_color_format {
	RGB = 0,
	YCC_422 = 1,
	YCC_444 = 2
};

/*
 * IEC60958 status bits
 */
enum r600_hdmi_iec_status_bits {
	AUDIO_STATUS_DIG_ENABLE   = 0x01,
	AUDIO_STATUS_V            = 0x02,
	AUDIO_STATUS_VCFG         = 0x04,
	AUDIO_STATUS_EMPHASIS     = 0x08,
	AUDIO_STATUS_COPYRIGHT    = 0x10,
	AUDIO_STATUS_NONAUDIO     = 0x20,
	AUDIO_STATUS_PROFESSIONAL = 0x40,
	AUDIO_STATUS_LEVEL        = 0x80
};

static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
{
	struct r600_audio_pin status = {};
	uint32_t value;

	value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);

	/* number of channels */
	status.channels = (value & 0x7) + 1;

	/* bits per sample */
	switch ((value & 0xF0) >> 4) {
	case 0x0:
		status.bits_per_sample = 8;
		break;
	case 0x1:
		status.bits_per_sample = 16;
		break;
	case 0x2:
		status.bits_per_sample = 20;
		break;
	case 0x3:
		status.bits_per_sample = 24;
		break;
	case 0x4:
		status.bits_per_sample = 32;
		break;
	default:
		dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
			(int)value);
		status.bits_per_sample = 16;
	}

	/* current sampling rate in HZ */
	if (value & 0x4000)
		status.rate = 44100;
	else
		status.rate = 48000;
	status.rate *= ((value >> 11) & 0x7) + 1;
	status.rate /= ((value >> 8) & 0x7) + 1;

	value = RREG32(R600_AUDIO_STATUS_BITS);

	/* iec 60958 status bits */
	status.status_bits = value & 0xff;

	/* iec 60958 category code */
	status.category_code = (value >> 8) & 0xff;

	return status;
}

/*
 * update all hdmi interfaces with current audio parameters
 */
void r600_audio_update_hdmi(struct work_struct *work)
{
	struct radeon_device *rdev = container_of(work, struct radeon_device,
						  audio_work);
	struct drm_device *dev = rdev->ddev;
	struct r600_audio_pin audio_status = r600_audio_status(rdev);
	struct drm_encoder *encoder;
	bool changed = false;

	if (rdev->audio.pin[0].channels != audio_status.channels ||
	    rdev->audio.pin[0].rate != audio_status.rate ||
	    rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
	    rdev->audio.pin[0].status_bits != audio_status.status_bits ||
	    rdev->audio.pin[0].category_code != audio_status.category_code) {
		rdev->audio.pin[0] = audio_status;
		changed = true;
	}

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (!radeon_encoder_is_digital(encoder))
			continue;
		if (changed || r600_hdmi_buffer_status_changed(encoder))
			r600_hdmi_update_audio_settings(encoder);
	}
}

/* enable the audio stream */
void r600_audio_enable(struct radeon_device *rdev,
		       struct r600_audio_pin *pin,
		       u8 enable_mask)
{
	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

	if (!pin)
		return;

	if (enable_mask) {
		tmp |= AUDIO_ENABLED;
		if (enable_mask & 1)
			tmp |= PIN0_AUDIO_ENABLED;
		if (enable_mask & 2)
			tmp |= PIN1_AUDIO_ENABLED;
		if (enable_mask & 4)
			tmp |= PIN2_AUDIO_ENABLED;
		if (enable_mask & 8)
			tmp |= PIN3_AUDIO_ENABLED;
	} else {
		tmp &= ~(AUDIO_ENABLED |
			 PIN0_AUDIO_ENABLED |
			 PIN1_AUDIO_ENABLED |
			 PIN2_AUDIO_ENABLED |
			 PIN3_AUDIO_ENABLED);
	}

	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
}

struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
{
	/* only one pin on 6xx-NI */
	return &rdev->audio.pin[0];
}

void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	const struct radeon_hdmi_acr *acr)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;

	/* DCE 3.0 uses register that's normally for CRC_CONTROL */
	uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
				       HDMI0_ACR_PACKET_CONTROL;
	WREG32_P(acr_ctl + offset,
		HDMI0_ACR_SOURCE |		/* select SW CTS value */
		HDMI0_ACR_AUTO_SEND,	/* allow hw to sent ACR packets when required */
		~(HDMI0_ACR_SOURCE |
		HDMI0_ACR_AUTO_SEND));

	WREG32_P(HDMI0_ACR_32_0 + offset,
		HDMI0_ACR_CTS_32(acr->cts_32khz),
		~HDMI0_ACR_CTS_32_MASK);
	WREG32_P(HDMI0_ACR_32_1 + offset,
		HDMI0_ACR_N_32(acr->n_32khz),
		~HDMI0_ACR_N_32_MASK);

	WREG32_P(HDMI0_ACR_44_0 + offset,
		HDMI0_ACR_CTS_44(acr->cts_44_1khz),
		~HDMI0_ACR_CTS_44_MASK);
	WREG32_P(HDMI0_ACR_44_1 + offset,
		HDMI0_ACR_N_44(acr->n_44_1khz),
		~HDMI0_ACR_N_44_MASK);

	WREG32_P(HDMI0_ACR_48_0 + offset,
		HDMI0_ACR_CTS_48(acr->cts_48khz),
		~HDMI0_ACR_CTS_48_MASK);
	WREG32_P(HDMI0_ACR_48_1 + offset,
		HDMI0_ACR_N_48(acr->n_48khz),
		~HDMI0_ACR_N_48_MASK);
}

/*
 * build a HDMI Video Info Frame
 */
void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
			 unsigned char *buffer, size_t size)
{
	uint8_t *frame = buffer + 3;

	WREG32(HDMI0_AVI_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(HDMI0_AVI_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
	WREG32(HDMI0_AVI_INFO2 + offset,
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
	WREG32(HDMI0_AVI_INFO3 + offset,
		frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));

	WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
		  HDMI0_AVI_INFO_LINE(2));	/* anything other than 0 */

	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
		  HDMI0_AVI_INFO_SEND |	/* enable AVI info frames */
		  HDMI0_AVI_INFO_CONT);	/* send AVI info frames every frame/field */

}

/*
 * build a Audio Info Frame
 */
static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
					     const void *buffer, size_t size)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;
	const u8 *frame = buffer + 3;

	WREG32(HDMI0_AUDIO_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(HDMI0_AUDIO_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
}

/*
 * test if audio buffer is filled enough to start playing
 */
static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;

	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
}

/*
 * have buffer status changed since last call?
 */
int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
{
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	int status, result;

	if (!dig->afmt || !dig->afmt->enabled)
		return 0;

	status = r600_hdmi_is_audio_buffer_filled(encoder);
	result = dig->afmt->last_buffer_filled_status != status;
	dig->afmt->last_buffer_filled_status = status;

	return result;
}

/*
 * write the audio workaround status to the hardware
 */
void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;
	bool hdmi_audio_workaround = false; /* FIXME */
	u32 value;

	if (!hdmi_audio_workaround ||
	    r600_hdmi_is_audio_buffer_filled(encoder))
		value = 0; /* disable workaround */
	else
		value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
		 value, ~HDMI0_AUDIO_TEST_EN);
}

void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
			     struct radeon_crtc *crtc, unsigned int clock)
{
	struct radeon_encoder *radeon_encoder;
	struct radeon_encoder_atom_dig *dig;

	if (!crtc)
		return;

	radeon_encoder = to_radeon_encoder(crtc->encoder);
	dig = radeon_encoder->enc_priv;

	if (!dig)
		return;

	if (dig->dig_encoder == 0) {
		WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
		WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
	} else {
		WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
		WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
		WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
	}
}

void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;

	WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
		HDMI0_NULL_SEND |	/* send null packets when required */
		HDMI0_GC_SEND |		/* send general control packets */
		HDMI0_GC_CONT);		/* send general control packets every frame */
}

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;

	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
		HDMI0_AUDIO_SAMPLE_SEND |			/* send audio packets */
		HDMI0_AUDIO_DELAY_EN(1) |			/* default audio delay */
		HDMI0_AUDIO_PACKETS_PER_LINE(3) |	/* should be suffient for all audio modes and small enough for all hblanks */
		HDMI0_60958_CS_UPDATE,				/* allow 60958 channel status fields to be updated */
		~(HDMI0_AUDIO_SAMPLE_SEND |
		HDMI0_AUDIO_DELAY_EN_MASK |
		HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
		HDMI0_60958_CS_UPDATE));

	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
		HDMI0_AUDIO_INFO_SEND |		/* enable audio info frames (frames won't be set until audio is enabled) */
		HDMI0_AUDIO_INFO_UPDATE);	/* required for audio info values to be updated */

	WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
		HDMI0_AUDIO_INFO_LINE(2),	/* anything other than 0 */
		~HDMI0_AUDIO_INFO_LINE_MASK);

	WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
		~(HDMI0_GENERIC0_SEND |
		HDMI0_GENERIC0_CONT |
		HDMI0_GENERIC0_UPDATE |
		HDMI0_GENERIC1_SEND |
		HDMI0_GENERIC1_CONT |
		HDMI0_GENERIC0_LINE_MASK |
		HDMI0_GENERIC1_LINE_MASK));

	WREG32_P(HDMI0_60958_0 + offset,
		HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
		~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
		HDMI0_60958_CS_CLOCK_ACCURACY_MASK));

	WREG32_P(HDMI0_60958_1 + offset,
		HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
		~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
}

void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;

	if (mute)
		WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
	else
		WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
}

/**
 * r600_hdmi_update_audio_settings - Update audio infoframe
 *
 * @encoder: drm encoder
 *
 * Gets info about current audio stream and updates audio infoframe.
 */
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct r600_audio_pin audio = r600_audio_status(rdev);
	uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
	struct hdmi_audio_infoframe frame;
	uint32_t offset;
	uint32_t value;
	ssize_t err;

	if (!dig->afmt || !dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
		  audio.channels, audio.rate, audio.bits_per_sample);
	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
		  (int)audio.status_bits, (int)audio.category_code);

	err = hdmi_audio_infoframe_init(&frame);
	if (err < 0) {
		DRM_ERROR("failed to setup audio infoframe\n");
		return;
	}

	frame.channels = audio.channels;

	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack audio infoframe\n");
		return;
	}

	value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
	if (value & HDMI0_AUDIO_TEST_EN)
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
		       value & ~HDMI0_AUDIO_TEST_EN);

	WREG32_OR(HDMI0_CONTROL + offset,
		  HDMI0_ERROR_ACK);

	WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
		   ~HDMI0_AUDIO_INFO_SOURCE);

	r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));

	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
		  HDMI0_AUDIO_INFO_CONT |
		  HDMI0_AUDIO_INFO_UPDATE);
}

/*
 * enable the HDMI engine
 */
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 hdmi = HDMI0_ERROR_ACK;

	if (!dig || !dig->afmt)
		return;

	/* Older chipsets require setting HDMI and routing manually */
	if (!ASIC_IS_DCE3(rdev)) {
		if (enable)
			hdmi |= HDMI0_ENABLE;
		switch (radeon_encoder->encoder_id) {
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
			if (enable) {
				WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
			} else {
				WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
			}
			break;
		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
			if (enable) {
				WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
			} else {
				WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
			}
			break;
		case ENCODER_OBJECT_ID_INTERNAL_DDI:
			if (enable) {
				WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
			} else {
				WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
			}
			break;
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
			if (enable)
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
			break;
		default:
			dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
				radeon_encoder->encoder_id);
			break;
		}
		WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
	}

	if (rdev->irq.installed) {
		/* if irq is available use it */
		/* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
		if (enable)
			radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
		else
			radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
	}

	dig->afmt->enabled = enable;

	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
}
Commit	Line	Data
dafc3bd5 CK	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Christian König.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Christian König
	25	*/
e3b2e034	26	#include <linux/hdmi.h>
a2098250	27	#include <linux/gcd.h>
c182615f	28
760285e7	29	#include <drm/radeon_drm.h>
dafc3bd5	30	#include "radeon.h"
3574dda4	31	#include "radeon_asic.h"
3cdde027	32	#include "radeon_audio.h"
312226f9	33	#include "r600.h"
c6543a6e	34	#include "r600d.h"
dafc3bd5 CK	35	#include "atom.h"
	36
	37	/*
	38	* HDMI color format
	39	*/
	40	enum r600_hdmi_color_format {
	41	RGB = 0,
	42	YCC_422 = 1,
	43	YCC_444 = 2
	44	};
	45
	46	/*
	47	* IEC60958 status bits
	48	*/
	49	enum r600_hdmi_iec_status_bits {
	50	AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9 RM	51	AUDIO_STATUS_V = 0x02,
3fe373d9 RM	52	AUDIO_STATUS_VCFG = 0x04,
dafc3bd5 CK	53	AUDIO_STATUS_EMPHASIS = 0x08,
	54	AUDIO_STATUS_COPYRIGHT = 0x10,
	55	AUDIO_STATUS_NONAUDIO = 0x20,
	56	AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9	57	AUDIO_STATUS_LEVEL = 0x80
dafc3bd5 CK	58	};
dafc3bd5 CK	59
72156676 AD	60	static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
72156676 AD	61	{
e8820646	62	struct r600_audio_pin status = {};
72156676 AD	63	uint32_t value;
	64
	65	value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
	66
	67	/* number of channels */
	68	status.channels = (value & 0x7) + 1;
	69
	70	/* bits per sample */
	71	switch ((value & 0xF0) >> 4) {
	72	case 0x0:
	73	status.bits_per_sample = 8;
	74	break;
	75	case 0x1:
	76	status.bits_per_sample = 16;
	77	break;
	78	case 0x2:
	79	status.bits_per_sample = 20;
	80	break;
	81	case 0x3:
	82	status.bits_per_sample = 24;
	83	break;
	84	case 0x4:
	85	status.bits_per_sample = 32;
	86	break;
	87	default:
	88	dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
	89	(int)value);
	90	status.bits_per_sample = 16;
	91	}
	92
	93	/* current sampling rate in HZ */
	94	if (value & 0x4000)
	95	status.rate = 44100;
	96	else
	97	status.rate = 48000;
	98	status.rate *= ((value >> 11) & 0x7) + 1;
	99	status.rate /= ((value >> 8) & 0x7) + 1;
	100
	101	value = RREG32(R600_AUDIO_STATUS_BITS);
	102
	103	/* iec 60958 status bits */
	104	status.status_bits = value & 0xff;
	105
	106	/* iec 60958 category code */
	107	status.category_code = (value >> 8) & 0xff;
	108
	109	return status;
	110	}
	111
	112	/*
	113	* update all hdmi interfaces with current audio parameters
	114	*/
	115	void r600_audio_update_hdmi(struct work_struct *work)
	116	{
	117	struct radeon_device *rdev = container_of(work, struct radeon_device,
	118	audio_work);
	119	struct drm_device *dev = rdev->ddev;
	120	struct r600_audio_pin audio_status = r600_audio_status(rdev);
	121	struct drm_encoder *encoder;
	122	bool changed = false;
	123
	124	if (rdev->audio.pin[0].channels != audio_status.channels \|\|
	125	rdev->audio.pin[0].rate != audio_status.rate \|\|
	126	rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample \|\|
127	rdev->audio.pin[0].status_bits != audio_status.status_bits \|\|
128	rdev->audio.pin[0].category_code != audio_status.category_code) {
129	rdev->audio.pin[0] = audio_status;
130	changed = true;
131	}
132
133	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
134	if (!radeon_encoder_is_digital(encoder))
135	continue;
136	if (changed \|\| r600_hdmi_buffer_status_changed(encoder))
137	r600_hdmi_update_audio_settings(encoder);
138	}
139	}
140
141	/* enable the audio stream */
142	void r600_audio_enable(struct radeon_device *rdev,
143	struct r600_audio_pin *pin,
d3d8c141	144	u8 enable_mask)
72156676	145	{
d3d8c141	146	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
72156676 AD	147
	148	if (!pin)
	149	return;
	150
d3d8c141 AD	151	if (enable_mask) {
	152	tmp \|= AUDIO_ENABLED;
	153	if (enable_mask & 1)
	154	tmp \|= PIN0_AUDIO_ENABLED;
	155	if (enable_mask & 2)
	156	tmp \|= PIN1_AUDIO_ENABLED;
	157	if (enable_mask & 4)
	158	tmp \|= PIN2_AUDIO_ENABLED;
	159	if (enable_mask & 8)
	160	tmp \|= PIN3_AUDIO_ENABLED;
72156676	161	} else {
d3d8c141 AD	162	tmp &= ~(AUDIO_ENABLED \|
	163	PIN0_AUDIO_ENABLED \|
	164	PIN1_AUDIO_ENABLED \|
	165	PIN2_AUDIO_ENABLED \|
	166	PIN3_AUDIO_ENABLED);
72156676	167	}
d3d8c141 AD	168
d3d8c141 AD	169	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
72156676 AD	170	}
72156676 AD	171
72156676 AD	172	struct r600_audio_pin r600_audio_get_pin(struct radeon_device rdev)
	173	{
	174	/* only one pin on 6xx-NI */
	175	return &rdev->audio.pin[0];
	176	}
	177
64424d6e SG	178	void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
64424d6e SG	179	const struct radeon_hdmi_acr *acr)
dafc3bd5 CK	180	{
	181	struct drm_device *dev = encoder->dev;
	182	struct radeon_device *rdev = dev->dev_private;
64424d6e SG	183
	184	/* DCE 3.0 uses register that's normally for CRC_CONTROL */
	185	uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
	186	HDMI0_ACR_PACKET_CONTROL;
	187	WREG32_P(acr_ctl + offset,
	188	HDMI0_ACR_SOURCE \| /* select SW CTS value */
	189	HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
	190	~(HDMI0_ACR_SOURCE \|
	191	HDMI0_ACR_AUTO_SEND));
dafc3bd5	192
68706337	193	WREG32_P(HDMI0_ACR_32_0 + offset,
64424d6e SG	194	HDMI0_ACR_CTS_32(acr->cts_32khz),
64424d6e SG	195	~HDMI0_ACR_CTS_32_MASK);
68706337	196	WREG32_P(HDMI0_ACR_32_1 + offset,
64424d6e SG	197	HDMI0_ACR_N_32(acr->n_32khz),
64424d6e SG	198	~HDMI0_ACR_N_32_MASK);
68706337 RM	199
68706337 RM	200	WREG32_P(HDMI0_ACR_44_0 + offset,
64424d6e SG	201	HDMI0_ACR_CTS_44(acr->cts_44_1khz),
64424d6e SG	202	~HDMI0_ACR_CTS_44_MASK);
68706337	203	WREG32_P(HDMI0_ACR_44_1 + offset,
64424d6e SG	204	HDMI0_ACR_N_44(acr->n_44_1khz),
64424d6e SG	205	~HDMI0_ACR_N_44_MASK);
68706337 RM	206
68706337 RM	207	WREG32_P(HDMI0_ACR_48_0 + offset,
64424d6e SG	208	HDMI0_ACR_CTS_48(acr->cts_48khz),
64424d6e SG	209	~HDMI0_ACR_CTS_48_MASK);
68706337	210	WREG32_P(HDMI0_ACR_48_1 + offset,
64424d6e SG	211	HDMI0_ACR_N_48(acr->n_48khz),
64424d6e SG	212	~HDMI0_ACR_N_48_MASK);
dafc3bd5 CK	213	}
dafc3bd5 CK	214
dafc3bd5 CK	215	/*
	216	* build a HDMI Video Info Frame
	217	*/
baa7d8e4	218	void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
3cf8bb1a	219	unsigned char *buffer, size_t size)
dafc3bd5	220	{
e3b2e034	221	uint8_t *frame = buffer + 3;
dafc3bd5	222
c6543a6e	223	WREG32(HDMI0_AVI_INFO0 + offset,
dafc3bd5	224	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
c6543a6e	225	WREG32(HDMI0_AVI_INFO1 + offset,
dafc3bd5	226	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x7] << 24));
c6543a6e	227	WREG32(HDMI0_AVI_INFO2 + offset,
dafc3bd5	228	frame[0x8] \| (frame[0x9] << 8) \| (frame[0xA] << 16) \| (frame[0xB] << 24));
c6543a6e	229	WREG32(HDMI0_AVI_INFO3 + offset,
96ea7afb	230	frame[0xC] \| (frame[0xD] << 8) \| (buffer[1] << 24));
baa7d8e4	231
304f07e9 AD	232	WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
	233	HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */
	234
baa7d8e4	235	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
304f07e9 AD	236	HDMI0_AVI_INFO_SEND \| /* enable AVI info frames */
304f07e9 AD	237	HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */
baa7d8e4	238
dafc3bd5 CK	239	}
	240
	241	/*
	242	* build a Audio Info Frame
	243	*/
e3b2e034 TR	244	static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
e3b2e034 TR	245	const void *buffer, size_t size)
dafc3bd5 CK	246	{
	247	struct drm_device *dev = encoder->dev;
	248	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	249	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	250	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	251	uint32_t offset = dig->afmt->offset;
e3b2e034	252	const u8 *frame = buffer + 3;
dafc3bd5	253
c6543a6e	254	WREG32(HDMI0_AUDIO_INFO0 + offset,
dafc3bd5	255	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
c6543a6e	256	WREG32(HDMI0_AUDIO_INFO1 + offset,
dafc3bd5 CK	257	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x8] << 24));
	258	}
	259
	260	/*
	261	* test if audio buffer is filled enough to start playing
	262	*/
cfcbd6d3	263	static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
dafc3bd5 CK	264	{
	265	struct drm_device *dev = encoder->dev;
	266	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	267	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	268	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	269	uint32_t offset = dig->afmt->offset;
dafc3bd5	270
c6543a6e	271	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
dafc3bd5 CK	272	}
	273
	274	/*
	275	* have buffer status changed since last call?
	276	*/
	277	int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
	278	{
	279	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3	280	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5 CK	281	int status, result;
dafc3bd5 CK	282
cfcbd6d3	283	if (!dig->afmt \|\| !dig->afmt->enabled)
dafc3bd5 CK	284	return 0;
	285
	286	status = r600_hdmi_is_audio_buffer_filled(encoder);
cfcbd6d3 RM	287	result = dig->afmt->last_buffer_filled_status != status;
cfcbd6d3 RM	288	dig->afmt->last_buffer_filled_status = status;
dafc3bd5 CK	289
	290	return result;
	291	}
	292
	293	/*
	294	* write the audio workaround status to the hardware
	295	*/
8f33a156	296	void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
dafc3bd5 CK	297	{
	298	struct drm_device *dev = encoder->dev;
	299	struct radeon_device *rdev = dev->dev_private;
	300	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	301	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	302	uint32_t offset = dig->afmt->offset;
	303	bool hdmi_audio_workaround = false; /* FIXME */
	304	u32 value;
	305
	306	if (!hdmi_audio_workaround \|\|
	307	r600_hdmi_is_audio_buffer_filled(encoder))
	308	value = 0; /* disable workaround */
	309	else
	310	value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
	311	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
	312	value, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5 CK	313	}
dafc3bd5 CK	314
a85d682a	315	void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
3cf8bb1a	316	struct radeon_crtc *crtc, unsigned int clock)
b1f6f47e	317	{
a85d682a SG	318	struct radeon_encoder *radeon_encoder;
a85d682a SG	319	struct radeon_encoder_atom_dig *dig;
b1f6f47e	320
a85d682a	321	if (!crtc)
b1f6f47e AD	322	return;
b1f6f47e AD	323
a85d682a SG	324	radeon_encoder = to_radeon_encoder(crtc->encoder);
a85d682a SG	325	dig = radeon_encoder->enc_priv;
1518dd8e	326
a85d682a SG	327	if (!dig)
	328	return;
	329
	330	if (dig->dig_encoder == 0) {
	331	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
	332	WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
	333	WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
55d4e020	334	} else {
a85d682a SG	335	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
	336	WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
	337	WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
1586505a	338	}
b1f6f47e	339	}
dafc3bd5	340
930a9785 AD	341	void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
	342	{
	343	struct drm_device *dev = encoder->dev;
	344	struct radeon_device *rdev = dev->dev_private;
	345
	346	WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
	347	HDMI0_NULL_SEND \| /* send null packets when required */
	348	HDMI0_GC_SEND \| /* send general control packets */
	349	HDMI0_GC_CONT); /* send general control packets every frame */
	350	}
	351
1852c9a0 SG	352	void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
	353	{
	354	struct drm_device *dev = encoder->dev;
	355	struct radeon_device *rdev = dev->dev_private;
	356
	357	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
	358	HDMI0_AUDIO_SAMPLE_SEND \| /* send audio packets */
	359	HDMI0_AUDIO_DELAY_EN(1) \| /* default audio delay */
	360	HDMI0_AUDIO_PACKETS_PER_LINE(3) \| /* should be suffient for all audio modes and small enough for all hblanks */
	361	HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
	362	~(HDMI0_AUDIO_SAMPLE_SEND \|
	363	HDMI0_AUDIO_DELAY_EN_MASK \|
	364	HDMI0_AUDIO_PACKETS_PER_LINE_MASK \|
	365	HDMI0_60958_CS_UPDATE));
	366
	367	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
	368	HDMI0_AUDIO_INFO_SEND \| /* enable audio info frames (frames won't be set until audio is enabled) */
	369	HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
	370
	371	WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
	372	HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
	373	~HDMI0_AUDIO_INFO_LINE_MASK);
	374
	375	WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
	376	~(HDMI0_GENERIC0_SEND \|
	377	HDMI0_GENERIC0_CONT \|
	378	HDMI0_GENERIC0_UPDATE \|
	379	HDMI0_GENERIC1_SEND \|
	380	HDMI0_GENERIC1_CONT \|
	381	HDMI0_GENERIC0_LINE_MASK \|
	382	HDMI0_GENERIC1_LINE_MASK));
	383
	384	WREG32_P(HDMI0_60958_0 + offset,
	385	HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
	386	~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK \|
	387	HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
	388
	389	WREG32_P(HDMI0_60958_1 + offset,
	390	HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
	391	~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
	392	}
	393
3be2e7d0 SG	394	void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
	395	{
	396	struct drm_device *dev = encoder->dev;
	397	struct radeon_device *rdev = dev->dev_private;
	398
	399	if (mute)
	400	WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
	401	else
	402	WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
	403	}
	404
8e4d9f81 RM	405	/**
	406	* r600_hdmi_update_audio_settings - Update audio infoframe
	407	*
	408	* @encoder: drm encoder
	409	*
	410	* Gets info about current audio stream and updates audio infoframe.
dafc3bd5	411	*/
58bd0863	412	void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5 CK	413	{
	414	struct drm_device *dev = encoder->dev;
	415	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	416	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	417	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b530602f	418	struct r600_audio_pin audio = r600_audio_status(rdev);
e3b2e034 TR	419	uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
e3b2e034 TR	420	struct hdmi_audio_infoframe frame;
cfcbd6d3	421	uint32_t offset;
8e4d9f81	422	uint32_t value;
e3b2e034	423	ssize_t err;
dafc3bd5	424
cfcbd6d3	425	if (!dig->afmt \|\| !dig->afmt->enabled)
dafc3bd5	426	return;
cfcbd6d3	427	offset = dig->afmt->offset;
dafc3bd5 CK	428
	429	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
	430	r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
3299de95	431	audio.channels, audio.rate, audio.bits_per_sample);
dafc3bd5	432	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
3299de95	433	(int)audio.status_bits, (int)audio.category_code);
dafc3bd5	434
e3b2e034 TR	435	err = hdmi_audio_infoframe_init(&frame);
	436	if (err < 0) {
	437	DRM_ERROR("failed to setup audio infoframe\n");
	438	return;
	439	}
	440
	441	frame.channels = audio.channels;
	442
	443	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
	444	if (err < 0) {
	445	DRM_ERROR("failed to pack audio infoframe\n");
	446	return;
	447	}
dafc3bd5	448
8e4d9f81 RM	449	value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
	450	if (value & HDMI0_AUDIO_TEST_EN)
	451	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
	452	value & ~HDMI0_AUDIO_TEST_EN);
	453
	454	WREG32_OR(HDMI0_CONTROL + offset,
	455	HDMI0_ERROR_ACK);
	456
	457	WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
	458	~HDMI0_AUDIO_INFO_SOURCE);
	459
e3b2e034	460	r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
8e4d9f81 RM	461
	462	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
	463	HDMI0_AUDIO_INFO_CONT \|
	464	HDMI0_AUDIO_INFO_UPDATE);
dafc3bd5 CK	465	}
dafc3bd5 CK	466
dafc3bd5	467	/*
2cd6218c	468	* enable the HDMI engine
dafc3bd5	469	*/
a973bea1	470	void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
dafc3bd5	471	{
2cd6218c RM	472	struct drm_device *dev = encoder->dev;
2cd6218c RM	473	struct radeon_device *rdev = dev->dev_private;
dafc3bd5	474	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3	475	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
a973bea1	476	u32 hdmi = HDMI0_ERROR_ACK;
16823d16	477
c2b4cacf AD	478	if (!dig \|\| !dig->afmt)
	479	return;
	480
64fb4fb0	481	/* Older chipsets require setting HDMI and routing manually */
a973bea1 AD	482	if (!ASIC_IS_DCE3(rdev)) {
	483	if (enable)
	484	hdmi \|= HDMI0_ENABLE;
5715f67c RM	485	switch (radeon_encoder->encoder_id) {
5715f67c RM	486	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
a973bea1 AD	487	if (enable) {
	488	WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
	489	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
	490	} else {
	491	WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
	492	}
5715f67c RM	493	break;
5715f67c RM	494	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
a973bea1 AD	495	if (enable) {
	496	WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
	497	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
	498	} else {
	499	WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
	500	}
64fb4fb0 RM	501	break;
64fb4fb0 RM	502	case ENCODER_OBJECT_ID_INTERNAL_DDI:
a973bea1 AD	503	if (enable) {
	504	WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
	505	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_DDIA);
	506	} else {
	507	WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
	508	}
64fb4fb0 RM	509	break;
64fb4fb0 RM	510	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
a973bea1 AD	511	if (enable)
a973bea1 AD	512	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_DVOA);
5715f67c RM	513	break;
5715f67c RM	514	default:
64fb4fb0 RM	515	dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
64fb4fb0 RM	516	radeon_encoder->encoder_id);
5715f67c RM	517	break;
5715f67c RM	518	}
a973bea1	519	WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
5715f67c	520	}
2cd6218c	521
f122c610	522	if (rdev->irq.installed) {
f2594933	523	/* if irq is available use it */
9054ae1c	524	/* XXX: shouldn't need this on any asics. Double check DCE2/3 */
a973bea1	525	if (enable)
9054ae1c	526	radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
a973bea1 AD	527	else
a973bea1 AD	528	radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
f2594933	529	}
58bd0863	530
a973bea1	531	dig->afmt->enabled = enable;
cfcbd6d3	532
a973bea1 AD	533	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
a973bea1 AD	534	enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
2cd6218c	535	}
dafc3bd5	536