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drm/radeon/dpm: disable sclk ss on rv6xx
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600_hdmi.c
CommitLineData
dafc3bd5
CK		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
e3b2e034 26#include <linux/hdmi.h>
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/radeon_drm.h>
dafc3bd5 29#include "radeon.h"
3574dda4 30#include "radeon_asic.h"
c6543a6e 31#include "r600d.h"
dafc3bd5
CK		 32#include "atom.h"
33
34/*
35 * HDMI color format
36 */
37enum r600_hdmi_color_format {
38 RGB = 0,
39 YCC_422 = 1,
40 YCC_444 = 2
41};
42
43/*
44 * IEC60958 status bits
45 */
46enum r600_hdmi_iec_status_bits {
47 AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9
RM		 48 AUDIO_STATUS_V = 0x02,
49 AUDIO_STATUS_VCFG = 0x04,
dafc3bd5
CK		 50 AUDIO_STATUS_EMPHASIS = 0x08,
51 AUDIO_STATUS_COPYRIGHT = 0x10,
52 AUDIO_STATUS_NONAUDIO = 0x20,
53 AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9 54 AUDIO_STATUS_LEVEL = 0x80
dafc3bd5
CK		 55};
56
1109ca09 57static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
dafc3bd5
CK		 58 /* 32kHz 44.1kHz 48kHz */
59 /* Clock N CTS N CTS N CTS */
60 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
66 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
68 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
71};
72
73/*
74 * calculate CTS value if it's not found in the table
75 */
1b688d08 76static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
dafc3bd5
CK		 77{
78 if (*CTS == 0)
3fe373d9 79 *CTS = clock * N / (128 * freq) * 1000;
dafc3bd5
CK		 80 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
81 N, *CTS, freq);
82}
83
1b688d08
RM		 84struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
85{
86 struct radeon_hdmi_acr res;
87 u8 i;
88
89 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
90 r600_hdmi_predefined_acr[i].clock != 0; i++)
91 ;
92 res = r600_hdmi_predefined_acr[i];
93
94 /* In case some CTS are missing */
95 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
96 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
97 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
98
99 return res;
100}
101
dafc3bd5
CK		 102/*
103 * update the N and CTS parameters for a given pixel clock rate
104 */
105static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
106{
107 struct drm_device *dev = encoder->dev;
108 struct radeon_device *rdev = dev->dev_private;
1b688d08 109 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
cfcbd6d3
RM		 110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
111 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
112 uint32_t offset = dig->afmt->offset;
dafc3bd5 113
1b688d08
RM		 114 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
115 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
dafc3bd5 116
1b688d08
RM		 117 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
118 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
dafc3bd5 119
1b688d08
RM		 120 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
121 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
dafc3bd5
CK		 122}
123
dafc3bd5
CK		 124/*
125 * build a HDMI Video Info Frame
126 */
e3b2e034
TR		 127static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
128 void *buffer, size_t size)
dafc3bd5
CK		 129{
130 struct drm_device *dev = encoder->dev;
131 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
134 uint32_t offset = dig->afmt->offset;
e3b2e034 135 uint8_t *frame = buffer + 3;
f100380e 136 uint8_t *header = buffer;
dafc3bd5 137
c6543a6e 138 WREG32(HDMI0_AVI_INFO0 + offset,
dafc3bd5 139 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 140 WREG32(HDMI0_AVI_INFO1 + offset,
dafc3bd5 141 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
c6543a6e 142 WREG32(HDMI0_AVI_INFO2 + offset,
dafc3bd5 143 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
c6543a6e 144 WREG32(HDMI0_AVI_INFO3 + offset,
f100380e 145 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
dafc3bd5
CK		 146}
147
148/*
149 * build a Audio Info Frame
150 */
e3b2e034
TR		 151static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
152 const void *buffer, size_t size)
dafc3bd5
CK		 153{
154 struct drm_device *dev = encoder->dev;
155 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
157 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
158 uint32_t offset = dig->afmt->offset;
e3b2e034 159 const u8 *frame = buffer + 3;
dafc3bd5 160
c6543a6e 161 WREG32(HDMI0_AUDIO_INFO0 + offset,
dafc3bd5 162 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 163 WREG32(HDMI0_AUDIO_INFO1 + offset,
dafc3bd5
CK		 164 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
165}
166
167/*
168 * test if audio buffer is filled enough to start playing
169 */
cfcbd6d3 170static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
dafc3bd5
CK		 171{
172 struct drm_device *dev = encoder->dev;
173 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
175 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
176 uint32_t offset = dig->afmt->offset;
dafc3bd5 177
c6543a6e 178 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
dafc3bd5
CK		 179}
180
181/*
182 * have buffer status changed since last call?
183 */
184int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
185{
186 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 187 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5
CK		 188 int status, result;
189
cfcbd6d3 190 if (!dig->afmt || !dig->afmt->enabled)
dafc3bd5
CK		 191 return 0;
192
193 status = r600_hdmi_is_audio_buffer_filled(encoder);
cfcbd6d3
RM		 194 result = dig->afmt->last_buffer_filled_status != status;
195 dig->afmt->last_buffer_filled_status = status;
dafc3bd5
CK		 196
197 return result;
198}
199
200/*
201 * write the audio workaround status to the hardware
202 */
cfcbd6d3 203static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
dafc3bd5
CK		 204{
205 struct drm_device *dev = encoder->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3
RM		 208 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
209 uint32_t offset = dig->afmt->offset;
210 bool hdmi_audio_workaround = false; /* FIXME */
211 u32 value;
212
213 if (!hdmi_audio_workaround ||
214 r600_hdmi_is_audio_buffer_filled(encoder))
215 value = 0; /* disable workaround */
216 else
217 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
218 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
219 value, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5
CK		 220}
221
b1f6f47e
AD		 222void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
223{
224 struct drm_device *dev = encoder->dev;
225 struct radeon_device *rdev = dev->dev_private;
226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
227 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
731da21b 228 u32 base_rate = 24000;
b1f6f47e
AD		 229
230 if (!dig || !dig->afmt)
231 return;
232
233 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
234 * doesn't matter which one you use. Just use the first one.
235 */
b1f6f47e
AD		 236 /* XXX two dtos; generally use dto0 for hdmi */
237 /* Express [24MHz / target pixel clock] as an exact rational
238 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
239 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
240 */
1586505a
AD		 241 if (ASIC_IS_DCE3(rdev)) {
242 /* according to the reg specs, this should DCE3.2 only, but in
243 * practice it seems to cover DCE3.0 as well.
244 */
e1accbf0
AD		 245 if (dig->dig_encoder == 0) {
246 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
247 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
248 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
249 } else {
250 WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
251 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
252 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
253 }
1586505a
AD		 254 } else {
255 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
731da21b
AD		 256 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
257 AUDIO_DTO_MODULE(clock / 10));
1586505a 258 }
b1f6f47e 259}
dafc3bd5
CK		 260
261/*
262 * update the info frames with the data from the current display mode
263 */
264void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
265{
266 struct drm_device *dev = encoder->dev;
267 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 268 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
269 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
e3b2e034
TR		 270 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
271 struct hdmi_avi_infoframe frame;
cfcbd6d3 272 uint32_t offset;
e3b2e034 273 ssize_t err;
dafc3bd5 274
c2b4cacf
AD		 275 if (!dig || !dig->afmt)
276 return;
277
cfcbd6d3
RM		 278 /* Silent, r600_hdmi_enable will raise WARN for us */
279 if (!dig->afmt->enabled)
dafc3bd5 280 return;
cfcbd6d3 281 offset = dig->afmt->offset;
dafc3bd5 282
b1f6f47e 283 r600_audio_set_dto(encoder, mode->clock);
dafc3bd5 284
1c3439f2
RM		 285 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
286 HDMI0_NULL_SEND); /* send null packets when required */
287
c6543a6e 288 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
a273a903 289
1c3439f2
RM		 290 if (ASIC_IS_DCE32(rdev)) {
291 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
292 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
293 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
294 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
295 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
296 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
297 } else {
298 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
299 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
300 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
1c3439f2
RM		 301 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
302 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
303 }
a273a903 304
1c3439f2
RM		 305 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
306 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
307 HDMI0_ACR_SOURCE); /* select SW CTS value */
dafc3bd5 308
1c3439f2
RM		 309 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
310 HDMI0_NULL_SEND | /* send null packets when required */
311 HDMI0_GC_SEND | /* send general control packets */
312 HDMI0_GC_CONT); /* send general control packets every frame */
dafc3bd5 313
1c3439f2
RM		 314 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
315 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
316 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
317 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
318 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
319 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
dafc3bd5 320
1c3439f2
RM		 321 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
322 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
323 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
324
325 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
dafc3bd5 326
e3b2e034
TR		 327 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
328 if (err < 0) {
329 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
330 return;
331 }
dafc3bd5 332
e3b2e034
TR		 333 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
334 if (err < 0) {
335 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
336 return;
337 }
338
339 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1c3439f2
RM		 340 r600_hdmi_update_ACR(encoder, mode->clock);
341
25985edc 342 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
c6543a6e
RM		 343 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
344 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
345 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
346 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
dafc3bd5
CK		 347
348 r600_hdmi_audio_workaround(encoder);
dafc3bd5
CK		 349}
350
351/*
352 * update settings with current parameters from audio engine
353 */
58bd0863 354void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5
CK		 355{
356 struct drm_device *dev = encoder->dev;
357 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 358 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
359 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3299de95 360 struct r600_audio audio = r600_audio_status(rdev);
e3b2e034
TR		 361 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
362 struct hdmi_audio_infoframe frame;
cfcbd6d3 363 uint32_t offset;
dafc3bd5 364 uint32_t iec;
e3b2e034 365 ssize_t err;
dafc3bd5 366
cfcbd6d3 367 if (!dig->afmt || !dig->afmt->enabled)
dafc3bd5 368 return;
cfcbd6d3 369 offset = dig->afmt->offset;
dafc3bd5
CK		 370
371 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
372 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
3299de95 373 audio.channels, audio.rate, audio.bits_per_sample);
dafc3bd5 374 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
3299de95 375 (int)audio.status_bits, (int)audio.category_code);
dafc3bd5
CK		 376
377 iec = 0;
3299de95 378 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
dafc3bd5 379 iec |= 1 << 0;
3299de95 380 if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
dafc3bd5 381 iec |= 1 << 1;
3299de95 382 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
dafc3bd5 383 iec |= 1 << 2;
3299de95 384 if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
dafc3bd5
CK		 385 iec |= 1 << 3;
386
3299de95 387 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
dafc3bd5 388
3299de95 389 switch (audio.rate) {
a366e392
RM		 390 case 32000:
391 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
392 break;
393 case 44100:
394 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
395 break;
396 case 48000:
397 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
398 break;
399 case 88200:
400 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
401 break;
402 case 96000:
403 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
404 break;
405 case 176400:
406 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
407 break;
408 case 192000:
409 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
410 break;
dafc3bd5
CK		 411 }
412
c6543a6e 413 WREG32(HDMI0_60958_0 + offset, iec);
dafc3bd5
CK		 414
415 iec = 0;
3299de95 416 switch (audio.bits_per_sample) {
a366e392
RM		 417 case 16:
418 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
419 break;
420 case 20:
421 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
422 break;
423 case 24:
424 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
425 break;
dafc3bd5 426 }
3299de95 427 if (audio.status_bits & AUDIO_STATUS_V)
dafc3bd5 428 iec |= 0x5 << 16;
c6543a6e 429 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
dafc3bd5 430
e3b2e034
TR		 431 err = hdmi_audio_infoframe_init(&frame);
432 if (err < 0) {
433 DRM_ERROR("failed to setup audio infoframe\n");
434 return;
435 }
436
437 frame.channels = audio.channels;
438
439 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
440 if (err < 0) {
441 DRM_ERROR("failed to pack audio infoframe\n");
442 return;
443 }
dafc3bd5 444
e3b2e034 445 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
dafc3bd5 446 r600_hdmi_audio_workaround(encoder);
dafc3bd5
CK		 447}
448
dafc3bd5 449/*
2cd6218c 450 * enable the HDMI engine
dafc3bd5 451 */
a973bea1 452void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
dafc3bd5 453{
2cd6218c
RM		 454 struct drm_device *dev = encoder->dev;
455 struct radeon_device *rdev = dev->dev_private;
dafc3bd5 456 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 457 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
a973bea1 458 u32 hdmi = HDMI0_ERROR_ACK;
16823d16 459
c2b4cacf
AD		 460 if (!dig || !dig->afmt)
461 return;
462
cfcbd6d3 463 /* Silent, r600_hdmi_enable will raise WARN for us */
a973bea1
AD		 464 if (enable && dig->afmt->enabled)
465 return;
466 if (!enable && !dig->afmt->enabled)
cfcbd6d3 467 return;
64fb4fb0
RM		 468
469 /* Older chipsets require setting HDMI and routing manually */
a973bea1
AD		 470 if (!ASIC_IS_DCE3(rdev)) {
471 if (enable)
472 hdmi |= HDMI0_ENABLE;
5715f67c
RM		 473 switch (radeon_encoder->encoder_id) {
474 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
a973bea1
AD		 475 if (enable) {
476 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
477 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
478 } else {
479 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
480 }
5715f67c
RM		 481 break;
482 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
a973bea1
AD		 483 if (enable) {
484 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
485 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
486 } else {
487 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
488 }
64fb4fb0
RM		 489 break;
490 case ENCODER_OBJECT_ID_INTERNAL_DDI:
a973bea1
AD		 491 if (enable) {
492 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
493 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
494 } else {
495 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
496 }
64fb4fb0
RM		 497 break;
498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
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AD		 499 if (enable)
500 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
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RM		 501 break;
502 default:
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RM		 503 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
504 radeon_encoder->encoder_id);
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RM		 505 break;
506 }
a973bea1 507 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
5715f67c 508 }
2cd6218c 509
f122c610 510 if (rdev->irq.installed) {
f2594933 511 /* if irq is available use it */
9054ae1c 512 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
a973bea1 513 if (enable)
9054ae1c 514 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
a973bea1
AD		 515 else
516 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
f2594933 517 }
58bd0863 518
a973bea1 519 dig->afmt->enabled = enable;
cfcbd6d3 520
a973bea1
AD		 521 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
522 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
2cd6218c 523}
dafc3bd5 524
Linux 6.x block layer and io_uring tree(s)