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dafc3bd5 CK |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
3574dda4 | 29 | #include "radeon_asic.h" |
c6543a6e | 30 | #include "r600d.h" |
dafc3bd5 CK |
31 | #include "atom.h" |
32 | ||
33 | /* | |
34 | * HDMI color format | |
35 | */ | |
36 | enum r600_hdmi_color_format { | |
37 | RGB = 0, | |
38 | YCC_422 = 1, | |
39 | YCC_444 = 2 | |
40 | }; | |
41 | ||
42 | /* | |
43 | * IEC60958 status bits | |
44 | */ | |
45 | enum r600_hdmi_iec_status_bits { | |
46 | AUDIO_STATUS_DIG_ENABLE = 0x01, | |
3fe373d9 RM |
47 | AUDIO_STATUS_V = 0x02, |
48 | AUDIO_STATUS_VCFG = 0x04, | |
dafc3bd5 CK |
49 | AUDIO_STATUS_EMPHASIS = 0x08, |
50 | AUDIO_STATUS_COPYRIGHT = 0x10, | |
51 | AUDIO_STATUS_NONAUDIO = 0x20, | |
52 | AUDIO_STATUS_PROFESSIONAL = 0x40, | |
3fe373d9 | 53 | AUDIO_STATUS_LEVEL = 0x80 |
dafc3bd5 CK |
54 | }; |
55 | ||
56 | struct { | |
57 | uint32_t Clock; | |
58 | ||
59 | int N_32kHz; | |
60 | int CTS_32kHz; | |
61 | ||
62 | int N_44_1kHz; | |
63 | int CTS_44_1kHz; | |
64 | ||
65 | int N_48kHz; | |
66 | int CTS_48kHz; | |
67 | ||
68 | } r600_hdmi_ACR[] = { | |
69 | /* 32kHz 44.1kHz 48kHz */ | |
70 | /* Clock N CTS N CTS N CTS */ | |
71 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ | |
72 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ | |
73 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ | |
74 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ | |
75 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ | |
76 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ | |
77 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ | |
78 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ | |
79 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ | |
80 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ | |
81 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ | |
82 | }; | |
83 | ||
84 | /* | |
85 | * calculate CTS value if it's not found in the table | |
86 | */ | |
87 | static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq) | |
88 | { | |
89 | if (*CTS == 0) | |
3fe373d9 | 90 | *CTS = clock * N / (128 * freq) * 1000; |
dafc3bd5 CK |
91 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
92 | N, *CTS, freq); | |
93 | } | |
94 | ||
95 | /* | |
96 | * update the N and CTS parameters for a given pixel clock rate | |
97 | */ | |
98 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
99 | { | |
100 | struct drm_device *dev = encoder->dev; | |
101 | struct radeon_device *rdev = dev->dev_private; | |
102 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; | |
103 | int CTS; | |
104 | int N; | |
105 | int i; | |
106 | ||
107 | for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++); | |
108 | ||
109 | CTS = r600_hdmi_ACR[i].CTS_32kHz; | |
110 | N = r600_hdmi_ACR[i].N_32kHz; | |
111 | r600_hdmi_calc_CTS(clock, &CTS, N, 32000); | |
c6543a6e RM |
112 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(CTS)); |
113 | WREG32(HDMI0_ACR_32_1 + offset, N); | |
dafc3bd5 CK |
114 | |
115 | CTS = r600_hdmi_ACR[i].CTS_44_1kHz; | |
116 | N = r600_hdmi_ACR[i].N_44_1kHz; | |
117 | r600_hdmi_calc_CTS(clock, &CTS, N, 44100); | |
c6543a6e RM |
118 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(CTS)); |
119 | WREG32(HDMI0_ACR_44_1 + offset, N); | |
dafc3bd5 CK |
120 | |
121 | CTS = r600_hdmi_ACR[i].CTS_48kHz; | |
122 | N = r600_hdmi_ACR[i].N_48kHz; | |
123 | r600_hdmi_calc_CTS(clock, &CTS, N, 48000); | |
c6543a6e RM |
124 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(CTS)); |
125 | WREG32(HDMI0_ACR_48_1 + offset, N); | |
dafc3bd5 CK |
126 | } |
127 | ||
128 | /* | |
129 | * calculate the crc for a given info frame | |
130 | */ | |
131 | static void r600_hdmi_infoframe_checksum(uint8_t packetType, | |
132 | uint8_t versionNumber, | |
133 | uint8_t length, | |
134 | uint8_t *frame) | |
135 | { | |
3fe373d9 RM |
136 | int i; |
137 | frame[0] = packetType + versionNumber + length; | |
138 | for (i = 1; i <= length; i++) | |
139 | frame[0] += frame[i]; | |
140 | frame[0] = 0x100 - frame[0]; | |
dafc3bd5 CK |
141 | } |
142 | ||
143 | /* | |
144 | * build a HDMI Video Info Frame | |
145 | */ | |
146 | static void r600_hdmi_videoinfoframe( | |
147 | struct drm_encoder *encoder, | |
148 | enum r600_hdmi_color_format color_format, | |
149 | int active_information_present, | |
150 | uint8_t active_format_aspect_ratio, | |
151 | uint8_t scan_information, | |
152 | uint8_t colorimetry, | |
153 | uint8_t ex_colorimetry, | |
154 | uint8_t quantization, | |
155 | int ITC, | |
156 | uint8_t picture_aspect_ratio, | |
157 | uint8_t video_format_identification, | |
158 | uint8_t pixel_repetition, | |
159 | uint8_t non_uniform_picture_scaling, | |
160 | uint8_t bar_info_data_valid, | |
161 | uint16_t top_bar, | |
162 | uint16_t bottom_bar, | |
163 | uint16_t left_bar, | |
164 | uint16_t right_bar | |
165 | ) | |
166 | { | |
167 | struct drm_device *dev = encoder->dev; | |
168 | struct radeon_device *rdev = dev->dev_private; | |
169 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; | |
170 | ||
171 | uint8_t frame[14]; | |
172 | ||
173 | frame[0x0] = 0; | |
174 | frame[0x1] = | |
175 | (scan_information & 0x3) | | |
176 | ((bar_info_data_valid & 0x3) << 2) | | |
177 | ((active_information_present & 0x1) << 4) | | |
178 | ((color_format & 0x3) << 5); | |
179 | frame[0x2] = | |
180 | (active_format_aspect_ratio & 0xF) | | |
181 | ((picture_aspect_ratio & 0x3) << 4) | | |
182 | ((colorimetry & 0x3) << 6); | |
183 | frame[0x3] = | |
184 | (non_uniform_picture_scaling & 0x3) | | |
185 | ((quantization & 0x3) << 2) | | |
186 | ((ex_colorimetry & 0x7) << 4) | | |
187 | ((ITC & 0x1) << 7); | |
188 | frame[0x4] = (video_format_identification & 0x7F); | |
189 | frame[0x5] = (pixel_repetition & 0xF); | |
190 | frame[0x6] = (top_bar & 0xFF); | |
191 | frame[0x7] = (top_bar >> 8); | |
192 | frame[0x8] = (bottom_bar & 0xFF); | |
193 | frame[0x9] = (bottom_bar >> 8); | |
194 | frame[0xA] = (left_bar & 0xFF); | |
195 | frame[0xB] = (left_bar >> 8); | |
196 | frame[0xC] = (right_bar & 0xFF); | |
197 | frame[0xD] = (right_bar >> 8); | |
198 | ||
199 | r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); | |
92db7f6c RM |
200 | /* Our header values (type, version, length) should be alright, Intel |
201 | * is using the same. Checksum function also seems to be OK, it works | |
202 | * fine for audio infoframe. However calculated value is always lower | |
203 | * by 2 in comparison to fglrx. It breaks displaying anything in case | |
204 | * of TVs that strictly check the checksum. Hack it manually here to | |
205 | * workaround this issue. */ | |
206 | frame[0x0] += 2; | |
dafc3bd5 | 207 | |
c6543a6e | 208 | WREG32(HDMI0_AVI_INFO0 + offset, |
dafc3bd5 | 209 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 210 | WREG32(HDMI0_AVI_INFO1 + offset, |
dafc3bd5 | 211 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
c6543a6e | 212 | WREG32(HDMI0_AVI_INFO2 + offset, |
dafc3bd5 | 213 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
c6543a6e | 214 | WREG32(HDMI0_AVI_INFO3 + offset, |
dafc3bd5 CK |
215 | frame[0xC] | (frame[0xD] << 8)); |
216 | } | |
217 | ||
218 | /* | |
219 | * build a Audio Info Frame | |
220 | */ | |
221 | static void r600_hdmi_audioinfoframe( | |
222 | struct drm_encoder *encoder, | |
223 | uint8_t channel_count, | |
224 | uint8_t coding_type, | |
225 | uint8_t sample_size, | |
226 | uint8_t sample_frequency, | |
227 | uint8_t format, | |
228 | uint8_t channel_allocation, | |
229 | uint8_t level_shift, | |
230 | int downmix_inhibit | |
231 | ) | |
232 | { | |
233 | struct drm_device *dev = encoder->dev; | |
234 | struct radeon_device *rdev = dev->dev_private; | |
235 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; | |
236 | ||
237 | uint8_t frame[11]; | |
238 | ||
239 | frame[0x0] = 0; | |
240 | frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); | |
241 | frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); | |
242 | frame[0x3] = format; | |
243 | frame[0x4] = channel_allocation; | |
244 | frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); | |
245 | frame[0x6] = 0; | |
246 | frame[0x7] = 0; | |
247 | frame[0x8] = 0; | |
248 | frame[0x9] = 0; | |
249 | frame[0xA] = 0; | |
250 | ||
251 | r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); | |
252 | ||
c6543a6e | 253 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
dafc3bd5 | 254 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 255 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
dafc3bd5 CK |
256 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
257 | } | |
258 | ||
259 | /* | |
260 | * test if audio buffer is filled enough to start playing | |
261 | */ | |
262 | static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) | |
263 | { | |
264 | struct drm_device *dev = encoder->dev; | |
265 | struct radeon_device *rdev = dev->dev_private; | |
266 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; | |
267 | ||
c6543a6e | 268 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
dafc3bd5 CK |
269 | } |
270 | ||
271 | /* | |
272 | * have buffer status changed since last call? | |
273 | */ | |
274 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) | |
275 | { | |
276 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
277 | int status, result; | |
278 | ||
af0b5743 | 279 | if (!radeon_encoder->hdmi_enabled) |
dafc3bd5 CK |
280 | return 0; |
281 | ||
282 | status = r600_hdmi_is_audio_buffer_filled(encoder); | |
283 | result = radeon_encoder->hdmi_buffer_status != status; | |
284 | radeon_encoder->hdmi_buffer_status = status; | |
285 | ||
286 | return result; | |
287 | } | |
288 | ||
289 | /* | |
290 | * write the audio workaround status to the hardware | |
291 | */ | |
292 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder) | |
293 | { | |
294 | struct drm_device *dev = encoder->dev; | |
295 | struct radeon_device *rdev = dev->dev_private; | |
296 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
297 | uint32_t offset = radeon_encoder->hdmi_offset; | |
298 | ||
af0b5743 | 299 | if (!radeon_encoder->hdmi_enabled) |
dafc3bd5 CK |
300 | return; |
301 | ||
f2594933 CK |
302 | if (!radeon_encoder->hdmi_audio_workaround || |
303 | r600_hdmi_is_audio_buffer_filled(encoder)) { | |
dafc3bd5 | 304 | |
f2594933 | 305 | /* disable audio workaround */ |
a273a903 RM |
306 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
307 | 0, ~HDMI0_AUDIO_TEST_EN); | |
dafc3bd5 CK |
308 | |
309 | } else { | |
f2594933 | 310 | /* enable audio workaround */ |
a273a903 RM |
311 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
312 | HDMI0_AUDIO_TEST_EN, ~HDMI0_AUDIO_TEST_EN); | |
dafc3bd5 CK |
313 | } |
314 | } | |
315 | ||
316 | ||
317 | /* | |
318 | * update the info frames with the data from the current display mode | |
319 | */ | |
320 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
321 | { | |
322 | struct drm_device *dev = encoder->dev; | |
323 | struct radeon_device *rdev = dev->dev_private; | |
324 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; | |
325 | ||
f83d926a | 326 | if (ASIC_IS_DCE5(rdev)) |
16823d16 AD |
327 | return; |
328 | ||
af0b5743 | 329 | if (!to_radeon_encoder(encoder)->hdmi_enabled) |
dafc3bd5 CK |
330 | return; |
331 | ||
332 | r600_audio_set_clock(encoder, mode->clock); | |
333 | ||
c6543a6e RM |
334 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
335 | WREG32(HDMI0_GC + offset, 0x0); | |
a273a903 RM |
336 | |
337 | /* Send audio packets */ | |
338 | if (ASIC_IS_DCE4(rdev)) | |
339 | WREG32_P(0x74fc + offset, | |
340 | AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND); | |
341 | else if (ASIC_IS_DCE32(rdev)) | |
342 | WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, | |
343 | AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND); | |
344 | else | |
345 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
346 | HDMI0_AUDIO_SAMPLE_SEND, ~HDMI0_AUDIO_SAMPLE_SEND); | |
347 | ||
c6543a6e | 348 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 0x1000); |
dafc3bd5 CK |
349 | |
350 | r600_hdmi_update_ACR(encoder, mode->clock); | |
351 | ||
c6543a6e | 352 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 0x13); |
dafc3bd5 | 353 | |
c6543a6e | 354 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 0x202); |
dafc3bd5 CK |
355 | |
356 | r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, | |
357 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); | |
358 | ||
25985edc | 359 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
c6543a6e RM |
360 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
361 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); | |
362 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); | |
363 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); | |
dafc3bd5 CK |
364 | |
365 | r600_hdmi_audio_workaround(encoder); | |
366 | ||
367 | /* audio packets per line, does anyone know how to calc this ? */ | |
c6543a6e | 368 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000); |
dafc3bd5 CK |
369 | } |
370 | ||
371 | /* | |
372 | * update settings with current parameters from audio engine | |
373 | */ | |
58bd0863 | 374 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
dafc3bd5 CK |
375 | { |
376 | struct drm_device *dev = encoder->dev; | |
377 | struct radeon_device *rdev = dev->dev_private; | |
378 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; | |
379 | ||
58bd0863 CK |
380 | int channels = r600_audio_channels(rdev); |
381 | int rate = r600_audio_rate(rdev); | |
382 | int bps = r600_audio_bits_per_sample(rdev); | |
383 | uint8_t status_bits = r600_audio_status_bits(rdev); | |
384 | uint8_t category_code = r600_audio_category_code(rdev); | |
385 | ||
dafc3bd5 CK |
386 | uint32_t iec; |
387 | ||
af0b5743 | 388 | if (!to_radeon_encoder(encoder)->hdmi_enabled) |
dafc3bd5 CK |
389 | return; |
390 | ||
391 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", | |
392 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", | |
393 | channels, rate, bps); | |
394 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", | |
395 | (int)status_bits, (int)category_code); | |
396 | ||
397 | iec = 0; | |
398 | if (status_bits & AUDIO_STATUS_PROFESSIONAL) | |
399 | iec |= 1 << 0; | |
400 | if (status_bits & AUDIO_STATUS_NONAUDIO) | |
401 | iec |= 1 << 1; | |
402 | if (status_bits & AUDIO_STATUS_COPYRIGHT) | |
403 | iec |= 1 << 2; | |
404 | if (status_bits & AUDIO_STATUS_EMPHASIS) | |
405 | iec |= 1 << 3; | |
406 | ||
407 | iec |= category_code << 8; | |
408 | ||
409 | switch (rate) { | |
410 | case 32000: iec |= 0x3 << 24; break; | |
411 | case 44100: iec |= 0x0 << 24; break; | |
412 | case 88200: iec |= 0x8 << 24; break; | |
413 | case 176400: iec |= 0xc << 24; break; | |
414 | case 48000: iec |= 0x2 << 24; break; | |
415 | case 96000: iec |= 0xa << 24; break; | |
416 | case 192000: iec |= 0xe << 24; break; | |
417 | } | |
418 | ||
c6543a6e | 419 | WREG32(HDMI0_60958_0 + offset, iec); |
dafc3bd5 CK |
420 | |
421 | iec = 0; | |
422 | switch (bps) { | |
423 | case 16: iec |= 0x2; break; | |
424 | case 20: iec |= 0x3; break; | |
425 | case 24: iec |= 0xb; break; | |
426 | } | |
427 | if (status_bits & AUDIO_STATUS_V) | |
428 | iec |= 0x5 << 16; | |
429 | ||
c6543a6e | 430 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
dafc3bd5 CK |
431 | |
432 | /* 0x021 or 0x031 sets the audio frame length */ | |
c6543a6e | 433 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 0x31); |
dafc3bd5 CK |
434 | r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0); |
435 | ||
436 | r600_hdmi_audio_workaround(encoder); | |
dafc3bd5 CK |
437 | } |
438 | ||
2cd6218c | 439 | static void r600_hdmi_assign_block(struct drm_encoder *encoder) |
dafc3bd5 CK |
440 | { |
441 | struct drm_device *dev = encoder->dev; | |
442 | struct radeon_device *rdev = dev->dev_private; | |
443 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2cd6218c | 444 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
dafc3bd5 | 445 | |
f83d926a RM |
446 | u16 eg_offsets[] = { |
447 | EVERGREEN_CRTC0_REGISTER_OFFSET, | |
448 | EVERGREEN_CRTC1_REGISTER_OFFSET, | |
449 | EVERGREEN_CRTC2_REGISTER_OFFSET, | |
450 | EVERGREEN_CRTC3_REGISTER_OFFSET, | |
451 | EVERGREEN_CRTC4_REGISTER_OFFSET, | |
452 | EVERGREEN_CRTC5_REGISTER_OFFSET, | |
453 | }; | |
454 | ||
2cd6218c RM |
455 | if (!dig) { |
456 | dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n"); | |
dafc3bd5 | 457 | return; |
2cd6218c | 458 | } |
dafc3bd5 | 459 | |
ebcb796f RM |
460 | if (ASIC_IS_DCE5(rdev)) { |
461 | /* TODO */ | |
462 | } else if (ASIC_IS_DCE4(rdev)) { | |
f83d926a RM |
463 | if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) { |
464 | dev_err(rdev->dev, "Enabling HDMI on unknown dig\n"); | |
465 | return; | |
466 | } | |
c6543a6e RM |
467 | radeon_encoder->hdmi_offset = eg_offsets[dig->dig_encoder]; |
468 | /* Temp hack for Evergreen until we split r600_hdmi.c | |
469 | * Evergreen first block is 0x7030 instead of 0x7400. | |
470 | */ | |
471 | radeon_encoder->hdmi_offset -= 0x3d0; | |
2cd6218c RM |
472 | } else if (ASIC_IS_DCE3(rdev)) { |
473 | radeon_encoder->hdmi_offset = dig->dig_encoder ? | |
c6543a6e | 474 | DCE3_HDMI_OFFSET1 : DCE3_HDMI_OFFSET0; |
816ce437 RM |
475 | } else if (rdev->family >= CHIP_R600) { |
476 | /* 2 routable blocks, but using dig_encoder should be fine */ | |
477 | radeon_encoder->hdmi_offset = dig->dig_encoder ? | |
c6543a6e | 478 | DCE2_HDMI_OFFSET1 : DCE2_HDMI_OFFSET0; |
816ce437 RM |
479 | } else if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || |
480 | rdev->family == CHIP_RS740) { | |
481 | /* Only 1 routable block */ | |
c6543a6e | 482 | radeon_encoder->hdmi_offset = DCE2_HDMI_OFFSET0; |
dafc3bd5 | 483 | } |
af0b5743 | 484 | radeon_encoder->hdmi_enabled = true; |
dafc3bd5 CK |
485 | } |
486 | ||
487 | /* | |
2cd6218c | 488 | * enable the HDMI engine |
dafc3bd5 | 489 | */ |
2cd6218c | 490 | void r600_hdmi_enable(struct drm_encoder *encoder) |
dafc3bd5 | 491 | { |
2cd6218c RM |
492 | struct drm_device *dev = encoder->dev; |
493 | struct radeon_device *rdev = dev->dev_private; | |
dafc3bd5 | 494 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
f2594933 | 495 | uint32_t offset; |
dafc3bd5 | 496 | |
f83d926a | 497 | if (ASIC_IS_DCE5(rdev)) |
16823d16 AD |
498 | return; |
499 | ||
af0b5743 | 500 | if (!radeon_encoder->hdmi_enabled) { |
2cd6218c | 501 | r600_hdmi_assign_block(encoder); |
af0b5743 | 502 | if (!radeon_encoder->hdmi_enabled) { |
2cd6218c RM |
503 | dev_warn(rdev->dev, "Could not find HDMI block for " |
504 | "0x%x encoder\n", radeon_encoder->encoder_id); | |
505 | return; | |
dafc3bd5 | 506 | } |
2cd6218c | 507 | } |
dafc3bd5 | 508 | |
f2594933 | 509 | offset = radeon_encoder->hdmi_offset; |
ebcb796f RM |
510 | if (ASIC_IS_DCE5(rdev)) { |
511 | /* TODO */ | |
ebcb796f RM |
512 | } else if (ASIC_IS_DCE3(rdev)) { |
513 | /* TODO */ | |
514 | } else if (rdev->family >= CHIP_R600) { | |
5715f67c RM |
515 | switch (radeon_encoder->encoder_id) { |
516 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
93a4ed87 RM |
517 | WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, |
518 | ~AVIVO_TMDSA_CNTL_HDMI_EN); | |
c6543a6e | 519 | WREG32(HDMI0_CONTROL + offset, 0x101); |
5715f67c RM |
520 | break; |
521 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
93a4ed87 RM |
522 | WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, |
523 | ~AVIVO_LVTMA_CNTL_HDMI_EN); | |
c6543a6e | 524 | WREG32(HDMI0_CONTROL + offset, 0x105); |
5715f67c RM |
525 | break; |
526 | default: | |
527 | dev_err(rdev->dev, "Unknown HDMI output type\n"); | |
528 | break; | |
529 | } | |
530 | } | |
2cd6218c | 531 | |
f122c610 | 532 | if (rdev->irq.installed) { |
f2594933 | 533 | /* if irq is available use it */ |
c6543a6e | 534 | rdev->irq.afmt[offset == 0 ? 0 : 1] = true; |
f2594933 | 535 | radeon_irq_set(rdev); |
f2594933 | 536 | } |
58bd0863 | 537 | |
2cd6218c RM |
538 | DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
539 | radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); | |
540 | } | |
dafc3bd5 | 541 | |
2cd6218c RM |
542 | /* |
543 | * disable the HDMI engine | |
544 | */ | |
545 | void r600_hdmi_disable(struct drm_encoder *encoder) | |
546 | { | |
547 | struct drm_device *dev = encoder->dev; | |
548 | struct radeon_device *rdev = dev->dev_private; | |
549 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
66989987 | 550 | uint32_t offset; |
2cd6218c | 551 | |
f83d926a | 552 | if (ASIC_IS_DCE5(rdev)) |
16823d16 AD |
553 | return; |
554 | ||
f2594933 | 555 | offset = radeon_encoder->hdmi_offset; |
af0b5743 | 556 | if (!radeon_encoder->hdmi_enabled) { |
2cd6218c RM |
557 | dev_err(rdev->dev, "Disabling not enabled HDMI\n"); |
558 | return; | |
dafc3bd5 CK |
559 | } |
560 | ||
2cd6218c | 561 | DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
f2594933 CK |
562 | offset, radeon_encoder->encoder_id); |
563 | ||
564 | /* disable irq */ | |
c6543a6e | 565 | rdev->irq.afmt[offset == 0 ? 0 : 1] = false; |
f2594933 CK |
566 | radeon_irq_set(rdev); |
567 | ||
2cd6218c | 568 | |
f83d926a RM |
569 | if (ASIC_IS_DCE5(rdev)) { |
570 | /* TODO */ | |
5715f67c | 571 | } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
5715f67c RM |
572 | switch (radeon_encoder->encoder_id) { |
573 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
93a4ed87 RM |
574 | WREG32_P(AVIVO_TMDSA_CNTL, 0, |
575 | ~AVIVO_TMDSA_CNTL_HDMI_EN); | |
c6543a6e | 576 | WREG32(HDMI0_CONTROL + offset, 0); |
5715f67c RM |
577 | break; |
578 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
93a4ed87 RM |
579 | WREG32_P(AVIVO_LVTMA_CNTL, 0, |
580 | ~AVIVO_LVTMA_CNTL_HDMI_EN); | |
c6543a6e | 581 | WREG32(HDMI0_CONTROL + offset, 0); |
5715f67c RM |
582 | break; |
583 | default: | |
584 | dev_err(rdev->dev, "Unknown HDMI output type\n"); | |
585 | break; | |
586 | } | |
587 | } | |
dafc3bd5 | 588 | |
af0b5743 | 589 | radeon_encoder->hdmi_enabled = false; |
2cd6218c | 590 | radeon_encoder->hdmi_offset = 0; |
dafc3bd5 | 591 | } |