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dafc3bd5 CK |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | */ | |
e3b2e034 | 26 | #include <linux/hdmi.h> |
a2098250 | 27 | #include <linux/gcd.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
dafc3bd5 | 30 | #include "radeon.h" |
3574dda4 | 31 | #include "radeon_asic.h" |
c6543a6e | 32 | #include "r600d.h" |
dafc3bd5 CK |
33 | #include "atom.h" |
34 | ||
35 | /* | |
36 | * HDMI color format | |
37 | */ | |
38 | enum r600_hdmi_color_format { | |
39 | RGB = 0, | |
40 | YCC_422 = 1, | |
41 | YCC_444 = 2 | |
42 | }; | |
43 | ||
44 | /* | |
45 | * IEC60958 status bits | |
46 | */ | |
47 | enum r600_hdmi_iec_status_bits { | |
48 | AUDIO_STATUS_DIG_ENABLE = 0x01, | |
3fe373d9 RM |
49 | AUDIO_STATUS_V = 0x02, |
50 | AUDIO_STATUS_VCFG = 0x04, | |
dafc3bd5 CK |
51 | AUDIO_STATUS_EMPHASIS = 0x08, |
52 | AUDIO_STATUS_COPYRIGHT = 0x10, | |
53 | AUDIO_STATUS_NONAUDIO = 0x20, | |
54 | AUDIO_STATUS_PROFESSIONAL = 0x40, | |
3fe373d9 | 55 | AUDIO_STATUS_LEVEL = 0x80 |
dafc3bd5 CK |
56 | }; |
57 | ||
1109ca09 | 58 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
dafc3bd5 CK |
59 | /* 32kHz 44.1kHz 48kHz */ |
60 | /* Clock N CTS N CTS N CTS */ | |
3e71985f | 61 | { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ |
dafc3bd5 CK |
62 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
63 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ | |
64 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ | |
65 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ | |
66 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ | |
3e71985f | 67 | { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ |
dafc3bd5 | 68 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
3e71985f | 69 | { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ |
dafc3bd5 | 70 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
dafc3bd5 CK |
71 | }; |
72 | ||
a2098250 | 73 | |
dafc3bd5 | 74 | /* |
a2098250 | 75 | * calculate CTS and N values if they are not found in the table |
dafc3bd5 | 76 | */ |
a2098250 | 77 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) |
dafc3bd5 | 78 | { |
a2098250 PO |
79 | int n, cts; |
80 | unsigned long div, mul; | |
81 | ||
82 | /* Safe, but overly large values */ | |
83 | n = 128 * freq; | |
84 | cts = clock * 1000; | |
85 | ||
86 | /* Smallest valid fraction */ | |
87 | div = gcd(n, cts); | |
88 | ||
89 | n /= div; | |
90 | cts /= div; | |
91 | ||
92 | /* | |
93 | * The optimal N is 128*freq/1000. Calculate the closest larger | |
94 | * value that doesn't truncate any bits. | |
95 | */ | |
96 | mul = ((128*freq/1000) + (n-1))/n; | |
97 | ||
98 | n *= mul; | |
99 | cts *= mul; | |
100 | ||
101 | /* Check that we are in spec (not always possible) */ | |
102 | if (n < (128*freq/1500)) | |
103 | printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); | |
104 | if (n > (128*freq/300)) | |
105 | printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); | |
106 | ||
107 | *N = n; | |
108 | *CTS = cts; | |
109 | ||
110 | DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", | |
111 | *N, *CTS, freq); | |
dafc3bd5 CK |
112 | } |
113 | ||
1b688d08 RM |
114 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
115 | { | |
116 | struct radeon_hdmi_acr res; | |
117 | u8 i; | |
118 | ||
a2098250 PO |
119 | /* Precalculated values for common clocks */ |
120 | for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) { | |
121 | if (r600_hdmi_predefined_acr[i].clock == clock) | |
122 | return r600_hdmi_predefined_acr[i]; | |
123 | } | |
1b688d08 | 124 | |
a2098250 PO |
125 | /* And odd clocks get manually calculated */ |
126 | r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); | |
127 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); | |
128 | r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); | |
1b688d08 RM |
129 | |
130 | return res; | |
131 | } | |
132 | ||
dafc3bd5 CK |
133 | /* |
134 | * update the N and CTS parameters for a given pixel clock rate | |
135 | */ | |
136 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
137 | { | |
138 | struct drm_device *dev = encoder->dev; | |
139 | struct radeon_device *rdev = dev->dev_private; | |
1b688d08 | 140 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
cfcbd6d3 RM |
141 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
142 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
143 | uint32_t offset = dig->afmt->offset; | |
dafc3bd5 | 144 | |
1b688d08 RM |
145 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); |
146 | WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); | |
dafc3bd5 | 147 | |
1b688d08 RM |
148 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); |
149 | WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); | |
dafc3bd5 | 150 | |
1b688d08 RM |
151 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); |
152 | WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); | |
dafc3bd5 CK |
153 | } |
154 | ||
dafc3bd5 CK |
155 | /* |
156 | * build a HDMI Video Info Frame | |
157 | */ | |
e3b2e034 TR |
158 | static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
159 | void *buffer, size_t size) | |
dafc3bd5 CK |
160 | { |
161 | struct drm_device *dev = encoder->dev; | |
162 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
163 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
164 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
165 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 166 | uint8_t *frame = buffer + 3; |
f100380e | 167 | uint8_t *header = buffer; |
dafc3bd5 | 168 | |
c6543a6e | 169 | WREG32(HDMI0_AVI_INFO0 + offset, |
dafc3bd5 | 170 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 171 | WREG32(HDMI0_AVI_INFO1 + offset, |
dafc3bd5 | 172 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
c6543a6e | 173 | WREG32(HDMI0_AVI_INFO2 + offset, |
dafc3bd5 | 174 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
c6543a6e | 175 | WREG32(HDMI0_AVI_INFO3 + offset, |
f100380e | 176 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
dafc3bd5 CK |
177 | } |
178 | ||
179 | /* | |
180 | * build a Audio Info Frame | |
181 | */ | |
e3b2e034 TR |
182 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
183 | const void *buffer, size_t size) | |
dafc3bd5 CK |
184 | { |
185 | struct drm_device *dev = encoder->dev; | |
186 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
187 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
188 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
189 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 190 | const u8 *frame = buffer + 3; |
dafc3bd5 | 191 | |
c6543a6e | 192 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
dafc3bd5 | 193 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 194 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
dafc3bd5 CK |
195 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
196 | } | |
197 | ||
198 | /* | |
199 | * test if audio buffer is filled enough to start playing | |
200 | */ | |
cfcbd6d3 | 201 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
dafc3bd5 CK |
202 | { |
203 | struct drm_device *dev = encoder->dev; | |
204 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
205 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
206 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
207 | uint32_t offset = dig->afmt->offset; | |
dafc3bd5 | 208 | |
c6543a6e | 209 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
dafc3bd5 CK |
210 | } |
211 | ||
212 | /* | |
213 | * have buffer status changed since last call? | |
214 | */ | |
215 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) | |
216 | { | |
217 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
cfcbd6d3 | 218 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
dafc3bd5 CK |
219 | int status, result; |
220 | ||
cfcbd6d3 | 221 | if (!dig->afmt || !dig->afmt->enabled) |
dafc3bd5 CK |
222 | return 0; |
223 | ||
224 | status = r600_hdmi_is_audio_buffer_filled(encoder); | |
cfcbd6d3 RM |
225 | result = dig->afmt->last_buffer_filled_status != status; |
226 | dig->afmt->last_buffer_filled_status = status; | |
dafc3bd5 CK |
227 | |
228 | return result; | |
229 | } | |
230 | ||
231 | /* | |
232 | * write the audio workaround status to the hardware | |
233 | */ | |
cfcbd6d3 | 234 | static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
dafc3bd5 CK |
235 | { |
236 | struct drm_device *dev = encoder->dev; | |
237 | struct radeon_device *rdev = dev->dev_private; | |
238 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
cfcbd6d3 RM |
239 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
240 | uint32_t offset = dig->afmt->offset; | |
241 | bool hdmi_audio_workaround = false; /* FIXME */ | |
242 | u32 value; | |
243 | ||
244 | if (!hdmi_audio_workaround || | |
245 | r600_hdmi_is_audio_buffer_filled(encoder)) | |
246 | value = 0; /* disable workaround */ | |
247 | else | |
248 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ | |
249 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
250 | value, ~HDMI0_AUDIO_TEST_EN); | |
dafc3bd5 CK |
251 | } |
252 | ||
b1f6f47e AD |
253 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
254 | { | |
255 | struct drm_device *dev = encoder->dev; | |
256 | struct radeon_device *rdev = dev->dev_private; | |
257 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
258 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
731da21b | 259 | u32 base_rate = 24000; |
1518dd8e AD |
260 | u32 max_ratio = clock / base_rate; |
261 | u32 dto_phase; | |
262 | u32 dto_modulo = clock; | |
263 | u32 wallclock_ratio; | |
264 | u32 dto_cntl; | |
b1f6f47e AD |
265 | |
266 | if (!dig || !dig->afmt) | |
267 | return; | |
268 | ||
1518dd8e AD |
269 | if (max_ratio >= 8) { |
270 | dto_phase = 192 * 1000; | |
271 | wallclock_ratio = 3; | |
272 | } else if (max_ratio >= 4) { | |
273 | dto_phase = 96 * 1000; | |
274 | wallclock_ratio = 2; | |
275 | } else if (max_ratio >= 2) { | |
276 | dto_phase = 48 * 1000; | |
277 | wallclock_ratio = 1; | |
278 | } else { | |
279 | dto_phase = 24 * 1000; | |
280 | wallclock_ratio = 0; | |
281 | } | |
282 | ||
b1f6f47e AD |
283 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
284 | * doesn't matter which one you use. Just use the first one. | |
285 | */ | |
b1f6f47e AD |
286 | /* XXX two dtos; generally use dto0 for hdmi */ |
287 | /* Express [24MHz / target pixel clock] as an exact rational | |
288 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
289 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
290 | */ | |
58d327da | 291 | if (ASIC_IS_DCE32(rdev)) { |
e1accbf0 | 292 | if (dig->dig_encoder == 0) { |
1518dd8e AD |
293 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
294 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); | |
295 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); | |
296 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); | |
297 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); | |
e1accbf0 AD |
298 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
299 | } else { | |
1518dd8e AD |
300 | dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
301 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); | |
302 | WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); | |
303 | WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); | |
304 | WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); | |
e1accbf0 AD |
305 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
306 | } | |
58d327da AD |
307 | } else if (ASIC_IS_DCE3(rdev)) { |
308 | /* according to the reg specs, this should DCE3.2 only, but in | |
309 | * practice it seems to cover DCE3.0/3.1 as well. | |
310 | */ | |
311 | if (dig->dig_encoder == 0) { | |
312 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); | |
313 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); | |
314 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ | |
315 | } else { | |
316 | WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); | |
317 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); | |
318 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ | |
319 | } | |
1586505a | 320 | } else { |
58d327da | 321 | /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */ |
731da21b AD |
322 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
323 | AUDIO_DTO_MODULE(clock / 10)); | |
1586505a | 324 | } |
b1f6f47e | 325 | } |
dafc3bd5 | 326 | |
0ffae60c AD |
327 | static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
328 | { | |
329 | struct radeon_device *rdev = encoder->dev->dev_private; | |
330 | struct drm_connector *connector; | |
331 | struct radeon_connector *radeon_connector = NULL; | |
332 | u32 tmp; | |
333 | u8 *sadb; | |
334 | int sad_count; | |
335 | ||
4b749577 AD |
336 | /* XXX: setting this register causes hangs on some asics */ |
337 | return; | |
338 | ||
0ffae60c | 339 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
8a992ee1 | 340 | if (connector->encoder == encoder) { |
0ffae60c | 341 | radeon_connector = to_radeon_connector(connector); |
8a992ee1 AD |
342 | break; |
343 | } | |
0ffae60c AD |
344 | } |
345 | ||
346 | if (!radeon_connector) { | |
347 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
348 | return; | |
349 | } | |
350 | ||
351 | sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); | |
352 | if (sad_count < 0) { | |
353 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); | |
354 | return; | |
355 | } | |
356 | ||
357 | /* program the speaker allocation */ | |
358 | tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); | |
359 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); | |
360 | /* set HDMI mode */ | |
361 | tmp |= HDMI_CONNECTION; | |
362 | if (sad_count) | |
363 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
364 | else | |
365 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
366 | WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); | |
367 | ||
368 | kfree(sadb); | |
369 | } | |
370 | ||
c1cbee0e AD |
371 | static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder) |
372 | { | |
373 | struct radeon_device *rdev = encoder->dev->dev_private; | |
374 | struct drm_connector *connector; | |
375 | struct radeon_connector *radeon_connector = NULL; | |
376 | struct cea_sad *sads; | |
377 | int i, sad_count; | |
378 | ||
379 | static const u16 eld_reg_to_type[][2] = { | |
380 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
381 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
382 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
383 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
384 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
385 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
386 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
387 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
388 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
389 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
390 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
391 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
392 | }; | |
393 | ||
394 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
8a992ee1 | 395 | if (connector->encoder == encoder) { |
c1cbee0e | 396 | radeon_connector = to_radeon_connector(connector); |
8a992ee1 AD |
397 | break; |
398 | } | |
c1cbee0e AD |
399 | } |
400 | ||
401 | if (!radeon_connector) { | |
402 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
403 | return; | |
404 | } | |
405 | ||
406 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); | |
407 | if (sad_count < 0) { | |
408 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); | |
409 | return; | |
410 | } | |
411 | BUG_ON(!sads); | |
412 | ||
413 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { | |
414 | u32 value = 0; | |
0f57bca9 AH |
415 | u8 stereo_freqs = 0; |
416 | int max_channels = -1; | |
c1cbee0e AD |
417 | int j; |
418 | ||
419 | for (j = 0; j < sad_count; j++) { | |
420 | struct cea_sad *sad = &sads[j]; | |
421 | ||
422 | if (sad->format == eld_reg_to_type[i][1]) { | |
0f57bca9 AH |
423 | if (sad->channels > max_channels) { |
424 | value = MAX_CHANNELS(sad->channels) | | |
425 | DESCRIPTOR_BYTE_2(sad->byte2) | | |
426 | SUPPORTED_FREQUENCIES(sad->freq); | |
427 | max_channels = sad->channels; | |
428 | } | |
429 | ||
c1cbee0e | 430 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
0f57bca9 AH |
431 | stereo_freqs |= sad->freq; |
432 | else | |
433 | break; | |
c1cbee0e AD |
434 | } |
435 | } | |
0f57bca9 AH |
436 | |
437 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); | |
438 | ||
c1cbee0e AD |
439 | WREG32(eld_reg_to_type[i][0], value); |
440 | } | |
441 | ||
442 | kfree(sads); | |
443 | } | |
444 | ||
dafc3bd5 CK |
445 | /* |
446 | * update the info frames with the data from the current display mode | |
447 | */ | |
448 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
449 | { | |
450 | struct drm_device *dev = encoder->dev; | |
451 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
452 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
453 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
e3b2e034 TR |
454 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
455 | struct hdmi_avi_infoframe frame; | |
cfcbd6d3 | 456 | uint32_t offset; |
e3b2e034 | 457 | ssize_t err; |
dafc3bd5 | 458 | |
c2b4cacf AD |
459 | if (!dig || !dig->afmt) |
460 | return; | |
461 | ||
cfcbd6d3 RM |
462 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
463 | if (!dig->afmt->enabled) | |
dafc3bd5 | 464 | return; |
cfcbd6d3 | 465 | offset = dig->afmt->offset; |
dafc3bd5 | 466 | |
b1f6f47e | 467 | r600_audio_set_dto(encoder, mode->clock); |
dafc3bd5 | 468 | |
1c3439f2 RM |
469 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
470 | HDMI0_NULL_SEND); /* send null packets when required */ | |
471 | ||
c6543a6e | 472 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
a273a903 | 473 | |
1c3439f2 RM |
474 | if (ASIC_IS_DCE32(rdev)) { |
475 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
476 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ | |
477 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | |
478 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, | |
479 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ | |
480 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | |
481 | } else { | |
482 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
483 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ | |
484 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ | |
1c3439f2 RM |
485 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
486 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | |
487 | } | |
a273a903 | 488 | |
c1cbee0e | 489 | if (ASIC_IS_DCE32(rdev)) { |
0ffae60c | 490 | dce3_2_afmt_write_speaker_allocation(encoder); |
c1cbee0e AD |
491 | dce3_2_afmt_write_sad_regs(encoder); |
492 | } | |
0ffae60c | 493 | |
1c3439f2 | 494 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
b852c985 | 495 | HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ |
ee0fec31 | 496 | HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
dafc3bd5 | 497 | |
1c3439f2 RM |
498 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
499 | HDMI0_NULL_SEND | /* send null packets when required */ | |
500 | HDMI0_GC_SEND | /* send general control packets */ | |
501 | HDMI0_GC_CONT); /* send general control packets every frame */ | |
dafc3bd5 | 502 | |
1c3439f2 RM |
503 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
504 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, | |
505 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ | |
506 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ | |
507 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | |
508 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ | |
dafc3bd5 | 509 | |
1c3439f2 RM |
510 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
511 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ | |
512 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ | |
513 | ||
514 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ | |
dafc3bd5 | 515 | |
e3b2e034 TR |
516 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
517 | if (err < 0) { | |
518 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
519 | return; | |
520 | } | |
dafc3bd5 | 521 | |
e3b2e034 TR |
522 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
523 | if (err < 0) { | |
524 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
525 | return; | |
526 | } | |
527 | ||
528 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); | |
1c3439f2 RM |
529 | r600_hdmi_update_ACR(encoder, mode->clock); |
530 | ||
25985edc | 531 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
c6543a6e RM |
532 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
533 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); | |
534 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); | |
535 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); | |
dafc3bd5 CK |
536 | |
537 | r600_hdmi_audio_workaround(encoder); | |
dafc3bd5 CK |
538 | } |
539 | ||
540 | /* | |
541 | * update settings with current parameters from audio engine | |
542 | */ | |
58bd0863 | 543 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
dafc3bd5 CK |
544 | { |
545 | struct drm_device *dev = encoder->dev; | |
546 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
547 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
548 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
b530602f | 549 | struct r600_audio_pin audio = r600_audio_status(rdev); |
e3b2e034 TR |
550 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
551 | struct hdmi_audio_infoframe frame; | |
cfcbd6d3 | 552 | uint32_t offset; |
dafc3bd5 | 553 | uint32_t iec; |
e3b2e034 | 554 | ssize_t err; |
dafc3bd5 | 555 | |
cfcbd6d3 | 556 | if (!dig->afmt || !dig->afmt->enabled) |
dafc3bd5 | 557 | return; |
cfcbd6d3 | 558 | offset = dig->afmt->offset; |
dafc3bd5 CK |
559 | |
560 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", | |
561 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", | |
3299de95 | 562 | audio.channels, audio.rate, audio.bits_per_sample); |
dafc3bd5 | 563 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
3299de95 | 564 | (int)audio.status_bits, (int)audio.category_code); |
dafc3bd5 CK |
565 | |
566 | iec = 0; | |
3299de95 | 567 | if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) |
dafc3bd5 | 568 | iec |= 1 << 0; |
3299de95 | 569 | if (audio.status_bits & AUDIO_STATUS_NONAUDIO) |
dafc3bd5 | 570 | iec |= 1 << 1; |
3299de95 | 571 | if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) |
dafc3bd5 | 572 | iec |= 1 << 2; |
3299de95 | 573 | if (audio.status_bits & AUDIO_STATUS_EMPHASIS) |
dafc3bd5 CK |
574 | iec |= 1 << 3; |
575 | ||
3299de95 | 576 | iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); |
dafc3bd5 | 577 | |
3299de95 | 578 | switch (audio.rate) { |
a366e392 RM |
579 | case 32000: |
580 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); | |
581 | break; | |
582 | case 44100: | |
583 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); | |
584 | break; | |
585 | case 48000: | |
586 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); | |
587 | break; | |
588 | case 88200: | |
589 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); | |
590 | break; | |
591 | case 96000: | |
592 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); | |
593 | break; | |
594 | case 176400: | |
595 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); | |
596 | break; | |
597 | case 192000: | |
598 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); | |
599 | break; | |
dafc3bd5 CK |
600 | } |
601 | ||
c6543a6e | 602 | WREG32(HDMI0_60958_0 + offset, iec); |
dafc3bd5 CK |
603 | |
604 | iec = 0; | |
3299de95 | 605 | switch (audio.bits_per_sample) { |
a366e392 RM |
606 | case 16: |
607 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); | |
608 | break; | |
609 | case 20: | |
610 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); | |
611 | break; | |
612 | case 24: | |
613 | iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); | |
614 | break; | |
dafc3bd5 | 615 | } |
3299de95 | 616 | if (audio.status_bits & AUDIO_STATUS_V) |
dafc3bd5 | 617 | iec |= 0x5 << 16; |
c6543a6e | 618 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
dafc3bd5 | 619 | |
e3b2e034 TR |
620 | err = hdmi_audio_infoframe_init(&frame); |
621 | if (err < 0) { | |
622 | DRM_ERROR("failed to setup audio infoframe\n"); | |
623 | return; | |
624 | } | |
625 | ||
626 | frame.channels = audio.channels; | |
627 | ||
628 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
629 | if (err < 0) { | |
630 | DRM_ERROR("failed to pack audio infoframe\n"); | |
631 | return; | |
632 | } | |
dafc3bd5 | 633 | |
e3b2e034 | 634 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
dafc3bd5 | 635 | r600_hdmi_audio_workaround(encoder); |
dafc3bd5 CK |
636 | } |
637 | ||
dafc3bd5 | 638 | /* |
2cd6218c | 639 | * enable the HDMI engine |
dafc3bd5 | 640 | */ |
a973bea1 | 641 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
dafc3bd5 | 642 | { |
2cd6218c RM |
643 | struct drm_device *dev = encoder->dev; |
644 | struct radeon_device *rdev = dev->dev_private; | |
dafc3bd5 | 645 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
cfcbd6d3 | 646 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
a973bea1 | 647 | u32 hdmi = HDMI0_ERROR_ACK; |
16823d16 | 648 | |
c2b4cacf AD |
649 | if (!dig || !dig->afmt) |
650 | return; | |
651 | ||
cfcbd6d3 | 652 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
a973bea1 AD |
653 | if (enable && dig->afmt->enabled) |
654 | return; | |
655 | if (!enable && !dig->afmt->enabled) | |
cfcbd6d3 | 656 | return; |
64fb4fb0 | 657 | |
b530602f AD |
658 | if (enable) |
659 | dig->afmt->pin = r600_audio_get_pin(rdev); | |
660 | else | |
661 | dig->afmt->pin = NULL; | |
662 | ||
64fb4fb0 | 663 | /* Older chipsets require setting HDMI and routing manually */ |
a973bea1 AD |
664 | if (!ASIC_IS_DCE3(rdev)) { |
665 | if (enable) | |
666 | hdmi |= HDMI0_ENABLE; | |
5715f67c RM |
667 | switch (radeon_encoder->encoder_id) { |
668 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
a973bea1 AD |
669 | if (enable) { |
670 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); | |
671 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); | |
672 | } else { | |
673 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); | |
674 | } | |
5715f67c RM |
675 | break; |
676 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
a973bea1 AD |
677 | if (enable) { |
678 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); | |
679 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); | |
680 | } else { | |
681 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); | |
682 | } | |
64fb4fb0 RM |
683 | break; |
684 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
a973bea1 AD |
685 | if (enable) { |
686 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); | |
687 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); | |
688 | } else { | |
689 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); | |
690 | } | |
64fb4fb0 RM |
691 | break; |
692 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
a973bea1 AD |
693 | if (enable) |
694 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); | |
5715f67c RM |
695 | break; |
696 | default: | |
64fb4fb0 RM |
697 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
698 | radeon_encoder->encoder_id); | |
5715f67c RM |
699 | break; |
700 | } | |
a973bea1 | 701 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
5715f67c | 702 | } |
2cd6218c | 703 | |
f122c610 | 704 | if (rdev->irq.installed) { |
f2594933 | 705 | /* if irq is available use it */ |
9054ae1c | 706 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
a973bea1 | 707 | if (enable) |
9054ae1c | 708 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
a973bea1 AD |
709 | else |
710 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); | |
f2594933 | 711 | } |
58bd0863 | 712 | |
a973bea1 | 713 | dig->afmt->enabled = enable; |
cfcbd6d3 | 714 | |
a973bea1 AD |
715 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
716 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | |
2cd6218c | 717 | } |
dafc3bd5 | 718 |