[linux-2.6-block.git] / drivers / gpu / drm / radeon / evergreen_hdmi.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Christian König.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 *          Rafał Miłecki
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_asic.h"
#include "radeon_audio.h"
#include "evergreend.h"
#include "atom.h"

/* enable the audio stream */
void dce4_audio_enable(struct radeon_device *rdev,
			      struct r600_audio_pin *pin,
			      u8 enable_mask)
{
	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

	if (!pin)
		return;

	if (enable_mask) {
		tmp |= AUDIO_ENABLED;
		if (enable_mask & 1)
			tmp |= PIN0_AUDIO_ENABLED;
		if (enable_mask & 2)
			tmp |= PIN1_AUDIO_ENABLED;
		if (enable_mask & 4)
			tmp |= PIN2_AUDIO_ENABLED;
		if (enable_mask & 8)
			tmp |= PIN3_AUDIO_ENABLED;
	} else {
		tmp &= ~(AUDIO_ENABLED |
			 PIN0_AUDIO_ENABLED |
			 PIN1_AUDIO_ENABLED |
			 PIN2_AUDIO_ENABLED |
			 PIN3_AUDIO_ENABLED);
	}

	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
}

/*
 * update the N and CTS parameters for a given pixel clock rate
 */
static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;

	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
	WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);

	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
	WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);

	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
}

void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
		struct drm_connector *connector, struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp = 0;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
	}
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
}

void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
	struct cea_sad *sads, int sad_count)
{
	int i;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
	}
}

/*
 * build a AVI Info Frame
 */
void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
    unsigned char *buffer, size_t size)
{
	uint8_t *frame = buffer + 3;

	WREG32(AFMT_AVI_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(AFMT_AVI_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
	WREG32(AFMT_AVI_INFO2 + offset,
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
	WREG32(AFMT_AVI_INFO3 + offset,
		frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
}

void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	unsigned int max_ratio = clock / 24000;
	u32 dto_phase;
	u32 wallclock_ratio;
	u32 value;

	if (max_ratio >= 8) {
		dto_phase = 192 * 1000;
		wallclock_ratio = 3;
	} else if (max_ratio >= 4) {
		dto_phase = 96 * 1000;
		wallclock_ratio = 2;
	} else if (max_ratio >= 2) {
		dto_phase = 48 * 1000;
		wallclock_ratio = 1;
	} else {
		dto_phase = 24 * 1000;
		wallclock_ratio = 0;
	}

	value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
	value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	WREG32(DCCG_AUDIO_DTO0_CNTL, value);

	/* Two dtos; generally use dto0 for HDMI */
	value = 0;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
}

void dce4_dp_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	u32 value;

	value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	WREG32(DCCG_AUDIO_DTO1_CNTL, value);

	/* Two dtos; generally use dto1 for DP */
	value = 0;
	value |= DCCG_AUDIO_DTO_SEL;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);
}

/*
 * update the info frames with the data from the current display mode
 */
void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
	struct hdmi_avi_infoframe frame;
	uint32_t offset;
	ssize_t err;
	uint32_t val;
	int bpc = 8;

	if (!dig || !dig->afmt)
		return;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (!dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	/* hdmi deep color mode general control packets setup, if bpc > 8 */
	if (encoder->crtc) {
		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		bpc = radeon_crtc->bpc;
	}

	/* disable audio prior to setting up hw */
	dig->afmt->pin = radeon_audio_get_pin(encoder);
	radeon_audio_enable(rdev, dig->afmt->pin, 0);

	radeon_audio_set_dto(encoder, mode->clock);

	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	       HDMI_NULL_SEND); /* send null packets when required */

	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);

	val = RREG32(HDMI_CONTROL + offset);
	val &= ~HDMI_DEEP_COLOR_ENABLE;
	val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;

	switch (bpc) {
		case 0:
		case 6:
		case 8:
		case 16:
		default:
			DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
					 connector->name, bpc);
			break;
		case 10:
			val |= HDMI_DEEP_COLOR_ENABLE;
			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
			DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
					 connector->name);
			break;
		case 12:
			val |= HDMI_DEEP_COLOR_ENABLE;
			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
			DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
					 connector->name);
			break;
	}

	WREG32(HDMI_CONTROL + offset, val);

	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	       HDMI_NULL_SEND | /* send null packets when required */
	       HDMI_GC_SEND | /* send general control packets */
	       HDMI_GC_CONT); /* send general control packets every frame */

	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */

	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */

	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */

	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */

	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */

	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */

	if (bpc > 8)
		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
		       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
	else
		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
		       HDMI_ACR_SOURCE | /* select SW CTS value */
		       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */

	evergreen_hdmi_update_ACR(encoder, mode->clock);

	WREG32(AFMT_60958_0 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_L(1));

	WREG32(AFMT_60958_1 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_R(2));

	WREG32(AFMT_60958_2 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
	       AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
	       AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
	       AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
	       AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
	       AFMT_60958_CS_CHANNEL_NUMBER_7(8));

	radeon_audio_write_speaker_allocation(encoder);

	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));

	/* fglrx sets 0x40 in 0x5f80 here */

	radeon_audio_select_pin(encoder);
	radeon_audio_write_sad_regs(encoder);
	radeon_audio_write_latency_fields(encoder, mode);

	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	if (err < 0) {
		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
		return;
	}

	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
		return;
	}

	radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));

	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */

	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
		 ~HDMI_AVI_INFO_LINE_MASK);

	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */

	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);

	/* enable audio after to setting up hw */
	radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
}

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	if (!dig || !dig->afmt)
		return;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (enable && dig->afmt->enabled)
		return;
	if (!enable && !dig->afmt->enabled)
		return;

	if (!enable && dig->afmt->pin) {
		radeon_audio_enable(rdev, dig->afmt->pin, 0);
		dig->afmt->pin = NULL;
	}

	dig->afmt->enabled = enable;

	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
}
Commit	Line	Data
e55d3e6c RM	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Christian König.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Christian König
	25	* Rafał Miłecki
	26	*/
e3b2e034	27	#include <linux/hdmi.h>
760285e7 DH	28	#include <drm/drmP.h>
760285e7 DH	29	#include <drm/radeon_drm.h>
e55d3e6c RM	30	#include "radeon.h"
e55d3e6c RM	31	#include "radeon_asic.h"
070a2e63	32	#include "radeon_audio.h"
e55d3e6c RM	33	#include "evergreend.h"
	34	#include "atom.h"
	35
d3d8c141	36	/* enable the audio stream */
8bf59820	37	void dce4_audio_enable(struct radeon_device *rdev,
d3d8c141 AD	38	struct r600_audio_pin *pin,
	39	u8 enable_mask)
	40	{
	41	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
	42
	43	if (!pin)
	44	return;
	45
	46	if (enable_mask) {
	47	tmp \|= AUDIO_ENABLED;
	48	if (enable_mask & 1)
	49	tmp \|= PIN0_AUDIO_ENABLED;
	50	if (enable_mask & 2)
	51	tmp \|= PIN1_AUDIO_ENABLED;
	52	if (enable_mask & 4)
	53	tmp \|= PIN2_AUDIO_ENABLED;
	54	if (enable_mask & 8)
	55	tmp \|= PIN3_AUDIO_ENABLED;
	56	} else {
	57	tmp &= ~(AUDIO_ENABLED \|
	58	PIN0_AUDIO_ENABLED \|
	59	PIN1_AUDIO_ENABLED \|
	60	PIN2_AUDIO_ENABLED \|
	61	PIN3_AUDIO_ENABLED);
	62	}
	63
	64	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
	65	}
	66
e55d3e6c RM	67	/*
	68	* update the N and CTS parameters for a given pixel clock rate
	69	*/
	70	static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
	71	{
	72	struct drm_device *dev = encoder->dev;
	73	struct radeon_device *rdev = dev->dev_private;
	74	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
cfcbd6d3 RM	75	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	76	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	77	uint32_t offset = dig->afmt->offset;
e55d3e6c RM	78
	79	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
	80	WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
	81
	82	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
	83	WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
	84
	85	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
	86	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
	87	}
	88
87654f87 SG	89	void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
87654f87 SG	90	struct drm_connector connector, struct drm_display_mode mode)
712fd8a2 AD	91	{
712fd8a2 AD	92	struct radeon_device *rdev = encoder->dev->dev_private;
712fd8a2 AD	93	u32 tmp = 0;
712fd8a2 AD	94
712fd8a2 AD	95	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	96	if (connector->latency_present[1])
	97	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	98	AUDIO_LIPSYNC(connector->audio_latency[1]);
	99	else
	100	tmp = VIDEO_LIPSYNC(255) \| AUDIO_LIPSYNC(255);
	101	} else {
	102	if (connector->latency_present[0])
	103	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	104	AUDIO_LIPSYNC(connector->audio_latency[0]);
	105	else
	106	tmp = VIDEO_LIPSYNC(255) \| AUDIO_LIPSYNC(255);
	107	}
87654f87	108	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
712fd8a2 AD	109	}
712fd8a2 AD	110
00a9d4bc SG	111	void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
00a9d4bc SG	112	u8 *sadb, int sad_count)
ba7def4f AD	113	{
ba7def4f AD	114	struct radeon_device *rdev = encoder->dev->dev_private;
ba7def4f	115	u32 tmp;
ba7def4f AD	116
ba7def4f AD	117	/* program the speaker allocation */
00a9d4bc	118	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
ba7def4f AD	119	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	120	/* set HDMI mode */
	121	tmp \|= HDMI_CONNECTION;
	122	if (sad_count)
	123	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	124	else
	125	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
00a9d4bc SG	126	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc SG	127	}
ba7def4f	128
00a9d4bc SG	129	void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	130	u8 *sadb, int sad_count)
	131	{
	132	struct radeon_device *rdev = encoder->dev->dev_private;
	133	u32 tmp;
	134
	135	/* program the speaker allocation */
	136	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	137	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	138	/* set DP mode */
	139	tmp \|= DP_CONNECTION;
	140	if (sad_count)
	141	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	142	else
	143	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	144	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
ba7def4f AD	145	}
ba7def4f AD	146
070a2e63 AD	147	void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
070a2e63 AD	148	struct cea_sad *sads, int sad_count)
46892caa	149	{
070a2e63	150	int i;
46892caa	151	struct radeon_device *rdev = encoder->dev->dev_private;
46892caa RM	152	static const u16 eld_reg_to_type[][2] = {
	153	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	154	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	155	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	156	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	157	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	158	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	159	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	160	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	161	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	162	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	163	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	164	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	165	};
	166
46892caa RM	167	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
46892caa RM	168	u32 value = 0;
0f57bca9 AH	169	u8 stereo_freqs = 0;
0f57bca9 AH	170	int max_channels = -1;
46892caa RM	171	int j;
	172
	173	for (j = 0; j < sad_count; j++) {
	174	struct cea_sad *sad = &sads[j];
	175
	176	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	177	if (sad->channels > max_channels) {
	178	value = MAX_CHANNELS(sad->channels) \|
	179	DESCRIPTOR_BYTE_2(sad->byte2) \|
	180	SUPPORTED_FREQUENCIES(sad->freq);
	181	max_channels = sad->channels;
	182	}
	183
46892caa	184	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	185	stereo_freqs \|= sad->freq;
	186	else
	187	break;
46892caa RM	188	}
46892caa RM	189	}
0f57bca9 AH	190
	191	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	192
070a2e63	193	WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
46892caa	194	}
46892caa RM	195	}
46892caa RM	196
e55d3e6c	197	/*
96ea7afb	198	* build a AVI Info Frame
e55d3e6c	199	*/
96ea7afb SG	200	void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
96ea7afb SG	201	unsigned char *buffer, size_t size)
e55d3e6c	202	{
e3b2e034	203	uint8_t *frame = buffer + 3;
e55d3e6c RM	204
	205	WREG32(AFMT_AVI_INFO0 + offset,
	206	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
	207	WREG32(AFMT_AVI_INFO1 + offset,
	208	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x7] << 24));
	209	WREG32(AFMT_AVI_INFO2 + offset,
	210	frame[0x8] \| (frame[0x9] << 8) \| (frame[0xA] << 16) \| (frame[0xB] << 24));
	211	WREG32(AFMT_AVI_INFO3 + offset,
96ea7afb	212	frame[0xC] \| (frame[0xD] << 8) \| (buffer[1] << 24));
e55d3e6c RM	213	}
e55d3e6c RM	214
a85d682a SG	215	void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
a85d682a SG	216	struct radeon_crtc *crtc, unsigned int clock)
b1f6f47e	217	{
a85d682a	218	unsigned int max_ratio = clock / 24000;
1518dd8e	219	u32 dto_phase;
1518dd8e	220	u32 wallclock_ratio;
a85d682a SG	221	u32 value;
	222
	223	if (max_ratio >= 8) {
	224	dto_phase = 192 * 1000;
	225	wallclock_ratio = 3;
	226	} else if (max_ratio >= 4) {
	227	dto_phase = 96 * 1000;
	228	wallclock_ratio = 2;
	229	} else if (max_ratio >= 2) {
	230	dto_phase = 48 * 1000;
	231	wallclock_ratio = 1;
b530602f	232	} else {
a85d682a SG	233	dto_phase = 24 * 1000;
a85d682a SG	234	wallclock_ratio = 0;
1518dd8e	235	}
1518dd8e	236
a85d682a SG	237	value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	238	value \|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
	239	value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	240	WREG32(DCCG_AUDIO_DTO0_CNTL, value);
	241
	242	/* Two dtos; generally use dto0 for HDMI */
	243	value = 0;
	244
	245	if (crtc)
	246	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	247
	248	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	249
b1f6f47e AD	250	/* Express [24MHz / target pixel clock] as an exact rational
	251	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	252	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	253	*/
1518dd8e	254	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
a85d682a	255	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
b1f6f47e AD	256	}
b1f6f47e AD	257
a85d682a SG	258	void dce4_dp_audio_set_dto(struct radeon_device *rdev,
	259	struct radeon_crtc *crtc, unsigned int clock)
	260	{
	261	u32 value;
	262
	263	value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	264	value \|= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	265	WREG32(DCCG_AUDIO_DTO1_CNTL, value);
	266
	267	/* Two dtos; generally use dto1 for DP */
	268	value = 0;
	269	value \|= DCCG_AUDIO_DTO_SEL;
	270
	271	if (crtc)
	272	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	273
	274	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	275
	276	/* Express [24MHz / target pixel clock] as an exact rational
	277	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	278	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	279	*/
	280	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	281	WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);
	282	}
b1f6f47e	283
e55d3e6c RM	284	/*
	285	* update the info frames with the data from the current display mode
	286	*/
	287	void evergreen_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mode)
	288	{
	289	struct drm_device *dev = encoder->dev;
	290	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	291	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	292	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
79766915	293	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
e3b2e034 TR	294	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
e3b2e034 TR	295	struct hdmi_avi_infoframe frame;
cfcbd6d3	296	uint32_t offset;
e3b2e034	297	ssize_t err;
7b555e06	298	uint32_t val;
79766915	299	int bpc = 8;
e55d3e6c	300
c2b4cacf AD	301	if (!dig \|\| !dig->afmt)
	302	return;
	303
cfcbd6d3 RM	304	/* Silent, r600_hdmi_enable will raise WARN for us */
cfcbd6d3 RM	305	if (!dig->afmt->enabled)
e55d3e6c	306	return;
cfcbd6d3	307	offset = dig->afmt->offset;
e55d3e6c	308
79766915 AD	309	/* hdmi deep color mode general control packets setup, if bpc > 8 */
	310	if (encoder->crtc) {
	311	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
	312	bpc = radeon_crtc->bpc;
	313	}
	314
832eafaf	315	/* disable audio prior to setting up hw */
3cdde027	316	dig->afmt->pin = radeon_audio_get_pin(encoder);
8bf59820	317	radeon_audio_enable(rdev, dig->afmt->pin, 0);
832eafaf	318
a85d682a	319	radeon_audio_set_dto(encoder, mode->clock);
e55d3e6c	320
1c3439f2 RM	321	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	322	HDMI_NULL_SEND); /* send null packets when required */
	323
e55d3e6c	324	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
e55d3e6c	325
7b555e06 AD	326	val = RREG32(HDMI_CONTROL + offset);
	327	val &= ~HDMI_DEEP_COLOR_ENABLE;
	328	val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
	329
	330	switch (bpc) {
	331	case 0:
	332	case 6:
	333	case 8:
	334	case 16:
	335	default:
	336	DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
72082093	337	connector->name, bpc);
7b555e06 AD	338	break;
	339	case 10:
	340	val \|= HDMI_DEEP_COLOR_ENABLE;
	341	val \|= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
	342	DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
72082093	343	connector->name);
7b555e06 AD	344	break;
	345	case 12:
	346	val \|= HDMI_DEEP_COLOR_ENABLE;
	347	val \|= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
	348	DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
72082093	349	connector->name);
7b555e06 AD	350	break;
	351	}
	352
	353	WREG32(HDMI_CONTROL + offset, val);
	354
1c3439f2 RM	355	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	356	HDMI_NULL_SEND \| /* send null packets when required */
	357	HDMI_GC_SEND \| /* send general control packets */
	358	HDMI_GC_CONT); /* send general control packets every frame */
	359
	360	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
1c3439f2 RM	361	HDMI_AUDIO_INFO_SEND \| /* enable audio info frames (frames won't be set until audio is enabled) */
1c3439f2 RM	362	HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
e55d3e6c	363
1c3439f2 RM	364	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
1c3439f2 RM	365	AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
e55d3e6c	366
1c3439f2	367	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
1c3439f2 RM	368	HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
	369
	370	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
e55d3e6c	371
91a44019 RM	372	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
	373	HDMI_AUDIO_DELAY_EN(1) \| /* set the default audio delay */
	374	HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
	375
	376	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	377	AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	378
	379	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
	380
79766915 AD	381	if (bpc > 8)
	382	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
	383	HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
	384	else
	385	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
	386	HDMI_ACR_SOURCE \| /* select SW CTS value */
	387	HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
91a44019 RM	388
	389	evergreen_hdmi_update_ACR(encoder, mode->clock);
	390
f93e3fc3 RM	391	WREG32(AFMT_60958_0 + offset,
	392	AFMT_60958_CS_CHANNEL_NUMBER_L(1));
	393
	394	WREG32(AFMT_60958_1 + offset,
	395	AFMT_60958_CS_CHANNEL_NUMBER_R(2));
	396
	397	WREG32(AFMT_60958_2 + offset,
	398	AFMT_60958_CS_CHANNEL_NUMBER_2(3) \|
	399	AFMT_60958_CS_CHANNEL_NUMBER_3(4) \|
	400	AFMT_60958_CS_CHANNEL_NUMBER_4(5) \|
	401	AFMT_60958_CS_CHANNEL_NUMBER_5(6) \|
	402	AFMT_60958_CS_CHANNEL_NUMBER_6(7) \|
	403	AFMT_60958_CS_CHANNEL_NUMBER_7(8));
	404
00a9d4bc	405	radeon_audio_write_speaker_allocation(encoder);
f93e3fc3 RM	406
	407	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
	408	AFMT_AUDIO_CHANNEL_ENABLE(0xff));
	409
	410	/* fglrx sets 0x40 in 0x5f80 here */
b530602f	411
88252d77	412	radeon_audio_select_pin(encoder);
070a2e63	413	radeon_audio_write_sad_regs(encoder);
87654f87	414	radeon_audio_write_latency_fields(encoder, mode);
070a2e63	415
e3b2e034 TR	416	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	417	if (err < 0) {
	418	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
	419	return;
	420	}
	421
	422	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	423	if (err < 0) {
	424	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
	425	return;
	426	}
e55d3e6c	427
96ea7afb	428	radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1c3439f2	429
d3418eac RM	430	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
	431	HDMI_AVI_INFO_SEND \| /* enable AVI info frames */
	432	HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
	433
	434	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
	435	HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
	436	~HDMI_AVI_INFO_LINE_MASK);
	437
	438	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
	439	AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
	440
e55d3e6c RM	441	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	442	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	443	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
	444	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
	445	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
832eafaf AD	446
832eafaf AD	447	/* enable audio after to setting up hw */
8bf59820	448	radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
e55d3e6c	449	}
a973bea1 AD	450
	451	void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
	452	{
4adb34ef AD	453	struct drm_device *dev = encoder->dev;
4adb34ef AD	454	struct radeon_device *rdev = dev->dev_private;
a973bea1 AD	455	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	456	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	457
c2b4cacf AD	458	if (!dig \|\| !dig->afmt)
	459	return;
	460
a973bea1 AD	461	/* Silent, r600_hdmi_enable will raise WARN for us */
	462	if (enable && dig->afmt->enabled)
	463	return;
	464	if (!enable && !dig->afmt->enabled)
	465	return;
	466
4adb34ef	467	if (!enable && dig->afmt->pin) {
8bf59820	468	radeon_audio_enable(rdev, dig->afmt->pin, 0);
4adb34ef AD	469	dig->afmt->pin = NULL;
	470	}
	471
a973bea1 AD	472	dig->afmt->enabled = enable;
	473
	474	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
	475	enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
	476	}