[linux-2.6-block.git] / drivers / gpu / drm / radeon / evergreen_hdmi.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Christian König.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 *          Rafał Miłecki
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_asic.h"
#include "radeon_audio.h"
#include "evergreend.h"
#include "atom.h"

/* enable the audio stream */
void dce4_audio_enable(struct radeon_device *rdev,
			      struct r600_audio_pin *pin,
			      u8 enable_mask)
{
	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

	if (!pin)
		return;

	if (enable_mask) {
		tmp |= AUDIO_ENABLED;
		if (enable_mask & 1)
			tmp |= PIN0_AUDIO_ENABLED;
		if (enable_mask & 2)
			tmp |= PIN1_AUDIO_ENABLED;
		if (enable_mask & 4)
			tmp |= PIN2_AUDIO_ENABLED;
		if (enable_mask & 8)
			tmp |= PIN3_AUDIO_ENABLED;
	} else {
		tmp &= ~(AUDIO_ENABLED |
			 PIN0_AUDIO_ENABLED |
			 PIN1_AUDIO_ENABLED |
			 PIN2_AUDIO_ENABLED |
			 PIN3_AUDIO_ENABLED);
	}

	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
}

void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
	const struct radeon_hdmi_acr *acr)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	int bpc = 8;

	if (encoder->crtc) {
		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		bpc = radeon_crtc->bpc;
	}

	if (bpc > 8)
		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
			HDMI_ACR_AUTO_SEND);	/* allow hw to sent ACR packets when required */
	else
		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
			HDMI_ACR_SOURCE |		/* select SW CTS value */
			HDMI_ACR_AUTO_SEND);	/* allow hw to sent ACR packets when required */

	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
	WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);

	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
	WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);

	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
	WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
}

void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
		struct drm_connector *connector, struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp = 0;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
	}
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	u32 tmp;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
}

void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
	struct cea_sad *sads, int sad_count)
{
	int i;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
	}
}

/*
 * build a AVI Info Frame
 */
void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
    unsigned char *buffer, size_t size)
{
	uint8_t *frame = buffer + 3;

	WREG32(AFMT_AVI_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(AFMT_AVI_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
	WREG32(AFMT_AVI_INFO2 + offset,
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
	WREG32(AFMT_AVI_INFO3 + offset,
		frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
}

void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	unsigned int max_ratio = clock / 24000;
	u32 dto_phase;
	u32 wallclock_ratio;
	u32 value;

	if (max_ratio >= 8) {
		dto_phase = 192 * 1000;
		wallclock_ratio = 3;
	} else if (max_ratio >= 4) {
		dto_phase = 96 * 1000;
		wallclock_ratio = 2;
	} else if (max_ratio >= 2) {
		dto_phase = 48 * 1000;
		wallclock_ratio = 1;
	} else {
		dto_phase = 24 * 1000;
		wallclock_ratio = 0;
	}

	value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
	value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	WREG32(DCCG_AUDIO_DTO0_CNTL, value);

	/* Two dtos; generally use dto0 for HDMI */
	value = 0;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
}

void dce4_dp_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	u32 value;

	value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	WREG32(DCCG_AUDIO_DTO1_CNTL, value);

	/* Two dtos; generally use dto1 for DP */
	value = 0;
	value |= DCCG_AUDIO_DTO_SEL;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);
}

void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;

	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
		HDMI_NULL_SEND |	/* send null packets when required */
		HDMI_GC_SEND |		/* send general control packets */
		HDMI_GC_CONT);		/* send general control packets every frame */
}

/*
 * update the info frames with the data from the current display mode
 */
void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
	struct hdmi_avi_infoframe frame;
	uint32_t offset;
	ssize_t err;
	uint32_t val;
	int bpc = 8;

	if (!dig || !dig->afmt)
		return;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (!dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	/* hdmi deep color mode general control packets setup, if bpc > 8 */
	if (encoder->crtc) {
		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		bpc = radeon_crtc->bpc;
	}

	/* disable audio prior to setting up hw */
	dig->afmt->pin = radeon_audio_get_pin(encoder);
	radeon_audio_enable(rdev, dig->afmt->pin, 0);

	radeon_audio_set_dto(encoder, mode->clock);
	radeon_audio_set_vbi_packet(encoder);

	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);

	val = RREG32(HDMI_CONTROL + offset);
	val &= ~HDMI_DEEP_COLOR_ENABLE;
	val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;

	switch (bpc) {
		case 0:
		case 6:
		case 8:
		case 16:
		default:
			DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
					 connector->name, bpc);
			break;
		case 10:
			val |= HDMI_DEEP_COLOR_ENABLE;
			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
			DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
					 connector->name);
			break;
		case 12:
			val |= HDMI_DEEP_COLOR_ENABLE;
			val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
			DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
					 connector->name);
			break;
	}

	WREG32(HDMI_CONTROL + offset, val);

	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */

	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */

	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */

	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */

	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */

	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */

	radeon_audio_update_acr(encoder, mode->clock);

	WREG32(AFMT_60958_0 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_L(1));

	WREG32(AFMT_60958_1 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_R(2));

	WREG32(AFMT_60958_2 + offset,
	       AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
	       AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
	       AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
	       AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
	       AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
	       AFMT_60958_CS_CHANNEL_NUMBER_7(8));

	radeon_audio_write_speaker_allocation(encoder);

	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));

	/* fglrx sets 0x40 in 0x5f80 here */

	radeon_audio_select_pin(encoder);
	radeon_audio_write_sad_regs(encoder);
	radeon_audio_write_latency_fields(encoder, mode);

	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	if (err < 0) {
		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
		return;
	}

	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
		return;
	}

	radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));

	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */
		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */

	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
		 ~HDMI_AVI_INFO_LINE_MASK);

	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */

	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);

	/* enable audio after to setting up hw */
	radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
}

void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	if (!dig || !dig->afmt)
		return;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (enable && dig->afmt->enabled)
		return;
	if (!enable && !dig->afmt->enabled)
		return;

	if (!enable && dig->afmt->pin) {
		radeon_audio_enable(rdev, dig->afmt->pin, 0);
		dig->afmt->pin = NULL;
	}

	dig->afmt->enabled = enable;

	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
}
Commit	Line	Data
e55d3e6c RM	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Christian König.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Christian König
	25	* Rafał Miłecki
	26	*/
e3b2e034	27	#include <linux/hdmi.h>
760285e7 DH	28	#include <drm/drmP.h>
760285e7 DH	29	#include <drm/radeon_drm.h>
e55d3e6c RM	30	#include "radeon.h"
e55d3e6c RM	31	#include "radeon_asic.h"
070a2e63	32	#include "radeon_audio.h"
e55d3e6c RM	33	#include "evergreend.h"
	34	#include "atom.h"
	35
d3d8c141	36	/* enable the audio stream */
8bf59820	37	void dce4_audio_enable(struct radeon_device *rdev,
d3d8c141 AD	38	struct r600_audio_pin *pin,
	39	u8 enable_mask)
	40	{
	41	u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
	42
	43	if (!pin)
	44	return;
	45
	46	if (enable_mask) {
	47	tmp \|= AUDIO_ENABLED;
	48	if (enable_mask & 1)
	49	tmp \|= PIN0_AUDIO_ENABLED;
	50	if (enable_mask & 2)
	51	tmp \|= PIN1_AUDIO_ENABLED;
	52	if (enable_mask & 4)
	53	tmp \|= PIN2_AUDIO_ENABLED;
	54	if (enable_mask & 8)
	55	tmp \|= PIN3_AUDIO_ENABLED;
	56	} else {
	57	tmp &= ~(AUDIO_ENABLED \|
	58	PIN0_AUDIO_ENABLED \|
	59	PIN1_AUDIO_ENABLED \|
	60	PIN2_AUDIO_ENABLED \|
	61	PIN3_AUDIO_ENABLED);
	62	}
	63
	64	WREG32(AZ_HOT_PLUG_CONTROL, tmp);
	65	}
	66
64424d6e SG	67	void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
64424d6e SG	68	const struct radeon_hdmi_acr *acr)
e55d3e6c RM	69	{
	70	struct drm_device *dev = encoder->dev;
	71	struct radeon_device *rdev = dev->dev_private;
64424d6e SG	72	int bpc = 8;
	73
	74	if (encoder->crtc) {
	75	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
	76	bpc = radeon_crtc->bpc;
	77	}
e55d3e6c	78
64424d6e SG	79	if (bpc > 8)
	80	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
	81	HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
	82	else
	83	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
	84	HDMI_ACR_SOURCE \| /* select SW CTS value */
	85	HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
	86
	87	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
	88	WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
e55d3e6c	89
64424d6e SG	90	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
64424d6e SG	91	WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
e55d3e6c	92
64424d6e SG	93	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
64424d6e SG	94	WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
e55d3e6c RM	95	}
e55d3e6c RM	96
87654f87 SG	97	void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
87654f87 SG	98	struct drm_connector connector, struct drm_display_mode mode)
712fd8a2 AD	99	{
712fd8a2 AD	100	struct radeon_device *rdev = encoder->dev->dev_private;
712fd8a2 AD	101	u32 tmp = 0;
712fd8a2 AD	102
712fd8a2 AD	103	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	104	if (connector->latency_present[1])
	105	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	106	AUDIO_LIPSYNC(connector->audio_latency[1]);
	107	else
	108	tmp = VIDEO_LIPSYNC(255) \| AUDIO_LIPSYNC(255);
	109	} else {
	110	if (connector->latency_present[0])
	111	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	112	AUDIO_LIPSYNC(connector->audio_latency[0]);
	113	else
	114	tmp = VIDEO_LIPSYNC(255) \| AUDIO_LIPSYNC(255);
	115	}
87654f87	116	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
712fd8a2 AD	117	}
712fd8a2 AD	118
00a9d4bc SG	119	void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
00a9d4bc SG	120	u8 *sadb, int sad_count)
ba7def4f AD	121	{
ba7def4f AD	122	struct radeon_device *rdev = encoder->dev->dev_private;
ba7def4f	123	u32 tmp;
ba7def4f AD	124
ba7def4f AD	125	/* program the speaker allocation */
00a9d4bc	126	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
ba7def4f AD	127	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	128	/* set HDMI mode */
	129	tmp \|= HDMI_CONNECTION;
	130	if (sad_count)
	131	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	132	else
	133	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
00a9d4bc SG	134	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc SG	135	}
ba7def4f	136
00a9d4bc SG	137	void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	138	u8 *sadb, int sad_count)
	139	{
	140	struct radeon_device *rdev = encoder->dev->dev_private;
	141	u32 tmp;
	142
	143	/* program the speaker allocation */
	144	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
	145	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	146	/* set DP mode */
	147	tmp \|= DP_CONNECTION;
	148	if (sad_count)
	149	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	150	else
	151	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	152	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
ba7def4f AD	153	}
ba7def4f AD	154
070a2e63 AD	155	void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
070a2e63 AD	156	struct cea_sad *sads, int sad_count)
46892caa	157	{
070a2e63	158	int i;
46892caa	159	struct radeon_device *rdev = encoder->dev->dev_private;
46892caa RM	160	static const u16 eld_reg_to_type[][2] = {
	161	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	162	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	163	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	164	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	165	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	166	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	167	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	168	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	169	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	170	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	171	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	172	{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	173	};
	174
46892caa RM	175	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
46892caa RM	176	u32 value = 0;
0f57bca9 AH	177	u8 stereo_freqs = 0;
0f57bca9 AH	178	int max_channels = -1;
46892caa RM	179	int j;
	180
	181	for (j = 0; j < sad_count; j++) {
	182	struct cea_sad *sad = &sads[j];
	183
	184	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	185	if (sad->channels > max_channels) {
	186	value = MAX_CHANNELS(sad->channels) \|
	187	DESCRIPTOR_BYTE_2(sad->byte2) \|
	188	SUPPORTED_FREQUENCIES(sad->freq);
	189	max_channels = sad->channels;
	190	}
	191
46892caa	192	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	193	stereo_freqs \|= sad->freq;
	194	else
	195	break;
46892caa RM	196	}
46892caa RM	197	}
0f57bca9 AH	198
	199	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	200
070a2e63	201	WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
46892caa	202	}
46892caa RM	203	}
46892caa RM	204
e55d3e6c	205	/*
96ea7afb	206	* build a AVI Info Frame
e55d3e6c	207	*/
96ea7afb SG	208	void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset,
96ea7afb SG	209	unsigned char *buffer, size_t size)
e55d3e6c	210	{
e3b2e034	211	uint8_t *frame = buffer + 3;
e55d3e6c RM	212
	213	WREG32(AFMT_AVI_INFO0 + offset,
	214	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
	215	WREG32(AFMT_AVI_INFO1 + offset,
	216	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x7] << 24));
	217	WREG32(AFMT_AVI_INFO2 + offset,
	218	frame[0x8] \| (frame[0x9] << 8) \| (frame[0xA] << 16) \| (frame[0xB] << 24));
	219	WREG32(AFMT_AVI_INFO3 + offset,
96ea7afb	220	frame[0xC] \| (frame[0xD] << 8) \| (buffer[1] << 24));
e55d3e6c RM	221	}
e55d3e6c RM	222
a85d682a SG	223	void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
a85d682a SG	224	struct radeon_crtc *crtc, unsigned int clock)
b1f6f47e	225	{
a85d682a	226	unsigned int max_ratio = clock / 24000;
1518dd8e	227	u32 dto_phase;
1518dd8e	228	u32 wallclock_ratio;
a85d682a SG	229	u32 value;
	230
	231	if (max_ratio >= 8) {
	232	dto_phase = 192 * 1000;
	233	wallclock_ratio = 3;
	234	} else if (max_ratio >= 4) {
	235	dto_phase = 96 * 1000;
	236	wallclock_ratio = 2;
	237	} else if (max_ratio >= 2) {
	238	dto_phase = 48 * 1000;
	239	wallclock_ratio = 1;
b530602f	240	} else {
a85d682a SG	241	dto_phase = 24 * 1000;
a85d682a SG	242	wallclock_ratio = 0;
1518dd8e	243	}
1518dd8e	244
a85d682a SG	245	value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	246	value \|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
	247	value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	248	WREG32(DCCG_AUDIO_DTO0_CNTL, value);
	249
	250	/* Two dtos; generally use dto0 for HDMI */
	251	value = 0;
	252
	253	if (crtc)
	254	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	255
	256	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	257
b1f6f47e AD	258	/* Express [24MHz / target pixel clock] as an exact rational
	259	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	260	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	261	*/
1518dd8e	262	WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
a85d682a	263	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
b1f6f47e AD	264	}
b1f6f47e AD	265
a85d682a SG	266	void dce4_dp_audio_set_dto(struct radeon_device *rdev,
	267	struct radeon_crtc *crtc, unsigned int clock)
	268	{
	269	u32 value;
	270
	271	value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
	272	value \|= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
	273	WREG32(DCCG_AUDIO_DTO1_CNTL, value);
	274
	275	/* Two dtos; generally use dto1 for DP */
	276	value = 0;
	277	value \|= DCCG_AUDIO_DTO_SEL;
	278
	279	if (crtc)
	280	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	281
	282	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	283
	284	/* Express [24MHz / target pixel clock] as an exact rational
	285	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	286	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	287	*/
	288	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	289	WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);
	290	}
b1f6f47e	291
930a9785 AD	292	void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
	293	{
	294	struct drm_device *dev = encoder->dev;
	295	struct radeon_device *rdev = dev->dev_private;
	296
	297	WREG32(HDMI_VBI_PACKET_CONTROL + offset,
	298	HDMI_NULL_SEND \| /* send null packets when required */
	299	HDMI_GC_SEND \| /* send general control packets */
	300	HDMI_GC_CONT); /* send general control packets every frame */
	301	}
	302
e55d3e6c RM	303	/*
	304	* update the info frames with the data from the current display mode
	305	*/
	306	void evergreen_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mode)
	307	{
	308	struct drm_device *dev = encoder->dev;
	309	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	310	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	311	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
79766915	312	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
e3b2e034 TR	313	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
e3b2e034 TR	314	struct hdmi_avi_infoframe frame;
cfcbd6d3	315	uint32_t offset;
e3b2e034	316	ssize_t err;
7b555e06	317	uint32_t val;
79766915	318	int bpc = 8;
e55d3e6c	319
c2b4cacf AD	320	if (!dig \|\| !dig->afmt)
	321	return;
	322
cfcbd6d3 RM	323	/* Silent, r600_hdmi_enable will raise WARN for us */
cfcbd6d3 RM	324	if (!dig->afmt->enabled)
e55d3e6c	325	return;
cfcbd6d3	326	offset = dig->afmt->offset;
e55d3e6c	327
79766915 AD	328	/* hdmi deep color mode general control packets setup, if bpc > 8 */
	329	if (encoder->crtc) {
	330	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
	331	bpc = radeon_crtc->bpc;
	332	}
	333
832eafaf	334	/* disable audio prior to setting up hw */
3cdde027	335	dig->afmt->pin = radeon_audio_get_pin(encoder);
8bf59820	336	radeon_audio_enable(rdev, dig->afmt->pin, 0);
832eafaf	337
a85d682a	338	radeon_audio_set_dto(encoder, mode->clock);
930a9785	339	radeon_audio_set_vbi_packet(encoder);
1c3439f2	340
e55d3e6c	341	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
e55d3e6c	342
7b555e06 AD	343	val = RREG32(HDMI_CONTROL + offset);
	344	val &= ~HDMI_DEEP_COLOR_ENABLE;
	345	val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
	346
	347	switch (bpc) {
	348	case 0:
	349	case 6:
	350	case 8:
	351	case 16:
	352	default:
	353	DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
72082093	354	connector->name, bpc);
7b555e06 AD	355	break;
	356	case 10:
	357	val \|= HDMI_DEEP_COLOR_ENABLE;
	358	val \|= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
	359	DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
72082093	360	connector->name);
7b555e06 AD	361	break;
	362	case 12:
	363	val \|= HDMI_DEEP_COLOR_ENABLE;
	364	val \|= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
	365	DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
72082093	366	connector->name);
7b555e06 AD	367	break;
	368	}
	369
	370	WREG32(HDMI_CONTROL + offset, val);
	371
1c3439f2	372	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
1c3439f2 RM	373	HDMI_AUDIO_INFO_SEND \| /* enable audio info frames (frames won't be set until audio is enabled) */
1c3439f2 RM	374	HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
e55d3e6c	375
1c3439f2 RM	376	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
1c3439f2 RM	377	AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
e55d3e6c	378
1c3439f2	379	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
1c3439f2 RM	380	HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
	381
	382	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
e55d3e6c	383
91a44019 RM	384	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
	385	HDMI_AUDIO_DELAY_EN(1) \| /* set the default audio delay */
	386	HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
	387
	388	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	389	AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	390
	391	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
	392
64424d6e	393	radeon_audio_update_acr(encoder, mode->clock);
91a44019	394
f93e3fc3 RM	395	WREG32(AFMT_60958_0 + offset,
	396	AFMT_60958_CS_CHANNEL_NUMBER_L(1));
	397
	398	WREG32(AFMT_60958_1 + offset,
	399	AFMT_60958_CS_CHANNEL_NUMBER_R(2));
	400
	401	WREG32(AFMT_60958_2 + offset,
	402	AFMT_60958_CS_CHANNEL_NUMBER_2(3) \|
	403	AFMT_60958_CS_CHANNEL_NUMBER_3(4) \|
	404	AFMT_60958_CS_CHANNEL_NUMBER_4(5) \|
	405	AFMT_60958_CS_CHANNEL_NUMBER_5(6) \|
	406	AFMT_60958_CS_CHANNEL_NUMBER_6(7) \|
	407	AFMT_60958_CS_CHANNEL_NUMBER_7(8));
	408
00a9d4bc	409	radeon_audio_write_speaker_allocation(encoder);
f93e3fc3 RM	410
	411	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
	412	AFMT_AUDIO_CHANNEL_ENABLE(0xff));
	413
	414	/* fglrx sets 0x40 in 0x5f80 here */
b530602f	415
88252d77	416	radeon_audio_select_pin(encoder);
070a2e63	417	radeon_audio_write_sad_regs(encoder);
87654f87	418	radeon_audio_write_latency_fields(encoder, mode);
070a2e63	419
e3b2e034 TR	420	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	421	if (err < 0) {
	422	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
	423	return;
	424	}
	425
	426	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	427	if (err < 0) {
	428	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
	429	return;
	430	}
e55d3e6c	431
96ea7afb	432	radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1c3439f2	433
d3418eac RM	434	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
	435	HDMI_AVI_INFO_SEND \| /* enable AVI info frames */
	436	HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
	437
	438	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
	439	HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
	440	~HDMI_AVI_INFO_LINE_MASK);
	441
	442	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
	443	AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
	444
e55d3e6c RM	445	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	446	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	447	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
	448	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
	449	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
832eafaf AD	450
832eafaf AD	451	/* enable audio after to setting up hw */
8bf59820	452	radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
e55d3e6c	453	}
a973bea1 AD	454
	455	void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
	456	{
4adb34ef AD	457	struct drm_device *dev = encoder->dev;
4adb34ef AD	458	struct radeon_device *rdev = dev->dev_private;
a973bea1 AD	459	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	460	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	461
c2b4cacf AD	462	if (!dig \|\| !dig->afmt)
	463	return;
	464
a973bea1 AD	465	/* Silent, r600_hdmi_enable will raise WARN for us */
	466	if (enable && dig->afmt->enabled)
	467	return;
	468	if (!enable && !dig->afmt->enabled)
	469	return;
	470
4adb34ef	471	if (!enable && dig->afmt->pin) {
8bf59820	472	radeon_audio_enable(rdev, dig->afmt->pin, 0);
4adb34ef AD	473	dig->afmt->pin = NULL;
	474	}
	475
a973bea1 AD	476	dig->afmt->enabled = enable;
	477
	478	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
	479	enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
	480	}