[linux-2.6-block.git] / drivers / gpu / drm / radeon / dce6_afmt.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_audio.h"
#include "sid.h"

u32 dce6_endpoint_rreg(struct radeon_device *rdev,
			      u32 block_offset, u32 reg)
{
	unsigned long flags;
	u32 r;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);

	return r;
}

void dce6_endpoint_wreg(struct radeon_device *rdev,
			       u32 block_offset, u32 reg, u32 v)
{
	unsigned long flags;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	if (ASIC_IS_DCE8(rdev))
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	else
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
}

static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
{
	int i;
	u32 offset, tmp;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		offset = rdev->audio.pin[i].offset;
		tmp = RREG32_ENDPOINT(offset,
				      AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
		if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
			rdev->audio.pin[i].connected = false;
		else
			rdev->audio.pin[i].connected = true;
	}
}

struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
{
	int i;

	dce6_afmt_get_connected_pins(rdev);

	for (i = 0; i < rdev->audio.num_pins; i++) {
		if (rdev->audio.pin[i].connected)
			return &rdev->audio.pin[i];
	}
	DRM_ERROR("No connected audio pins found!\n");
	return NULL;
}

void dce6_afmt_select_pin(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->offset;

	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
	       AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
}

void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
		struct drm_connector *connector, struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 tmp = 0, offset;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	}
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset, tmp;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset, tmp;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
	struct cea_sad *sads, int sad_count)
{
	u32 offset;
	int i;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
	}
}

void dce6_audio_enable(struct radeon_device *rdev,
		       struct r600_audio_pin *pin,
		       u8 enable_mask)
{
	if (!pin)
		return;

	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
			enable_mask ? AUDIO_ENABLED : 0);
}

void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	/* Two dtos; generally use dto0 for HDMI */
	u32 value = 0;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
}

void dce6_dp_audio_set_dto(struct radeon_device *rdev,
	struct radeon_crtc *crtc, unsigned int clock)
{
	/* Two dtos; generally use dto1 for DP */
	u32 value = 0;
	value |= DCCG_AUDIO_DTO_SEL;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
}

void dce6_dp_enable(struct drm_encoder *encoder, bool enable)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	if (!dig || !dig->afmt)
		return;

	if (enable) {
		WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
		       EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
		       EVERGREEN_DP_SEC_ASP_ENABLE |		/* Audio packet transmission */
		       EVERGREEN_DP_SEC_ATP_ENABLE |		/* Audio timestamp packet transmission */
		       EVERGREEN_DP_SEC_AIP_ENABLE |		/* Audio infoframe packet transmission */
		       EVERGREEN_DP_SEC_STREAM_ENABLE);	/* Master enable for secondary stream engine */
	} else {
		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
	}

	dig->afmt->enabled = enable;
}
Commit	Line	Data
b530602f AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/hdmi.h>
	24	#include <drm/drmP.h>
	25	#include "radeon.h"
1a626b68	26	#include "radeon_audio.h"
b530602f AD	27	#include "sid.h"
b530602f AD	28
1a626b68	29	u32 dce6_endpoint_rreg(struct radeon_device *rdev,
b530602f AD	30	u32 block_offset, u32 reg)
b530602f AD	31	{
0a5b7b0b	32	unsigned long flags;
b530602f AD	33	u32 r;
b530602f AD	34
0a5b7b0b	35	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	36	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
b530602f AD	37	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
0a5b7b0b AD	38	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0a5b7b0b AD	39
b530602f AD	40	return r;
	41	}
	42
1a626b68	43	void dce6_endpoint_wreg(struct radeon_device *rdev,
b530602f AD	44	u32 block_offset, u32 reg, u32 v)
b530602f AD	45	{
0a5b7b0b AD	46	unsigned long flags;
	47
	48	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	49	if (ASIC_IS_DCE8(rdev))
	50	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	51	else
	52	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
	53	AZ_ENDPOINT_REG_WRITE_EN \| AZ_ENDPOINT_REG_INDEX(reg));
	54	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
0a5b7b0b	55	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
b530602f AD	56	}
b530602f AD	57
b530602f AD	58	static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
	59	{
	60	int i;
	61	u32 offset, tmp;
	62
	63	for (i = 0; i < rdev->audio.num_pins; i++) {
	64	offset = rdev->audio.pin[i].offset;
	65	tmp = RREG32_ENDPOINT(offset,
	66	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
	67	if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
	68	rdev->audio.pin[i].connected = false;
	69	else
	70	rdev->audio.pin[i].connected = true;
	71	}
	72	}
	73
	74	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev)
	75	{
	76	int i;
	77
	78	dce6_afmt_get_connected_pins(rdev);
	79
	80	for (i = 0; i < rdev->audio.num_pins; i++) {
	81	if (rdev->audio.pin[i].connected)
	82	return &rdev->audio.pin[i];
	83	}
	84	DRM_ERROR("No connected audio pins found!\n");
	85	return NULL;
	86	}
	87
	88	void dce6_afmt_select_pin(struct drm_encoder *encoder)
	89	{
	90	struct radeon_device *rdev = encoder->dev->dev_private;
	91	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	92	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
53dc0b0c	93	u32 offset;
b530602f	94
53dc0b0c	95	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b530602f AD	96	return;
b530602f AD	97
53dc0b0c AD	98	offset = dig->afmt->offset;
53dc0b0c AD	99
7cc0a3d8 AD	100	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
7cc0a3d8 AD	101	AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
b530602f AD	102	}
b530602f AD	103
b1880258	104	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
87654f87	105	struct drm_connector connector, struct drm_display_mode mode)
b1880258 AD	106	{
	107	struct radeon_device *rdev = encoder->dev->dev_private;
	108	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	109	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b1880258 AD	110	u32 tmp = 0, offset;
b1880258 AD	111
53dc0b0c	112	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b1880258 AD	113	return;
	114
	115	offset = dig->afmt->pin->offset;
	116
b1880258 AD	117	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	118	if (connector->latency_present[1])
	119	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	120	AUDIO_LIPSYNC(connector->audio_latency[1]);
	121	else
c748990b	122	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	123	} else {
	124	if (connector->latency_present[0])
	125	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	126	AUDIO_LIPSYNC(connector->audio_latency[0]);
	127	else
c748990b	128	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	129	}
	130	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
	131	}
	132
00a9d4bc SG	133	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
00a9d4bc SG	134	u8 *sadb, int sad_count)
b530602f AD	135	{
	136	struct radeon_device *rdev = encoder->dev->dev_private;
	137	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	138	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	139	u32 offset, tmp;
6159b65a	140
53dc0b0c	141	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
6159b65a RM	142	return;
	143
	144	offset = dig->afmt->pin->offset;
	145
6159b65a RM	146	/* program the speaker allocation */
	147	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	148	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	149	/* set HDMI mode */
	150	tmp \|= HDMI_CONNECTION;
	151	if (sad_count)
	152	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	153	else
	154	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	155	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc	156	}
6159b65a	157
00a9d4bc SG	158	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	159	u8 *sadb, int sad_count)
	160	{
	161	struct radeon_device *rdev = encoder->dev->dev_private;
	162	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	163	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	164	u32 offset, tmp;
	165
	166	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
	167	return;
	168
	169	offset = dig->afmt->pin->offset;
	170
	171	/* program the speaker allocation */
	172	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	173	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	174	/* set DP mode */
	175	tmp \|= DP_CONNECTION;
	176	if (sad_count)
	177	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	178	else
	179	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	180	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
6159b65a RM	181	}
6159b65a RM	182
070a2e63 AD	183	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
070a2e63 AD	184	struct cea_sad *sads, int sad_count)
6159b65a	185	{
070a2e63 AD	186	u32 offset;
070a2e63 AD	187	int i;
6159b65a RM	188	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
6159b65a RM	189	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
070a2e63	190	struct radeon_device *rdev = encoder->dev->dev_private;
b530602f AD	191	static const u16 eld_reg_to_type[][2] = {
	192	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	193	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	194	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	195	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	196	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	197	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	198	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	199	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	200	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	201	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	202	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	203	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	204	};
	205
53dc0b0c	206	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b530602f AD	207	return;
	208
	209	offset = dig->afmt->pin->offset;
	210
b530602f AD	211	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
b530602f AD	212	u32 value = 0;
0f57bca9 AH	213	u8 stereo_freqs = 0;
0f57bca9 AH	214	int max_channels = -1;
b530602f AD	215	int j;
	216
	217	for (j = 0; j < sad_count; j++) {
	218	struct cea_sad *sad = &sads[j];
	219
	220	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	221	if (sad->channels > max_channels) {
	222	value = MAX_CHANNELS(sad->channels) \|
	223	DESCRIPTOR_BYTE_2(sad->byte2) \|
	224	SUPPORTED_FREQUENCIES(sad->freq);
	225	max_channels = sad->channels;
	226	}
	227
b530602f	228	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	229	stereo_freqs \|= sad->freq;
	230	else
	231	break;
b530602f AD	232	}
b530602f AD	233	}
0f57bca9 AH	234
	235	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	236
b530602f AD	237	WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
b530602f AD	238	}
b530602f AD	239	}
b530602f AD	240
832eafaf AD	241	void dce6_audio_enable(struct radeon_device *rdev,
832eafaf AD	242	struct r600_audio_pin *pin,
d3d8c141	243	u8 enable_mask)
b530602f	244	{
832eafaf AD	245	if (!pin)
	246	return;
	247
f68fdbe4	248	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
d3d8c141	249	enable_mask ? AUDIO_ENABLED : 0);
b530602f	250	}
a85d682a SG	251
	252	void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
	253	struct radeon_crtc *crtc, unsigned int clock)
	254	{
b983a8f4	255	/* Two dtos; generally use dto0 for HDMI */
a85d682a SG	256	u32 value = 0;
a85d682a SG	257
b983a8f4	258	if (crtc)
a85d682a SG	259	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	260
	261	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	262
b983a8f4 SG	263	/* Express [24MHz / target pixel clock] as an exact rational
	264	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	265	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	266	*/
	267	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
	268	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
a85d682a SG	269	}
	270
	271	void dce6_dp_audio_set_dto(struct radeon_device *rdev,
	272	struct radeon_crtc *crtc, unsigned int clock)
	273	{
b983a8f4	274	/* Two dtos; generally use dto1 for DP */
a85d682a SG	275	u32 value = 0;
	276	value \|= DCCG_AUDIO_DTO_SEL;
	277
b983a8f4	278	if (crtc)
a85d682a SG	279	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	280
	281	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	282
b983a8f4 SG	283	/* Express [24MHz / target pixel clock] as an exact rational
	284	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	285	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	286	*/
	287	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	288	WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
a85d682a	289	}
e55bca26	290
add7d759	291	void dce6_dp_enable(struct drm_encoder *encoder, bool enable)
e55bca26 SG	292	{
	293	struct drm_device *dev = encoder->dev;
	294	struct radeon_device *rdev = dev->dev_private;
	295	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	296	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
e55bca26 SG	297
	298	if (!dig \|\| !dig->afmt)
	299	return;
	300
e55bca26	301	if (enable) {
add7d759 AD	302	WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
	303	EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
	304	WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
	305	EVERGREEN_DP_SEC_ASP_ENABLE \| /* Audio packet transmission */
	306	EVERGREEN_DP_SEC_ATP_ENABLE \| /* Audio timestamp packet transmission */
	307	EVERGREEN_DP_SEC_AIP_ENABLE \| /* Audio infoframe packet transmission */
	308	EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */
e55bca26	309	} else {
add7d759	310	WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
e55bca26 SG	311	}
	312
	313	dig->afmt->enabled = enable;
	314	}