[linux-2.6-block.git] / drivers / gpu / drm / radeon / dce6_afmt.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_audio.h"
#include "sid.h"

u32 dce6_endpoint_rreg(struct radeon_device *rdev,
			      u32 block_offset, u32 reg)
{
	unsigned long flags;
	u32 r;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);

	return r;
}

void dce6_endpoint_wreg(struct radeon_device *rdev,
			       u32 block_offset, u32 reg, u32 v)
{
	unsigned long flags;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	if (ASIC_IS_DCE8(rdev))
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	else
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
}

static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
{
	int i;
	u32 offset, tmp;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		offset = rdev->audio.pin[i].offset;
		tmp = RREG32_ENDPOINT(offset,
				      AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
		if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
			rdev->audio.pin[i].connected = false;
		else
			rdev->audio.pin[i].connected = true;
	}
}

struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
{
	int i;

	dce6_afmt_get_connected_pins(rdev);

	for (i = 0; i < rdev->audio.num_pins; i++) {
		if (rdev->audio.pin[i].connected)
			return &rdev->audio.pin[i];
	}
	DRM_ERROR("No connected audio pins found!\n");
	return NULL;
}

void dce6_afmt_select_pin(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->offset;

	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
	       AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
}

void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
				    struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct drm_connector *connector;
	struct radeon_connector *radeon_connector = NULL;
	u32 tmp = 0, offset;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
		if (connector->encoder == encoder) {
			radeon_connector = to_radeon_connector(connector);
			break;
		}
	}

	if (!radeon_connector) {
		DRM_ERROR("Couldn't find encoder's connector\n");
		return;
	}

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	}
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset, tmp;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 offset, tmp;

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
	struct cea_sad *sads, int sad_count)
{
	u32 offset;
	int i;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	if (!dig || !dig->afmt || !dig->afmt->pin)
		return;

	offset = dig->afmt->pin->offset;

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
	}
}

void dce6_audio_enable(struct radeon_device *rdev,
		       struct r600_audio_pin *pin,
		       u8 enable_mask)
{
	if (!pin)
		return;

	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
			enable_mask ? AUDIO_ENABLED : 0);
}

void dce6_audio_fini(struct radeon_device *rdev)
{
	int i;

	if (!rdev->audio.enabled)
		return;

	for (i = 0; i < rdev->audio.num_pins; i++)
		dce6_audio_enable(rdev, &rdev->audio.pin[i], false);

	rdev->audio.enabled = false;
}
Commit	Line	Data
b530602f AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/hdmi.h>
	24	#include <drm/drmP.h>
	25	#include "radeon.h"
1a626b68	26	#include "radeon_audio.h"
b530602f AD	27	#include "sid.h"
b530602f AD	28
1a626b68	29	u32 dce6_endpoint_rreg(struct radeon_device *rdev,
b530602f AD	30	u32 block_offset, u32 reg)
b530602f AD	31	{
0a5b7b0b	32	unsigned long flags;
b530602f AD	33	u32 r;
b530602f AD	34
0a5b7b0b	35	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	36	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
b530602f AD	37	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
0a5b7b0b AD	38	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0a5b7b0b AD	39
b530602f AD	40	return r;
	41	}
	42
1a626b68	43	void dce6_endpoint_wreg(struct radeon_device *rdev,
b530602f AD	44	u32 block_offset, u32 reg, u32 v)
b530602f AD	45	{
0a5b7b0b AD	46	unsigned long flags;
	47
	48	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	49	if (ASIC_IS_DCE8(rdev))
	50	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	51	else
	52	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
	53	AZ_ENDPOINT_REG_WRITE_EN \| AZ_ENDPOINT_REG_INDEX(reg));
	54	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
0a5b7b0b	55	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
b530602f AD	56	}
b530602f AD	57
b530602f AD	58	static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
	59	{
	60	int i;
	61	u32 offset, tmp;
	62
	63	for (i = 0; i < rdev->audio.num_pins; i++) {
	64	offset = rdev->audio.pin[i].offset;
	65	tmp = RREG32_ENDPOINT(offset,
	66	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
	67	if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
	68	rdev->audio.pin[i].connected = false;
	69	else
	70	rdev->audio.pin[i].connected = true;
	71	}
	72	}
	73
	74	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev)
	75	{
	76	int i;
	77
	78	dce6_afmt_get_connected_pins(rdev);
	79
	80	for (i = 0; i < rdev->audio.num_pins; i++) {
	81	if (rdev->audio.pin[i].connected)
	82	return &rdev->audio.pin[i];
	83	}
	84	DRM_ERROR("No connected audio pins found!\n");
	85	return NULL;
	86	}
	87
	88	void dce6_afmt_select_pin(struct drm_encoder *encoder)
	89	{
	90	struct radeon_device *rdev = encoder->dev->dev_private;
	91	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	92	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
53dc0b0c	93	u32 offset;
b530602f	94
53dc0b0c	95	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b530602f AD	96	return;
b530602f AD	97
53dc0b0c AD	98	offset = dig->afmt->offset;
53dc0b0c AD	99
7cc0a3d8 AD	100	WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
7cc0a3d8 AD	101	AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
b530602f AD	102	}
b530602f AD	103
b1880258 AD	104	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
	105	struct drm_display_mode *mode)
	106	{
	107	struct radeon_device *rdev = encoder->dev->dev_private;
	108	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	109	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	110	struct drm_connector *connector;
	111	struct radeon_connector *radeon_connector = NULL;
	112	u32 tmp = 0, offset;
	113
53dc0b0c	114	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b1880258 AD	115	return;
	116
	117	offset = dig->afmt->pin->offset;
	118
	119	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
	120	if (connector->encoder == encoder) {
	121	radeon_connector = to_radeon_connector(connector);
	122	break;
	123	}
	124	}
	125
	126	if (!radeon_connector) {
	127	DRM_ERROR("Couldn't find encoder's connector\n");
	128	return;
	129	}
	130
	131	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	132	if (connector->latency_present[1])
	133	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	134	AUDIO_LIPSYNC(connector->audio_latency[1]);
	135	else
c748990b	136	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	137	} else {
	138	if (connector->latency_present[0])
	139	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	140	AUDIO_LIPSYNC(connector->audio_latency[0]);
	141	else
c748990b	142	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	143	}
	144	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
	145	}
	146
00a9d4bc SG	147	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
00a9d4bc SG	148	u8 *sadb, int sad_count)
b530602f AD	149	{
	150	struct radeon_device *rdev = encoder->dev->dev_private;
	151	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	152	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	153	u32 offset, tmp;
6159b65a	154
53dc0b0c	155	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
6159b65a RM	156	return;
	157
	158	offset = dig->afmt->pin->offset;
	159
6159b65a RM	160	/* program the speaker allocation */
	161	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	162	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	163	/* set HDMI mode */
	164	tmp \|= HDMI_CONNECTION;
	165	if (sad_count)
	166	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	167	else
	168	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	169	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc	170	}
6159b65a	171
00a9d4bc SG	172	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
	173	u8 *sadb, int sad_count)
	174	{
	175	struct radeon_device *rdev = encoder->dev->dev_private;
	176	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	177	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	178	u32 offset, tmp;
	179
	180	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
	181	return;
	182
	183	offset = dig->afmt->pin->offset;
	184
	185	/* program the speaker allocation */
	186	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	187	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	188	/* set DP mode */
	189	tmp \|= DP_CONNECTION;
	190	if (sad_count)
	191	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	192	else
	193	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
	194	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
6159b65a RM	195	}
6159b65a RM	196
070a2e63 AD	197	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
070a2e63 AD	198	struct cea_sad *sads, int sad_count)
6159b65a	199	{
070a2e63 AD	200	u32 offset;
070a2e63 AD	201	int i;
6159b65a RM	202	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
6159b65a RM	203	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
070a2e63	204	struct radeon_device *rdev = encoder->dev->dev_private;
b530602f AD	205	static const u16 eld_reg_to_type[][2] = {
	206	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	207	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	208	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	209	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	210	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	211	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	212	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	213	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	214	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	215	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	216	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	217	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	218	};
	219
53dc0b0c	220	if (!dig \|\| !dig->afmt \|\| !dig->afmt->pin)
b530602f AD	221	return;
	222
	223	offset = dig->afmt->pin->offset;
	224
b530602f AD	225	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
b530602f AD	226	u32 value = 0;
0f57bca9 AH	227	u8 stereo_freqs = 0;
0f57bca9 AH	228	int max_channels = -1;
b530602f AD	229	int j;
	230
	231	for (j = 0; j < sad_count; j++) {
	232	struct cea_sad *sad = &sads[j];
	233
	234	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	235	if (sad->channels > max_channels) {
	236	value = MAX_CHANNELS(sad->channels) \|
	237	DESCRIPTOR_BYTE_2(sad->byte2) \|
	238	SUPPORTED_FREQUENCIES(sad->freq);
	239	max_channels = sad->channels;
	240	}
	241
b530602f	242	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	243	stereo_freqs \|= sad->freq;
	244	else
	245	break;
b530602f AD	246	}
b530602f AD	247	}
0f57bca9 AH	248
	249	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	250
b530602f AD	251	WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
b530602f AD	252	}
b530602f AD	253	}
b530602f AD	254
832eafaf AD	255	void dce6_audio_enable(struct radeon_device *rdev,
832eafaf AD	256	struct r600_audio_pin *pin,
d3d8c141	257	u8 enable_mask)
b530602f	258	{
832eafaf AD	259	if (!pin)
	260	return;
	261
f68fdbe4	262	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
d3d8c141	263	enable_mask ? AUDIO_ENABLED : 0);
b530602f AD	264	}
b530602f AD	265
b530602f AD	266	void dce6_audio_fini(struct radeon_device *rdev)
	267	{
	268	int i;
	269
	270	if (!rdev->audio.enabled)
	271	return;
	272
	273	for (i = 0; i < rdev->audio.num_pins; i++)
	274	dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
	275
	276	rdev->audio.enabled = false;
	277	}