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drm/radeon/atom: fix typo in SetPixelClock handling
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
36
37static u8
38radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
39{
40 u8 backlight_level;
41 u32 bios_2_scratch;
42
43 if (rdev->family >= CHIP_R600)
44 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 else
46 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47
48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50
51 return backlight_level;
52}
53
54static void
55radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
56 u8 backlight_level)
57{
58 u32 bios_2_scratch;
59
60 if (rdev->family >= CHIP_R600)
61 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 else
63 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64
65 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
66 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
67 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68
69 if (rdev->family >= CHIP_R600)
70 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 else
72 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
73}
74
fda4b25c 75void
37e9b6a6 76atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 77{
78 struct drm_encoder *encoder = &radeon_encoder->base;
79 struct drm_device *dev = radeon_encoder->base.dev;
80 struct radeon_device *rdev = dev->dev_private;
81 struct radeon_encoder_atom_dig *dig;
82 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
83 int index;
84
37e9b6a6
AD		 85 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
86 return;
87
88 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
89 radeon_encoder->enc_priv) {
f3728734 90 dig = radeon_encoder->enc_priv;
37e9b6a6 91 dig->backlight_level = level;
f3728734
AD		 92 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
93
94 switch (radeon_encoder->encoder_id) {
95 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
96 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
97 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
98 if (dig->backlight_level == 0) {
99 args.ucAction = ATOM_LCD_BLOFF;
100 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
101 } else {
102 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
103 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
104 args.ucAction = ATOM_LCD_BLON;
105 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
106 }
107 break;
108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
109 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
112 if (dig->backlight_level == 0)
113 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
114 else {
115 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
116 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
117 }
118 break;
119 default:
120 break;
121 }
122 }
123}
124
125static u8 radeon_atom_bl_level(struct backlight_device *bd)
126{
127 u8 level;
128
129 /* Convert brightness to hardware level */
130 if (bd->props.brightness < 0)
131 level = 0;
132 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
133 level = RADEON_MAX_BL_LEVEL;
134 else
135 level = bd->props.brightness;
136
137 return level;
138}
139
140static int radeon_atom_backlight_update_status(struct backlight_device *bd)
141{
142 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
143 struct radeon_encoder *radeon_encoder = pdata->encoder;
144
37e9b6a6 145 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 146
147 return 0;
148}
149
150static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
151{
152 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
153 struct radeon_encoder *radeon_encoder = pdata->encoder;
154 struct drm_device *dev = radeon_encoder->base.dev;
155 struct radeon_device *rdev = dev->dev_private;
156
157 return radeon_atom_get_backlight_level_from_reg(rdev);
158}
159
160static const struct backlight_ops radeon_atom_backlight_ops = {
161 .get_brightness = radeon_atom_backlight_get_brightness,
162 .update_status = radeon_atom_backlight_update_status,
163};
164
165void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
166 struct drm_connector *drm_connector)
167{
168 struct drm_device *dev = radeon_encoder->base.dev;
169 struct radeon_device *rdev = dev->dev_private;
170 struct backlight_device *bd;
171 struct backlight_properties props;
172 struct radeon_backlight_privdata *pdata;
173 struct radeon_encoder_atom_dig *dig;
174 u8 backlight_level;
175
176 if (!radeon_encoder->enc_priv)
177 return;
178
179 if (!rdev->is_atom_bios)
180 return;
181
182 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
183 return;
184
185 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
186 if (!pdata) {
187 DRM_ERROR("Memory allocation failed\n");
188 goto error;
189 }
190
191 memset(&props, 0, sizeof(props));
192 props.max_brightness = RADEON_MAX_BL_LEVEL;
193 props.type = BACKLIGHT_RAW;
194 bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
195 pdata, &radeon_atom_backlight_ops, &props);
196 if (IS_ERR(bd)) {
197 DRM_ERROR("Backlight registration failed\n");
198 goto error;
199 }
200
201 pdata->encoder = radeon_encoder;
202
203 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
204
205 dig = radeon_encoder->enc_priv;
206 dig->bl_dev = bd;
207
208 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
209 bd->props.power = FB_BLANK_UNBLANK;
210 backlight_update_status(bd);
211
212 DRM_INFO("radeon atom DIG backlight initialized\n");
213
214 return;
215
216error:
217 kfree(pdata);
218 return;
219}
220
221static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
222{
223 struct drm_device *dev = radeon_encoder->base.dev;
224 struct radeon_device *rdev = dev->dev_private;
225 struct backlight_device *bd = NULL;
226 struct radeon_encoder_atom_dig *dig;
227
228 if (!radeon_encoder->enc_priv)
229 return;
230
231 if (!rdev->is_atom_bios)
232 return;
233
234 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
235 return;
236
237 dig = radeon_encoder->enc_priv;
238 bd = dig->bl_dev;
239 dig->bl_dev = NULL;
240
241 if (bd) {
242 struct radeon_legacy_backlight_privdata *pdata;
243
244 pdata = bl_get_data(bd);
245 backlight_device_unregister(bd);
246 kfree(pdata);
247
248 DRM_INFO("radeon atom LVDS backlight unloaded\n");
249 }
250}
251
252#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
253
254void radeon_atom_backlight_init(struct radeon_encoder *encoder)
255{
256}
257
258static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
259{
260}
261
262#endif
263
3f03ced8
AD		 264/* evil but including atombios.h is much worse */
265bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
266 struct drm_display_mode *mode);
267
268
269static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
270{
271 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
272 switch (radeon_encoder->encoder_id) {
273 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
274 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
275 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
276 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
277 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
278 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
279 case ENCODER_OBJECT_ID_INTERNAL_DDI:
280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
281 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
282 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
284 return true;
285 default:
286 return false;
287 }
288}
289
3f03ced8 290static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 291 const struct drm_display_mode *mode,
3f03ced8
AD		 292 struct drm_display_mode *adjusted_mode)
293{
294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
295 struct drm_device *dev = encoder->dev;
296 struct radeon_device *rdev = dev->dev_private;
297
298 /* set the active encoder to connector routing */
299 radeon_encoder_set_active_device(encoder);
300 drm_mode_set_crtcinfo(adjusted_mode, 0);
301
302 /* hw bug */
303 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
304 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
305 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
306
307 /* get the native mode for LVDS */
308 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
309 radeon_panel_mode_fixup(encoder, adjusted_mode);
310
311 /* get the native mode for TV */
312 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
313 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
314 if (tv_dac) {
315 if (tv_dac->tv_std == TV_STD_NTSC ||
316 tv_dac->tv_std == TV_STD_NTSC_J ||
317 tv_dac->tv_std == TV_STD_PAL_M)
318 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
319 else
320 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
321 }
322 }
323
324 if (ASIC_IS_DCE3(rdev) &&
325 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
326 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
327 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
328 radeon_dp_set_link_config(connector, mode);
329 }
330
331 return true;
332}
333
334static void
335atombios_dac_setup(struct drm_encoder *encoder, int action)
336{
337 struct drm_device *dev = encoder->dev;
338 struct radeon_device *rdev = dev->dev_private;
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
341 int index = 0;
342 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
343
344 memset(&args, 0, sizeof(args));
345
346 switch (radeon_encoder->encoder_id) {
347 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
348 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
349 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
350 break;
351 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
352 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
353 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
354 break;
355 }
356
357 args.ucAction = action;
358
359 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
360 args.ucDacStandard = ATOM_DAC1_PS2;
361 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
362 args.ucDacStandard = ATOM_DAC1_CV;
363 else {
364 switch (dac_info->tv_std) {
365 case TV_STD_PAL:
366 case TV_STD_PAL_M:
367 case TV_STD_SCART_PAL:
368 case TV_STD_SECAM:
369 case TV_STD_PAL_CN:
370 args.ucDacStandard = ATOM_DAC1_PAL;
371 break;
372 case TV_STD_NTSC:
373 case TV_STD_NTSC_J:
374 case TV_STD_PAL_60:
375 default:
376 args.ucDacStandard = ATOM_DAC1_NTSC;
377 break;
378 }
379 }
380 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
381
382 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
383
384}
385
386static void
387atombios_tv_setup(struct drm_encoder *encoder, int action)
388{
389 struct drm_device *dev = encoder->dev;
390 struct radeon_device *rdev = dev->dev_private;
391 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
392 TV_ENCODER_CONTROL_PS_ALLOCATION args;
393 int index = 0;
394 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
395
396 memset(&args, 0, sizeof(args));
397
398 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
399
400 args.sTVEncoder.ucAction = action;
401
402 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
403 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
404 else {
405 switch (dac_info->tv_std) {
406 case TV_STD_NTSC:
407 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
408 break;
409 case TV_STD_PAL:
410 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
411 break;
412 case TV_STD_PAL_M:
413 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
414 break;
415 case TV_STD_PAL_60:
416 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
417 break;
418 case TV_STD_NTSC_J:
419 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
420 break;
421 case TV_STD_SCART_PAL:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
423 break;
424 case TV_STD_SECAM:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
426 break;
427 case TV_STD_PAL_CN:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
429 break;
430 default:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
432 break;
433 }
434 }
435
436 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
437
438 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
439
440}
441
1f0e2943
AD		 442static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
443{
444 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
445 int bpc = 8;
446
447 if (connector)
448 bpc = radeon_get_monitor_bpc(connector);
449
450 switch (bpc) {
451 case 0:
452 return PANEL_BPC_UNDEFINE;
453 case 6:
454 return PANEL_6BIT_PER_COLOR;
455 case 8:
456 default:
457 return PANEL_8BIT_PER_COLOR;
458 case 10:
459 return PANEL_10BIT_PER_COLOR;
460 case 12:
461 return PANEL_12BIT_PER_COLOR;
462 case 16:
463 return PANEL_16BIT_PER_COLOR;
464 }
465}
466
467
3f03ced8
AD		 468union dvo_encoder_control {
469 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
470 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
471 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
472};
473
474void
475atombios_dvo_setup(struct drm_encoder *encoder, int action)
476{
477 struct drm_device *dev = encoder->dev;
478 struct radeon_device *rdev = dev->dev_private;
479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
480 union dvo_encoder_control args;
481 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 482 uint8_t frev, crev;
3f03ced8
AD		 483
484 memset(&args, 0, sizeof(args));
485
24153dd3
AD		 486 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
487 return;
488
afceb931
AD		 489 /* some R4xx chips have the wrong frev */
490 if (rdev->family <= CHIP_RV410)
491 frev = 1;
492
24153dd3
AD		 493 switch (frev) {
494 case 1:
495 switch (crev) {
496 case 1:
497 /* R4xx, R5xx */
498 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
499
9aa59993 500 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 501 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
502
503 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
504 break;
505 case 2:
506 /* RS600/690/740 */
507 args.dvo.sDVOEncoder.ucAction = action;
508 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
509 /* DFP1, CRT1, TV1 depending on the type of port */
510 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
511
9aa59993 512 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 513 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
514 break;
515 case 3:
516 /* R6xx */
517 args.dvo_v3.ucAction = action;
518 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
519 args.dvo_v3.ucDVOConfig = 0; /* XXX */
520 break;
521 default:
522 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
523 break;
524 }
525 break;
526 default:
527 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
528 break;
3f03ced8
AD		 529 }
530
531 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
532}
533
534union lvds_encoder_control {
535 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
536 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
537};
538
539void
540atombios_digital_setup(struct drm_encoder *encoder, int action)
541{
542 struct drm_device *dev = encoder->dev;
543 struct radeon_device *rdev = dev->dev_private;
544 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
545 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
546 union lvds_encoder_control args;
547 int index = 0;
548 int hdmi_detected = 0;
549 uint8_t frev, crev;
550
551 if (!dig)
552 return;
553
554 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
555 hdmi_detected = 1;
556
557 memset(&args, 0, sizeof(args));
558
559 switch (radeon_encoder->encoder_id) {
560 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
561 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
562 break;
563 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
564 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
565 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
566 break;
567 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
568 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
569 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
570 else
571 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
572 break;
573 }
574
575 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
576 return;
577
578 switch (frev) {
579 case 1:
580 case 2:
581 switch (crev) {
582 case 1:
583 args.v1.ucMisc = 0;
584 args.v1.ucAction = action;
585 if (hdmi_detected)
586 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
587 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
589 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
590 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
591 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
592 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
593 } else {
594 if (dig->linkb)
595 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 596 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 597 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
598 /*if (pScrn->rgbBits == 8) */
599 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
600 }
601 break;
602 case 2:
603 case 3:
604 args.v2.ucMisc = 0;
605 args.v2.ucAction = action;
606 if (crev == 3) {
607 if (dig->coherent_mode)
608 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
609 }
610 if (hdmi_detected)
611 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
612 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
613 args.v2.ucTruncate = 0;
614 args.v2.ucSpatial = 0;
615 args.v2.ucTemporal = 0;
616 args.v2.ucFRC = 0;
617 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
618 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
619 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
620 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
621 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
622 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
623 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
624 }
625 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
626 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
627 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
628 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
629 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
630 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
631 }
632 } else {
633 if (dig->linkb)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 635 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 636 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
637 }
638 break;
639 default:
640 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
641 break;
642 }
643 break;
644 default:
645 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
646 break;
647 }
648
649 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
650}
651
652int
653atombios_get_encoder_mode(struct drm_encoder *encoder)
654{
655 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 656 struct drm_connector *connector;
657 struct radeon_connector *radeon_connector;
658 struct radeon_connector_atom_dig *dig_connector;
659
660 /* dp bridges are always DP */
661 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
662 return ATOM_ENCODER_MODE_DP;
663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
668 connector = radeon_get_connector_for_encoder(encoder);
669 /* if we don't have an active device yet, just use one of
670 * the connectors tied to the encoder.
671 */
672 if (!connector)
673 connector = radeon_get_connector_for_encoder_init(encoder);
674 radeon_connector = to_radeon_connector(connector);
675
676 switch (connector->connector_type) {
677 case DRM_MODE_CONNECTOR_DVII:
678 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 679 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 680 radeon_audio)
681 return ATOM_ENCODER_MODE_HDMI;
682 else if (radeon_connector->use_digital)
3f03ced8
AD		 683 return ATOM_ENCODER_MODE_DVI;
684 else
685 return ATOM_ENCODER_MODE_CRT;
686 break;
687 case DRM_MODE_CONNECTOR_DVID:
688 case DRM_MODE_CONNECTOR_HDMIA:
689 default:
27d9cc84 690 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 691 radeon_audio)
692 return ATOM_ENCODER_MODE_HDMI;
693 else
3f03ced8
AD		 694 return ATOM_ENCODER_MODE_DVI;
695 break;
696 case DRM_MODE_CONNECTOR_LVDS:
697 return ATOM_ENCODER_MODE_LVDS;
698 break;
699 case DRM_MODE_CONNECTOR_DisplayPort:
700 dig_connector = radeon_connector->con_priv;
701 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
702 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
703 return ATOM_ENCODER_MODE_DP;
27d9cc84 704 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
f92e70ca
RM		 705 radeon_audio)
706 return ATOM_ENCODER_MODE_HDMI;
707 else
3f03ced8
AD		 708 return ATOM_ENCODER_MODE_DVI;
709 break;
710 case DRM_MODE_CONNECTOR_eDP:
711 return ATOM_ENCODER_MODE_DP;
712 case DRM_MODE_CONNECTOR_DVIA:
713 case DRM_MODE_CONNECTOR_VGA:
714 return ATOM_ENCODER_MODE_CRT;
715 break;
716 case DRM_MODE_CONNECTOR_Composite:
717 case DRM_MODE_CONNECTOR_SVIDEO:
718 case DRM_MODE_CONNECTOR_9PinDIN:
719 /* fix me */
720 return ATOM_ENCODER_MODE_TV;
721 /*return ATOM_ENCODER_MODE_CV;*/
722 break;
723 }
724}
725
726/*
727 * DIG Encoder/Transmitter Setup
728 *
729 * DCE 3.0/3.1
730 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
731 * Supports up to 3 digital outputs
732 * - 2 DIG encoder blocks.
733 * DIG1 can drive UNIPHY link A or link B
734 * DIG2 can drive UNIPHY link B or LVTMA
735 *
736 * DCE 3.2
737 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
738 * Supports up to 5 digital outputs
739 * - 2 DIG encoder blocks.
740 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
741 *
2d415869 742 * DCE 4.0/5.0/6.0
3f03ced8
AD		 743 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
744 * Supports up to 6 digital outputs
745 * - 6 DIG encoder blocks.
746 * - DIG to PHY mapping is hardcoded
747 * DIG1 drives UNIPHY0 link A, A+B
748 * DIG2 drives UNIPHY0 link B
749 * DIG3 drives UNIPHY1 link A, A+B
750 * DIG4 drives UNIPHY1 link B
751 * DIG5 drives UNIPHY2 link A, A+B
752 * DIG6 drives UNIPHY2 link B
753 *
754 * DCE 4.1
755 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
756 * Supports up to 6 digital outputs
757 * - 2 DIG encoder blocks.
2d415869 758 * llano
3f03ced8 759 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 760 * ontario
761 * DIG1 drives UNIPHY0/1/2 link A
762 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 763 *
764 * Routing
765 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
766 * Examples:
767 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
768 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
769 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
770 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
771 */
772
773union dig_encoder_control {
774 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
775 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
776 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
777 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
778};
779
780void
781atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
782{
783 struct drm_device *dev = encoder->dev;
784 struct radeon_device *rdev = dev->dev_private;
785 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
786 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
787 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
788 union dig_encoder_control args;
789 int index = 0;
790 uint8_t frev, crev;
791 int dp_clock = 0;
792 int dp_lane_count = 0;
793 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 794
795 if (connector) {
796 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
797 struct radeon_connector_atom_dig *dig_connector =
798 radeon_connector->con_priv;
799
800 dp_clock = dig_connector->dp_clock;
801 dp_lane_count = dig_connector->dp_lane_count;
802 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 803 }
804
805 /* no dig encoder assigned */
806 if (dig->dig_encoder == -1)
807 return;
808
809 memset(&args, 0, sizeof(args));
810
811 if (ASIC_IS_DCE4(rdev))
812 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
813 else {
814 if (dig->dig_encoder)
815 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
816 else
817 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
818 }
819
820 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
821 return;
822
58cdcb8b
AD		 823 switch (frev) {
824 case 1:
825 switch (crev) {
826 case 1:
827 args.v1.ucAction = action;
828 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
829 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
830 args.v3.ucPanelMode = panel_mode;
831 else
832 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
833
834 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
835 args.v1.ucLaneNum = dp_lane_count;
9aa59993 836 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 837 args.v1.ucLaneNum = 8;
838 else
839 args.v1.ucLaneNum = 4;
840
841 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
842 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
843 switch (radeon_encoder->encoder_id) {
844 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
845 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
846 break;
847 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
848 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
849 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
850 break;
851 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
852 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
853 break;
854 }
855 if (dig->linkb)
856 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
857 else
858 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 859 break;
58cdcb8b
AD		 860 case 2:
861 case 3:
862 args.v3.ucAction = action;
863 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
864 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
865 args.v3.ucPanelMode = panel_mode;
866 else
867 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
868
2f6fa79a 869 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 870 args.v3.ucLaneNum = dp_lane_count;
9aa59993 871 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 872 args.v3.ucLaneNum = 8;
873 else
874 args.v3.ucLaneNum = 4;
875
2f6fa79a 876 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
878 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 879 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 880 break;
58cdcb8b
AD		 881 case 4:
882 args.v4.ucAction = action;
883 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
884 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
885 args.v4.ucPanelMode = panel_mode;
886 else
887 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
888
2f6fa79a 889 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 890 args.v4.ucLaneNum = dp_lane_count;
9aa59993 891 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 892 args.v4.ucLaneNum = 8;
893 else
894 args.v4.ucLaneNum = 4;
895
2f6fa79a 896 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
58cdcb8b
AD		 897 if (dp_clock == 270000)
898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
899 else if (dp_clock == 540000)
900 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
901 }
902 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 903 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 904 if (hpd_id == RADEON_HPD_NONE)
905 args.v4.ucHPD_ID = 0;
906 else
907 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 908 break;
3f03ced8 909 default:
58cdcb8b 910 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 911 break;
912 }
58cdcb8b
AD		 913 break;
914 default:
915 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
916 break;
3f03ced8
AD		 917 }
918
919 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
920
921}
922
923union dig_transmitter_control {
924 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
925 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
926 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
927 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 928 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 929};
930
931void
932atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
933{
934 struct drm_device *dev = encoder->dev;
935 struct radeon_device *rdev = dev->dev_private;
936 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
938 struct drm_connector *connector;
939 union dig_transmitter_control args;
940 int index = 0;
941 uint8_t frev, crev;
942 bool is_dp = false;
943 int pll_id = 0;
944 int dp_clock = 0;
945 int dp_lane_count = 0;
946 int connector_object_id = 0;
947 int igp_lane_info = 0;
948 int dig_encoder = dig->dig_encoder;
47aef7a8 949 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 950
951 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
952 connector = radeon_get_connector_for_encoder_init(encoder);
953 /* just needed to avoid bailing in the encoder check. the encoder
954 * isn't used for init
955 */
956 dig_encoder = 0;
957 } else
958 connector = radeon_get_connector_for_encoder(encoder);
959
960 if (connector) {
961 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
962 struct radeon_connector_atom_dig *dig_connector =
963 radeon_connector->con_priv;
964
47aef7a8 965 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 966 dp_clock = dig_connector->dp_clock;
967 dp_lane_count = dig_connector->dp_lane_count;
968 connector_object_id =
969 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
970 igp_lane_info = dig_connector->igp_lane_info;
971 }
972
a3b08294
AD		 973 if (encoder->crtc) {
974 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
975 pll_id = radeon_crtc->pll_id;
976 }
977
3f03ced8
AD		 978 /* no dig encoder assigned */
979 if (dig_encoder == -1)
980 return;
981
982 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
983 is_dp = true;
984
985 memset(&args, 0, sizeof(args));
986
987 switch (radeon_encoder->encoder_id) {
988 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
989 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
990 break;
991 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
992 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
994 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
995 break;
996 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
997 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
998 break;
999 }
1000
1001 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1002 return;
1003
a3b08294
AD		 1004 switch (frev) {
1005 case 1:
1006 switch (crev) {
1007 case 1:
1008 args.v1.ucAction = action;
1009 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1010 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1011 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1012 args.v1.asMode.ucLaneSel = lane_num;
1013 args.v1.asMode.ucLaneSet = lane_set;
1014 } else {
1015 if (is_dp)
6e76a2df 1016 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1017 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1018 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1019 else
1020 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1021 }
3f03ced8 1022
a3b08294 1023 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1024
a3b08294
AD		 1025 if (dig_encoder)
1026 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1027 else
1028 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1029
1030 if ((rdev->flags & RADEON_IS_IGP) &&
1031 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1032 if (is_dp ||
1033 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1034 if (igp_lane_info & 0x1)
1035 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1036 else if (igp_lane_info & 0x2)
1037 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1038 else if (igp_lane_info & 0x4)
1039 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1040 else if (igp_lane_info & 0x8)
1041 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1042 } else {
1043 if (igp_lane_info & 0x3)
1044 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1045 else if (igp_lane_info & 0xc)
1046 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1047 }
1048 }
1049
1050 if (dig->linkb)
1051 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1052 else
1053 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1054
1055 if (is_dp)
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1057 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1058 if (dig->coherent_mode)
1059 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1060 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1061 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1062 }
1063 break;
1064 case 2:
1065 args.v2.ucAction = action;
1066 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1067 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1068 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1069 args.v2.asMode.ucLaneSel = lane_num;
1070 args.v2.asMode.ucLaneSet = lane_set;
1071 } else {
1072 if (is_dp)
6e76a2df 1073 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1074 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1075 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1076 else
1077 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1078 }
1079
1080 args.v2.acConfig.ucEncoderSel = dig_encoder;
1081 if (dig->linkb)
1082 args.v2.acConfig.ucLinkSel = 1;
1083
1084 switch (radeon_encoder->encoder_id) {
1085 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1086 args.v2.acConfig.ucTransmitterSel = 0;
1087 break;
1088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1089 args.v2.acConfig.ucTransmitterSel = 1;
1090 break;
1091 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1092 args.v2.acConfig.ucTransmitterSel = 2;
1093 break;
1094 }
3f03ced8 1095
3f03ced8 1096 if (is_dp) {
a3b08294
AD		 1097 args.v2.acConfig.fCoherentMode = 1;
1098 args.v2.acConfig.fDPConnector = 1;
1099 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1100 if (dig->coherent_mode)
1101 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1102 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1103 args.v2.acConfig.fDualLinkConnector = 1;
1104 }
1105 break;
1106 case 3:
1107 args.v3.ucAction = action;
1108 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1109 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1110 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1111 args.v3.asMode.ucLaneSel = lane_num;
1112 args.v3.asMode.ucLaneSet = lane_set;
1113 } else {
1114 if (is_dp)
6e76a2df 1115 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1116 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1117 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1118 else
a3b08294
AD		 1119 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1120 }
1121
1122 if (is_dp)
1123 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1124 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1125 args.v3.ucLaneNum = 8;
1126 else
1127 args.v3.ucLaneNum = 4;
1128
1129 if (dig->linkb)
1130 args.v3.acConfig.ucLinkSel = 1;
1131 if (dig_encoder & 1)
1132 args.v3.acConfig.ucEncoderSel = 1;
1133
1134 /* Select the PLL for the PHY
1135 * DP PHY should be clocked from external src if there is
1136 * one.
1137 */
3f03ced8
AD		 1138 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1139 if (is_dp && rdev->clock.dp_extclk)
1140 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1141 else
1142 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1143
a3b08294
AD		 1144 switch (radeon_encoder->encoder_id) {
1145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1146 args.v3.acConfig.ucTransmitterSel = 0;
1147 break;
1148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1149 args.v3.acConfig.ucTransmitterSel = 1;
1150 break;
1151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1152 args.v3.acConfig.ucTransmitterSel = 2;
1153 break;
1154 }
3f03ced8 1155
a3b08294
AD		 1156 if (is_dp)
1157 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1158 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1159 if (dig->coherent_mode)
1160 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1161 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1162 args.v3.acConfig.fDualLinkConnector = 1;
1163 }
3f03ced8 1164 break;
a3b08294
AD		 1165 case 4:
1166 args.v4.ucAction = action;
1167 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1168 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1169 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1170 args.v4.asMode.ucLaneSel = lane_num;
1171 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1172 } else {
a3b08294 1173 if (is_dp)
6e76a2df 1174 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1175 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1176 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1177 else
1178 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1179 }
3f03ced8 1180
a3b08294
AD		 1181 if (is_dp)
1182 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1183 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1184 args.v4.ucLaneNum = 8;
1185 else
1186 args.v4.ucLaneNum = 4;
3f03ced8 1187
a3b08294
AD		 1188 if (dig->linkb)
1189 args.v4.acConfig.ucLinkSel = 1;
1190 if (dig_encoder & 1)
1191 args.v4.acConfig.ucEncoderSel = 1;
1192
1193 /* Select the PLL for the PHY
1194 * DP PHY should be clocked from external src if there is
1195 * one.
1196 */
1197 /* On DCE5 DCPLL usually generates the DP ref clock */
1198 if (is_dp) {
1199 if (rdev->clock.dp_extclk)
1200 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1201 else
1202 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1203 } else
1204 args.v4.acConfig.ucRefClkSource = pll_id;
1205
1206 switch (radeon_encoder->encoder_id) {
1207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1208 args.v4.acConfig.ucTransmitterSel = 0;
1209 break;
1210 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1211 args.v4.acConfig.ucTransmitterSel = 1;
1212 break;
1213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1214 args.v4.acConfig.ucTransmitterSel = 2;
1215 break;
1216 }
1217
1218 if (is_dp)
1219 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1220 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1221 if (dig->coherent_mode)
1222 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1223 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1224 args.v4.acConfig.fDualLinkConnector = 1;
1225 }
1226 break;
47aef7a8
AD		 1227 case 5:
1228 args.v5.ucAction = action;
1229 if (is_dp)
1230 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1231 else
1232 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1233
1234 switch (radeon_encoder->encoder_id) {
1235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1236 if (dig->linkb)
1237 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1238 else
1239 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1240 break;
1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1242 if (dig->linkb)
1243 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1244 else
1245 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1246 break;
1247 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1248 if (dig->linkb)
1249 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1250 else
1251 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1252 break;
1253 }
1254 if (is_dp)
1255 args.v5.ucLaneNum = dp_lane_count;
1256 else if (radeon_encoder->pixel_clock > 165000)
1257 args.v5.ucLaneNum = 8;
1258 else
1259 args.v5.ucLaneNum = 4;
1260 args.v5.ucConnObjId = connector_object_id;
1261 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1262
1263 if (is_dp && rdev->clock.dp_extclk)
1264 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1265 else
1266 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1267
1268 if (is_dp)
1269 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1270 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1271 if (dig->coherent_mode)
1272 args.v5.asConfig.ucCoherentMode = 1;
1273 }
1274 if (hpd_id == RADEON_HPD_NONE)
1275 args.v5.asConfig.ucHPDSel = 0;
1276 else
1277 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1278 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1279 args.v5.ucDPLaneSet = lane_set;
1280 break;
a3b08294
AD		 1281 default:
1282 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1283 break;
3f03ced8 1284 }
a3b08294
AD		 1285 break;
1286 default:
1287 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1288 break;
3f03ced8
AD		 1289 }
1290
1291 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1292}
1293
1294bool
1295atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1296{
1297 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1298 struct drm_device *dev = radeon_connector->base.dev;
1299 struct radeon_device *rdev = dev->dev_private;
1300 union dig_transmitter_control args;
1301 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1302 uint8_t frev, crev;
1303
1304 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1305 goto done;
1306
1307 if (!ASIC_IS_DCE4(rdev))
1308 goto done;
1309
1310 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1311 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1312 goto done;
1313
1314 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1315 goto done;
1316
1317 memset(&args, 0, sizeof(args));
1318
1319 args.v1.ucAction = action;
1320
1321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1322
1323 /* wait for the panel to power up */
1324 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1325 int i;
1326
1327 for (i = 0; i < 300; i++) {
1328 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1329 return true;
1330 mdelay(1);
1331 }
1332 return false;
1333 }
1334done:
1335 return true;
1336}
1337
1338union external_encoder_control {
1339 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1340 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1341};
1342
1343static void
1344atombios_external_encoder_setup(struct drm_encoder *encoder,
1345 struct drm_encoder *ext_encoder,
1346 int action)
1347{
1348 struct drm_device *dev = encoder->dev;
1349 struct radeon_device *rdev = dev->dev_private;
1350 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1351 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1352 union external_encoder_control args;
1353 struct drm_connector *connector;
1354 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1355 u8 frev, crev;
1356 int dp_clock = 0;
1357 int dp_lane_count = 0;
1358 int connector_object_id = 0;
1359 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1360
1361 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1362 connector = radeon_get_connector_for_encoder_init(encoder);
1363 else
1364 connector = radeon_get_connector_for_encoder(encoder);
1365
1366 if (connector) {
1367 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1368 struct radeon_connector_atom_dig *dig_connector =
1369 radeon_connector->con_priv;
1370
1371 dp_clock = dig_connector->dp_clock;
1372 dp_lane_count = dig_connector->dp_lane_count;
1373 connector_object_id =
1374 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1375 }
1376
1377 memset(&args, 0, sizeof(args));
1378
1379 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1380 return;
1381
1382 switch (frev) {
1383 case 1:
1384 /* no params on frev 1 */
1385 break;
1386 case 2:
1387 switch (crev) {
1388 case 1:
1389 case 2:
1390 args.v1.sDigEncoder.ucAction = action;
1391 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1392 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1393
1394 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1395 if (dp_clock == 270000)
1396 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1397 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1398 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1399 args.v1.sDigEncoder.ucLaneNum = 8;
1400 else
1401 args.v1.sDigEncoder.ucLaneNum = 4;
1402 break;
1403 case 3:
1404 args.v3.sExtEncoder.ucAction = action;
1405 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1406 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1407 else
1408 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1409 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1410
1411 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1412 if (dp_clock == 270000)
1413 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1414 else if (dp_clock == 540000)
1415 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1416 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1417 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1418 args.v3.sExtEncoder.ucLaneNum = 8;
1419 else
1420 args.v3.sExtEncoder.ucLaneNum = 4;
1421 switch (ext_enum) {
1422 case GRAPH_OBJECT_ENUM_ID1:
1423 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1424 break;
1425 case GRAPH_OBJECT_ENUM_ID2:
1426 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1427 break;
1428 case GRAPH_OBJECT_ENUM_ID3:
1429 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1430 break;
1431 }
1f0e2943 1432 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1433 break;
1434 default:
1435 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1436 return;
1437 }
1438 break;
1439 default:
1440 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1441 return;
1442 }
1443 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1444}
1445
1446static void
1447atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1448{
1449 struct drm_device *dev = encoder->dev;
1450 struct radeon_device *rdev = dev->dev_private;
1451 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1453 ENABLE_YUV_PS_ALLOCATION args;
1454 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1455 uint32_t temp, reg;
1456
1457 memset(&args, 0, sizeof(args));
1458
1459 if (rdev->family >= CHIP_R600)
1460 reg = R600_BIOS_3_SCRATCH;
1461 else
1462 reg = RADEON_BIOS_3_SCRATCH;
1463
1464 /* XXX: fix up scratch reg handling */
1465 temp = RREG32(reg);
1466 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1467 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1468 (radeon_crtc->crtc_id << 18)));
1469 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1470 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1471 else
1472 WREG32(reg, 0);
1473
1474 if (enable)
1475 args.ucEnable = ATOM_ENABLE;
1476 args.ucCRTC = radeon_crtc->crtc_id;
1477
1478 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1479
1480 WREG32(reg, temp);
1481}
1482
1483static void
1484radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1485{
1486 struct drm_device *dev = encoder->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1489 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1490 int index = 0;
1491
1492 memset(&args, 0, sizeof(args));
1493
1494 switch (radeon_encoder->encoder_id) {
1495 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1496 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1497 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1498 break;
1499 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1500 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1501 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1502 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1503 break;
1504 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1505 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1506 break;
1507 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1508 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1509 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1510 else
1511 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1512 break;
1513 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1514 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1515 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1516 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1517 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1518 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1519 else
1520 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1521 break;
1522 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1524 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1525 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1526 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1527 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1528 else
1529 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1530 break;
1531 default:
1532 return;
1533 }
1534
1535 switch (mode) {
1536 case DRM_MODE_DPMS_ON:
1537 args.ucAction = ATOM_ENABLE;
1538 /* workaround for DVOOutputControl on some RS690 systems */
1539 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1540 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1541 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1542 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1543 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1544 } else
1545 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1546 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1547 args.ucAction = ATOM_LCD_BLON;
1548 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1549 }
1550 break;
1551 case DRM_MODE_DPMS_STANDBY:
1552 case DRM_MODE_DPMS_SUSPEND:
1553 case DRM_MODE_DPMS_OFF:
1554 args.ucAction = ATOM_DISABLE;
1555 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1556 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1557 args.ucAction = ATOM_LCD_BLOFF;
1558 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1559 }
1560 break;
1561 }
1562}
1563
1564static void
1565radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1566{
1567 struct drm_device *dev = encoder->dev;
1568 struct radeon_device *rdev = dev->dev_private;
1569 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1570 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1571 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1572 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1573 struct radeon_connector *radeon_connector = NULL;
1574 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1575
1576 if (connector) {
1577 radeon_connector = to_radeon_connector(connector);
1578 radeon_dig_connector = radeon_connector->con_priv;
1579 }
1580
1581 switch (mode) {
1582 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1583 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1584 if (!connector)
1585 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1586 else
1587 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1588
1589 /* setup and enable the encoder */
1590 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1591 atombios_dig_encoder_setup(encoder,
1592 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1593 dig->panel_mode);
1594 if (ext_encoder) {
1595 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1596 atombios_external_encoder_setup(encoder, ext_encoder,
1597 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1598 }
3f03ced8 1599 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1600 } else if (ASIC_IS_DCE4(rdev)) {
1601 /* setup and enable the encoder */
1602 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1603 /* enable the transmitter */
1604 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1605 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1606 } else {
1607 /* setup and enable the encoder and transmitter */
1608 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1609 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1610 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1611 /* some early dce3.2 boards have a bug in their transmitter control table */
1612 if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1613 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1614 }
3f03ced8
AD		 1615 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1616 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1617 atombios_set_edp_panel_power(connector,
1618 ATOM_TRANSMITTER_ACTION_POWER_ON);
1619 radeon_dig_connector->edp_on = true;
1620 }
3f03ced8
AD		 1621 radeon_dp_link_train(encoder, connector);
1622 if (ASIC_IS_DCE4(rdev))
1623 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1624 }
1625 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1627 break;
1628 case DRM_MODE_DPMS_STANDBY:
1629 case DRM_MODE_DPMS_SUSPEND:
1630 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1631 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1632 /* disable the transmitter */
3a47824d 1633 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1634 } else if (ASIC_IS_DCE4(rdev)) {
1635 /* disable the transmitter */
1636 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1637 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1638 } else {
1639 /* disable the encoder and transmitter */
3a47824d 1640 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1642 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1643 }
3f03ced8
AD		 1644 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1645 if (ASIC_IS_DCE4(rdev))
1646 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1647 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1648 atombios_set_edp_panel_power(connector,
1649 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1650 radeon_dig_connector->edp_on = false;
1651 }
1652 }
1653 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1654 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1655 break;
1656 }
1657}
1658
1659static void
1660radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1661 struct drm_encoder *ext_encoder,
1662 int mode)
1663{
1664 struct drm_device *dev = encoder->dev;
1665 struct radeon_device *rdev = dev->dev_private;
1666
1667 switch (mode) {
1668 case DRM_MODE_DPMS_ON:
1669 default:
1d3949c4 1670 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1671 atombios_external_encoder_setup(encoder, ext_encoder,
1672 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1673 atombios_external_encoder_setup(encoder, ext_encoder,
1674 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1675 } else
1676 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1677 break;
1678 case DRM_MODE_DPMS_STANDBY:
1679 case DRM_MODE_DPMS_SUSPEND:
1680 case DRM_MODE_DPMS_OFF:
1d3949c4 1681 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1682 atombios_external_encoder_setup(encoder, ext_encoder,
1683 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1684 atombios_external_encoder_setup(encoder, ext_encoder,
1685 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1686 } else
1687 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1688 break;
1689 }
1690}
1691
1692static void
1693radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1694{
1695 struct drm_device *dev = encoder->dev;
1696 struct radeon_device *rdev = dev->dev_private;
1697 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1698 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1699
1700 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1701 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1702 radeon_encoder->active_device);
1703 switch (radeon_encoder->encoder_id) {
1704 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1705 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1706 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1707 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1708 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1709 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1710 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1711 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1712 radeon_atom_encoder_dpms_avivo(encoder, mode);
1713 break;
1714 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1715 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1716 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1717 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1718 radeon_atom_encoder_dpms_dig(encoder, mode);
1719 break;
1720 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1721 if (ASIC_IS_DCE5(rdev)) {
1722 switch (mode) {
1723 case DRM_MODE_DPMS_ON:
1724 atombios_dvo_setup(encoder, ATOM_ENABLE);
1725 break;
1726 case DRM_MODE_DPMS_STANDBY:
1727 case DRM_MODE_DPMS_SUSPEND:
1728 case DRM_MODE_DPMS_OFF:
1729 atombios_dvo_setup(encoder, ATOM_DISABLE);
1730 break;
1731 }
1732 } else if (ASIC_IS_DCE3(rdev))
1733 radeon_atom_encoder_dpms_dig(encoder, mode);
1734 else
1735 radeon_atom_encoder_dpms_avivo(encoder, mode);
1736 break;
1737 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1738 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1739 if (ASIC_IS_DCE5(rdev)) {
1740 switch (mode) {
1741 case DRM_MODE_DPMS_ON:
1742 atombios_dac_setup(encoder, ATOM_ENABLE);
1743 break;
1744 case DRM_MODE_DPMS_STANDBY:
1745 case DRM_MODE_DPMS_SUSPEND:
1746 case DRM_MODE_DPMS_OFF:
1747 atombios_dac_setup(encoder, ATOM_DISABLE);
1748 break;
1749 }
1750 } else
1751 radeon_atom_encoder_dpms_avivo(encoder, mode);
1752 break;
1753 default:
1754 return;
1755 }
1756
1757 if (ext_encoder)
1758 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1759
1760 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1761
1762}
1763
1764union crtc_source_param {
1765 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1766 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1767};
1768
1769static void
1770atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1771{
1772 struct drm_device *dev = encoder->dev;
1773 struct radeon_device *rdev = dev->dev_private;
1774 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1775 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1776 union crtc_source_param args;
1777 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1778 uint8_t frev, crev;
1779 struct radeon_encoder_atom_dig *dig;
1780
1781 memset(&args, 0, sizeof(args));
1782
1783 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1784 return;
1785
1786 switch (frev) {
1787 case 1:
1788 switch (crev) {
1789 case 1:
1790 default:
1791 if (ASIC_IS_AVIVO(rdev))
1792 args.v1.ucCRTC = radeon_crtc->crtc_id;
1793 else {
1794 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1795 args.v1.ucCRTC = radeon_crtc->crtc_id;
1796 } else {
1797 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1798 }
1799 }
1800 switch (radeon_encoder->encoder_id) {
1801 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1802 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1803 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1804 break;
1805 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1806 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1807 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1808 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1809 else
1810 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1811 break;
1812 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1813 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1814 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1815 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1816 break;
1817 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1818 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1819 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1820 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1821 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1822 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1823 else
1824 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1825 break;
1826 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1827 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1828 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1829 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1830 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1831 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1832 else
1833 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1834 break;
1835 }
1836 break;
1837 case 2:
1838 args.v2.ucCRTC = radeon_crtc->crtc_id;
1839 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1840 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1841
1842 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1843 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1844 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1845 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1846 else
1847 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1848 } else
1849 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1850 switch (radeon_encoder->encoder_id) {
1851 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1852 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1853 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1855 dig = radeon_encoder->enc_priv;
1856 switch (dig->dig_encoder) {
1857 case 0:
1858 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1859 break;
1860 case 1:
1861 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1862 break;
1863 case 2:
1864 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1865 break;
1866 case 3:
1867 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1868 break;
1869 case 4:
1870 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1871 break;
1872 case 5:
1873 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1874 break;
1875 }
1876 break;
1877 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1878 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1879 break;
1880 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1881 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1882 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1883 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1884 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1885 else
1886 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1887 break;
1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1889 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1890 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1891 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1892 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1893 else
1894 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1895 break;
1896 }
1897 break;
1898 }
1899 break;
1900 default:
1901 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1902 return;
1903 }
1904
1905 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1906
1907 /* update scratch regs with new routing */
1908 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1909}
1910
1911static void
1912atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1913 struct drm_display_mode *mode)
1914{
1915 struct drm_device *dev = encoder->dev;
1916 struct radeon_device *rdev = dev->dev_private;
1917 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1918 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1919
1920 /* Funky macbooks */
1921 if ((dev->pdev->device == 0x71C5) &&
1922 (dev->pdev->subsystem_vendor == 0x106b) &&
1923 (dev->pdev->subsystem_device == 0x0080)) {
1924 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1925 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1926
1927 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1928 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1929
1930 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1931 }
1932 }
1933
1934 /* set scaler clears this on some chips */
1935 if (ASIC_IS_AVIVO(rdev) &&
1936 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1937 if (ASIC_IS_DCE4(rdev)) {
1938 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1939 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1940 EVERGREEN_INTERLEAVE_EN);
1941 else
1942 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1943 } else {
1944 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1945 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1946 AVIVO_D1MODE_INTERLEAVE_EN);
1947 else
1948 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1949 }
1950 }
1951}
1952
1953static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1954{
1955 struct drm_device *dev = encoder->dev;
1956 struct radeon_device *rdev = dev->dev_private;
1957 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1958 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1959 struct drm_encoder *test_encoder;
41fa5437 1960 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1961 uint32_t dig_enc_in_use = 0;
1962
41fa5437
AD		 1963 if (ASIC_IS_DCE6(rdev)) {
1964 /* DCE6 */
1965 switch (radeon_encoder->encoder_id) {
1966 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1967 if (dig->linkb)
1968 return 1;
1969 else
1970 return 0;
1971 break;
1972 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1973 if (dig->linkb)
1974 return 3;
1975 else
1976 return 2;
1977 break;
1978 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1979 if (dig->linkb)
1980 return 5;
1981 else
1982 return 4;
1983 break;
1984 }
1985 } else if (ASIC_IS_DCE4(rdev)) {
1986 /* DCE4/5 */
1987 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1988 /* ontario follows DCE4 */
1989 if (rdev->family == CHIP_PALM) {
1990 if (dig->linkb)
1991 return 1;
1992 else
1993 return 0;
1994 } else
1995 /* llano follows DCE3.2 */
1996 return radeon_crtc->crtc_id;
1997 } else {
1998 switch (radeon_encoder->encoder_id) {
1999 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2000 if (dig->linkb)
2001 return 1;
2002 else
2003 return 0;
2004 break;
2005 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2006 if (dig->linkb)
2007 return 3;
2008 else
2009 return 2;
2010 break;
2011 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2012 if (dig->linkb)
2013 return 5;
2014 else
2015 return 4;
2016 break;
2017 }
2018 }
2019 }
2020
2021 /* on DCE32 and encoder can driver any block so just crtc id */
2022 if (ASIC_IS_DCE32(rdev)) {
2023 return radeon_crtc->crtc_id;
2024 }
2025
2026 /* on DCE3 - LVTMA can only be driven by DIGB */
2027 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2028 struct radeon_encoder *radeon_test_encoder;
2029
2030 if (encoder == test_encoder)
2031 continue;
2032
2033 if (!radeon_encoder_is_digital(test_encoder))
2034 continue;
2035
2036 radeon_test_encoder = to_radeon_encoder(test_encoder);
2037 dig = radeon_test_encoder->enc_priv;
2038
2039 if (dig->dig_encoder >= 0)
2040 dig_enc_in_use |= (1 << dig->dig_encoder);
2041 }
2042
2043 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2044 if (dig_enc_in_use & 0x2)
2045 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2046 return 1;
2047 }
2048 if (!(dig_enc_in_use & 1))
2049 return 0;
2050 return 1;
2051}
2052
2053/* This only needs to be called once at startup */
2054void
2055radeon_atom_encoder_init(struct radeon_device *rdev)
2056{
2057 struct drm_device *dev = rdev->ddev;
2058 struct drm_encoder *encoder;
2059
2060 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2061 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2062 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2063
2064 switch (radeon_encoder->encoder_id) {
2065 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2066 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2067 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2068 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2069 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2070 break;
2071 default:
2072 break;
2073 }
2074
1d3949c4 2075 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2076 atombios_external_encoder_setup(encoder, ext_encoder,
2077 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2078 }
2079}
2080
2081static void
2082radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2083 struct drm_display_mode *mode,
2084 struct drm_display_mode *adjusted_mode)
2085{
2086 struct drm_device *dev = encoder->dev;
2087 struct radeon_device *rdev = dev->dev_private;
2088 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2089
2090 radeon_encoder->pixel_clock = adjusted_mode->clock;
2091
8d1af57a
AD		 2092 /* need to call this here rather than in prepare() since we need some crtc info */
2093 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2094
3f03ced8
AD		 2095 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2096 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2097 atombios_yuv_setup(encoder, true);
2098 else
2099 atombios_yuv_setup(encoder, false);
2100 }
2101
2102 switch (radeon_encoder->encoder_id) {
2103 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2104 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2107 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2108 break;
2109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2112 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2113 /* handled in dpms */
3f03ced8
AD		 2114 break;
2115 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2116 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2117 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2118 atombios_dvo_setup(encoder, ATOM_ENABLE);
2119 break;
2120 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2122 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2123 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2124 atombios_dac_setup(encoder, ATOM_ENABLE);
2125 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2126 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2127 atombios_tv_setup(encoder, ATOM_ENABLE);
2128 else
2129 atombios_tv_setup(encoder, ATOM_DISABLE);
2130 }
2131 break;
2132 }
2133
3f03ced8
AD		 2134 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2135
2136 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2137 r600_hdmi_enable(encoder);
6b53a050
RM		 2138 if (ASIC_IS_DCE6(rdev))
2139 ; /* TODO (use pointers instead of if-s?) */
2140 else if (ASIC_IS_DCE4(rdev))
e55d3e6c
RM		 2141 evergreen_hdmi_setmode(encoder, adjusted_mode);
2142 else
2143 r600_hdmi_setmode(encoder, adjusted_mode);
3f03ced8
AD		 2144 }
2145}
2146
2147static bool
2148atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2149{
2150 struct drm_device *dev = encoder->dev;
2151 struct radeon_device *rdev = dev->dev_private;
2152 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2153 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2154
2155 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2156 ATOM_DEVICE_CV_SUPPORT |
2157 ATOM_DEVICE_CRT_SUPPORT)) {
2158 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2159 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2160 uint8_t frev, crev;
2161
2162 memset(&args, 0, sizeof(args));
2163
2164 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2165 return false;
2166
2167 args.sDacload.ucMisc = 0;
2168
2169 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2170 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2171 args.sDacload.ucDacType = ATOM_DAC_A;
2172 else
2173 args.sDacload.ucDacType = ATOM_DAC_B;
2174
2175 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2176 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2177 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2178 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2179 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2180 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2181 if (crev >= 3)
2182 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2183 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2184 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2185 if (crev >= 3)
2186 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2187 }
2188
2189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2190
2191 return true;
2192 } else
2193 return false;
2194}
2195
2196static enum drm_connector_status
2197radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2198{
2199 struct drm_device *dev = encoder->dev;
2200 struct radeon_device *rdev = dev->dev_private;
2201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2202 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2203 uint32_t bios_0_scratch;
2204
2205 if (!atombios_dac_load_detect(encoder, connector)) {
2206 DRM_DEBUG_KMS("detect returned false \n");
2207 return connector_status_unknown;
2208 }
2209
2210 if (rdev->family >= CHIP_R600)
2211 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2212 else
2213 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2214
2215 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2216 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2217 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2218 return connector_status_connected;
2219 }
2220 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2221 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2222 return connector_status_connected;
2223 }
2224 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2225 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2226 return connector_status_connected;
2227 }
2228 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2229 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2230 return connector_status_connected; /* CTV */
2231 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2232 return connector_status_connected; /* STV */
2233 }
2234 return connector_status_disconnected;
2235}
2236
2237static enum drm_connector_status
2238radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2239{
2240 struct drm_device *dev = encoder->dev;
2241 struct radeon_device *rdev = dev->dev_private;
2242 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2243 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2244 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2245 u32 bios_0_scratch;
2246
2247 if (!ASIC_IS_DCE4(rdev))
2248 return connector_status_unknown;
2249
2250 if (!ext_encoder)
2251 return connector_status_unknown;
2252
2253 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2254 return connector_status_unknown;
2255
2256 /* load detect on the dp bridge */
2257 atombios_external_encoder_setup(encoder, ext_encoder,
2258 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2259
2260 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2261
2262 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2263 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2264 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2265 return connector_status_connected;
2266 }
2267 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2268 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2269 return connector_status_connected;
2270 }
2271 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2272 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2273 return connector_status_connected;
2274 }
2275 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2276 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2277 return connector_status_connected; /* CTV */
2278 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2279 return connector_status_connected; /* STV */
2280 }
2281 return connector_status_disconnected;
2282}
2283
2284void
2285radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2286{
2287 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2288
2289 if (ext_encoder)
2290 /* ddc_setup on the dp bridge */
2291 atombios_external_encoder_setup(encoder, ext_encoder,
2292 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2293
2294}
2295
2296static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2297{
cfcbd6d3 2298 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2300 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2301
2302 if ((radeon_encoder->active_device &
2303 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2304 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2305 ENCODER_OBJECT_ID_NONE)) {
2306 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2307 if (dig) {
3f03ced8 2308 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2309 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2310 if (rdev->family >= CHIP_R600)
2311 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2312 else
2313 /* RS600/690/740 have only 1 afmt block */
2314 dig->afmt = rdev->mode_info.afmt[0];
2315 }
2316 }
3f03ced8
AD		 2317 }
2318
2319 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2320
2321 if (connector) {
2322 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2323
2324 /* select the clock/data port if it uses a router */
2325 if (radeon_connector->router.cd_valid)
2326 radeon_router_select_cd_port(radeon_connector);
2327
2328 /* turn eDP panel on for mode set */
2329 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2330 atombios_set_edp_panel_power(connector,
2331 ATOM_TRANSMITTER_ACTION_POWER_ON);
2332 }
2333
2334 /* this is needed for the pll/ss setup to work correctly in some cases */
2335 atombios_set_encoder_crtc_source(encoder);
2336}
2337
2338static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2339{
8d1af57a 2340 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2341 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2342 radeon_atom_output_lock(encoder, false);
2343}
2344
2345static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2346{
2347 struct drm_device *dev = encoder->dev;
2348 struct radeon_device *rdev = dev->dev_private;
2349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2350 struct radeon_encoder_atom_dig *dig;
2351
2352 /* check for pre-DCE3 cards with shared encoders;
2353 * can't really use the links individually, so don't disable
2354 * the encoder if it's in use by another connector
2355 */
2356 if (!ASIC_IS_DCE3(rdev)) {
2357 struct drm_encoder *other_encoder;
2358 struct radeon_encoder *other_radeon_encoder;
2359
2360 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2361 other_radeon_encoder = to_radeon_encoder(other_encoder);
2362 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2363 drm_helper_encoder_in_use(other_encoder))
2364 goto disable_done;
2365 }
2366 }
2367
2368 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2369
2370 switch (radeon_encoder->encoder_id) {
2371 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2372 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2373 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2374 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2375 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2376 break;
2377 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2378 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2380 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2381 /* handled in dpms */
3f03ced8
AD		 2382 break;
2383 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2384 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2385 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2386 atombios_dvo_setup(encoder, ATOM_DISABLE);
2387 break;
2388 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2389 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2390 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2392 atombios_dac_setup(encoder, ATOM_DISABLE);
2393 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2394 atombios_tv_setup(encoder, ATOM_DISABLE);
2395 break;
2396 }
2397
2398disable_done:
2399 if (radeon_encoder_is_digital(encoder)) {
2400 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2401 r600_hdmi_disable(encoder);
2402 dig = radeon_encoder->enc_priv;
2403 dig->dig_encoder = -1;
2404 }
2405 radeon_encoder->active_device = 0;
2406}
2407
2408/* these are handled by the primary encoders */
2409static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2410{
2411
2412}
2413
2414static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2415{
2416
2417}
2418
2419static void
2420radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2421 struct drm_display_mode *mode,
2422 struct drm_display_mode *adjusted_mode)
2423{
2424
2425}
2426
2427static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2428{
2429
2430}
2431
2432static void
2433radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2434{
2435
2436}
2437
2438static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2439 const struct drm_display_mode *mode,
3f03ced8
AD		 2440 struct drm_display_mode *adjusted_mode)
2441{
2442 return true;
2443}
2444
2445static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2446 .dpms = radeon_atom_ext_dpms,
2447 .mode_fixup = radeon_atom_ext_mode_fixup,
2448 .prepare = radeon_atom_ext_prepare,
2449 .mode_set = radeon_atom_ext_mode_set,
2450 .commit = radeon_atom_ext_commit,
2451 .disable = radeon_atom_ext_disable,
2452 /* no detect for TMDS/LVDS yet */
2453};
2454
2455static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2456 .dpms = radeon_atom_encoder_dpms,
2457 .mode_fixup = radeon_atom_mode_fixup,
2458 .prepare = radeon_atom_encoder_prepare,
2459 .mode_set = radeon_atom_encoder_mode_set,
2460 .commit = radeon_atom_encoder_commit,
2461 .disable = radeon_atom_encoder_disable,
2462 .detect = radeon_atom_dig_detect,
2463};
2464
2465static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2466 .dpms = radeon_atom_encoder_dpms,
2467 .mode_fixup = radeon_atom_mode_fixup,
2468 .prepare = radeon_atom_encoder_prepare,
2469 .mode_set = radeon_atom_encoder_mode_set,
2470 .commit = radeon_atom_encoder_commit,
2471 .detect = radeon_atom_dac_detect,
2472};
2473
2474void radeon_enc_destroy(struct drm_encoder *encoder)
2475{
2476 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2477 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2478 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2479 kfree(radeon_encoder->enc_priv);
2480 drm_encoder_cleanup(encoder);
2481 kfree(radeon_encoder);
2482}
2483
2484static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2485 .destroy = radeon_enc_destroy,
2486};
2487
1109ca09 2488static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2489radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2490{
2491 struct drm_device *dev = radeon_encoder->base.dev;
2492 struct radeon_device *rdev = dev->dev_private;
2493 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2494
2495 if (!dac)
2496 return NULL;
2497
2498 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2499 return dac;
2500}
2501
1109ca09 2502static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2503radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2504{
2505 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2506 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2507
2508 if (!dig)
2509 return NULL;
2510
2511 /* coherent mode by default */
2512 dig->coherent_mode = true;
2513 dig->dig_encoder = -1;
2514
2515 if (encoder_enum == 2)
2516 dig->linkb = true;
2517 else
2518 dig->linkb = false;
2519
2520 return dig;
2521}
2522
2523void
2524radeon_add_atom_encoder(struct drm_device *dev,
2525 uint32_t encoder_enum,
2526 uint32_t supported_device,
2527 u16 caps)
2528{
2529 struct radeon_device *rdev = dev->dev_private;
2530 struct drm_encoder *encoder;
2531 struct radeon_encoder *radeon_encoder;
2532
2533 /* see if we already added it */
2534 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2535 radeon_encoder = to_radeon_encoder(encoder);
2536 if (radeon_encoder->encoder_enum == encoder_enum) {
2537 radeon_encoder->devices |= supported_device;
2538 return;
2539 }
2540
2541 }
2542
2543 /* add a new one */
2544 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2545 if (!radeon_encoder)
2546 return;
2547
2548 encoder = &radeon_encoder->base;
2549 switch (rdev->num_crtc) {
2550 case 1:
2551 encoder->possible_crtcs = 0x1;
2552 break;
2553 case 2:
2554 default:
2555 encoder->possible_crtcs = 0x3;
2556 break;
2557 case 4:
2558 encoder->possible_crtcs = 0xf;
2559 break;
2560 case 6:
2561 encoder->possible_crtcs = 0x3f;
2562 break;
2563 }
2564
2565 radeon_encoder->enc_priv = NULL;
2566
2567 radeon_encoder->encoder_enum = encoder_enum;
2568 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2569 radeon_encoder->devices = supported_device;
2570 radeon_encoder->rmx_type = RMX_OFF;
2571 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2572 radeon_encoder->is_ext_encoder = false;
2573 radeon_encoder->caps = caps;
2574
2575 switch (radeon_encoder->encoder_id) {
2576 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2577 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2579 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2580 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2581 radeon_encoder->rmx_type = RMX_FULL;
2582 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2583 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2584 } else {
2585 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2586 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2587 }
2588 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2589 break;
2590 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2591 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2592 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2593 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2594 break;
2595 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2596 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2597 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2598 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2599 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2600 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2601 break;
2602 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2604 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2605 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2606 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2607 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2608 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2609 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2610 radeon_encoder->rmx_type = RMX_FULL;
2611 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2612 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2613 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2614 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2615 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2616 } else {
2617 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2618 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2619 }
2620 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2621 break;
2622 case ENCODER_OBJECT_ID_SI170B:
2623 case ENCODER_OBJECT_ID_CH7303:
2624 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2625 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2626 case ENCODER_OBJECT_ID_TITFP513:
2627 case ENCODER_OBJECT_ID_VT1623:
2628 case ENCODER_OBJECT_ID_HDMI_SI1930:
2629 case ENCODER_OBJECT_ID_TRAVIS:
2630 case ENCODER_OBJECT_ID_NUTMEG:
2631 /* these are handled by the primary encoders */
2632 radeon_encoder->is_ext_encoder = true;
2633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2634 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2635 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2636 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2637 else
2638 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2639 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2640 break;
2641 }
2642}
Linux 6.x block layer and io_uring tree(s)