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drm/radeon/kms: make atombios_dig_encoder_setup() version based
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_encoders.c
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3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38
39static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40{
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54 return true;
55 default:
56 return false;
57 }
58}
59
60static struct drm_connector *
61radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
62{
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
67
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
71 return connector;
72 }
73 return NULL;
74}
75
76static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
79{
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct drm_device *dev = encoder->dev;
82 struct radeon_device *rdev = dev->dev_private;
83
84 /* set the active encoder to connector routing */
85 radeon_encoder_set_active_device(encoder);
86 drm_mode_set_crtcinfo(adjusted_mode, 0);
87
88 /* hw bug */
89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
92
93 /* get the native mode for LVDS */
94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95 radeon_panel_mode_fixup(encoder, adjusted_mode);
96
97 /* get the native mode for TV */
98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
100 if (tv_dac) {
101 if (tv_dac->tv_std == TV_STD_NTSC ||
102 tv_dac->tv_std == TV_STD_NTSC_J ||
103 tv_dac->tv_std == TV_STD_PAL_M)
104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
105 else
106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
107 }
108 }
109
110 if (ASIC_IS_DCE3(rdev) &&
111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114 radeon_dp_set_link_config(connector, mode);
115 }
116
117 return true;
118}
119
120static void
121atombios_dac_setup(struct drm_encoder *encoder, int action)
122{
123 struct drm_device *dev = encoder->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
127 int index = 0;
128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
129
130 memset(&args, 0, sizeof(args));
131
132 switch (radeon_encoder->encoder_id) {
133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
136 break;
137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
140 break;
141 }
142
143 args.ucAction = action;
144
145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146 args.ucDacStandard = ATOM_DAC1_PS2;
147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148 args.ucDacStandard = ATOM_DAC1_CV;
149 else {
150 switch (dac_info->tv_std) {
151 case TV_STD_PAL:
152 case TV_STD_PAL_M:
153 case TV_STD_SCART_PAL:
154 case TV_STD_SECAM:
155 case TV_STD_PAL_CN:
156 args.ucDacStandard = ATOM_DAC1_PAL;
157 break;
158 case TV_STD_NTSC:
159 case TV_STD_NTSC_J:
160 case TV_STD_PAL_60:
161 default:
162 args.ucDacStandard = ATOM_DAC1_NTSC;
163 break;
164 }
165 }
166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
167
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
169
170}
171
172static void
173atombios_tv_setup(struct drm_encoder *encoder, int action)
174{
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 TV_ENCODER_CONTROL_PS_ALLOCATION args;
179 int index = 0;
180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
181
182 memset(&args, 0, sizeof(args));
183
184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
185
186 args.sTVEncoder.ucAction = action;
187
188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
190 else {
191 switch (dac_info->tv_std) {
192 case TV_STD_NTSC:
193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
194 break;
195 case TV_STD_PAL:
196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
197 break;
198 case TV_STD_PAL_M:
199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
200 break;
201 case TV_STD_PAL_60:
202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
203 break;
204 case TV_STD_NTSC_J:
205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
206 break;
207 case TV_STD_SCART_PAL:
208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
209 break;
210 case TV_STD_SECAM:
211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
212 break;
213 case TV_STD_PAL_CN:
214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
215 break;
216 default:
217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
218 break;
219 }
220 }
221
222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
223
224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
225
226}
227
228union dvo_encoder_control {
229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
232};
233
234void
235atombios_dvo_setup(struct drm_encoder *encoder, int action)
236{
237 struct drm_device *dev = encoder->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240 union dvo_encoder_control args;
241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 242 uint8_t frev, crev;
3f03ced8
AD		 243
244 memset(&args, 0, sizeof(args));
245
24153dd3
AD		 246 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
247 return;
248
249 switch (frev) {
250 case 1:
251 switch (crev) {
252 case 1:
253 /* R4xx, R5xx */
254 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
255
256 if (radeon_encoder->pixel_clock > 165000)
257 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
258
259 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
260 break;
261 case 2:
262 /* RS600/690/740 */
263 args.dvo.sDVOEncoder.ucAction = action;
264 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
265 /* DFP1, CRT1, TV1 depending on the type of port */
266 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
267
268 if (radeon_encoder->pixel_clock > 165000)
269 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
270 break;
271 case 3:
272 /* R6xx */
273 args.dvo_v3.ucAction = action;
274 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
275 args.dvo_v3.ucDVOConfig = 0; /* XXX */
276 break;
277 default:
278 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
279 break;
280 }
281 break;
282 default:
283 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
284 break;
3f03ced8
AD		 285 }
286
287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
288}
289
290union lvds_encoder_control {
291 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
292 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
293};
294
295void
296atombios_digital_setup(struct drm_encoder *encoder, int action)
297{
298 struct drm_device *dev = encoder->dev;
299 struct radeon_device *rdev = dev->dev_private;
300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
301 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
302 union lvds_encoder_control args;
303 int index = 0;
304 int hdmi_detected = 0;
305 uint8_t frev, crev;
306
307 if (!dig)
308 return;
309
310 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
311 hdmi_detected = 1;
312
313 memset(&args, 0, sizeof(args));
314
315 switch (radeon_encoder->encoder_id) {
316 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
317 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
318 break;
319 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
321 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
322 break;
323 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
324 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
325 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
326 else
327 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
328 break;
329 }
330
331 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
332 return;
333
334 switch (frev) {
335 case 1:
336 case 2:
337 switch (crev) {
338 case 1:
339 args.v1.ucMisc = 0;
340 args.v1.ucAction = action;
341 if (hdmi_detected)
342 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
343 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
344 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
345 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
346 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
347 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
348 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
349 } else {
350 if (dig->linkb)
351 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
352 if (radeon_encoder->pixel_clock > 165000)
353 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
354 /*if (pScrn->rgbBits == 8) */
355 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
356 }
357 break;
358 case 2:
359 case 3:
360 args.v2.ucMisc = 0;
361 args.v2.ucAction = action;
362 if (crev == 3) {
363 if (dig->coherent_mode)
364 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
365 }
366 if (hdmi_detected)
367 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
368 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
369 args.v2.ucTruncate = 0;
370 args.v2.ucSpatial = 0;
371 args.v2.ucTemporal = 0;
372 args.v2.ucFRC = 0;
373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
374 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
376 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
377 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
378 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
379 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
380 }
381 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
382 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
383 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
384 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
385 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
386 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
387 }
388 } else {
389 if (dig->linkb)
390 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
391 if (radeon_encoder->pixel_clock > 165000)
392 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
393 }
394 break;
395 default:
396 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
397 break;
398 }
399 break;
400 default:
401 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
402 break;
403 }
404
405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406}
407
408int
409atombios_get_encoder_mode(struct drm_encoder *encoder)
410{
411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
412 struct drm_device *dev = encoder->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 struct drm_connector *connector;
415 struct radeon_connector *radeon_connector;
416 struct radeon_connector_atom_dig *dig_connector;
417
418 /* dp bridges are always DP */
419 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
420 return ATOM_ENCODER_MODE_DP;
421
422 /* DVO is always DVO */
423 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
424 return ATOM_ENCODER_MODE_DVO;
425
426 connector = radeon_get_connector_for_encoder(encoder);
427 /* if we don't have an active device yet, just use one of
428 * the connectors tied to the encoder.
429 */
430 if (!connector)
431 connector = radeon_get_connector_for_encoder_init(encoder);
432 radeon_connector = to_radeon_connector(connector);
433
434 switch (connector->connector_type) {
435 case DRM_MODE_CONNECTOR_DVII:
436 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
437 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
438 /* fix me */
439 if (ASIC_IS_DCE4(rdev))
440 return ATOM_ENCODER_MODE_DVI;
441 else
442 return ATOM_ENCODER_MODE_HDMI;
443 } else if (radeon_connector->use_digital)
444 return ATOM_ENCODER_MODE_DVI;
445 else
446 return ATOM_ENCODER_MODE_CRT;
447 break;
448 case DRM_MODE_CONNECTOR_DVID:
449 case DRM_MODE_CONNECTOR_HDMIA:
450 default:
451 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
452 /* fix me */
453 if (ASIC_IS_DCE4(rdev))
454 return ATOM_ENCODER_MODE_DVI;
455 else
456 return ATOM_ENCODER_MODE_HDMI;
457 } else
458 return ATOM_ENCODER_MODE_DVI;
459 break;
460 case DRM_MODE_CONNECTOR_LVDS:
461 return ATOM_ENCODER_MODE_LVDS;
462 break;
463 case DRM_MODE_CONNECTOR_DisplayPort:
464 dig_connector = radeon_connector->con_priv;
465 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
466 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
467 return ATOM_ENCODER_MODE_DP;
468 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
469 /* fix me */
470 if (ASIC_IS_DCE4(rdev))
471 return ATOM_ENCODER_MODE_DVI;
472 else
473 return ATOM_ENCODER_MODE_HDMI;
474 } else
475 return ATOM_ENCODER_MODE_DVI;
476 break;
477 case DRM_MODE_CONNECTOR_eDP:
478 return ATOM_ENCODER_MODE_DP;
479 case DRM_MODE_CONNECTOR_DVIA:
480 case DRM_MODE_CONNECTOR_VGA:
481 return ATOM_ENCODER_MODE_CRT;
482 break;
483 case DRM_MODE_CONNECTOR_Composite:
484 case DRM_MODE_CONNECTOR_SVIDEO:
485 case DRM_MODE_CONNECTOR_9PinDIN:
486 /* fix me */
487 return ATOM_ENCODER_MODE_TV;
488 /*return ATOM_ENCODER_MODE_CV;*/
489 break;
490 }
491}
492
493/*
494 * DIG Encoder/Transmitter Setup
495 *
496 * DCE 3.0/3.1
497 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
498 * Supports up to 3 digital outputs
499 * - 2 DIG encoder blocks.
500 * DIG1 can drive UNIPHY link A or link B
501 * DIG2 can drive UNIPHY link B or LVTMA
502 *
503 * DCE 3.2
504 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
505 * Supports up to 5 digital outputs
506 * - 2 DIG encoder blocks.
507 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
508 *
509 * DCE 4.0/5.0
510 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
511 * Supports up to 6 digital outputs
512 * - 6 DIG encoder blocks.
513 * - DIG to PHY mapping is hardcoded
514 * DIG1 drives UNIPHY0 link A, A+B
515 * DIG2 drives UNIPHY0 link B
516 * DIG3 drives UNIPHY1 link A, A+B
517 * DIG4 drives UNIPHY1 link B
518 * DIG5 drives UNIPHY2 link A, A+B
519 * DIG6 drives UNIPHY2 link B
520 *
521 * DCE 4.1
522 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
523 * Supports up to 6 digital outputs
524 * - 2 DIG encoder blocks.
525 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
526 *
527 * Routing
528 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
529 * Examples:
530 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
531 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
532 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
533 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
534 */
535
536union dig_encoder_control {
537 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
538 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
539 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
540 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
541};
542
543void
544atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
545{
546 struct drm_device *dev = encoder->dev;
547 struct radeon_device *rdev = dev->dev_private;
548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
549 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
550 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
551 union dig_encoder_control args;
552 int index = 0;
553 uint8_t frev, crev;
554 int dp_clock = 0;
555 int dp_lane_count = 0;
556 int hpd_id = RADEON_HPD_NONE;
557 int bpc = 8;
558
559 if (connector) {
560 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
561 struct radeon_connector_atom_dig *dig_connector =
562 radeon_connector->con_priv;
563
564 dp_clock = dig_connector->dp_clock;
565 dp_lane_count = dig_connector->dp_lane_count;
566 hpd_id = radeon_connector->hpd.hpd;
567 bpc = connector->display_info.bpc;
568 }
569
570 /* no dig encoder assigned */
571 if (dig->dig_encoder == -1)
572 return;
573
574 memset(&args, 0, sizeof(args));
575
576 if (ASIC_IS_DCE4(rdev))
577 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
578 else {
579 if (dig->dig_encoder)
580 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
581 else
582 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
583 }
584
585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
586 return;
587
58cdcb8b
AD		 588 switch (frev) {
589 case 1:
590 switch (crev) {
591 case 1:
592 args.v1.ucAction = action;
593 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
594 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
595 args.v3.ucPanelMode = panel_mode;
596 else
597 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
598
599 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
600 args.v1.ucLaneNum = dp_lane_count;
601 else if (radeon_encoder->pixel_clock > 165000)
602 args.v1.ucLaneNum = 8;
603 else
604 args.v1.ucLaneNum = 4;
605
606 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
607 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
608 switch (radeon_encoder->encoder_id) {
609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
610 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
611 break;
612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
614 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
615 break;
616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
617 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
618 break;
619 }
620 if (dig->linkb)
621 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
622 else
623 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 624 break;
58cdcb8b
AD		 625 case 2:
626 case 3:
627 args.v3.ucAction = action;
628 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
629 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
630 args.v3.ucPanelMode = panel_mode;
631 else
632 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
633
634 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
635 args.v3.ucLaneNum = dp_lane_count;
636 else if (radeon_encoder->pixel_clock > 165000)
637 args.v3.ucLaneNum = 8;
638 else
639 args.v3.ucLaneNum = 4;
640
641 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
642 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
643 args.v3.acConfig.ucDigSel = dig->dig_encoder;
644 switch (bpc) {
645 case 0:
646 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
647 break;
648 case 6:
649 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
650 break;
651 case 8:
652 default:
653 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
654 break;
655 case 10:
656 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
657 break;
658 case 12:
659 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
660 break;
661 case 16:
662 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
663 break;
664 }
3f03ced8 665 break;
58cdcb8b
AD		 666 case 4:
667 args.v4.ucAction = action;
668 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
669 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
670 args.v4.ucPanelMode = panel_mode;
671 else
672 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
673
674 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
675 args.v4.ucLaneNum = dp_lane_count;
676 else if (radeon_encoder->pixel_clock > 165000)
677 args.v4.ucLaneNum = 8;
678 else
679 args.v4.ucLaneNum = 4;
680
681 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
682 if (dp_clock == 270000)
683 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
684 else if (dp_clock == 540000)
685 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
686 }
687 args.v4.acConfig.ucDigSel = dig->dig_encoder;
688 switch (bpc) {
689 case 0:
690 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
691 break;
692 case 6:
693 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
694 break;
695 case 8:
696 default:
697 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
698 break;
699 case 10:
700 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
701 break;
702 case 12:
703 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
704 break;
705 case 16:
706 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
707 break;
708 }
709 if (hpd_id == RADEON_HPD_NONE)
710 args.v4.ucHPD_ID = 0;
711 else
712 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 713 break;
3f03ced8 714 default:
58cdcb8b 715 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 716 break;
717 }
58cdcb8b
AD		 718 break;
719 default:
720 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
721 break;
3f03ced8
AD		 722 }
723
724 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
725
726}
727
728union dig_transmitter_control {
729 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
730 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
731 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
732 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
733};
734
735void
736atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
737{
738 struct drm_device *dev = encoder->dev;
739 struct radeon_device *rdev = dev->dev_private;
740 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
741 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
742 struct drm_connector *connector;
743 union dig_transmitter_control args;
744 int index = 0;
745 uint8_t frev, crev;
746 bool is_dp = false;
747 int pll_id = 0;
748 int dp_clock = 0;
749 int dp_lane_count = 0;
750 int connector_object_id = 0;
751 int igp_lane_info = 0;
752 int dig_encoder = dig->dig_encoder;
753
754 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
755 connector = radeon_get_connector_for_encoder_init(encoder);
756 /* just needed to avoid bailing in the encoder check. the encoder
757 * isn't used for init
758 */
759 dig_encoder = 0;
760 } else
761 connector = radeon_get_connector_for_encoder(encoder);
762
763 if (connector) {
764 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
765 struct radeon_connector_atom_dig *dig_connector =
766 radeon_connector->con_priv;
767
768 dp_clock = dig_connector->dp_clock;
769 dp_lane_count = dig_connector->dp_lane_count;
770 connector_object_id =
771 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
772 igp_lane_info = dig_connector->igp_lane_info;
773 }
774
775 /* no dig encoder assigned */
776 if (dig_encoder == -1)
777 return;
778
779 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
780 is_dp = true;
781
782 memset(&args, 0, sizeof(args));
783
784 switch (radeon_encoder->encoder_id) {
785 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
786 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
787 break;
788 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
789 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
791 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
792 break;
793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
794 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
795 break;
796 }
797
798 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
799 return;
800
801 args.v1.ucAction = action;
802 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
803 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
804 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
805 args.v1.asMode.ucLaneSel = lane_num;
806 args.v1.asMode.ucLaneSet = lane_set;
807 } else {
808 if (is_dp)
809 args.v1.usPixelClock =
810 cpu_to_le16(dp_clock / 10);
811 else if (radeon_encoder->pixel_clock > 165000)
812 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
813 else
814 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
815 }
816 if (ASIC_IS_DCE4(rdev)) {
817 if (is_dp)
818 args.v3.ucLaneNum = dp_lane_count;
819 else if (radeon_encoder->pixel_clock > 165000)
820 args.v3.ucLaneNum = 8;
821 else
822 args.v3.ucLaneNum = 4;
823
824 if (dig->linkb)
825 args.v3.acConfig.ucLinkSel = 1;
826 if (dig_encoder & 1)
827 args.v3.acConfig.ucEncoderSel = 1;
828
829 /* Select the PLL for the PHY
830 * DP PHY should be clocked from external src if there is
831 * one.
832 */
833 if (encoder->crtc) {
834 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
835 pll_id = radeon_crtc->pll_id;
836 }
837
838 if (ASIC_IS_DCE5(rdev)) {
839 /* On DCE5 DCPLL usually generates the DP ref clock */
840 if (is_dp) {
841 if (rdev->clock.dp_extclk)
842 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
843 else
844 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
845 } else
846 args.v4.acConfig.ucRefClkSource = pll_id;
847 } else {
848 /* On DCE4, if there is an external clock, it generates the DP ref clock */
849 if (is_dp && rdev->clock.dp_extclk)
850 args.v3.acConfig.ucRefClkSource = 2; /* external src */
851 else
852 args.v3.acConfig.ucRefClkSource = pll_id;
853 }
854
855 switch (radeon_encoder->encoder_id) {
856 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
857 args.v3.acConfig.ucTransmitterSel = 0;
858 break;
859 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
860 args.v3.acConfig.ucTransmitterSel = 1;
861 break;
862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
863 args.v3.acConfig.ucTransmitterSel = 2;
864 break;
865 }
866
867 if (is_dp)
868 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
869 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
870 if (dig->coherent_mode)
871 args.v3.acConfig.fCoherentMode = 1;
872 if (radeon_encoder->pixel_clock > 165000)
873 args.v3.acConfig.fDualLinkConnector = 1;
874 }
875 } else if (ASIC_IS_DCE32(rdev)) {
876 args.v2.acConfig.ucEncoderSel = dig_encoder;
877 if (dig->linkb)
878 args.v2.acConfig.ucLinkSel = 1;
879
880 switch (radeon_encoder->encoder_id) {
881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
882 args.v2.acConfig.ucTransmitterSel = 0;
883 break;
884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
885 args.v2.acConfig.ucTransmitterSel = 1;
886 break;
887 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
888 args.v2.acConfig.ucTransmitterSel = 2;
889 break;
890 }
891
892 if (is_dp) {
893 args.v2.acConfig.fCoherentMode = 1;
894 args.v2.acConfig.fDPConnector = 1;
895 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
896 if (dig->coherent_mode)
897 args.v2.acConfig.fCoherentMode = 1;
898 if (radeon_encoder->pixel_clock > 165000)
899 args.v2.acConfig.fDualLinkConnector = 1;
900 }
901 } else {
902 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
903
904 if (dig_encoder)
905 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
906 else
907 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
908
909 if ((rdev->flags & RADEON_IS_IGP) &&
910 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
911 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
912 if (igp_lane_info & 0x1)
913 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
914 else if (igp_lane_info & 0x2)
915 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
916 else if (igp_lane_info & 0x4)
917 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
918 else if (igp_lane_info & 0x8)
919 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
920 } else {
921 if (igp_lane_info & 0x3)
922 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
923 else if (igp_lane_info & 0xc)
924 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
925 }
926 }
927
928 if (dig->linkb)
929 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
930 else
931 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
932
933 if (is_dp)
934 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
935 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
936 if (dig->coherent_mode)
937 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
938 if (radeon_encoder->pixel_clock > 165000)
939 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
940 }
941 }
942
943 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
944}
945
946bool
947atombios_set_edp_panel_power(struct drm_connector *connector, int action)
948{
949 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
950 struct drm_device *dev = radeon_connector->base.dev;
951 struct radeon_device *rdev = dev->dev_private;
952 union dig_transmitter_control args;
953 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
954 uint8_t frev, crev;
955
956 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
957 goto done;
958
959 if (!ASIC_IS_DCE4(rdev))
960 goto done;
961
962 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
963 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
964 goto done;
965
966 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
967 goto done;
968
969 memset(&args, 0, sizeof(args));
970
971 args.v1.ucAction = action;
972
973 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
974
975 /* wait for the panel to power up */
976 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
977 int i;
978
979 for (i = 0; i < 300; i++) {
980 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
981 return true;
982 mdelay(1);
983 }
984 return false;
985 }
986done:
987 return true;
988}
989
990union external_encoder_control {
991 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
992 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
993};
994
995static void
996atombios_external_encoder_setup(struct drm_encoder *encoder,
997 struct drm_encoder *ext_encoder,
998 int action)
999{
1000 struct drm_device *dev = encoder->dev;
1001 struct radeon_device *rdev = dev->dev_private;
1002 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1003 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1004 union external_encoder_control args;
1005 struct drm_connector *connector;
1006 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1007 u8 frev, crev;
1008 int dp_clock = 0;
1009 int dp_lane_count = 0;
1010 int connector_object_id = 0;
1011 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1012 int bpc = 8;
1013
1014 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1015 connector = radeon_get_connector_for_encoder_init(encoder);
1016 else
1017 connector = radeon_get_connector_for_encoder(encoder);
1018
1019 if (connector) {
1020 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1021 struct radeon_connector_atom_dig *dig_connector =
1022 radeon_connector->con_priv;
1023
1024 dp_clock = dig_connector->dp_clock;
1025 dp_lane_count = dig_connector->dp_lane_count;
1026 connector_object_id =
1027 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1028 bpc = connector->display_info.bpc;
1029 }
1030
1031 memset(&args, 0, sizeof(args));
1032
1033 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1034 return;
1035
1036 switch (frev) {
1037 case 1:
1038 /* no params on frev 1 */
1039 break;
1040 case 2:
1041 switch (crev) {
1042 case 1:
1043 case 2:
1044 args.v1.sDigEncoder.ucAction = action;
1045 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1046 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1047
1048 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1049 if (dp_clock == 270000)
1050 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1051 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1052 } else if (radeon_encoder->pixel_clock > 165000)
1053 args.v1.sDigEncoder.ucLaneNum = 8;
1054 else
1055 args.v1.sDigEncoder.ucLaneNum = 4;
1056 break;
1057 case 3:
1058 args.v3.sExtEncoder.ucAction = action;
1059 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1060 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1061 else
1062 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1063 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1064
1065 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1066 if (dp_clock == 270000)
1067 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1068 else if (dp_clock == 540000)
1069 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1070 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1071 } else if (radeon_encoder->pixel_clock > 165000)
1072 args.v3.sExtEncoder.ucLaneNum = 8;
1073 else
1074 args.v3.sExtEncoder.ucLaneNum = 4;
1075 switch (ext_enum) {
1076 case GRAPH_OBJECT_ENUM_ID1:
1077 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1078 break;
1079 case GRAPH_OBJECT_ENUM_ID2:
1080 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1081 break;
1082 case GRAPH_OBJECT_ENUM_ID3:
1083 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1084 break;
1085 }
1086 switch (bpc) {
1087 case 0:
1088 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1089 break;
1090 case 6:
1091 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1092 break;
1093 case 8:
1094 default:
1095 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1096 break;
1097 case 10:
1098 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1099 break;
1100 case 12:
1101 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1102 break;
1103 case 16:
1104 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1105 break;
1106 }
1107 break;
1108 default:
1109 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1110 return;
1111 }
1112 break;
1113 default:
1114 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1115 return;
1116 }
1117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1118}
1119
1120static void
1121atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1122{
1123 struct drm_device *dev = encoder->dev;
1124 struct radeon_device *rdev = dev->dev_private;
1125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1127 ENABLE_YUV_PS_ALLOCATION args;
1128 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1129 uint32_t temp, reg;
1130
1131 memset(&args, 0, sizeof(args));
1132
1133 if (rdev->family >= CHIP_R600)
1134 reg = R600_BIOS_3_SCRATCH;
1135 else
1136 reg = RADEON_BIOS_3_SCRATCH;
1137
1138 /* XXX: fix up scratch reg handling */
1139 temp = RREG32(reg);
1140 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1141 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1142 (radeon_crtc->crtc_id << 18)));
1143 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1144 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1145 else
1146 WREG32(reg, 0);
1147
1148 if (enable)
1149 args.ucEnable = ATOM_ENABLE;
1150 args.ucCRTC = radeon_crtc->crtc_id;
1151
1152 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1153
1154 WREG32(reg, temp);
1155}
1156
1157static void
1158radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1159{
1160 struct drm_device *dev = encoder->dev;
1161 struct radeon_device *rdev = dev->dev_private;
1162 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1163 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1164 int index = 0;
1165
1166 memset(&args, 0, sizeof(args));
1167
1168 switch (radeon_encoder->encoder_id) {
1169 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1170 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1171 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1172 break;
1173 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1174 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1175 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1176 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1177 break;
1178 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1179 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1180 break;
1181 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1182 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1183 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1184 else
1185 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1186 break;
1187 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1188 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1189 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1190 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1191 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1192 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1193 else
1194 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1195 break;
1196 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1198 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1199 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1200 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1201 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1202 else
1203 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1204 break;
1205 default:
1206 return;
1207 }
1208
1209 switch (mode) {
1210 case DRM_MODE_DPMS_ON:
1211 args.ucAction = ATOM_ENABLE;
1212 /* workaround for DVOOutputControl on some RS690 systems */
1213 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1214 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1215 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1216 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1217 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1218 } else
1219 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1220 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1221 args.ucAction = ATOM_LCD_BLON;
1222 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1223 }
1224 break;
1225 case DRM_MODE_DPMS_STANDBY:
1226 case DRM_MODE_DPMS_SUSPEND:
1227 case DRM_MODE_DPMS_OFF:
1228 args.ucAction = ATOM_DISABLE;
1229 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1230 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1231 args.ucAction = ATOM_LCD_BLOFF;
1232 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1233 }
1234 break;
1235 }
1236}
1237
1238static void
1239radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1240{
1241 struct drm_device *dev = encoder->dev;
1242 struct radeon_device *rdev = dev->dev_private;
1243 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1244 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1245 struct radeon_connector *radeon_connector = NULL;
1246 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1247
1248 if (connector) {
1249 radeon_connector = to_radeon_connector(connector);
1250 radeon_dig_connector = radeon_connector->con_priv;
1251 }
1252
1253 switch (mode) {
1254 case DRM_MODE_DPMS_ON:
1255 /* some early dce3.2 boards have a bug in their transmitter control table */
1256 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1257 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1258 else
1259 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1260 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1261 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1262 atombios_set_edp_panel_power(connector,
1263 ATOM_TRANSMITTER_ACTION_POWER_ON);
1264 radeon_dig_connector->edp_on = true;
1265 }
1266 if (ASIC_IS_DCE4(rdev))
1267 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1268 radeon_dp_link_train(encoder, connector);
1269 if (ASIC_IS_DCE4(rdev))
1270 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1271 }
1272 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1273 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1274 break;
1275 case DRM_MODE_DPMS_STANDBY:
1276 case DRM_MODE_DPMS_SUSPEND:
1277 case DRM_MODE_DPMS_OFF:
1278 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1279 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1280 if (ASIC_IS_DCE4(rdev))
1281 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1282 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1283 atombios_set_edp_panel_power(connector,
1284 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1285 radeon_dig_connector->edp_on = false;
1286 }
1287 }
1288 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1289 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1290 break;
1291 }
1292}
1293
1294static void
1295radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1296 struct drm_encoder *ext_encoder,
1297 int mode)
1298{
1299 struct drm_device *dev = encoder->dev;
1300 struct radeon_device *rdev = dev->dev_private;
1301
1302 switch (mode) {
1303 case DRM_MODE_DPMS_ON:
1304 default:
1305 if (ASIC_IS_DCE41(rdev)) {
1306 atombios_external_encoder_setup(encoder, ext_encoder,
1307 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1308 atombios_external_encoder_setup(encoder, ext_encoder,
1309 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1310 } else
1311 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1312 break;
1313 case DRM_MODE_DPMS_STANDBY:
1314 case DRM_MODE_DPMS_SUSPEND:
1315 case DRM_MODE_DPMS_OFF:
1316 if (ASIC_IS_DCE41(rdev)) {
1317 atombios_external_encoder_setup(encoder, ext_encoder,
1318 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1319 atombios_external_encoder_setup(encoder, ext_encoder,
1320 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1321 } else
1322 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1323 break;
1324 }
1325}
1326
1327static void
1328radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1329{
1330 struct drm_device *dev = encoder->dev;
1331 struct radeon_device *rdev = dev->dev_private;
1332 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1333 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1334
1335 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1336 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1337 radeon_encoder->active_device);
1338 switch (radeon_encoder->encoder_id) {
1339 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1340 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1341 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1342 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1343 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1344 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1345 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1346 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1347 radeon_atom_encoder_dpms_avivo(encoder, mode);
1348 break;
1349 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1350 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1352 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1353 radeon_atom_encoder_dpms_dig(encoder, mode);
1354 break;
1355 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1356 if (ASIC_IS_DCE5(rdev)) {
1357 switch (mode) {
1358 case DRM_MODE_DPMS_ON:
1359 atombios_dvo_setup(encoder, ATOM_ENABLE);
1360 break;
1361 case DRM_MODE_DPMS_STANDBY:
1362 case DRM_MODE_DPMS_SUSPEND:
1363 case DRM_MODE_DPMS_OFF:
1364 atombios_dvo_setup(encoder, ATOM_DISABLE);
1365 break;
1366 }
1367 } else if (ASIC_IS_DCE3(rdev))
1368 radeon_atom_encoder_dpms_dig(encoder, mode);
1369 else
1370 radeon_atom_encoder_dpms_avivo(encoder, mode);
1371 break;
1372 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1373 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1374 if (ASIC_IS_DCE5(rdev)) {
1375 switch (mode) {
1376 case DRM_MODE_DPMS_ON:
1377 atombios_dac_setup(encoder, ATOM_ENABLE);
1378 break;
1379 case DRM_MODE_DPMS_STANDBY:
1380 case DRM_MODE_DPMS_SUSPEND:
1381 case DRM_MODE_DPMS_OFF:
1382 atombios_dac_setup(encoder, ATOM_DISABLE);
1383 break;
1384 }
1385 } else
1386 radeon_atom_encoder_dpms_avivo(encoder, mode);
1387 break;
1388 default:
1389 return;
1390 }
1391
1392 if (ext_encoder)
1393 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1394
1395 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1396
1397}
1398
1399union crtc_source_param {
1400 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1401 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1402};
1403
1404static void
1405atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1406{
1407 struct drm_device *dev = encoder->dev;
1408 struct radeon_device *rdev = dev->dev_private;
1409 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1410 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1411 union crtc_source_param args;
1412 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1413 uint8_t frev, crev;
1414 struct radeon_encoder_atom_dig *dig;
1415
1416 memset(&args, 0, sizeof(args));
1417
1418 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1419 return;
1420
1421 switch (frev) {
1422 case 1:
1423 switch (crev) {
1424 case 1:
1425 default:
1426 if (ASIC_IS_AVIVO(rdev))
1427 args.v1.ucCRTC = radeon_crtc->crtc_id;
1428 else {
1429 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1430 args.v1.ucCRTC = radeon_crtc->crtc_id;
1431 } else {
1432 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1433 }
1434 }
1435 switch (radeon_encoder->encoder_id) {
1436 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1437 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1438 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1439 break;
1440 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1441 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1442 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1443 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1444 else
1445 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1446 break;
1447 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1448 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1449 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1450 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1451 break;
1452 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1454 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1455 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1456 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1457 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1458 else
1459 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1460 break;
1461 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1462 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1463 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1464 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1465 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1466 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1467 else
1468 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1469 break;
1470 }
1471 break;
1472 case 2:
1473 args.v2.ucCRTC = radeon_crtc->crtc_id;
1474 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1475 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1476
1477 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1478 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1479 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1480 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1481 else
1482 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1483 } else
1484 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1485 switch (radeon_encoder->encoder_id) {
1486 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1487 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1488 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1489 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1490 dig = radeon_encoder->enc_priv;
1491 switch (dig->dig_encoder) {
1492 case 0:
1493 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1494 break;
1495 case 1:
1496 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1497 break;
1498 case 2:
1499 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1500 break;
1501 case 3:
1502 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1503 break;
1504 case 4:
1505 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1506 break;
1507 case 5:
1508 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1509 break;
1510 }
1511 break;
1512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1513 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1514 break;
1515 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1516 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1517 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1518 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1519 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1520 else
1521 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1522 break;
1523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1524 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1525 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1526 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1527 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1528 else
1529 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1530 break;
1531 }
1532 break;
1533 }
1534 break;
1535 default:
1536 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1537 return;
1538 }
1539
1540 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1541
1542 /* update scratch regs with new routing */
1543 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1544}
1545
1546static void
1547atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1548 struct drm_display_mode *mode)
1549{
1550 struct drm_device *dev = encoder->dev;
1551 struct radeon_device *rdev = dev->dev_private;
1552 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1553 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1554
1555 /* Funky macbooks */
1556 if ((dev->pdev->device == 0x71C5) &&
1557 (dev->pdev->subsystem_vendor == 0x106b) &&
1558 (dev->pdev->subsystem_device == 0x0080)) {
1559 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1560 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1561
1562 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1563 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1564
1565 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1566 }
1567 }
1568
1569 /* set scaler clears this on some chips */
1570 if (ASIC_IS_AVIVO(rdev) &&
1571 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1572 if (ASIC_IS_DCE4(rdev)) {
1573 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1574 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1575 EVERGREEN_INTERLEAVE_EN);
1576 else
1577 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1578 } else {
1579 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1580 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1581 AVIVO_D1MODE_INTERLEAVE_EN);
1582 else
1583 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1584 }
1585 }
1586}
1587
1588static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1589{
1590 struct drm_device *dev = encoder->dev;
1591 struct radeon_device *rdev = dev->dev_private;
1592 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1593 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1594 struct drm_encoder *test_encoder;
1595 struct radeon_encoder_atom_dig *dig;
1596 uint32_t dig_enc_in_use = 0;
1597
1598 /* DCE4/5 */
1599 if (ASIC_IS_DCE4(rdev)) {
1600 dig = radeon_encoder->enc_priv;
1601 if (ASIC_IS_DCE41(rdev)) {
1602 /* ontario follows DCE4 */
1603 if (rdev->family == CHIP_PALM) {
1604 if (dig->linkb)
1605 return 1;
1606 else
1607 return 0;
1608 } else
1609 /* llano follows DCE3.2 */
1610 return radeon_crtc->crtc_id;
1611 } else {
1612 switch (radeon_encoder->encoder_id) {
1613 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1614 if (dig->linkb)
1615 return 1;
1616 else
1617 return 0;
1618 break;
1619 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1620 if (dig->linkb)
1621 return 3;
1622 else
1623 return 2;
1624 break;
1625 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1626 if (dig->linkb)
1627 return 5;
1628 else
1629 return 4;
1630 break;
1631 }
1632 }
1633 }
1634
1635 /* on DCE32 and encoder can driver any block so just crtc id */
1636 if (ASIC_IS_DCE32(rdev)) {
1637 return radeon_crtc->crtc_id;
1638 }
1639
1640 /* on DCE3 - LVTMA can only be driven by DIGB */
1641 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1642 struct radeon_encoder *radeon_test_encoder;
1643
1644 if (encoder == test_encoder)
1645 continue;
1646
1647 if (!radeon_encoder_is_digital(test_encoder))
1648 continue;
1649
1650 radeon_test_encoder = to_radeon_encoder(test_encoder);
1651 dig = radeon_test_encoder->enc_priv;
1652
1653 if (dig->dig_encoder >= 0)
1654 dig_enc_in_use |= (1 << dig->dig_encoder);
1655 }
1656
1657 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1658 if (dig_enc_in_use & 0x2)
1659 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1660 return 1;
1661 }
1662 if (!(dig_enc_in_use & 1))
1663 return 0;
1664 return 1;
1665}
1666
1667/* This only needs to be called once at startup */
1668void
1669radeon_atom_encoder_init(struct radeon_device *rdev)
1670{
1671 struct drm_device *dev = rdev->ddev;
1672 struct drm_encoder *encoder;
1673
1674 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1675 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1676 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1677
1678 switch (radeon_encoder->encoder_id) {
1679 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1680 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1681 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1682 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1683 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1684 break;
1685 default:
1686 break;
1687 }
1688
1689 if (ext_encoder && ASIC_IS_DCE41(rdev))
1690 atombios_external_encoder_setup(encoder, ext_encoder,
1691 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1692 }
1693}
1694
1695static void
1696radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1697 struct drm_display_mode *mode,
1698 struct drm_display_mode *adjusted_mode)
1699{
1700 struct drm_device *dev = encoder->dev;
1701 struct radeon_device *rdev = dev->dev_private;
1702 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1703 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1704
1705 radeon_encoder->pixel_clock = adjusted_mode->clock;
1706
1707 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1708 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1709 atombios_yuv_setup(encoder, true);
1710 else
1711 atombios_yuv_setup(encoder, false);
1712 }
1713
1714 switch (radeon_encoder->encoder_id) {
1715 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1716 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1717 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1718 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1719 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1720 break;
1721 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1722 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1723 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1724 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1725 if (ASIC_IS_DCE4(rdev)) {
1726 /* disable the transmitter */
1727 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1728 /* setup and enable the encoder */
1729 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1730
1731 /* enable the transmitter */
1732 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1733 } else {
1734 /* disable the encoder and transmitter */
1735 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1736 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1737
1738 /* setup and enable the encoder and transmitter */
1739 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1740 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1741 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1742 }
1743 break;
1744 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1745 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1746 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1747 atombios_dvo_setup(encoder, ATOM_ENABLE);
1748 break;
1749 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1750 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1751 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1752 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1753 atombios_dac_setup(encoder, ATOM_ENABLE);
1754 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1755 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1756 atombios_tv_setup(encoder, ATOM_ENABLE);
1757 else
1758 atombios_tv_setup(encoder, ATOM_DISABLE);
1759 }
1760 break;
1761 }
1762
1763 if (ext_encoder) {
1764 if (ASIC_IS_DCE41(rdev))
1765 atombios_external_encoder_setup(encoder, ext_encoder,
1766 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1767 else
1768 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1769 }
1770
1771 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1772
1773 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1774 r600_hdmi_enable(encoder);
1775 r600_hdmi_setmode(encoder, adjusted_mode);
1776 }
1777}
1778
1779static bool
1780atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1781{
1782 struct drm_device *dev = encoder->dev;
1783 struct radeon_device *rdev = dev->dev_private;
1784 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1785 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1786
1787 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1788 ATOM_DEVICE_CV_SUPPORT |
1789 ATOM_DEVICE_CRT_SUPPORT)) {
1790 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1791 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1792 uint8_t frev, crev;
1793
1794 memset(&args, 0, sizeof(args));
1795
1796 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1797 return false;
1798
1799 args.sDacload.ucMisc = 0;
1800
1801 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1802 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1803 args.sDacload.ucDacType = ATOM_DAC_A;
1804 else
1805 args.sDacload.ucDacType = ATOM_DAC_B;
1806
1807 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1808 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1809 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1810 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1811 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1812 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1813 if (crev >= 3)
1814 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1815 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1816 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1817 if (crev >= 3)
1818 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1819 }
1820
1821 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1822
1823 return true;
1824 } else
1825 return false;
1826}
1827
1828static enum drm_connector_status
1829radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1830{
1831 struct drm_device *dev = encoder->dev;
1832 struct radeon_device *rdev = dev->dev_private;
1833 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1834 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1835 uint32_t bios_0_scratch;
1836
1837 if (!atombios_dac_load_detect(encoder, connector)) {
1838 DRM_DEBUG_KMS("detect returned false \n");
1839 return connector_status_unknown;
1840 }
1841
1842 if (rdev->family >= CHIP_R600)
1843 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1844 else
1845 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1846
1847 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1848 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1849 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1850 return connector_status_connected;
1851 }
1852 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1853 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1854 return connector_status_connected;
1855 }
1856 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1857 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1858 return connector_status_connected;
1859 }
1860 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1861 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1862 return connector_status_connected; /* CTV */
1863 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1864 return connector_status_connected; /* STV */
1865 }
1866 return connector_status_disconnected;
1867}
1868
1869static enum drm_connector_status
1870radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1871{
1872 struct drm_device *dev = encoder->dev;
1873 struct radeon_device *rdev = dev->dev_private;
1874 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1875 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1876 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1877 u32 bios_0_scratch;
1878
1879 if (!ASIC_IS_DCE4(rdev))
1880 return connector_status_unknown;
1881
1882 if (!ext_encoder)
1883 return connector_status_unknown;
1884
1885 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1886 return connector_status_unknown;
1887
1888 /* load detect on the dp bridge */
1889 atombios_external_encoder_setup(encoder, ext_encoder,
1890 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1891
1892 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1893
1894 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1895 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1896 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1897 return connector_status_connected;
1898 }
1899 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1900 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1901 return connector_status_connected;
1902 }
1903 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1904 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1905 return connector_status_connected;
1906 }
1907 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1908 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1909 return connector_status_connected; /* CTV */
1910 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1911 return connector_status_connected; /* STV */
1912 }
1913 return connector_status_disconnected;
1914}
1915
1916void
1917radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
1918{
1919 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1920
1921 if (ext_encoder)
1922 /* ddc_setup on the dp bridge */
1923 atombios_external_encoder_setup(encoder, ext_encoder,
1924 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
1925
1926}
1927
1928static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1929{
1930 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1931 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1932
1933 if ((radeon_encoder->active_device &
1934 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
1935 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
1936 ENCODER_OBJECT_ID_NONE)) {
1937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1938 if (dig)
1939 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1940 }
1941
1942 radeon_atom_output_lock(encoder, true);
1943 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1944
1945 if (connector) {
1946 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1947
1948 /* select the clock/data port if it uses a router */
1949 if (radeon_connector->router.cd_valid)
1950 radeon_router_select_cd_port(radeon_connector);
1951
1952 /* turn eDP panel on for mode set */
1953 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1954 atombios_set_edp_panel_power(connector,
1955 ATOM_TRANSMITTER_ACTION_POWER_ON);
1956 }
1957
1958 /* this is needed for the pll/ss setup to work correctly in some cases */
1959 atombios_set_encoder_crtc_source(encoder);
1960}
1961
1962static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1963{
1964 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1965 radeon_atom_output_lock(encoder, false);
1966}
1967
1968static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1969{
1970 struct drm_device *dev = encoder->dev;
1971 struct radeon_device *rdev = dev->dev_private;
1972 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1973 struct radeon_encoder_atom_dig *dig;
1974
1975 /* check for pre-DCE3 cards with shared encoders;
1976 * can't really use the links individually, so don't disable
1977 * the encoder if it's in use by another connector
1978 */
1979 if (!ASIC_IS_DCE3(rdev)) {
1980 struct drm_encoder *other_encoder;
1981 struct radeon_encoder *other_radeon_encoder;
1982
1983 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1984 other_radeon_encoder = to_radeon_encoder(other_encoder);
1985 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1986 drm_helper_encoder_in_use(other_encoder))
1987 goto disable_done;
1988 }
1989 }
1990
1991 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1992
1993 switch (radeon_encoder->encoder_id) {
1994 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1995 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1996 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1997 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1998 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1999 break;
2000 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2001 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2002 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2003 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2004 if (ASIC_IS_DCE4(rdev))
2005 /* disable the transmitter */
2006 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2007 else {
2008 /* disable the encoder and transmitter */
2009 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2010 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2011 }
2012 break;
2013 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2014 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2015 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2016 atombios_dvo_setup(encoder, ATOM_DISABLE);
2017 break;
2018 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2019 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2020 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2021 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2022 atombios_dac_setup(encoder, ATOM_DISABLE);
2023 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2024 atombios_tv_setup(encoder, ATOM_DISABLE);
2025 break;
2026 }
2027
2028disable_done:
2029 if (radeon_encoder_is_digital(encoder)) {
2030 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2031 r600_hdmi_disable(encoder);
2032 dig = radeon_encoder->enc_priv;
2033 dig->dig_encoder = -1;
2034 }
2035 radeon_encoder->active_device = 0;
2036}
2037
2038/* these are handled by the primary encoders */
2039static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2040{
2041
2042}
2043
2044static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2045{
2046
2047}
2048
2049static void
2050radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2051 struct drm_display_mode *mode,
2052 struct drm_display_mode *adjusted_mode)
2053{
2054
2055}
2056
2057static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2058{
2059
2060}
2061
2062static void
2063radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2064{
2065
2066}
2067
2068static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2069 struct drm_display_mode *mode,
2070 struct drm_display_mode *adjusted_mode)
2071{
2072 return true;
2073}
2074
2075static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2076 .dpms = radeon_atom_ext_dpms,
2077 .mode_fixup = radeon_atom_ext_mode_fixup,
2078 .prepare = radeon_atom_ext_prepare,
2079 .mode_set = radeon_atom_ext_mode_set,
2080 .commit = radeon_atom_ext_commit,
2081 .disable = radeon_atom_ext_disable,
2082 /* no detect for TMDS/LVDS yet */
2083};
2084
2085static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2086 .dpms = radeon_atom_encoder_dpms,
2087 .mode_fixup = radeon_atom_mode_fixup,
2088 .prepare = radeon_atom_encoder_prepare,
2089 .mode_set = radeon_atom_encoder_mode_set,
2090 .commit = radeon_atom_encoder_commit,
2091 .disable = radeon_atom_encoder_disable,
2092 .detect = radeon_atom_dig_detect,
2093};
2094
2095static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2096 .dpms = radeon_atom_encoder_dpms,
2097 .mode_fixup = radeon_atom_mode_fixup,
2098 .prepare = radeon_atom_encoder_prepare,
2099 .mode_set = radeon_atom_encoder_mode_set,
2100 .commit = radeon_atom_encoder_commit,
2101 .detect = radeon_atom_dac_detect,
2102};
2103
2104void radeon_enc_destroy(struct drm_encoder *encoder)
2105{
2106 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2107 kfree(radeon_encoder->enc_priv);
2108 drm_encoder_cleanup(encoder);
2109 kfree(radeon_encoder);
2110}
2111
2112static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2113 .destroy = radeon_enc_destroy,
2114};
2115
2116struct radeon_encoder_atom_dac *
2117radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2118{
2119 struct drm_device *dev = radeon_encoder->base.dev;
2120 struct radeon_device *rdev = dev->dev_private;
2121 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2122
2123 if (!dac)
2124 return NULL;
2125
2126 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2127 return dac;
2128}
2129
2130struct radeon_encoder_atom_dig *
2131radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2132{
2133 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2134 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2135
2136 if (!dig)
2137 return NULL;
2138
2139 /* coherent mode by default */
2140 dig->coherent_mode = true;
2141 dig->dig_encoder = -1;
2142
2143 if (encoder_enum == 2)
2144 dig->linkb = true;
2145 else
2146 dig->linkb = false;
2147
2148 return dig;
2149}
2150
2151void
2152radeon_add_atom_encoder(struct drm_device *dev,
2153 uint32_t encoder_enum,
2154 uint32_t supported_device,
2155 u16 caps)
2156{
2157 struct radeon_device *rdev = dev->dev_private;
2158 struct drm_encoder *encoder;
2159 struct radeon_encoder *radeon_encoder;
2160
2161 /* see if we already added it */
2162 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2163 radeon_encoder = to_radeon_encoder(encoder);
2164 if (radeon_encoder->encoder_enum == encoder_enum) {
2165 radeon_encoder->devices |= supported_device;
2166 return;
2167 }
2168
2169 }
2170
2171 /* add a new one */
2172 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2173 if (!radeon_encoder)
2174 return;
2175
2176 encoder = &radeon_encoder->base;
2177 switch (rdev->num_crtc) {
2178 case 1:
2179 encoder->possible_crtcs = 0x1;
2180 break;
2181 case 2:
2182 default:
2183 encoder->possible_crtcs = 0x3;
2184 break;
2185 case 4:
2186 encoder->possible_crtcs = 0xf;
2187 break;
2188 case 6:
2189 encoder->possible_crtcs = 0x3f;
2190 break;
2191 }
2192
2193 radeon_encoder->enc_priv = NULL;
2194
2195 radeon_encoder->encoder_enum = encoder_enum;
2196 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2197 radeon_encoder->devices = supported_device;
2198 radeon_encoder->rmx_type = RMX_OFF;
2199 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2200 radeon_encoder->is_ext_encoder = false;
2201 radeon_encoder->caps = caps;
2202
2203 switch (radeon_encoder->encoder_id) {
2204 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2205 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2206 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2207 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2208 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2209 radeon_encoder->rmx_type = RMX_FULL;
2210 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2211 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2212 } else {
2213 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2214 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2215 }
2216 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2217 break;
2218 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2219 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2220 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2221 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2222 break;
2223 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2224 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2225 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2226 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2227 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2228 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2229 break;
2230 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2231 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2232 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2234 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2236 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2237 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2238 radeon_encoder->rmx_type = RMX_FULL;
2239 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2240 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2241 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2242 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2243 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2244 } else {
2245 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2246 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2247 }
2248 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2249 break;
2250 case ENCODER_OBJECT_ID_SI170B:
2251 case ENCODER_OBJECT_ID_CH7303:
2252 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2253 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2254 case ENCODER_OBJECT_ID_TITFP513:
2255 case ENCODER_OBJECT_ID_VT1623:
2256 case ENCODER_OBJECT_ID_HDMI_SI1930:
2257 case ENCODER_OBJECT_ID_TRAVIS:
2258 case ENCODER_OBJECT_ID_NUTMEG:
2259 /* these are handled by the primary encoders */
2260 radeon_encoder->is_ext_encoder = true;
2261 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2262 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2263 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2264 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2265 else
2266 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2267 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2268 break;
2269 }
2270}
Linux 6.x block layer and io_uring tree(s)