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Merge remote branch 'intel/drm-intel-fixes' of /ssd/git/drm-next into drm-fixes
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
4589433c
CC		 64 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 258 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 261 radeon_crtc->enabled = false;
d7311171
AD		 262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 264 break;
265 }
771fe6b9
JG		 266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 270 struct drm_display_mode *mode)
771fe6b9 271{
5a9bcacc 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 277 u16 misc = 0;
771fe6b9 278
5a9bcacc 279 memset(&args, 0, sizeof(args));
5b1714d3 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 281 args.usH_Blanking_Time =
5b1714d3
AD		 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 284 args.usV_Blanking_Time =
5b1714d3 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 286 args.usH_SyncOffset =
5b1714d3 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
5b1714d3 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 310
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
54bfe496
AD		 336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
5a9bcacc
AD		 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a 401union atom_enable_ss {
ba032a58
AD		 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 407};
408
ba032a58
AD		 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
ebbe1cb9 413{
ebbe1cb9
AD		 414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
ebbe1cb9 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 417 union atom_enable_ss args;
ebbe1cb9 418
ba032a58 419 memset(&args, 0, sizeof(args));
bcc1c2a1 420
a572eaa3 421 if (ASIC_IS_DCE5(rdev)) {
4589433c 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
a572eaa3
AD		 423 args.v3.ucSpreadSpectrumType = ss->type;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
4589433c
CC		 427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
4589433c
CC		 432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
4589433c
CC		 437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
a572eaa3
AD		 439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58
AD		 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type;
447 switch (pll_id) {
448 case ATOM_PPLL1:
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
4589433c
CC		 450 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
451 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 452 break;
453 case ATOM_PPLL2:
454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
4589433c
CC		 455 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
456 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ebbe1cb9 457 break;
ba032a58
AD		 458 case ATOM_DCPLL:
459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
4589433c
CC		 460 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
461 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
ba032a58
AD		 462 break;
463 case ATOM_PPLL_INVALID:
464 return;
ebbe1cb9 465 }
ba032a58
AD		 466 args.v2.ucEnable = enable;
467 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type;
470 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) {
477 atombios_disable_ss(crtc);
478 return;
479 }
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 486 } else {
ba032a58
AD		 487 if (enable == ATOM_DISABLE) {
488 atombios_disable_ss(crtc);
489 return;
490 }
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable;
ebbe1cb9 496 }
26b9fc3a 497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 498}
499
4eaeca33
AD		 500union adjust_pixel_clock {
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 503};
504
505static u32 atombios_adjust_pll(struct drm_crtc *crtc,
506 struct drm_display_mode *mode,
ba032a58
AD		 507 struct radeon_pll *pll,
508 bool ss_enabled,
509 struct radeon_atom_ss *ss)
771fe6b9 510{
771fe6b9
JG		 511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 515 u32 adjusted_clock = mode->clock;
bcc1c2a1 516 int encoder_mode = 0;
fbee67a6
AD		 517 u32 dp_clock = mode->clock;
518 int bpc = 8;
fc10332b 519
4eaeca33
AD		 520 /* reset the pll flags */
521 pll->flags = 0;
771fe6b9
JG		 522
523 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 524 if ((rdev->family == CHIP_RS600) ||
525 (rdev->family == CHIP_RS690) ||
526 (rdev->family == CHIP_RS740))
2ff776cf 527 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 528 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 529
530 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
532 else
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
534 } else {
fc10332b 535 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 536
5480f727
DA		 537 if (mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 }
543
771fe6b9
JG		 544 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
545 if (encoder->crtc == crtc) {
4eaeca33 546 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 547 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6
AD		 548 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
549 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
550 if (connector) {
551 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
552 struct radeon_connector_atom_dig *dig_connector =
553 radeon_connector->con_priv;
554
555 dp_clock = dig_connector->dp_clock;
556 }
557 }
619efb10 558/* this might work properly with the new pll algo */
e5fd205f 559#if 0 /* doesn't work properly on some laptops */
ba032a58
AD		 560 /* use recommended ref_div for ss */
561 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
562 if (ss_enabled) {
563 if (ss->refdiv) {
564 pll->flags |= RADEON_PLL_USE_REF_DIV;
565 pll->reference_div = ss->refdiv;
566 }
567 }
568 }
e5fd205f 569#endif
4eaeca33
AD		 570 if (ASIC_IS_AVIVO(rdev)) {
571 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
572 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
573 adjusted_clock = mode->clock * 2;
48dfaaeb 574 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 575 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
619efb10
AD		 576 /* rv515 needs more testing with this option */
577 if (rdev->family != CHIP_RV515) {
578 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
579 pll->flags |= RADEON_PLL_IS_LCD;
580 }
4eaeca33
AD		 581 } else {
582 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 583 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 584 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 585 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 586 }
3ce0a23d 587 break;
771fe6b9
JG		 588 }
589 }
590
2606c886
AD		 591 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
592 * accordingly based on the encoder/transmitter to work around
593 * special hw requirements.
594 */
595 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 596 union adjust_pixel_clock args;
4eaeca33
AD		 597 u8 frev, crev;
598 int index;
2606c886 599
2606c886 600 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 601 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
602 &crev))
603 return adjusted_clock;
4eaeca33
AD		 604
605 memset(&args, 0, sizeof(args));
606
607 switch (frev) {
608 case 1:
609 switch (crev) {
610 case 1:
611 case 2:
612 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
613 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 614 args.v1.ucEncodeMode = encoder_mode;
b526ce22 615 if (ss_enabled)
fbee67a6
AD		 616 args.v1.ucConfig |=
617 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 618
619 atom_execute_table(rdev->mode_info.atom_context,
620 index, (uint32_t *)&args);
621 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
622 break;
bcc1c2a1
AD		 623 case 3:
624 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
625 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
626 args.v3.sInput.ucEncodeMode = encoder_mode;
627 args.v3.sInput.ucDispPllConfig = 0;
b526ce22
AD		 628 if (ss_enabled)
629 args.v3.sInput.ucDispPllConfig |=
630 DISPPLL_CONFIG_SS_ENABLE;
bcc1c2a1
AD		 631 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
632 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
fbee67a6 633 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1
AD		 634 args.v3.sInput.ucDispPllConfig |=
635 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 636 /* 16200 or 27000 */
637 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
638 } else {
639 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
640 /* deep color support */
641 args.v3.sInput.usPixelClock =
642 cpu_to_le16((mode->clock * bpc / 8) / 10);
643 }
bcc1c2a1
AD		 644 if (dig->coherent_mode)
645 args.v3.sInput.ucDispPllConfig |=
646 DISPPLL_CONFIG_COHERENT_MODE;
647 if (mode->clock > 165000)
648 args.v3.sInput.ucDispPllConfig |=
649 DISPPLL_CONFIG_DUAL_LINK;
650 }
651 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6 652 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1 653 args.v3.sInput.ucDispPllConfig |=
9f998ad7 654 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 655 /* 16200 or 27000 */
656 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
b526ce22 657 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
9f998ad7
AD		 658 if (mode->clock > 165000)
659 args.v3.sInput.ucDispPllConfig |=
660 DISPPLL_CONFIG_DUAL_LINK;
661 }
bcc1c2a1
AD		 662 }
663 atom_execute_table(rdev->mode_info.atom_context,
664 index, (uint32_t *)&args);
665 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
666 if (args.v3.sOutput.ucRefDiv) {
667 pll->flags |= RADEON_PLL_USE_REF_DIV;
668 pll->reference_div = args.v3.sOutput.ucRefDiv;
669 }
670 if (args.v3.sOutput.ucPostDiv) {
671 pll->flags |= RADEON_PLL_USE_POST_DIV;
672 pll->post_div = args.v3.sOutput.ucPostDiv;
673 }
674 break;
4eaeca33
AD		 675 default:
676 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
677 return adjusted_clock;
678 }
679 break;
680 default:
681 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
682 return adjusted_clock;
683 }
d56ef9c8 684 }
4eaeca33
AD		 685 return adjusted_clock;
686}
687
688union set_pixel_clock {
689 SET_PIXEL_CLOCK_PS_ALLOCATION base;
690 PIXEL_CLOCK_PARAMETERS v1;
691 PIXEL_CLOCK_PARAMETERS_V2 v2;
692 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 693 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 694 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 695};
696
f82b3ddc
AD		 697/* on DCE5, make sure the voltage is high enough to support the
698 * required disp clk.
699 */
700static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
701 u32 dispclk)
bcc1c2a1
AD		 702{
703 struct drm_device *dev = crtc->dev;
704 struct radeon_device *rdev = dev->dev_private;
705 u8 frev, crev;
706 int index;
707 union set_pixel_clock args;
708
709 memset(&args, 0, sizeof(args));
710
711 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 712 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
713 &crev))
714 return;
bcc1c2a1
AD		 715
716 switch (frev) {
717 case 1:
718 switch (crev) {
719 case 5:
720 /* if the default dcpll clock is specified,
721 * SetPixelClock provides the dividers
722 */
723 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 724 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 725 args.v5.ucPpll = ATOM_DCPLL;
726 break;
f82b3ddc
AD		 727 case 6:
728 /* if the default dcpll clock is specified,
729 * SetPixelClock provides the dividers
730 */
731 args.v6.ulDispEngClkFreq = dispclk;
732 args.v6.ucPpll = ATOM_DCPLL;
733 break;
bcc1c2a1
AD		 734 default:
735 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
736 return;
737 }
738 break;
739 default:
740 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
741 return;
742 }
743 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
744}
745
37f9003b
AD		 746static void atombios_crtc_program_pll(struct drm_crtc *crtc,
747 int crtc_id,
748 int pll_id,
749 u32 encoder_mode,
750 u32 encoder_id,
751 u32 clock,
752 u32 ref_div,
753 u32 fb_div,
754 u32 frac_fb_div,
755 u32 post_div)
4eaeca33 756{
4eaeca33
AD		 757 struct drm_device *dev = crtc->dev;
758 struct radeon_device *rdev = dev->dev_private;
4eaeca33 759 u8 frev, crev;
37f9003b 760 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 761 union set_pixel_clock args;
4eaeca33
AD		 762
763 memset(&args, 0, sizeof(args));
764
a084e6ee
AD		 765 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
766 &crev))
767 return;
771fe6b9
JG		 768
769 switch (frev) {
770 case 1:
771 switch (crev) {
772 case 1:
37f9003b
AD		 773 if (clock == ATOM_DISABLE)
774 return;
775 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 776 args.v1.usRefDiv = cpu_to_le16(ref_div);
777 args.v1.usFbDiv = cpu_to_le16(fb_div);
778 args.v1.ucFracFbDiv = frac_fb_div;
779 args.v1.ucPostDiv = post_div;
37f9003b
AD		 780 args.v1.ucPpll = pll_id;
781 args.v1.ucCRTC = crtc_id;
4eaeca33 782 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 783 break;
784 case 2:
37f9003b 785 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 786 args.v2.usRefDiv = cpu_to_le16(ref_div);
787 args.v2.usFbDiv = cpu_to_le16(fb_div);
788 args.v2.ucFracFbDiv = frac_fb_div;
789 args.v2.ucPostDiv = post_div;
37f9003b
AD		 790 args.v2.ucPpll = pll_id;
791 args.v2.ucCRTC = crtc_id;
4eaeca33 792 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 793 break;
794 case 3:
37f9003b 795 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 796 args.v3.usRefDiv = cpu_to_le16(ref_div);
797 args.v3.usFbDiv = cpu_to_le16(fb_div);
798 args.v3.ucFracFbDiv = frac_fb_div;
799 args.v3.ucPostDiv = post_div;
37f9003b
AD		 800 args.v3.ucPpll = pll_id;
801 args.v3.ucMiscInfo = (pll_id << 2);
802 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 803 args.v3.ucEncoderMode = encoder_mode;
804 break;
805 case 5:
37f9003b
AD		 806 args.v5.ucCRTC = crtc_id;
807 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 808 args.v5.ucRefDiv = ref_div;
809 args.v5.usFbDiv = cpu_to_le16(fb_div);
810 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
811 args.v5.ucPostDiv = post_div;
812 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 813 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 814 args.v5.ucEncoderMode = encoder_mode;
37f9003b 815 args.v5.ucPpll = pll_id;
771fe6b9 816 break;
f82b3ddc
AD		 817 case 6:
818 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
819 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
820 args.v6.ucRefDiv = ref_div;
821 args.v6.usFbDiv = cpu_to_le16(fb_div);
822 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
823 args.v6.ucPostDiv = post_div;
824 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
825 args.v6.ucTransmitterID = encoder_id;
826 args.v6.ucEncoderMode = encoder_mode;
827 args.v6.ucPpll = pll_id;
828 break;
771fe6b9
JG		 829 default:
830 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
831 return;
832 }
833 break;
834 default:
835 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
836 return;
837 }
838
771fe6b9
JG		 839 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
840}
841
37f9003b
AD		 842static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
843{
844 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
845 struct drm_device *dev = crtc->dev;
846 struct radeon_device *rdev = dev->dev_private;
847 struct drm_encoder *encoder = NULL;
848 struct radeon_encoder *radeon_encoder = NULL;
849 u32 pll_clock = mode->clock;
850 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
851 struct radeon_pll *pll;
852 u32 adjusted_clock;
853 int encoder_mode = 0;
ba032a58
AD		 854 struct radeon_atom_ss ss;
855 bool ss_enabled = false;
37f9003b
AD		 856
857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
858 if (encoder->crtc == crtc) {
859 radeon_encoder = to_radeon_encoder(encoder);
860 encoder_mode = atombios_get_encoder_mode(encoder);
861 break;
862 }
863 }
864
865 if (!radeon_encoder)
866 return;
867
868 switch (radeon_crtc->pll_id) {
869 case ATOM_PPLL1:
870 pll = &rdev->clock.p1pll;
871 break;
872 case ATOM_PPLL2:
873 pll = &rdev->clock.p2pll;
874 break;
875 case ATOM_DCPLL:
876 case ATOM_PPLL_INVALID:
877 default:
878 pll = &rdev->clock.dcpll;
879 break;
880 }
881
ba032a58
AD		 882 if (radeon_encoder->active_device &
883 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
884 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
885 struct drm_connector *connector =
886 radeon_get_connector_for_encoder(encoder);
887 struct radeon_connector *radeon_connector =
888 to_radeon_connector(connector);
889 struct radeon_connector_atom_dig *dig_connector =
890 radeon_connector->con_priv;
891 int dp_clock;
892
893 switch (encoder_mode) {
894 case ATOM_ENCODER_MODE_DP:
895 /* DP/eDP */
896 dp_clock = dig_connector->dp_clock / 10;
897 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
898 if (ASIC_IS_DCE4(rdev))
899 ss_enabled =
900 radeon_atombios_get_asic_ss_info(rdev, &ss,
901 dig->lcd_ss_id,
902 dp_clock);
903 else
904 ss_enabled =
905 radeon_atombios_get_ppll_ss_info(rdev, &ss,
906 dig->lcd_ss_id);
907 } else {
908 if (ASIC_IS_DCE4(rdev))
909 ss_enabled =
910 radeon_atombios_get_asic_ss_info(rdev, &ss,
911 ASIC_INTERNAL_SS_ON_DP,
912 dp_clock);
913 else {
914 if (dp_clock == 16200) {
915 ss_enabled =
916 radeon_atombios_get_ppll_ss_info(rdev, &ss,
917 ATOM_DP_SS_ID2);
918 if (!ss_enabled)
919 ss_enabled =
920 radeon_atombios_get_ppll_ss_info(rdev, &ss,
921 ATOM_DP_SS_ID1);
922 } else
923 ss_enabled =
924 radeon_atombios_get_ppll_ss_info(rdev, &ss,
925 ATOM_DP_SS_ID1);
926 }
927 }
928 break;
929 case ATOM_ENCODER_MODE_LVDS:
930 if (ASIC_IS_DCE4(rdev))
931 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
932 dig->lcd_ss_id,
933 mode->clock / 10);
934 else
935 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
936 dig->lcd_ss_id);
937 break;
938 case ATOM_ENCODER_MODE_DVI:
939 if (ASIC_IS_DCE4(rdev))
940 ss_enabled =
941 radeon_atombios_get_asic_ss_info(rdev, &ss,
942 ASIC_INTERNAL_SS_ON_TMDS,
943 mode->clock / 10);
944 break;
945 case ATOM_ENCODER_MODE_HDMI:
946 if (ASIC_IS_DCE4(rdev))
947 ss_enabled =
948 radeon_atombios_get_asic_ss_info(rdev, &ss,
949 ASIC_INTERNAL_SS_ON_HDMI,
950 mode->clock / 10);
951 break;
952 default:
953 break;
954 }
955 }
956
37f9003b 957 /* adjust pixel clock as needed */
ba032a58 958 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b 959
619efb10
AD		 960 /* rv515 seems happier with the old algo */
961 if (rdev->family == CHIP_RV515)
962 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
963 &ref_div, &post_div);
964 else if (ASIC_IS_AVIVO(rdev))
965 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
966 &ref_div, &post_div);
967 else
968 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
969 &ref_div, &post_div);
37f9003b 970
ba032a58
AD		 971 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
972
37f9003b
AD		 973 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
974 encoder_mode, radeon_encoder->encoder_id, mode->clock,
975 ref_div, fb_div, frac_fb_div, post_div);
976
ba032a58
AD		 977 if (ss_enabled) {
978 /* calculate ss amount and step size */
979 if (ASIC_IS_DCE4(rdev)) {
980 u32 step_size;
981 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
982 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
983 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
984 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
985 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
986 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
987 (125 * 25 * pll->reference_freq / 100);
988 else
989 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
990 (125 * 25 * pll->reference_freq / 100);
991 ss.step = step_size;
992 }
993
994 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
995 }
37f9003b
AD		 996}
997
c9417bdd
AD		 998static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
999 struct drm_framebuffer *fb,
1000 int x, int y, int atomic)
bcc1c2a1
AD		 1001{
1002 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1003 struct drm_device *dev = crtc->dev;
1004 struct radeon_device *rdev = dev->dev_private;
1005 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1006 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1007 struct drm_gem_object *obj;
1008 struct radeon_bo *rbo;
1009 uint64_t fb_location;
1010 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1011 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
bcc1c2a1
AD		 1012 int r;
1013
1014 /* no fb bound */
4dd19b0d 1015 if (!atomic && !crtc->fb) {
d9fdaafb 1016 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1017 return 0;
1018 }
1019
4dd19b0d
CB		 1020 if (atomic) {
1021 radeon_fb = to_radeon_framebuffer(fb);
1022 target_fb = fb;
1023 }
1024 else {
1025 radeon_fb = to_radeon_framebuffer(crtc->fb);
1026 target_fb = crtc->fb;
1027 }
bcc1c2a1 1028
4dd19b0d
CB		 1029 /* If atomic, assume fb object is pinned & idle & fenced and
1030 * just update base pointers
1031 */
bcc1c2a1
AD		 1032 obj = radeon_fb->obj;
1033 rbo = obj->driver_private;
1034 r = radeon_bo_reserve(rbo, false);
1035 if (unlikely(r != 0))
1036 return r;
4dd19b0d
CB		 1037
1038 if (atomic)
1039 fb_location = radeon_bo_gpu_offset(rbo);
1040 else {
1041 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1042 if (unlikely(r != 0)) {
1043 radeon_bo_unreserve(rbo);
1044 return -EINVAL;
1045 }
bcc1c2a1 1046 }
4dd19b0d 1047
bcc1c2a1
AD		 1048 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1049 radeon_bo_unreserve(rbo);
1050
4dd19b0d 1051 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1052 case 8:
1053 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1054 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1055 break;
1056 case 15:
1057 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1058 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1059 break;
1060 case 16:
1061 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1062 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1063#ifdef __BIG_ENDIAN
1064 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1065#endif
bcc1c2a1
AD		 1066 break;
1067 case 24:
1068 case 32:
1069 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1070 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1071#ifdef __BIG_ENDIAN
1072 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1073#endif
bcc1c2a1
AD		 1074 break;
1075 default:
1076 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1077 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1078 return -EINVAL;
1079 }
1080
97d66328
AD		 1081 if (tiling_flags & RADEON_TILING_MACRO)
1082 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1083 else if (tiling_flags & RADEON_TILING_MICRO)
1084 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1085
bcc1c2a1
AD		 1086 switch (radeon_crtc->crtc_id) {
1087 case 0:
1088 WREG32(AVIVO_D1VGA_CONTROL, 0);
1089 break;
1090 case 1:
1091 WREG32(AVIVO_D2VGA_CONTROL, 0);
1092 break;
1093 case 2:
1094 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1095 break;
1096 case 3:
1097 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1098 break;
1099 case 4:
1100 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1101 break;
1102 case 5:
1103 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1104 break;
1105 default:
1106 break;
1107 }
1108
1109 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1110 upper_32_bits(fb_location));
1111 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1112 upper_32_bits(fb_location));
1113 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1114 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1115 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1116 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1117 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1118 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1119
1120 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1121 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1122 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1123 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1124 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1125 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1126
4dd19b0d 1127 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1128 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1129 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1130
1131 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1132 crtc->mode.vdisplay);
1133 x &= ~3;
1134 y &= ~1;
1135 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1136 (x << 16) | y);
1137 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1138 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1139
4dd19b0d
CB		 1140 if (!atomic && fb && fb != crtc->fb) {
1141 radeon_fb = to_radeon_framebuffer(fb);
bcc1c2a1
AD		 1142 rbo = radeon_fb->obj->driver_private;
1143 r = radeon_bo_reserve(rbo, false);
1144 if (unlikely(r != 0))
1145 return r;
1146 radeon_bo_unpin(rbo);
1147 radeon_bo_unreserve(rbo);
1148 }
1149
1150 /* Bytes per pixel may have changed */
1151 radeon_bandwidth_update(rdev);
1152
1153 return 0;
1154}
1155
4dd19b0d
CB		 1156static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1157 struct drm_framebuffer *fb,
1158 int x, int y, int atomic)
771fe6b9
JG		 1159{
1160 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1161 struct drm_device *dev = crtc->dev;
1162 struct radeon_device *rdev = dev->dev_private;
1163 struct radeon_framebuffer *radeon_fb;
1164 struct drm_gem_object *obj;
4c788679 1165 struct radeon_bo *rbo;
4dd19b0d 1166 struct drm_framebuffer *target_fb;
771fe6b9 1167 uint64_t fb_location;
e024e110 1168 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1169 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
4c788679 1170 int r;
771fe6b9 1171
2de3b484 1172 /* no fb bound */
4dd19b0d 1173 if (!atomic && !crtc->fb) {
d9fdaafb 1174 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1175 return 0;
1176 }
771fe6b9 1177
4dd19b0d
CB		 1178 if (atomic) {
1179 radeon_fb = to_radeon_framebuffer(fb);
1180 target_fb = fb;
1181 }
1182 else {
1183 radeon_fb = to_radeon_framebuffer(crtc->fb);
1184 target_fb = crtc->fb;
1185 }
771fe6b9
JG		 1186
1187 obj = radeon_fb->obj;
4c788679
JG		 1188 rbo = obj->driver_private;
1189 r = radeon_bo_reserve(rbo, false);
1190 if (unlikely(r != 0))
1191 return r;
4dd19b0d
CB		 1192
1193 /* If atomic, assume fb object is pinned & idle & fenced and
1194 * just update base pointers
1195 */
1196 if (atomic)
1197 fb_location = radeon_bo_gpu_offset(rbo);
1198 else {
1199 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1200 if (unlikely(r != 0)) {
1201 radeon_bo_unreserve(rbo);
1202 return -EINVAL;
1203 }
771fe6b9 1204 }
4c788679
JG		 1205 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1206 radeon_bo_unreserve(rbo);
771fe6b9 1207
4dd19b0d 1208 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1209 case 8:
1210 fb_format =
1211 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1212 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1213 break;
771fe6b9
JG		 1214 case 15:
1215 fb_format =
1216 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1217 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1218 break;
1219 case 16:
1220 fb_format =
1221 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1222 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1223#ifdef __BIG_ENDIAN
1224 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1225#endif
771fe6b9
JG		 1226 break;
1227 case 24:
1228 case 32:
1229 fb_format =
1230 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1231 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1232#ifdef __BIG_ENDIAN
1233 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1234#endif
771fe6b9
JG		 1235 break;
1236 default:
1237 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1238 target_fb->bits_per_pixel);
771fe6b9
JG		 1239 return -EINVAL;
1240 }
1241
40c4ac1c
AD		 1242 if (rdev->family >= CHIP_R600) {
1243 if (tiling_flags & RADEON_TILING_MACRO)
1244 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1245 else if (tiling_flags & RADEON_TILING_MICRO)
1246 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1247 } else {
1248 if (tiling_flags & RADEON_TILING_MACRO)
1249 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1250
40c4ac1c
AD		 1251 if (tiling_flags & RADEON_TILING_MICRO)
1252 fb_format |= AVIVO_D1GRPH_TILED;
1253 }
e024e110 1254
771fe6b9
JG		 1255 if (radeon_crtc->crtc_id == 0)
1256 WREG32(AVIVO_D1VGA_CONTROL, 0);
1257 else
1258 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1259
1260 if (rdev->family >= CHIP_RV770) {
1261 if (radeon_crtc->crtc_id) {
95347871
AD		 1262 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1263 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1264 } else {
95347871
AD		 1265 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1266 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1267 }
1268 }
771fe6b9
JG		 1269 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1270 (u32) fb_location);
1271 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1272 radeon_crtc->crtc_offset, (u32) fb_location);
1273 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1274 if (rdev->family >= CHIP_R600)
1275 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1276
1277 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1278 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1279 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1280 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1281 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1282 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1283
4dd19b0d 1284 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1285 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1286 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1287
1288 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1289 crtc->mode.vdisplay);
1290 x &= ~3;
1291 y &= ~1;
1292 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1293 (x << 16) | y);
1294 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1295 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1296
4dd19b0d
CB		 1297 if (!atomic && fb && fb != crtc->fb) {
1298 radeon_fb = to_radeon_framebuffer(fb);
4c788679
JG		 1299 rbo = radeon_fb->obj->driver_private;
1300 r = radeon_bo_reserve(rbo, false);
1301 if (unlikely(r != 0))
1302 return r;
1303 radeon_bo_unpin(rbo);
1304 radeon_bo_unreserve(rbo);
771fe6b9 1305 }
f30f37de
MD		 1306
1307 /* Bytes per pixel may have changed */
1308 radeon_bandwidth_update(rdev);
1309
771fe6b9
JG		 1310 return 0;
1311}
1312
54f088a9
AD		 1313int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1314 struct drm_framebuffer *old_fb)
1315{
1316 struct drm_device *dev = crtc->dev;
1317 struct radeon_device *rdev = dev->dev_private;
1318
bcc1c2a1 1319 if (ASIC_IS_DCE4(rdev))
c9417bdd 1320 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1321 else if (ASIC_IS_AVIVO(rdev))
1322 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1323 else
1324 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1325}
1326
1327int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1328 struct drm_framebuffer *fb,
21c74a8e 1329 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1330{
1331 struct drm_device *dev = crtc->dev;
1332 struct radeon_device *rdev = dev->dev_private;
1333
1334 if (ASIC_IS_DCE4(rdev))
c9417bdd 1335 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1336 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1337 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1338 else
4dd19b0d 1339 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1340}
1341
615e0cb6
AD		 1342/* properly set additional regs when using atombios */
1343static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1344{
1345 struct drm_device *dev = crtc->dev;
1346 struct radeon_device *rdev = dev->dev_private;
1347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1348 u32 disp_merge_cntl;
1349
1350 switch (radeon_crtc->crtc_id) {
1351 case 0:
1352 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1353 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1354 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1355 break;
1356 case 1:
1357 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1358 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1359 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1360 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1361 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1362 break;
1363 }
1364}
1365
bcc1c2a1
AD		 1366static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1367{
1368 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1369 struct drm_device *dev = crtc->dev;
1370 struct radeon_device *rdev = dev->dev_private;
1371 struct drm_encoder *test_encoder;
1372 struct drm_crtc *test_crtc;
1373 uint32_t pll_in_use = 0;
1374
1375 if (ASIC_IS_DCE4(rdev)) {
1376 /* if crtc is driving DP and we have an ext clock, use that */
1377 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1378 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1379 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1380 if (rdev->clock.dp_extclk)
1381 return ATOM_PPLL_INVALID;
1382 }
1383 }
1384 }
1385
1386 /* otherwise, pick one of the plls */
1387 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1388 struct radeon_crtc *radeon_test_crtc;
1389
1390 if (crtc == test_crtc)
1391 continue;
1392
1393 radeon_test_crtc = to_radeon_crtc(test_crtc);
1394 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1395 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1396 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1397 }
1398 if (!(pll_in_use & 1))
1399 return ATOM_PPLL1;
1400 return ATOM_PPLL2;
1401 } else
1402 return radeon_crtc->crtc_id;
1403
1404}
1405
771fe6b9
JG		 1406int atombios_crtc_mode_set(struct drm_crtc *crtc,
1407 struct drm_display_mode *mode,
1408 struct drm_display_mode *adjusted_mode,
1409 int x, int y, struct drm_framebuffer *old_fb)
1410{
1411 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1412 struct drm_device *dev = crtc->dev;
1413 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1414 struct drm_encoder *encoder;
1415 bool is_tvcv = false;
771fe6b9 1416
54bfe496
AD		 1417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1418 /* find tv std */
1419 if (encoder->crtc == crtc) {
1420 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1421 if (radeon_encoder->active_device &
1422 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1423 is_tvcv = true;
1424 }
1425 }
771fe6b9 1426
bcc1c2a1 1427 /* always set DCPLL */
ba032a58
AD		 1428 if (ASIC_IS_DCE4(rdev)) {
1429 struct radeon_atom_ss ss;
1430 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1431 ASIC_INTERNAL_SS_ON_DCPLL,
1432 rdev->clock.default_dispclk);
1433 if (ss_enabled)
1434 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
f82b3ddc
AD		 1435 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1436 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
ba032a58
AD		 1437 if (ss_enabled)
1438 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1439 }
771fe6b9 1440 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1441
54bfe496 1442 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1443 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1444 else if (ASIC_IS_AVIVO(rdev)) {
1445 if (is_tvcv)
1446 atombios_crtc_set_timing(crtc, adjusted_mode);
1447 else
1448 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1449 } else {
bcc1c2a1 1450 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1451 if (radeon_crtc->crtc_id == 0)
1452 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1453 radeon_legacy_atom_fixup(crtc);
771fe6b9 1454 }
bcc1c2a1 1455 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1456 atombios_overscan_setup(crtc, mode, adjusted_mode);
1457 atombios_scaler_setup(crtc);
771fe6b9
JG		 1458 return 0;
1459}
1460
1461static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1462 struct drm_display_mode *mode,
1463 struct drm_display_mode *adjusted_mode)
1464{
03214bd5
AD		 1465 struct drm_device *dev = crtc->dev;
1466 struct radeon_device *rdev = dev->dev_private;
1467
1468 /* adjust pm to upcoming mode change */
1469 radeon_pm_compute_clocks(rdev);
1470
c93bb85b
JG		 1471 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1472 return false;
771fe6b9
JG		 1473 return true;
1474}
1475
1476static void atombios_crtc_prepare(struct drm_crtc *crtc)
1477{
267364ac
AD		 1478 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1479
1480 /* pick pll */
1481 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1482
37b4390e 1483 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1484 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1485}
1486
1487static void atombios_crtc_commit(struct drm_crtc *crtc)
1488{
1489 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1490 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1491}
1492
37f9003b
AD		 1493static void atombios_crtc_disable(struct drm_crtc *crtc)
1494{
1495 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1496 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1497
1498 switch (radeon_crtc->pll_id) {
1499 case ATOM_PPLL1:
1500 case ATOM_PPLL2:
1501 /* disable the ppll */
1502 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1503 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1504 break;
1505 default:
1506 break;
1507 }
1508 radeon_crtc->pll_id = -1;
1509}
1510
771fe6b9
JG		 1511static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1512 .dpms = atombios_crtc_dpms,
1513 .mode_fixup = atombios_crtc_mode_fixup,
1514 .mode_set = atombios_crtc_mode_set,
1515 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1516 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1517 .prepare = atombios_crtc_prepare,
1518 .commit = atombios_crtc_commit,
068143d3 1519 .load_lut = radeon_crtc_load_lut,
37f9003b 1520 .disable = atombios_crtc_disable,
771fe6b9
JG		 1521};
1522
1523void radeon_atombios_init_crtc(struct drm_device *dev,
1524 struct radeon_crtc *radeon_crtc)
1525{
bcc1c2a1
AD		 1526 struct radeon_device *rdev = dev->dev_private;
1527
1528 if (ASIC_IS_DCE4(rdev)) {
1529 switch (radeon_crtc->crtc_id) {
1530 case 0:
1531 default:
12d7798f 1532 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1533 break;
1534 case 1:
12d7798f 1535 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1536 break;
1537 case 2:
12d7798f 1538 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1539 break;
1540 case 3:
12d7798f 1541 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1542 break;
1543 case 4:
12d7798f 1544 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1545 break;
1546 case 5:
12d7798f 1547 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1548 break;
1549 }
1550 } else {
1551 if (radeon_crtc->crtc_id == 1)
1552 radeon_crtc->crtc_offset =
1553 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1554 else
1555 radeon_crtc->crtc_offset = 0;
1556 }
1557 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1558 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1559}
Linux 6.x block layer and io_uring tree(s)