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drm/radeon: improve encoder picking functions (v2)
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
5df3196b
AD		 86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
c93bb85b
JG		 88 /* fixme - fill in enc_priv for atom dac */
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab 90 bool is_tv = false, is_cv = false;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
5df3196b
AD		 95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
98 is_tv = true;
4ce001ab
DA		 99 }
100
c93bb85b
JG		 101 memset(&args, 0, sizeof(args));
102
103 args.ucScaler = radeon_crtc->crtc_id;
104
4ce001ab 105 if (is_tv) {
c93bb85b
JG		 106 switch (tv_std) {
107 case TV_STD_NTSC:
108 default:
109 args.ucTVStandard = ATOM_TV_NTSC;
110 break;
111 case TV_STD_PAL:
112 args.ucTVStandard = ATOM_TV_PAL;
113 break;
114 case TV_STD_PAL_M:
115 args.ucTVStandard = ATOM_TV_PALM;
116 break;
117 case TV_STD_PAL_60:
118 args.ucTVStandard = ATOM_TV_PAL60;
119 break;
120 case TV_STD_NTSC_J:
121 args.ucTVStandard = ATOM_TV_NTSCJ;
122 break;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
125 break;
126 case TV_STD_SECAM:
127 args.ucTVStandard = ATOM_TV_SECAM;
128 break;
129 case TV_STD_PAL_CN:
130 args.ucTVStandard = ATOM_TV_PALCN;
131 break;
132 }
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 134 } else if (is_cv) {
c93bb85b
JG		 135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
137 } else {
138 switch (radeon_crtc->rmx_type) {
139 case RMX_FULL:
140 args.ucEnable = ATOM_SCALER_EXPANSION;
141 break;
142 case RMX_CENTER:
143 args.ucEnable = ATOM_SCALER_CENTER;
144 break;
145 case RMX_ASPECT:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 default:
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
151 else
152 args.ucEnable = ATOM_SCALER_CENTER;
153 break;
154 }
155 }
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 157 if ((is_tv || is_cv)
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 160 }
161}
162
771fe6b9
JG		 163static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
164{
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 int index =
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
171
172 memset(&args, 0, sizeof(args));
173
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
176
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
178}
179
180static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
181{
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194}
195
196static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
197{
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210}
211
78fe9e54
AD		 212static const u32 vga_control_regs[6] =
213{
214 AVIVO_D1VGA_CONTROL,
215 AVIVO_D2VGA_CONTROL,
216 EVERGREEN_D3VGA_CONTROL,
217 EVERGREEN_D4VGA_CONTROL,
218 EVERGREEN_D5VGA_CONTROL,
219 EVERGREEN_D6VGA_CONTROL,
220};
221
771fe6b9
JG		 222static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
223{
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
225 struct drm_device *dev = crtc->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
228 BLANK_CRTC_PS_ALLOCATION args;
78fe9e54 229 u32 vga_control = 0;
771fe6b9
JG		 230
231 memset(&args, 0, sizeof(args));
232
78fe9e54
AD		 233 if (ASIC_IS_DCE8(rdev)) {
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
236 }
237
771fe6b9
JG		 238 args.ucCRTC = radeon_crtc->crtc_id;
239 args.ucBlanking = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
78fe9e54
AD		 242
243 if (ASIC_IS_DCE8(rdev)) {
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
245 }
771fe6b9
JG		 246}
247
fef9f91f
AD		 248static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
249{
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 struct drm_device *dev = crtc->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
254 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
255
256 memset(&args, 0, sizeof(args));
257
258 args.ucDispPipeId = radeon_crtc->crtc_id;
259 args.ucEnable = state;
260
261 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
262}
263
771fe6b9
JG		 264void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
265{
266 struct drm_device *dev = crtc->dev;
267 struct radeon_device *rdev = dev->dev_private;
500b7587 268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 269
270 switch (mode) {
271 case DRM_MODE_DPMS_ON:
d7311171 272 radeon_crtc->enabled = true;
37b4390e 273 atombios_enable_crtc(crtc, ATOM_ENABLE);
79f17c64 274 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 275 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
276 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 277 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 278 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 279 break;
280 case DRM_MODE_DPMS_STANDBY:
281 case DRM_MODE_DPMS_SUSPEND:
282 case DRM_MODE_DPMS_OFF:
45f9a39b 283 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 284 if (radeon_crtc->enabled)
285 atombios_blank_crtc(crtc, ATOM_ENABLE);
79f17c64 286 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 287 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
288 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 289 radeon_crtc->enabled = false;
771fe6b9
JG		 290 break;
291 }
3640da2f
AD		 292 /* adjust pm to dpms */
293 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 294}
295
296static void
297atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 298 struct drm_display_mode *mode)
771fe6b9 299{
5a9bcacc 300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 303 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 304 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 305 u16 misc = 0;
771fe6b9 306
5a9bcacc 307 memset(&args, 0, sizeof(args));
5b1714d3 308 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 309 args.usH_Blanking_Time =
5b1714d3
AD		 310 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
311 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 312 args.usV_Blanking_Time =
5b1714d3 313 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 314 args.usH_SyncOffset =
5b1714d3 315 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 316 args.usH_SyncWidth =
317 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
318 args.usV_SyncOffset =
5b1714d3 319 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 320 args.usV_SyncWidth =
321 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 322 args.ucH_Border = radeon_crtc->h_border;
323 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 324
325 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
326 misc |= ATOM_VSYNC_POLARITY;
327 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
328 misc |= ATOM_HSYNC_POLARITY;
329 if (mode->flags & DRM_MODE_FLAG_CSYNC)
330 misc |= ATOM_COMPOSITESYNC;
331 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
332 misc |= ATOM_INTERLACE;
fd99a094 333 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5a9bcacc 334 misc |= ATOM_DOUBLE_CLOCK_MODE;
fd99a094
AD		 335 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
336 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
5a9bcacc
AD		 337
338 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
339 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 340
5a9bcacc 341 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 342}
343
5a9bcacc
AD		 344static void atombios_crtc_set_timing(struct drm_crtc *crtc,
345 struct drm_display_mode *mode)
771fe6b9 346{
5a9bcacc 347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 348 struct drm_device *dev = crtc->dev;
349 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 350 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 351 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 352 u16 misc = 0;
771fe6b9 353
5a9bcacc
AD		 354 memset(&args, 0, sizeof(args));
355 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
356 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
357 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
358 args.usH_SyncWidth =
359 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
360 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
361 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
362 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
363 args.usV_SyncWidth =
364 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
365
54bfe496
AD		 366 args.ucOverscanRight = radeon_crtc->h_border;
367 args.ucOverscanLeft = radeon_crtc->h_border;
368 args.ucOverscanBottom = radeon_crtc->v_border;
369 args.ucOverscanTop = radeon_crtc->v_border;
370
5a9bcacc
AD		 371 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
372 misc |= ATOM_VSYNC_POLARITY;
373 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
374 misc |= ATOM_HSYNC_POLARITY;
375 if (mode->flags & DRM_MODE_FLAG_CSYNC)
376 misc |= ATOM_COMPOSITESYNC;
377 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
378 misc |= ATOM_INTERLACE;
fd99a094 379 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5a9bcacc 380 misc |= ATOM_DOUBLE_CLOCK_MODE;
fd99a094
AD		 381 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
382 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
5a9bcacc
AD		 383
384 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
385 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 386
5a9bcacc 387 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 388}
389
3fa47d9e 390static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
b792210e 391{
b792210e
AD		 392 u32 ss_cntl;
393
394 if (ASIC_IS_DCE4(rdev)) {
3fa47d9e 395 switch (pll_id) {
b792210e
AD		 396 case ATOM_PPLL1:
397 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
398 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
399 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
400 break;
401 case ATOM_PPLL2:
402 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
403 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
404 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
405 break;
406 case ATOM_DCPLL:
407 case ATOM_PPLL_INVALID:
408 return;
409 }
410 } else if (ASIC_IS_AVIVO(rdev)) {
3fa47d9e 411 switch (pll_id) {
b792210e
AD		 412 case ATOM_PPLL1:
413 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
414 ss_cntl &= ~1;
415 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
416 break;
417 case ATOM_PPLL2:
418 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
419 ss_cntl &= ~1;
420 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
421 break;
422 case ATOM_DCPLL:
423 case ATOM_PPLL_INVALID:
424 return;
425 }
426 }
427}
428
429
26b9fc3a 430union atom_enable_ss {
ba032a58
AD		 431 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
432 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 433 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 434 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 435 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 436};
437
3fa47d9e 438static void atombios_crtc_program_ss(struct radeon_device *rdev,
ba032a58
AD		 439 int enable,
440 int pll_id,
5efcc76c 441 int crtc_id,
ba032a58 442 struct radeon_atom_ss *ss)
ebbe1cb9 443{
5efcc76c 444 unsigned i;
ebbe1cb9 445 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 446 union atom_enable_ss args;
ebbe1cb9 447
c4756baa
AD		 448 if (enable) {
449 /* Don't mess with SS if percentage is 0 or external ss.
450 * SS is already disabled previously, and disabling it
451 * again can cause display problems if the pll is already
452 * programmed.
453 */
454 if (ss->percentage == 0)
455 return;
456 if (ss->type & ATOM_EXTERNAL_SS_MASK)
457 return;
458 } else {
53176706 459 for (i = 0; i < rdev->num_crtc; i++) {
5efcc76c
JG		 460 if (rdev->mode_info.crtcs[i] &&
461 rdev->mode_info.crtcs[i]->enabled &&
462 i != crtc_id &&
463 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
464 /* one other crtc is using this pll don't turn
465 * off spread spectrum as it might turn off
466 * display on active crtc
467 */
468 return;
469 }
470 }
471 }
472
ba032a58 473 memset(&args, 0, sizeof(args));
bcc1c2a1 474
a572eaa3 475 if (ASIC_IS_DCE5(rdev)) {
4589433c 476 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
8e8e523d 477 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
a572eaa3
AD		 478 switch (pll_id) {
479 case ATOM_PPLL1:
480 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
a572eaa3
AD		 481 break;
482 case ATOM_PPLL2:
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
a572eaa3
AD		 484 break;
485 case ATOM_DCPLL:
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
a572eaa3
AD		 487 break;
488 case ATOM_PPLL_INVALID:
489 return;
490 }
f312f093
AD		 491 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
492 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
d0ae3e89 493 args.v3.ucEnable = enable;
a572eaa3 494 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58 495 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 496 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 497 switch (pll_id) {
498 case ATOM_PPLL1:
499 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
ba032a58
AD		 500 break;
501 case ATOM_PPLL2:
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
ebbe1cb9 503 break;
ba032a58
AD		 504 case ATOM_DCPLL:
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
ba032a58
AD		 506 break;
507 case ATOM_PPLL_INVALID:
508 return;
ebbe1cb9 509 }
f312f093
AD		 510 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
511 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 512 args.v2.ucEnable = enable;
513 } else if (ASIC_IS_DCE3(rdev)) {
514 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 515 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 516 args.v1.ucSpreadSpectrumStep = ss->step;
517 args.v1.ucSpreadSpectrumDelay = ss->delay;
518 args.v1.ucSpreadSpectrumRange = ss->range;
519 args.v1.ucPpll = pll_id;
520 args.v1.ucEnable = enable;
521 } else if (ASIC_IS_AVIVO(rdev)) {
8e8e523d
AD		 522 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
523 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
3fa47d9e 524 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 525 return;
526 }
527 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 528 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 529 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
530 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
531 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
532 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 533 } else {
c4756baa 534 if (enable == ATOM_DISABLE) {
3fa47d9e 535 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 536 return;
537 }
538 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 539 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 540 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
541 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
542 args.lvds_ss.ucEnable = enable;
ebbe1cb9 543 }
26b9fc3a 544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 545}
546
4eaeca33
AD		 547union adjust_pixel_clock {
548 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 549 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 550};
551
552static u32 atombios_adjust_pll(struct drm_crtc *crtc,
19eca43e 553 struct drm_display_mode *mode)
771fe6b9 554{
19eca43e 555 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 556 struct drm_device *dev = crtc->dev;
557 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 558 struct drm_encoder *encoder = radeon_crtc->encoder;
559 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
560 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
4eaeca33 561 u32 adjusted_clock = mode->clock;
5df3196b 562 int encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6 563 u32 dp_clock = mode->clock;
f71d9ebd 564 u32 clock = mode->clock;
7d5a33b0 565 int bpc = radeon_crtc->bpc;
5df3196b 566 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
fc10332b 567
4eaeca33 568 /* reset the pll flags */
19eca43e 569 radeon_crtc->pll_flags = 0;
771fe6b9
JG		 570
571 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 572 if ((rdev->family == CHIP_RS600) ||
573 (rdev->family == CHIP_RS690) ||
574 (rdev->family == CHIP_RS740))
19eca43e
AD		 575 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
576 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 577
578 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
19eca43e 579 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
5480f727 580 else
19eca43e 581 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1 582
5785e53f 583 if (rdev->family < CHIP_RV770)
19eca43e 584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
37d4174d 585 /* use frac fb div on APUs */
c7d2f227 586 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
19eca43e 587 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
41167828
AD		 588 /* use frac fb div on RS780/RS880 */
589 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
a02dc74b
AD		 591 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
5480f727 593 } else {
19eca43e 594 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
771fe6b9 595
5480f727 596 if (mode->clock > 200000) /* range limits??? */
19eca43e 597 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
5480f727 598 else
19eca43e 599 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 600 }
601
5df3196b
AD		 602 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
603 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
604 if (connector) {
605 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
606 struct radeon_connector_atom_dig *dig_connector =
607 radeon_connector->con_priv;
5b40ddf8 608
5df3196b
AD		 609 dp_clock = dig_connector->dp_clock;
610 }
611 }
5b40ddf8 612
5df3196b
AD		 613 /* use recommended ref_div for ss */
614 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
615 if (radeon_crtc->ss_enabled) {
616 if (radeon_crtc->ss.refdiv) {
617 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
618 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
619 if (ASIC_IS_AVIVO(rdev))
620 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
771fe6b9 621 }
771fe6b9
JG		 622 }
623 }
624
5df3196b
AD		 625 if (ASIC_IS_AVIVO(rdev)) {
626 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
627 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
628 adjusted_clock = mode->clock * 2;
629 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
630 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
631 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
632 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
633 } else {
634 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
635 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
636 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
637 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
638 }
639
f71d9ebd
AD		 640 /* adjust pll for deep color modes */
641 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
642 switch (bpc) {
643 case 8:
644 default:
645 break;
646 case 10:
647 clock = (clock * 5) / 4;
648 break;
649 case 12:
650 clock = (clock * 3) / 2;
651 break;
652 case 16:
653 clock = clock * 2;
654 break;
655 }
656 }
657
2606c886
AD		 658 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
659 * accordingly based on the encoder/transmitter to work around
660 * special hw requirements.
661 */
662 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 663 union adjust_pixel_clock args;
4eaeca33
AD		 664 u8 frev, crev;
665 int index;
2606c886 666
2606c886 667 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 668 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
669 &crev))
670 return adjusted_clock;
4eaeca33
AD		 671
672 memset(&args, 0, sizeof(args));
673
674 switch (frev) {
675 case 1:
676 switch (crev) {
677 case 1:
678 case 2:
f71d9ebd 679 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33 680 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 681 args.v1.ucEncodeMode = encoder_mode;
19eca43e 682 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
fbee67a6
AD		 683 args.v1.ucConfig |=
684 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 685
686 atom_execute_table(rdev->mode_info.atom_context,
687 index, (uint32_t *)&args);
688 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
689 break;
bcc1c2a1 690 case 3:
f71d9ebd 691 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 692 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
693 args.v3.sInput.ucEncodeMode = encoder_mode;
694 args.v3.sInput.ucDispPllConfig = 0;
19eca43e 695 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
b526ce22
AD		 696 args.v3.sInput.ucDispPllConfig |=
697 DISPPLL_CONFIG_SS_ENABLE;
996d5c59 698 if (ENCODER_MODE_IS_DP(encoder_mode)) {
b4f15f80
AD		 699 args.v3.sInput.ucDispPllConfig |=
700 DISPPLL_CONFIG_COHERENT_MODE;
701 /* 16200 or 27000 */
702 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
703 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
bcc1c2a1 704 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b4f15f80 705 if (dig->coherent_mode)
bcc1c2a1
AD		 706 args.v3.sInput.ucDispPllConfig |=
707 DISPPLL_CONFIG_COHERENT_MODE;
9aa59993 708 if (is_duallink)
bcc1c2a1 709 args.v3.sInput.ucDispPllConfig |=
b4f15f80 710 DISPPLL_CONFIG_DUAL_LINK;
bcc1c2a1 711 }
1d33e1fc
AD		 712 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
713 ENCODER_OBJECT_ID_NONE)
714 args.v3.sInput.ucExtTransmitterID =
715 radeon_encoder_get_dp_bridge_encoder_id(encoder);
716 else
cc9f67a0
AD		 717 args.v3.sInput.ucExtTransmitterID = 0;
718
bcc1c2a1
AD		 719 atom_execute_table(rdev->mode_info.atom_context,
720 index, (uint32_t *)&args);
721 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
722 if (args.v3.sOutput.ucRefDiv) {
19eca43e
AD		 723 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
724 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
725 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
bcc1c2a1
AD		 726 }
727 if (args.v3.sOutput.ucPostDiv) {
19eca43e
AD		 728 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
729 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
730 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
bcc1c2a1
AD		 731 }
732 break;
4eaeca33
AD		 733 default:
734 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
735 return adjusted_clock;
736 }
737 break;
738 default:
739 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
740 return adjusted_clock;
741 }
d56ef9c8 742 }
4eaeca33
AD		 743 return adjusted_clock;
744}
745
746union set_pixel_clock {
747 SET_PIXEL_CLOCK_PS_ALLOCATION base;
748 PIXEL_CLOCK_PARAMETERS v1;
749 PIXEL_CLOCK_PARAMETERS_V2 v2;
750 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 751 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 752 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 753};
754
f82b3ddc
AD		 755/* on DCE5, make sure the voltage is high enough to support the
756 * required disp clk.
757 */
f3f1f03e 758static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
f82b3ddc 759 u32 dispclk)
bcc1c2a1 760{
bcc1c2a1
AD		 761 u8 frev, crev;
762 int index;
763 union set_pixel_clock args;
764
765 memset(&args, 0, sizeof(args));
766
767 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 768 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
769 &crev))
770 return;
bcc1c2a1
AD		 771
772 switch (frev) {
773 case 1:
774 switch (crev) {
775 case 5:
776 /* if the default dcpll clock is specified,
777 * SetPixelClock provides the dividers
778 */
779 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 780 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 781 args.v5.ucPpll = ATOM_DCPLL;
782 break;
f82b3ddc
AD		 783 case 6:
784 /* if the default dcpll clock is specified,
785 * SetPixelClock provides the dividers
786 */
265aa6c8 787 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
8542c12b 788 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
729b95ef
AD		 789 args.v6.ucPpll = ATOM_EXT_PLL1;
790 else if (ASIC_IS_DCE6(rdev))
f3f1f03e
AD		 791 args.v6.ucPpll = ATOM_PPLL0;
792 else
793 args.v6.ucPpll = ATOM_DCPLL;
f82b3ddc 794 break;
bcc1c2a1
AD		 795 default:
796 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
797 return;
798 }
799 break;
800 default:
801 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
802 return;
803 }
804 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
805}
806
37f9003b 807static void atombios_crtc_program_pll(struct drm_crtc *crtc,
f1bece7f 808 u32 crtc_id,
37f9003b
AD		 809 int pll_id,
810 u32 encoder_mode,
811 u32 encoder_id,
812 u32 clock,
813 u32 ref_div,
814 u32 fb_div,
815 u32 frac_fb_div,
df271bec 816 u32 post_div,
8e8e523d
AD		 817 int bpc,
818 bool ss_enabled,
819 struct radeon_atom_ss *ss)
4eaeca33 820{
4eaeca33
AD		 821 struct drm_device *dev = crtc->dev;
822 struct radeon_device *rdev = dev->dev_private;
4eaeca33 823 u8 frev, crev;
37f9003b 824 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 825 union set_pixel_clock args;
4eaeca33
AD		 826
827 memset(&args, 0, sizeof(args));
828
a084e6ee
AD		 829 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
830 &crev))
831 return;
771fe6b9
JG		 832
833 switch (frev) {
834 case 1:
835 switch (crev) {
836 case 1:
37f9003b
AD		 837 if (clock == ATOM_DISABLE)
838 return;
839 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 840 args.v1.usRefDiv = cpu_to_le16(ref_div);
841 args.v1.usFbDiv = cpu_to_le16(fb_div);
842 args.v1.ucFracFbDiv = frac_fb_div;
843 args.v1.ucPostDiv = post_div;
37f9003b
AD		 844 args.v1.ucPpll = pll_id;
845 args.v1.ucCRTC = crtc_id;
4eaeca33 846 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 847 break;
848 case 2:
37f9003b 849 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 850 args.v2.usRefDiv = cpu_to_le16(ref_div);
851 args.v2.usFbDiv = cpu_to_le16(fb_div);
852 args.v2.ucFracFbDiv = frac_fb_div;
853 args.v2.ucPostDiv = post_div;
37f9003b
AD		 854 args.v2.ucPpll = pll_id;
855 args.v2.ucCRTC = crtc_id;
4eaeca33 856 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 857 break;
858 case 3:
37f9003b 859 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 860 args.v3.usRefDiv = cpu_to_le16(ref_div);
861 args.v3.usFbDiv = cpu_to_le16(fb_div);
862 args.v3.ucFracFbDiv = frac_fb_div;
863 args.v3.ucPostDiv = post_div;
37f9003b 864 args.v3.ucPpll = pll_id;
e729586e
AD		 865 if (crtc_id == ATOM_CRTC2)
866 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
867 else
868 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
6f15c506
AD		 869 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
870 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
37f9003b 871 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 872 args.v3.ucEncoderMode = encoder_mode;
873 break;
874 case 5:
37f9003b
AD		 875 args.v5.ucCRTC = crtc_id;
876 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 877 args.v5.ucRefDiv = ref_div;
878 args.v5.usFbDiv = cpu_to_le16(fb_div);
879 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
880 args.v5.ucPostDiv = post_div;
881 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 882 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
883 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
7d5ab300
AD		 884 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
885 switch (bpc) {
886 case 8:
887 default:
888 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
889 break;
890 case 10:
f71d9ebd
AD		 891 /* yes this is correct, the atom define is wrong */
892 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
893 break;
894 case 12:
895 /* yes this is correct, the atom define is wrong */
7d5ab300
AD		 896 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
897 break;
898 }
df271bec 899 }
37f9003b 900 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 901 args.v5.ucEncoderMode = encoder_mode;
37f9003b 902 args.v5.ucPpll = pll_id;
771fe6b9 903 break;
f82b3ddc 904 case 6:
f1bece7f 905 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
f82b3ddc
AD		 906 args.v6.ucRefDiv = ref_div;
907 args.v6.usFbDiv = cpu_to_le16(fb_div);
908 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
909 args.v6.ucPostDiv = post_div;
910 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 911 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
912 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
7d5ab300
AD		 913 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
914 switch (bpc) {
915 case 8:
916 default:
917 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
918 break;
919 case 10:
f71d9ebd 920 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
7d5ab300
AD		 921 break;
922 case 12:
f71d9ebd 923 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
7d5ab300
AD		 924 break;
925 case 16:
926 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
927 break;
928 }
df271bec 929 }
f82b3ddc
AD		 930 args.v6.ucTransmitterID = encoder_id;
931 args.v6.ucEncoderMode = encoder_mode;
932 args.v6.ucPpll = pll_id;
933 break;
771fe6b9
JG		 934 default:
935 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
936 return;
937 }
938 break;
939 default:
940 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
941 return;
942 }
943
771fe6b9
JG		 944 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
945}
946
19eca43e 947static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
37f9003b
AD		 948{
949 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
950 struct drm_device *dev = crtc->dev;
951 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 952 struct radeon_encoder *radeon_encoder =
953 to_radeon_encoder(radeon_crtc->encoder);
954 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
19eca43e
AD		 955
956 radeon_crtc->bpc = 8;
957 radeon_crtc->ss_enabled = false;
37f9003b 958
700698e7 959 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
5df3196b 960 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
ba032a58
AD		 961 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
962 struct drm_connector *connector =
5df3196b 963 radeon_get_connector_for_encoder(radeon_crtc->encoder);
ba032a58
AD		 964 struct radeon_connector *radeon_connector =
965 to_radeon_connector(connector);
966 struct radeon_connector_atom_dig *dig_connector =
967 radeon_connector->con_priv;
968 int dp_clock;
ea292861
MK		 969
970 /* Assign mode clock for hdmi deep color max clock limit check */
971 radeon_connector->pixelclock_for_modeset = mode->clock;
19eca43e 972 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
ba032a58
AD		 973
974 switch (encoder_mode) {
996d5c59 975 case ATOM_ENCODER_MODE_DP_MST:
ba032a58
AD		 976 case ATOM_ENCODER_MODE_DP:
977 /* DP/eDP */
978 dp_clock = dig_connector->dp_clock / 10;
2307790f 979 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 980 radeon_crtc->ss_enabled =
981 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
2307790f
AD		 982 ASIC_INTERNAL_SS_ON_DP,
983 dp_clock);
984 else {
985 if (dp_clock == 16200) {
19eca43e
AD		 986 radeon_crtc->ss_enabled =
987 radeon_atombios_get_ppll_ss_info(rdev,
988 &radeon_crtc->ss,
2307790f 989 ATOM_DP_SS_ID2);
19eca43e
AD		 990 if (!radeon_crtc->ss_enabled)
991 radeon_crtc->ss_enabled =
992 radeon_atombios_get_ppll_ss_info(rdev,
993 &radeon_crtc->ss,
2307790f 994 ATOM_DP_SS_ID1);
d8e24525 995 } else {
19eca43e
AD		 996 radeon_crtc->ss_enabled =
997 radeon_atombios_get_ppll_ss_info(rdev,
998 &radeon_crtc->ss,
2307790f 999 ATOM_DP_SS_ID1);
d8e24525
AD		 1000 }
1001 /* disable spread spectrum on DCE3 DP */
1002 radeon_crtc->ss_enabled = false;
ba032a58
AD		 1003 }
1004 break;
1005 case ATOM_ENCODER_MODE_LVDS:
1006 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 1007 radeon_crtc->ss_enabled =
1008 radeon_atombios_get_asic_ss_info(rdev,
1009 &radeon_crtc->ss,
1010 dig->lcd_ss_id,
1011 mode->clock / 10);
ba032a58 1012 else
19eca43e
AD		 1013 radeon_crtc->ss_enabled =
1014 radeon_atombios_get_ppll_ss_info(rdev,
1015 &radeon_crtc->ss,
1016 dig->lcd_ss_id);
ba032a58
AD		 1017 break;
1018 case ATOM_ENCODER_MODE_DVI:
1019 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 1020 radeon_crtc->ss_enabled =
1021 radeon_atombios_get_asic_ss_info(rdev,
1022 &radeon_crtc->ss,
ba032a58
AD		 1023 ASIC_INTERNAL_SS_ON_TMDS,
1024 mode->clock / 10);
1025 break;
1026 case ATOM_ENCODER_MODE_HDMI:
1027 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 1028 radeon_crtc->ss_enabled =
1029 radeon_atombios_get_asic_ss_info(rdev,
1030 &radeon_crtc->ss,
ba032a58
AD		 1031 ASIC_INTERNAL_SS_ON_HDMI,
1032 mode->clock / 10);
1033 break;
1034 default:
1035 break;
1036 }
1037 }
1038
37f9003b 1039 /* adjust pixel clock as needed */
19eca43e
AD		 1040 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1041
1042 return true;
1043}
1044
1045static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1046{
1047 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1048 struct drm_device *dev = crtc->dev;
1049 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 1050 struct radeon_encoder *radeon_encoder =
1051 to_radeon_encoder(radeon_crtc->encoder);
19eca43e 1052 u32 pll_clock = mode->clock;
f71d9ebd 1053 u32 clock = mode->clock;
19eca43e
AD		 1054 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1055 struct radeon_pll *pll;
5df3196b 1056 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
19eca43e 1057
f71d9ebd 1058 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
5c868229 1059 if (ASIC_IS_DCE5(rdev) &&
f71d9ebd
AD		 1060 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1061 (radeon_crtc->bpc > 8))
1062 clock = radeon_crtc->adjusted_clock;
1063
19eca43e
AD		 1064 switch (radeon_crtc->pll_id) {
1065 case ATOM_PPLL1:
1066 pll = &rdev->clock.p1pll;
1067 break;
1068 case ATOM_PPLL2:
1069 pll = &rdev->clock.p2pll;
1070 break;
1071 case ATOM_DCPLL:
1072 case ATOM_PPLL_INVALID:
1073 default:
1074 pll = &rdev->clock.dcpll;
1075 break;
1076 }
1077
1078 /* update pll params */
1079 pll->flags = radeon_crtc->pll_flags;
1080 pll->reference_div = radeon_crtc->pll_reference_div;
1081 pll->post_div = radeon_crtc->pll_post_div;
37f9003b 1082
64146f8b
AD		 1083 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1084 /* TV seems to prefer the legacy algo on some boards */
19eca43e
AD		 1085 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1086 &fb_div, &frac_fb_div, &ref_div, &post_div);
64146f8b 1087 else if (ASIC_IS_AVIVO(rdev))
19eca43e
AD		 1088 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1089 &fb_div, &frac_fb_div, &ref_div, &post_div);
619efb10 1090 else
19eca43e
AD		 1091 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1092 &fb_div, &frac_fb_div, &ref_div, &post_div);
37f9003b 1093
19eca43e
AD		 1094 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1095 radeon_crtc->crtc_id, &radeon_crtc->ss);
ba032a58 1096
37f9003b 1097 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
f71d9ebd 1098 encoder_mode, radeon_encoder->encoder_id, clock,
19eca43e
AD		 1099 ref_div, fb_div, frac_fb_div, post_div,
1100 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
37f9003b 1101
19eca43e 1102 if (radeon_crtc->ss_enabled) {
ba032a58
AD		 1103 /* calculate ss amount and step size */
1104 if (ASIC_IS_DCE4(rdev)) {
1105 u32 step_size;
18f8f52b
AD		 1106 u32 amount = (((fb_div * 10) + frac_fb_div) *
1107 (u32)radeon_crtc->ss.percentage) /
1108 (100 * (u32)radeon_crtc->ss.percentage_divider);
19eca43e
AD		 1109 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1110 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
ba032a58 1111 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
19eca43e 1112 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
18f8f52b 1113 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
ba032a58
AD		 1114 (125 * 25 * pll->reference_freq / 100);
1115 else
18f8f52b 1116 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
ba032a58 1117 (125 * 25 * pll->reference_freq / 100);
19eca43e 1118 radeon_crtc->ss.step = step_size;
ba032a58
AD		 1119 }
1120
19eca43e
AD		 1121 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1122 radeon_crtc->crtc_id, &radeon_crtc->ss);
ba032a58 1123 }
37f9003b
AD		 1124}
1125
c9417bdd
AD		 1126static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1127 struct drm_framebuffer *fb,
1128 int x, int y, int atomic)
bcc1c2a1
AD		 1129{
1130 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1131 struct drm_device *dev = crtc->dev;
1132 struct radeon_device *rdev = dev->dev_private;
1133 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1134 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1135 struct drm_gem_object *obj;
1136 struct radeon_bo *rbo;
1137 uint64_t fb_location;
1138 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
285484e2 1139 unsigned bankw, bankh, mtaspect, tile_split;
fa6bee46 1140 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
adcfde51 1141 u32 tmp, viewport_w, viewport_h;
bcc1c2a1 1142 int r;
4366f3b5 1143 bool bypass_lut = false;
bcc1c2a1
AD		 1144
1145 /* no fb bound */
f4510a27 1146 if (!atomic && !crtc->primary->fb) {
d9fdaafb 1147 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1148 return 0;
1149 }
1150
4dd19b0d
CB		 1151 if (atomic) {
1152 radeon_fb = to_radeon_framebuffer(fb);
1153 target_fb = fb;
1154 }
1155 else {
f4510a27
MR		 1156 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1157 target_fb = crtc->primary->fb;
4dd19b0d 1158 }
bcc1c2a1 1159
4dd19b0d
CB		 1160 /* If atomic, assume fb object is pinned & idle & fenced and
1161 * just update base pointers
1162 */
bcc1c2a1 1163 obj = radeon_fb->obj;
7e4d15d9 1164 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1165 r = radeon_bo_reserve(rbo, false);
1166 if (unlikely(r != 0))
1167 return r;
4dd19b0d
CB		 1168
1169 if (atomic)
1170 fb_location = radeon_bo_gpu_offset(rbo);
1171 else {
1172 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1173 if (unlikely(r != 0)) {
1174 radeon_bo_unreserve(rbo);
1175 return -EINVAL;
1176 }
bcc1c2a1 1177 }
4dd19b0d 1178
bcc1c2a1
AD		 1179 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1180 radeon_bo_unreserve(rbo);
1181
8bae4276
FH		 1182 switch (target_fb->pixel_format) {
1183 case DRM_FORMAT_C8:
bcc1c2a1
AD		 1184 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1185 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1186 break;
8bae4276
FH		 1187 case DRM_FORMAT_XRGB4444:
1188 case DRM_FORMAT_ARGB4444:
1189 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1190 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1191#ifdef __BIG_ENDIAN
1192 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1193#endif
1194 break;
1195 case DRM_FORMAT_XRGB1555:
1196 case DRM_FORMAT_ARGB1555:
bcc1c2a1
AD		 1197 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1198 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
8bae4276
FH		 1199#ifdef __BIG_ENDIAN
1200 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1201#endif
bcc1c2a1 1202 break;
8bae4276
FH		 1203 case DRM_FORMAT_BGRX5551:
1204 case DRM_FORMAT_BGRA5551:
1205 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1206 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1207#ifdef __BIG_ENDIAN
1208 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1209#endif
1210 break;
1211 case DRM_FORMAT_RGB565:
bcc1c2a1
AD		 1212 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1213 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1214#ifdef __BIG_ENDIAN
1215 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1216#endif
bcc1c2a1 1217 break;
8bae4276
FH		 1218 case DRM_FORMAT_XRGB8888:
1219 case DRM_FORMAT_ARGB8888:
bcc1c2a1
AD		 1220 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1221 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1222#ifdef __BIG_ENDIAN
1223 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
8bae4276
FH		 1224#endif
1225 break;
1226 case DRM_FORMAT_XRGB2101010:
1227 case DRM_FORMAT_ARGB2101010:
1228 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1229 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1230#ifdef __BIG_ENDIAN
1231 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1232#endif
4366f3b5
MK		 1233 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1234 bypass_lut = true;
8bae4276
FH		 1235 break;
1236 case DRM_FORMAT_BGRX1010102:
1237 case DRM_FORMAT_BGRA1010102:
1238 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1239 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1240#ifdef __BIG_ENDIAN
1241 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
fa6bee46 1242#endif
4366f3b5
MK		 1243 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1244 bypass_lut = true;
bcc1c2a1
AD		 1245 break;
1246 default:
8bae4276
FH		 1247 DRM_ERROR("Unsupported screen format %s\n",
1248 drm_get_format_name(target_fb->pixel_format));
bcc1c2a1
AD		 1249 return -EINVAL;
1250 }
1251
392e3722 1252 if (tiling_flags & RADEON_TILING_MACRO) {
e3ea94a6 1253 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
392e3722 1254
e3ea94a6 1255 /* Set NUM_BANKS. */
6d8ea7de 1256 if (rdev->family >= CHIP_TAHITI) {
e9d14aeb 1257 unsigned index, num_banks;
e3ea94a6 1258
e9d14aeb
MD		 1259 if (rdev->family >= CHIP_BONAIRE) {
1260 unsigned tileb, tile_split_bytes;
e3ea94a6 1261
e9d14aeb
MD		 1262 /* Calculate the macrotile mode index. */
1263 tile_split_bytes = 64 << tile_split;
1264 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1265 tileb = min(tile_split_bytes, tileb);
e3ea94a6 1266
e9d14aeb
MD		 1267 for (index = 0; tileb > 64; index++)
1268 tileb >>= 1;
1269
1270 if (index >= 16) {
1271 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1272 target_fb->bits_per_pixel, tile_split);
1273 return -EINVAL;
1274 }
e3ea94a6 1275
6d8ea7de 1276 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
e9d14aeb
MD		 1277 } else {
1278 switch (target_fb->bits_per_pixel) {
1279 case 8:
1280 index = 10;
1281 break;
1282 case 16:
1283 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1284 break;
1285 default:
1286 case 32:
1287 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1288 break;
1289 }
1290
6d8ea7de 1291 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
e9d14aeb
MD		 1292 }
1293
e3ea94a6
MO		 1294 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1295 } else {
6d8ea7de
AD		 1296 /* NI and older. */
1297 if (rdev->family >= CHIP_CAYMAN)
e3ea94a6
MO		 1298 tmp = rdev->config.cayman.tile_config;
1299 else
1300 tmp = rdev->config.evergreen.tile_config;
1301
1302 switch ((tmp & 0xf0) >> 4) {
1303 case 0: /* 4 banks */
1304 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1305 break;
1306 case 1: /* 8 banks */
1307 default:
1308 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1309 break;
1310 case 2: /* 16 banks */
1311 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1312 break;
1313 }
392e3722
AD		 1314 }
1315
97d66328 1316 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
285484e2
JG		 1317 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1318 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1319 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1320 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
8da0e500
AD		 1321 if (rdev->family >= CHIP_BONAIRE) {
1322 /* XXX need to know more about the surface tiling mode */
1323 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1324 }
392e3722 1325 } else if (tiling_flags & RADEON_TILING_MICRO)
97d66328
AD		 1326 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1327
8da0e500 1328 if (rdev->family >= CHIP_BONAIRE) {
35a90528
MO		 1329 /* Read the pipe config from the 2D TILED SCANOUT mode.
1330 * It should be the same for the other modes too, but not all
1331 * modes set the pipe config field. */
1332 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1333
1334 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
8da0e500
AD		 1335 } else if ((rdev->family == CHIP_TAHITI) ||
1336 (rdev->family == CHIP_PITCAIRN))
b7019b2f 1337 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
227ae10f
AD		 1338 else if ((rdev->family == CHIP_VERDE) ||
1339 (rdev->family == CHIP_OLAND) ||
1340 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
b7019b2f
AD		 1341 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1342
bcc1c2a1
AD		 1343 switch (radeon_crtc->crtc_id) {
1344 case 0:
1345 WREG32(AVIVO_D1VGA_CONTROL, 0);
1346 break;
1347 case 1:
1348 WREG32(AVIVO_D2VGA_CONTROL, 0);
1349 break;
1350 case 2:
1351 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1352 break;
1353 case 3:
1354 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1355 break;
1356 case 4:
1357 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1358 break;
1359 case 5:
1360 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1361 break;
1362 default:
1363 break;
1364 }
1365
1366 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1367 upper_32_bits(fb_location));
1368 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1369 upper_32_bits(fb_location));
1370 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1371 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1372 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1373 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1374 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1375 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1 1376
4366f3b5
MK		 1377 /*
1378 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1379 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1380 * retain the full precision throughout the pipeline.
1381 */
1382 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1383 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1384 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1385
1386 if (bypass_lut)
1387 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1388
bcc1c2a1
AD		 1389 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1390 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1391 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1392 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1393 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1394 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1395
01f2c773 1396 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1397 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1398 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1399
8da0e500
AD		 1400 if (rdev->family >= CHIP_BONAIRE)
1401 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1402 target_fb->height);
1403 else
1404 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1405 target_fb->height);
bcc1c2a1
AD		 1406 x &= ~3;
1407 y &= ~1;
1408 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1409 (x << 16) | y);
adcfde51
AD		 1410 viewport_w = crtc->mode.hdisplay;
1411 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
77ae5f4b
AD		 1412 if ((rdev->family >= CHIP_BONAIRE) &&
1413 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1414 viewport_h *= 2;
bcc1c2a1 1415 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1416 (viewport_w << 16) | viewport_h);
bcc1c2a1 1417
fb9674bd
AD		 1418 /* pageflip setup */
1419 /* make sure flip is at vb rather than hb */
1420 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1421 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1422 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1423
f53f81b2
MK		 1424 /* set pageflip to happen only at start of vblank interval (front porch) */
1425 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
fb9674bd 1426
f4510a27 1427 if (!atomic && fb && fb != crtc->primary->fb) {
4dd19b0d 1428 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1429 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1430 r = radeon_bo_reserve(rbo, false);
1431 if (unlikely(r != 0))
1432 return r;
1433 radeon_bo_unpin(rbo);
1434 radeon_bo_unreserve(rbo);
1435 }
1436
1437 /* Bytes per pixel may have changed */
1438 radeon_bandwidth_update(rdev);
1439
1440 return 0;
1441}
1442
4dd19b0d
CB		 1443static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1444 struct drm_framebuffer *fb,
1445 int x, int y, int atomic)
771fe6b9
JG		 1446{
1447 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1448 struct drm_device *dev = crtc->dev;
1449 struct radeon_device *rdev = dev->dev_private;
1450 struct radeon_framebuffer *radeon_fb;
1451 struct drm_gem_object *obj;
4c788679 1452 struct radeon_bo *rbo;
4dd19b0d 1453 struct drm_framebuffer *target_fb;
771fe6b9 1454 uint64_t fb_location;
e024e110 1455 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1456 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
adcfde51 1457 u32 tmp, viewport_w, viewport_h;
4c788679 1458 int r;
4366f3b5 1459 bool bypass_lut = false;
771fe6b9 1460
2de3b484 1461 /* no fb bound */
f4510a27 1462 if (!atomic && !crtc->primary->fb) {
d9fdaafb 1463 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1464 return 0;
1465 }
771fe6b9 1466
4dd19b0d
CB		 1467 if (atomic) {
1468 radeon_fb = to_radeon_framebuffer(fb);
1469 target_fb = fb;
1470 }
1471 else {
f4510a27
MR		 1472 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1473 target_fb = crtc->primary->fb;
4dd19b0d 1474 }
771fe6b9
JG		 1475
1476 obj = radeon_fb->obj;
7e4d15d9 1477 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1478 r = radeon_bo_reserve(rbo, false);
1479 if (unlikely(r != 0))
1480 return r;
4dd19b0d
CB		 1481
1482 /* If atomic, assume fb object is pinned & idle & fenced and
1483 * just update base pointers
1484 */
1485 if (atomic)
1486 fb_location = radeon_bo_gpu_offset(rbo);
1487 else {
1488 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1489 if (unlikely(r != 0)) {
1490 radeon_bo_unreserve(rbo);
1491 return -EINVAL;
1492 }
771fe6b9 1493 }
4c788679
JG		 1494 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1495 radeon_bo_unreserve(rbo);
771fe6b9 1496
8bae4276
FH		 1497 switch (target_fb->pixel_format) {
1498 case DRM_FORMAT_C8:
41456df2
DA		 1499 fb_format =
1500 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1501 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1502 break;
8bae4276
FH		 1503 case DRM_FORMAT_XRGB4444:
1504 case DRM_FORMAT_ARGB4444:
1505 fb_format =
1506 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1507 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1508#ifdef __BIG_ENDIAN
1509 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1510#endif
1511 break;
1512 case DRM_FORMAT_XRGB1555:
771fe6b9
JG		 1513 fb_format =
1514 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1515 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
8bae4276
FH		 1516#ifdef __BIG_ENDIAN
1517 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1518#endif
771fe6b9 1519 break;
8bae4276 1520 case DRM_FORMAT_RGB565:
771fe6b9
JG		 1521 fb_format =
1522 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1523 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1524#ifdef __BIG_ENDIAN
1525 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1526#endif
771fe6b9 1527 break;
8bae4276
FH		 1528 case DRM_FORMAT_XRGB8888:
1529 case DRM_FORMAT_ARGB8888:
771fe6b9
JG		 1530 fb_format =
1531 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1532 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1533#ifdef __BIG_ENDIAN
1534 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
8bae4276
FH		 1535#endif
1536 break;
1537 case DRM_FORMAT_XRGB2101010:
1538 case DRM_FORMAT_ARGB2101010:
1539 fb_format =
1540 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1541 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1542#ifdef __BIG_ENDIAN
1543 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
fa6bee46 1544#endif
4366f3b5
MK		 1545 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1546 bypass_lut = true;
771fe6b9
JG		 1547 break;
1548 default:
8bae4276
FH		 1549 DRM_ERROR("Unsupported screen format %s\n",
1550 drm_get_format_name(target_fb->pixel_format));
771fe6b9
JG		 1551 return -EINVAL;
1552 }
1553
40c4ac1c
AD		 1554 if (rdev->family >= CHIP_R600) {
1555 if (tiling_flags & RADEON_TILING_MACRO)
1556 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1557 else if (tiling_flags & RADEON_TILING_MICRO)
1558 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1559 } else {
1560 if (tiling_flags & RADEON_TILING_MACRO)
1561 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1562
40c4ac1c
AD		 1563 if (tiling_flags & RADEON_TILING_MICRO)
1564 fb_format |= AVIVO_D1GRPH_TILED;
1565 }
e024e110 1566
771fe6b9
JG		 1567 if (radeon_crtc->crtc_id == 0)
1568 WREG32(AVIVO_D1VGA_CONTROL, 0);
1569 else
1570 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1571
1572 if (rdev->family >= CHIP_RV770) {
1573 if (radeon_crtc->crtc_id) {
95347871
AD		 1574 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1575 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1576 } else {
95347871
AD		 1577 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1578 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1579 }
1580 }
771fe6b9
JG		 1581 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1582 (u32) fb_location);
1583 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1584 radeon_crtc->crtc_offset, (u32) fb_location);
1585 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1586 if (rdev->family >= CHIP_R600)
1587 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9 1588
4366f3b5
MK		 1589 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1590 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1591 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1592
1593 if (bypass_lut)
1594 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1595
771fe6b9
JG		 1596 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1597 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1598 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1599 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1600 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1601 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1602
01f2c773 1603 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1604 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1605 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1606
1607 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1b619250 1608 target_fb->height);
771fe6b9
JG		 1609 x &= ~3;
1610 y &= ~1;
1611 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1612 (x << 16) | y);
adcfde51
AD		 1613 viewport_w = crtc->mode.hdisplay;
1614 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
771fe6b9 1615 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1616 (viewport_w << 16) | viewport_h);
771fe6b9 1617
fb9674bd
AD		 1618 /* pageflip setup */
1619 /* make sure flip is at vb rather than hb */
1620 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1621 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1622 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1623
f53f81b2
MK		 1624 /* set pageflip to happen only at start of vblank interval (front porch) */
1625 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
fb9674bd 1626
f4510a27 1627 if (!atomic && fb && fb != crtc->primary->fb) {
4dd19b0d 1628 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1629 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1630 r = radeon_bo_reserve(rbo, false);
1631 if (unlikely(r != 0))
1632 return r;
1633 radeon_bo_unpin(rbo);
1634 radeon_bo_unreserve(rbo);
771fe6b9 1635 }
f30f37de
MD		 1636
1637 /* Bytes per pixel may have changed */
1638 radeon_bandwidth_update(rdev);
1639
771fe6b9
JG		 1640 return 0;
1641}
1642
54f088a9
AD		 1643int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1644 struct drm_framebuffer *old_fb)
1645{
1646 struct drm_device *dev = crtc->dev;
1647 struct radeon_device *rdev = dev->dev_private;
1648
bcc1c2a1 1649 if (ASIC_IS_DCE4(rdev))
c9417bdd 1650 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1651 else if (ASIC_IS_AVIVO(rdev))
1652 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1653 else
1654 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1655}
1656
1657int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1658 struct drm_framebuffer *fb,
21c74a8e 1659 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1660{
1661 struct drm_device *dev = crtc->dev;
1662 struct radeon_device *rdev = dev->dev_private;
1663
1664 if (ASIC_IS_DCE4(rdev))
c9417bdd 1665 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1666 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1667 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1668 else
4dd19b0d 1669 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1670}
1671
615e0cb6
AD		 1672/* properly set additional regs when using atombios */
1673static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1674{
1675 struct drm_device *dev = crtc->dev;
1676 struct radeon_device *rdev = dev->dev_private;
1677 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1678 u32 disp_merge_cntl;
1679
1680 switch (radeon_crtc->crtc_id) {
1681 case 0:
1682 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1683 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1684 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1685 break;
1686 case 1:
1687 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1688 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1689 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1690 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1691 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1692 break;
1693 }
1694}
1695
f3dd8508
AD		 1696/**
1697 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1698 *
1699 * @crtc: drm crtc
1700 *
1701 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1702 */
1703static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1704{
1705 struct drm_device *dev = crtc->dev;
1706 struct drm_crtc *test_crtc;
57b35e29 1707 struct radeon_crtc *test_radeon_crtc;
f3dd8508
AD		 1708 u32 pll_in_use = 0;
1709
1710 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1711 if (crtc == test_crtc)
1712 continue;
1713
57b35e29
AD		 1714 test_radeon_crtc = to_radeon_crtc(test_crtc);
1715 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1716 pll_in_use |= (1 << test_radeon_crtc->pll_id);
f3dd8508
AD		 1717 }
1718 return pll_in_use;
1719}
1720
1721/**
1722 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1723 *
1724 * @crtc: drm crtc
1725 *
1726 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1727 * also in DP mode. For DP, a single PPLL can be used for all DP
1728 * crtcs/encoders.
1729 */
1730static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1731{
1732 struct drm_device *dev = crtc->dev;
57b35e29 1733 struct drm_crtc *test_crtc;
5df3196b 1734 struct radeon_crtc *test_radeon_crtc;
f3dd8508 1735
57b35e29
AD		 1736 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1737 if (crtc == test_crtc)
1738 continue;
1739 test_radeon_crtc = to_radeon_crtc(test_crtc);
1740 if (test_radeon_crtc->encoder &&
1741 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1742 /* for DP use the same PLL for all */
1743 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1744 return test_radeon_crtc->pll_id;
f3dd8508
AD		 1745 }
1746 }
1747 return ATOM_PPLL_INVALID;
1748}
1749
2f454cf1
AD		 1750/**
1751 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1752 *
1753 * @crtc: drm crtc
1754 * @encoder: drm encoder
1755 *
1756 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1757 * be shared (i.e., same clock).
1758 */
5df3196b 1759static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
2f454cf1 1760{
5df3196b 1761 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2f454cf1 1762 struct drm_device *dev = crtc->dev;
9642ac0e 1763 struct drm_crtc *test_crtc;
5df3196b 1764 struct radeon_crtc *test_radeon_crtc;
9642ac0e 1765 u32 adjusted_clock, test_adjusted_clock;
2f454cf1 1766
9642ac0e
AD		 1767 adjusted_clock = radeon_crtc->adjusted_clock;
1768
1769 if (adjusted_clock == 0)
1770 return ATOM_PPLL_INVALID;
2f454cf1 1771
57b35e29
AD		 1772 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1773 if (crtc == test_crtc)
1774 continue;
1775 test_radeon_crtc = to_radeon_crtc(test_crtc);
1776 if (test_radeon_crtc->encoder &&
1777 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1778 /* check if we are already driving this connector with another crtc */
1779 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1780 /* if we are, return that pll */
1781 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
5df3196b 1782 return test_radeon_crtc->pll_id;
2f454cf1 1783 }
57b35e29
AD		 1784 /* for non-DP check the clock */
1785 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1786 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1787 (adjusted_clock == test_adjusted_clock) &&
1788 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1789 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1790 return test_radeon_crtc->pll_id;
2f454cf1
AD		 1791 }
1792 }
1793 return ATOM_PPLL_INVALID;
1794}
1795
f3dd8508
AD		 1796/**
1797 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1798 *
1799 * @crtc: drm crtc
1800 *
1801 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1802 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1803 * monitors a dedicated PPLL must be used. If a particular board has
1804 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1805 * as there is no need to program the PLL itself. If we are not able to
1806 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1807 * avoid messing up an existing monitor.
1808 *
1809 * Asic specific PLL information
1810 *
0331f674
AD		 1811 * DCE 8.x
1812 * KB/KV
1813 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1814 * CI
1815 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1816 *
f3dd8508
AD		 1817 * DCE 6.1
1818 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1819 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1820 *
1821 * DCE 6.0
1822 * - PPLL0 is available to all UNIPHY (DP only)
1823 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1824 *
1825 * DCE 5.0
1826 * - DCPLL is available to all UNIPHY (DP only)
1827 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1828 *
1829 * DCE 3.0/4.0/4.1
1830 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1831 *
1832 */
bcc1c2a1
AD		 1833static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1834{
5df3196b 1835 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
bcc1c2a1
AD		 1836 struct drm_device *dev = crtc->dev;
1837 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 1838 struct radeon_encoder *radeon_encoder =
1839 to_radeon_encoder(radeon_crtc->encoder);
f3dd8508
AD		 1840 u32 pll_in_use;
1841 int pll;
bcc1c2a1 1842
0331f674
AD		 1843 if (ASIC_IS_DCE8(rdev)) {
1844 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1845 if (rdev->clock.dp_extclk)
1846 /* skip PPLL programming if using ext clock */
1847 return ATOM_PPLL_INVALID;
1848 else {
1849 /* use the same PPLL for all DP monitors */
1850 pll = radeon_get_shared_dp_ppll(crtc);
1851 if (pll != ATOM_PPLL_INVALID)
1852 return pll;
1853 }
1854 } else {
1855 /* use the same PPLL for all monitors with the same clock */
1856 pll = radeon_get_shared_nondp_ppll(crtc);
1857 if (pll != ATOM_PPLL_INVALID)
1858 return pll;
1859 }
1860 /* otherwise, pick one of the plls */
fbedf1c3 1861 if ((rdev->family == CHIP_KABINI) ||
b214f2a4 1862 (rdev->family == CHIP_MULLINS)) {
fbedf1c3 1863 /* KB/ML has PPLL1 and PPLL2 */
0331f674
AD		 1864 pll_in_use = radeon_get_pll_use_mask(crtc);
1865 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1866 return ATOM_PPLL2;
1867 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1868 return ATOM_PPLL1;
1869 DRM_ERROR("unable to allocate a PPLL\n");
1870 return ATOM_PPLL_INVALID;
1871 } else {
fbedf1c3 1872 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
0331f674
AD		 1873 pll_in_use = radeon_get_pll_use_mask(crtc);
1874 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1875 return ATOM_PPLL2;
1876 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1877 return ATOM_PPLL1;
1878 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1879 return ATOM_PPLL0;
1880 DRM_ERROR("unable to allocate a PPLL\n");
1881 return ATOM_PPLL_INVALID;
1882 }
1883 } else if (ASIC_IS_DCE61(rdev)) {
5df3196b
AD		 1884 struct radeon_encoder_atom_dig *dig =
1885 radeon_encoder->enc_priv;
1886
1887 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1888 (dig->linkb == false))
1889 /* UNIPHY A uses PPLL2 */
1890 return ATOM_PPLL2;
1891 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1892 /* UNIPHY B/C/D/E/F */
1893 if (rdev->clock.dp_extclk)
1894 /* skip PPLL programming if using ext clock */
1895 return ATOM_PPLL_INVALID;
1896 else {
1897 /* use the same PPLL for all DP monitors */
1898 pll = radeon_get_shared_dp_ppll(crtc);
1899 if (pll != ATOM_PPLL_INVALID)
1900 return pll;
24e1f794 1901 }
5df3196b
AD		 1902 } else {
1903 /* use the same PPLL for all monitors with the same clock */
1904 pll = radeon_get_shared_nondp_ppll(crtc);
1905 if (pll != ATOM_PPLL_INVALID)
1906 return pll;
24e1f794
AD		 1907 }
1908 /* UNIPHY B/C/D/E/F */
f3dd8508
AD		 1909 pll_in_use = radeon_get_pll_use_mask(crtc);
1910 if (!(pll_in_use & (1 << ATOM_PPLL0)))
24e1f794 1911 return ATOM_PPLL0;
f3dd8508
AD		 1912 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1913 return ATOM_PPLL1;
1914 DRM_ERROR("unable to allocate a PPLL\n");
1915 return ATOM_PPLL_INVALID;
9ef4e1d0
AD		 1916 } else if (ASIC_IS_DCE41(rdev)) {
1917 /* Don't share PLLs on DCE4.1 chips */
1918 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1919 if (rdev->clock.dp_extclk)
1920 /* skip PPLL programming if using ext clock */
1921 return ATOM_PPLL_INVALID;
1922 }
1923 pll_in_use = radeon_get_pll_use_mask(crtc);
1924 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1925 return ATOM_PPLL1;
1926 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1927 return ATOM_PPLL2;
1928 DRM_ERROR("unable to allocate a PPLL\n");
1929 return ATOM_PPLL_INVALID;
24e1f794 1930 } else if (ASIC_IS_DCE4(rdev)) {
5df3196b
AD		 1931 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1932 * depending on the asic:
1933 * DCE4: PPLL or ext clock
1934 * DCE5: PPLL, DCPLL, or ext clock
1935 * DCE6: PPLL, PPLL0, or ext clock
1936 *
1937 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1938 * PPLL/DCPLL programming and only program the DP DTO for the
1939 * crtc virtual pixel clock.
1940 */
1941 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1942 if (rdev->clock.dp_extclk)
1943 /* skip PPLL programming if using ext clock */
1944 return ATOM_PPLL_INVALID;
1945 else if (ASIC_IS_DCE6(rdev))
1946 /* use PPLL0 for all DP */
1947 return ATOM_PPLL0;
1948 else if (ASIC_IS_DCE5(rdev))
1949 /* use DCPLL for all DP */
1950 return ATOM_DCPLL;
1951 else {
1952 /* use the same PPLL for all DP monitors */
1953 pll = radeon_get_shared_dp_ppll(crtc);
1954 if (pll != ATOM_PPLL_INVALID)
1955 return pll;
bcc1c2a1 1956 }
9ef4e1d0 1957 } else {
5df3196b
AD		 1958 /* use the same PPLL for all monitors with the same clock */
1959 pll = radeon_get_shared_nondp_ppll(crtc);
1960 if (pll != ATOM_PPLL_INVALID)
1961 return pll;
bcc1c2a1 1962 }
f3dd8508
AD		 1963 /* all other cases */
1964 pll_in_use = radeon_get_pll_use_mask(crtc);
f3dd8508 1965 if (!(pll_in_use & (1 << ATOM_PPLL1)))
bcc1c2a1 1966 return ATOM_PPLL1;
29dbe3bc
AD		 1967 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1968 return ATOM_PPLL2;
f3dd8508
AD		 1969 DRM_ERROR("unable to allocate a PPLL\n");
1970 return ATOM_PPLL_INVALID;
1e4db5f2
AD		 1971 } else {
1972 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
fc58acdb
JG		 1973 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1974 * the matching btw pll and crtc is done through
1975 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1976 * pll (1 or 2) to select which register to write. ie if using
1977 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1978 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1979 * choose which value to write. Which is reverse order from
1980 * register logic. So only case that works is when pllid is
1981 * same as crtcid or when both pll and crtc are enabled and
1982 * both use same clock.
1983 *
1984 * So just return crtc id as if crtc and pll were hard linked
1985 * together even if they aren't
1986 */
1e4db5f2 1987 return radeon_crtc->crtc_id;
2f454cf1 1988 }
bcc1c2a1
AD		 1989}
1990
f3f1f03e 1991void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
3fa47d9e
AD		 1992{
1993 /* always set DCPLL */
f3f1f03e
AD		 1994 if (ASIC_IS_DCE6(rdev))
1995 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1996 else if (ASIC_IS_DCE4(rdev)) {
3fa47d9e
AD		 1997 struct radeon_atom_ss ss;
1998 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1999 ASIC_INTERNAL_SS_ON_DCPLL,
2000 rdev->clock.default_dispclk);
2001 if (ss_enabled)
5efcc76c 2002 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
3fa47d9e 2003 /* XXX: DCE5, make sure voltage, dispclk is high enough */
f3f1f03e 2004 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
3fa47d9e 2005 if (ss_enabled)
5efcc76c 2006 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
3fa47d9e
AD		 2007 }
2008
2009}
2010
771fe6b9
JG		 2011int atombios_crtc_mode_set(struct drm_crtc *crtc,
2012 struct drm_display_mode *mode,
2013 struct drm_display_mode *adjusted_mode,
2014 int x, int y, struct drm_framebuffer *old_fb)
2015{
2016 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2017 struct drm_device *dev = crtc->dev;
2018 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 2019 struct radeon_encoder *radeon_encoder =
2020 to_radeon_encoder(radeon_crtc->encoder);
54bfe496 2021 bool is_tvcv = false;
771fe6b9 2022
5df3196b
AD		 2023 if (radeon_encoder->active_device &
2024 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2025 is_tvcv = true;
771fe6b9 2026
cde10122
CK		 2027 if (!radeon_crtc->adjusted_clock)
2028 return -EINVAL;
2029
771fe6b9 2030 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 2031
54bfe496 2032 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 2033 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 2034 else if (ASIC_IS_AVIVO(rdev)) {
2035 if (is_tvcv)
2036 atombios_crtc_set_timing(crtc, adjusted_mode);
2037 else
2038 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2039 } else {
bcc1c2a1 2040 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 2041 if (radeon_crtc->crtc_id == 0)
2042 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 2043 radeon_legacy_atom_fixup(crtc);
771fe6b9 2044 }
bcc1c2a1 2045 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 2046 atombios_overscan_setup(crtc, mode, adjusted_mode);
2047 atombios_scaler_setup(crtc);
6d3759fa 2048 radeon_cursor_reset(crtc);
66edc1c9
AD		 2049 /* update the hw version fpr dpm */
2050 radeon_crtc->hw_mode = *adjusted_mode;
2051
771fe6b9
JG		 2052 return 0;
2053}
2054
2055static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae 2056 const struct drm_display_mode *mode,
771fe6b9
JG		 2057 struct drm_display_mode *adjusted_mode)
2058{
5df3196b
AD		 2059 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2060 struct drm_device *dev = crtc->dev;
2061 struct drm_encoder *encoder;
2062
2063 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2064 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2065 if (encoder->crtc == crtc) {
2066 radeon_crtc->encoder = encoder;
57b35e29 2067 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
5df3196b
AD		 2068 break;
2069 }
2070 }
57b35e29
AD		 2071 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2072 radeon_crtc->encoder = NULL;
2073 radeon_crtc->connector = NULL;
5df3196b 2074 return false;
57b35e29 2075 }
643b1f56
AD		 2076 if (radeon_crtc->encoder) {
2077 struct radeon_encoder *radeon_encoder =
2078 to_radeon_encoder(radeon_crtc->encoder);
2079
2080 radeon_crtc->output_csc = radeon_encoder->output_csc;
2081 }
c93bb85b
JG		 2082 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2083 return false;
19eca43e
AD		 2084 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2085 return false;
c0fd0834
AD		 2086 /* pick pll */
2087 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2088 /* if we can't get a PPLL for a non-DP encoder, fail */
2089 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2090 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2091 return false;
2092
771fe6b9
JG		 2093 return true;
2094}
2095
2096static void atombios_crtc_prepare(struct drm_crtc *crtc)
2097{
6c0ae2ab
AD		 2098 struct drm_device *dev = crtc->dev;
2099 struct radeon_device *rdev = dev->dev_private;
267364ac 2100
6c0ae2ab
AD		 2101 /* disable crtc pair power gating before programming */
2102 if (ASIC_IS_DCE6(rdev))
2103 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2104
37b4390e 2105 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 2106 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 2107}
2108
2109static void atombios_crtc_commit(struct drm_crtc *crtc)
2110{
2111 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 2112 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 2113}
2114
37f9003b
AD		 2115static void atombios_crtc_disable(struct drm_crtc *crtc)
2116{
2117 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
64199870
AD		 2118 struct drm_device *dev = crtc->dev;
2119 struct radeon_device *rdev = dev->dev_private;
8e8e523d 2120 struct radeon_atom_ss ss;
4e58591c 2121 int i;
8e8e523d 2122
37f9003b 2123 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
f4510a27 2124 if (crtc->primary->fb) {
75b871e2
IH		 2125 int r;
2126 struct radeon_framebuffer *radeon_fb;
2127 struct radeon_bo *rbo;
2128
f4510a27 2129 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
75b871e2
IH		 2130 rbo = gem_to_radeon_bo(radeon_fb->obj);
2131 r = radeon_bo_reserve(rbo, false);
2132 if (unlikely(r))
2133 DRM_ERROR("failed to reserve rbo before unpin\n");
2134 else {
2135 radeon_bo_unpin(rbo);
2136 radeon_bo_unreserve(rbo);
2137 }
2138 }
ac4d04d4
AD		 2139 /* disable the GRPH */
2140 if (ASIC_IS_DCE4(rdev))
2141 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2142 else if (ASIC_IS_AVIVO(rdev))
2143 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2144
0e3d50bf
AD		 2145 if (ASIC_IS_DCE6(rdev))
2146 atombios_powergate_crtc(crtc, ATOM_ENABLE);
37f9003b 2147
4e58591c
AD		 2148 for (i = 0; i < rdev->num_crtc; i++) {
2149 if (rdev->mode_info.crtcs[i] &&
2150 rdev->mode_info.crtcs[i]->enabled &&
2151 i != radeon_crtc->crtc_id &&
2152 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2153 /* one other crtc is using this pll don't turn
2154 * off the pll
2155 */
2156 goto done;
2157 }
2158 }
2159
37f9003b
AD		 2160 switch (radeon_crtc->pll_id) {
2161 case ATOM_PPLL1:
2162 case ATOM_PPLL2:
2163 /* disable the ppll */
2164 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
8e8e523d 2165 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
37f9003b 2166 break;
64199870
AD		 2167 case ATOM_PPLL0:
2168 /* disable the ppll */
7eeeabfc 2169 if ((rdev->family == CHIP_ARUBA) ||
fbedf1c3 2170 (rdev->family == CHIP_KAVERI) ||
7eeeabfc
AD		 2171 (rdev->family == CHIP_BONAIRE) ||
2172 (rdev->family == CHIP_HAWAII))
64199870
AD		 2173 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2174 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2175 break;
37f9003b
AD		 2176 default:
2177 break;
2178 }
4e58591c 2179done:
f3dd8508 2180 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
9642ac0e 2181 radeon_crtc->adjusted_clock = 0;
5df3196b 2182 radeon_crtc->encoder = NULL;
57b35e29 2183 radeon_crtc->connector = NULL;
37f9003b
AD		 2184}
2185
771fe6b9
JG		 2186static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2187 .dpms = atombios_crtc_dpms,
2188 .mode_fixup = atombios_crtc_mode_fixup,
2189 .mode_set = atombios_crtc_mode_set,
2190 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 2191 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 2192 .prepare = atombios_crtc_prepare,
2193 .commit = atombios_crtc_commit,
068143d3 2194 .load_lut = radeon_crtc_load_lut,
37f9003b 2195 .disable = atombios_crtc_disable,
771fe6b9
JG		 2196};
2197
2198void radeon_atombios_init_crtc(struct drm_device *dev,
2199 struct radeon_crtc *radeon_crtc)
2200{
bcc1c2a1
AD		 2201 struct radeon_device *rdev = dev->dev_private;
2202
2203 if (ASIC_IS_DCE4(rdev)) {
2204 switch (radeon_crtc->crtc_id) {
2205 case 0:
2206 default:
12d7798f 2207 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 2208 break;
2209 case 1:
12d7798f 2210 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 2211 break;
2212 case 2:
12d7798f 2213 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 2214 break;
2215 case 3:
12d7798f 2216 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 2217 break;
2218 case 4:
12d7798f 2219 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 2220 break;
2221 case 5:
12d7798f 2222 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 2223 break;
2224 }
2225 } else {
2226 if (radeon_crtc->crtc_id == 1)
2227 radeon_crtc->crtc_offset =
2228 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2229 else
2230 radeon_crtc->crtc_offset = 0;
2231 }
f3dd8508 2232 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
9642ac0e 2233 radeon_crtc->adjusted_clock = 0;
5df3196b 2234 radeon_crtc->encoder = NULL;
57b35e29 2235 radeon_crtc->connector = NULL;
771fe6b9
JG		 2236 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2237}
Linux 6.x block layer and io_uring tree(s)