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drm/radeon/kms: match r6xx/r7xx/evergreen asic_reset with previous asics
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
63 } else if (a2 > a1) {
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
5b1714d3
AD		 70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 258 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 261 radeon_crtc->enabled = false;
d7311171
AD		 262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 264 break;
265 }
771fe6b9
JG		 266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 270 struct drm_display_mode *mode)
771fe6b9 271{
5a9bcacc 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 277 u16 misc = 0;
771fe6b9 278
5a9bcacc 279 memset(&args, 0, sizeof(args));
5b1714d3 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 281 args.usH_Blanking_Time =
5b1714d3
AD		 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 284 args.usV_Blanking_Time =
5b1714d3 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 286 args.usH_SyncOffset =
5b1714d3 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
5b1714d3 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 310
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
54bfe496
AD		 336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
5a9bcacc
AD		 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a 401union atom_enable_ss {
ba032a58
AD		 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 407};
408
ba032a58
AD		 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
ebbe1cb9 413{
ebbe1cb9
AD		 414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
ebbe1cb9 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 417 union atom_enable_ss args;
ebbe1cb9 418
ba032a58 419 memset(&args, 0, sizeof(args));
bcc1c2a1 420
a572eaa3
AD		 421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = 0;
423 args.v3.ucSpreadSpectrumType = ss->type;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = ss->amount;
428 args.v3.usSpreadSpectrumStep = ss->step;
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = ss->amount;
433 args.v3.usSpreadSpectrumStep = ss->step;
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = 0;
438 args.v3.usSpreadSpectrumStep = 0;
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58
AD		 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type;
447 switch (pll_id) {
448 case ATOM_PPLL1:
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
450 args.v2.usSpreadSpectrumAmount = ss->amount;
451 args.v2.usSpreadSpectrumStep = ss->step;
452 break;
453 case ATOM_PPLL2:
454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
455 args.v2.usSpreadSpectrumAmount = ss->amount;
456 args.v2.usSpreadSpectrumStep = ss->step;
ebbe1cb9 457 break;
ba032a58
AD		 458 case ATOM_DCPLL:
459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
460 args.v2.usSpreadSpectrumAmount = 0;
461 args.v2.usSpreadSpectrumStep = 0;
462 break;
463 case ATOM_PPLL_INVALID:
464 return;
ebbe1cb9 465 }
ba032a58
AD		 466 args.v2.ucEnable = enable;
467 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type;
470 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) {
477 atombios_disable_ss(crtc);
478 return;
479 }
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 486 } else {
ba032a58
AD		 487 if (enable == ATOM_DISABLE) {
488 atombios_disable_ss(crtc);
489 return;
490 }
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable;
ebbe1cb9 496 }
26b9fc3a 497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 498}
499
4eaeca33
AD		 500union adjust_pixel_clock {
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 503};
504
505static u32 atombios_adjust_pll(struct drm_crtc *crtc,
506 struct drm_display_mode *mode,
ba032a58
AD		 507 struct radeon_pll *pll,
508 bool ss_enabled,
509 struct radeon_atom_ss *ss)
771fe6b9 510{
771fe6b9
JG		 511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 515 u32 adjusted_clock = mode->clock;
bcc1c2a1 516 int encoder_mode = 0;
fbee67a6
AD		 517 u32 dp_clock = mode->clock;
518 int bpc = 8;
fc10332b 519
4eaeca33
AD		 520 /* reset the pll flags */
521 pll->flags = 0;
771fe6b9
JG		 522
523 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 524 if ((rdev->family == CHIP_RS600) ||
525 (rdev->family == CHIP_RS690) ||
526 (rdev->family == CHIP_RS740))
2ff776cf 527 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 528 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 529
530 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
532 else
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
534 } else {
fc10332b 535 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 536
5480f727
DA		 537 if (mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 }
543
771fe6b9
JG		 544 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
545 if (encoder->crtc == crtc) {
4eaeca33 546 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 547 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6
AD		 548 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
549 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
550 if (connector) {
551 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
552 struct radeon_connector_atom_dig *dig_connector =
553 radeon_connector->con_priv;
554
555 dp_clock = dig_connector->dp_clock;
556 }
557 }
e5fd205f 558#if 0 /* doesn't work properly on some laptops */
ba032a58
AD		 559 /* use recommended ref_div for ss */
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
561 if (ss_enabled) {
562 if (ss->refdiv) {
563 pll->flags |= RADEON_PLL_USE_REF_DIV;
564 pll->reference_div = ss->refdiv;
565 }
566 }
567 }
e5fd205f 568#endif
4eaeca33
AD		 569 if (ASIC_IS_AVIVO(rdev)) {
570 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
571 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
572 adjusted_clock = mode->clock * 2;
48dfaaeb 573 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 574 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
4eaeca33
AD		 575 } else {
576 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 577 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 578 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 579 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 580 }
3ce0a23d 581 break;
771fe6b9
JG		 582 }
583 }
584
2606c886
AD		 585 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
586 * accordingly based on the encoder/transmitter to work around
587 * special hw requirements.
588 */
589 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 590 union adjust_pixel_clock args;
4eaeca33
AD		 591 u8 frev, crev;
592 int index;
2606c886 593
2606c886 594 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 595 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
596 &crev))
597 return adjusted_clock;
4eaeca33
AD		 598
599 memset(&args, 0, sizeof(args));
600
601 switch (frev) {
602 case 1:
603 switch (crev) {
604 case 1:
605 case 2:
606 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
607 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 608 args.v1.ucEncodeMode = encoder_mode;
fbee67a6 609 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
ba032a58
AD		 610 if (ss_enabled)
611 args.v1.ucConfig |=
612 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
fbee67a6
AD		 613 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
614 args.v1.ucConfig |=
615 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
616 }
4eaeca33
AD		 617
618 atom_execute_table(rdev->mode_info.atom_context,
619 index, (uint32_t *)&args);
620 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
621 break;
bcc1c2a1
AD		 622 case 3:
623 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
624 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
625 args.v3.sInput.ucEncodeMode = encoder_mode;
626 args.v3.sInput.ucDispPllConfig = 0;
627 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
628 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
fbee67a6 629 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
ba032a58
AD		 630 if (ss_enabled)
631 args.v3.sInput.ucDispPllConfig |=
632 DISPPLL_CONFIG_SS_ENABLE;
bcc1c2a1
AD		 633 args.v3.sInput.ucDispPllConfig |=
634 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 635 /* 16200 or 27000 */
636 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
637 } else {
638 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
639 /* deep color support */
640 args.v3.sInput.usPixelClock =
641 cpu_to_le16((mode->clock * bpc / 8) / 10);
642 }
bcc1c2a1
AD		 643 if (dig->coherent_mode)
644 args.v3.sInput.ucDispPllConfig |=
645 DISPPLL_CONFIG_COHERENT_MODE;
646 if (mode->clock > 165000)
647 args.v3.sInput.ucDispPllConfig |=
648 DISPPLL_CONFIG_DUAL_LINK;
649 }
650 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6 651 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
ba032a58
AD		 652 if (ss_enabled)
653 args.v3.sInput.ucDispPllConfig |=
654 DISPPLL_CONFIG_SS_ENABLE;
bcc1c2a1 655 args.v3.sInput.ucDispPllConfig |=
9f998ad7 656 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 657 /* 16200 or 27000 */
658 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
659 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
ba032a58
AD		 660 if (ss_enabled)
661 args.v3.sInput.ucDispPllConfig |=
662 DISPPLL_CONFIG_SS_ENABLE;
fbee67a6 663 } else {
9f998ad7
AD		 664 if (mode->clock > 165000)
665 args.v3.sInput.ucDispPllConfig |=
666 DISPPLL_CONFIG_DUAL_LINK;
667 }
bcc1c2a1
AD		 668 }
669 atom_execute_table(rdev->mode_info.atom_context,
670 index, (uint32_t *)&args);
671 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
672 if (args.v3.sOutput.ucRefDiv) {
673 pll->flags |= RADEON_PLL_USE_REF_DIV;
674 pll->reference_div = args.v3.sOutput.ucRefDiv;
675 }
676 if (args.v3.sOutput.ucPostDiv) {
677 pll->flags |= RADEON_PLL_USE_POST_DIV;
678 pll->post_div = args.v3.sOutput.ucPostDiv;
679 }
680 break;
4eaeca33
AD		 681 default:
682 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
683 return adjusted_clock;
684 }
685 break;
686 default:
687 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
688 return adjusted_clock;
689 }
d56ef9c8 690 }
4eaeca33
AD		 691 return adjusted_clock;
692}
693
694union set_pixel_clock {
695 SET_PIXEL_CLOCK_PS_ALLOCATION base;
696 PIXEL_CLOCK_PARAMETERS v1;
697 PIXEL_CLOCK_PARAMETERS_V2 v2;
698 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 699 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 700 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 701};
702
f82b3ddc
AD		 703/* on DCE5, make sure the voltage is high enough to support the
704 * required disp clk.
705 */
706static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
707 u32 dispclk)
bcc1c2a1
AD		 708{
709 struct drm_device *dev = crtc->dev;
710 struct radeon_device *rdev = dev->dev_private;
711 u8 frev, crev;
712 int index;
713 union set_pixel_clock args;
714
715 memset(&args, 0, sizeof(args));
716
717 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 718 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
719 &crev))
720 return;
bcc1c2a1
AD		 721
722 switch (frev) {
723 case 1:
724 switch (crev) {
725 case 5:
726 /* if the default dcpll clock is specified,
727 * SetPixelClock provides the dividers
728 */
729 args.v5.ucCRTC = ATOM_CRTC_INVALID;
f82b3ddc 730 args.v5.usPixelClock = dispclk;
bcc1c2a1
AD		 731 args.v5.ucPpll = ATOM_DCPLL;
732 break;
f82b3ddc
AD		 733 case 6:
734 /* if the default dcpll clock is specified,
735 * SetPixelClock provides the dividers
736 */
737 args.v6.ulDispEngClkFreq = dispclk;
738 args.v6.ucPpll = ATOM_DCPLL;
739 break;
bcc1c2a1
AD		 740 default:
741 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
742 return;
743 }
744 break;
745 default:
746 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
747 return;
748 }
749 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
750}
751
37f9003b
AD		 752static void atombios_crtc_program_pll(struct drm_crtc *crtc,
753 int crtc_id,
754 int pll_id,
755 u32 encoder_mode,
756 u32 encoder_id,
757 u32 clock,
758 u32 ref_div,
759 u32 fb_div,
760 u32 frac_fb_div,
761 u32 post_div)
4eaeca33 762{
4eaeca33
AD		 763 struct drm_device *dev = crtc->dev;
764 struct radeon_device *rdev = dev->dev_private;
4eaeca33 765 u8 frev, crev;
37f9003b 766 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 767 union set_pixel_clock args;
4eaeca33
AD		 768
769 memset(&args, 0, sizeof(args));
770
a084e6ee
AD		 771 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
772 &crev))
773 return;
771fe6b9
JG		 774
775 switch (frev) {
776 case 1:
777 switch (crev) {
778 case 1:
37f9003b
AD		 779 if (clock == ATOM_DISABLE)
780 return;
781 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 782 args.v1.usRefDiv = cpu_to_le16(ref_div);
783 args.v1.usFbDiv = cpu_to_le16(fb_div);
784 args.v1.ucFracFbDiv = frac_fb_div;
785 args.v1.ucPostDiv = post_div;
37f9003b
AD		 786 args.v1.ucPpll = pll_id;
787 args.v1.ucCRTC = crtc_id;
4eaeca33 788 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 789 break;
790 case 2:
37f9003b 791 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 792 args.v2.usRefDiv = cpu_to_le16(ref_div);
793 args.v2.usFbDiv = cpu_to_le16(fb_div);
794 args.v2.ucFracFbDiv = frac_fb_div;
795 args.v2.ucPostDiv = post_div;
37f9003b
AD		 796 args.v2.ucPpll = pll_id;
797 args.v2.ucCRTC = crtc_id;
4eaeca33 798 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 799 break;
800 case 3:
37f9003b 801 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 802 args.v3.usRefDiv = cpu_to_le16(ref_div);
803 args.v3.usFbDiv = cpu_to_le16(fb_div);
804 args.v3.ucFracFbDiv = frac_fb_div;
805 args.v3.ucPostDiv = post_div;
37f9003b
AD		 806 args.v3.ucPpll = pll_id;
807 args.v3.ucMiscInfo = (pll_id << 2);
808 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 809 args.v3.ucEncoderMode = encoder_mode;
810 break;
811 case 5:
37f9003b
AD		 812 args.v5.ucCRTC = crtc_id;
813 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 814 args.v5.ucRefDiv = ref_div;
815 args.v5.usFbDiv = cpu_to_le16(fb_div);
816 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
817 args.v5.ucPostDiv = post_div;
818 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 819 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 820 args.v5.ucEncoderMode = encoder_mode;
37f9003b 821 args.v5.ucPpll = pll_id;
771fe6b9 822 break;
f82b3ddc
AD		 823 case 6:
824 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
825 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
826 args.v6.ucRefDiv = ref_div;
827 args.v6.usFbDiv = cpu_to_le16(fb_div);
828 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
829 args.v6.ucPostDiv = post_div;
830 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
831 args.v6.ucTransmitterID = encoder_id;
832 args.v6.ucEncoderMode = encoder_mode;
833 args.v6.ucPpll = pll_id;
834 break;
771fe6b9
JG		 835 default:
836 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
837 return;
838 }
839 break;
840 default:
841 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
842 return;
843 }
844
771fe6b9
JG		 845 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
846}
847
37f9003b
AD		 848static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
849{
850 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
851 struct drm_device *dev = crtc->dev;
852 struct radeon_device *rdev = dev->dev_private;
853 struct drm_encoder *encoder = NULL;
854 struct radeon_encoder *radeon_encoder = NULL;
855 u32 pll_clock = mode->clock;
856 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
857 struct radeon_pll *pll;
858 u32 adjusted_clock;
859 int encoder_mode = 0;
ba032a58
AD		 860 struct radeon_atom_ss ss;
861 bool ss_enabled = false;
37f9003b
AD		 862
863 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
864 if (encoder->crtc == crtc) {
865 radeon_encoder = to_radeon_encoder(encoder);
866 encoder_mode = atombios_get_encoder_mode(encoder);
867 break;
868 }
869 }
870
871 if (!radeon_encoder)
872 return;
873
874 switch (radeon_crtc->pll_id) {
875 case ATOM_PPLL1:
876 pll = &rdev->clock.p1pll;
877 break;
878 case ATOM_PPLL2:
879 pll = &rdev->clock.p2pll;
880 break;
881 case ATOM_DCPLL:
882 case ATOM_PPLL_INVALID:
883 default:
884 pll = &rdev->clock.dcpll;
885 break;
886 }
887
ba032a58
AD		 888 if (radeon_encoder->active_device &
889 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
890 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
891 struct drm_connector *connector =
892 radeon_get_connector_for_encoder(encoder);
893 struct radeon_connector *radeon_connector =
894 to_radeon_connector(connector);
895 struct radeon_connector_atom_dig *dig_connector =
896 radeon_connector->con_priv;
897 int dp_clock;
898
899 switch (encoder_mode) {
900 case ATOM_ENCODER_MODE_DP:
901 /* DP/eDP */
902 dp_clock = dig_connector->dp_clock / 10;
903 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
904 if (ASIC_IS_DCE4(rdev))
905 ss_enabled =
906 radeon_atombios_get_asic_ss_info(rdev, &ss,
907 dig->lcd_ss_id,
908 dp_clock);
909 else
910 ss_enabled =
911 radeon_atombios_get_ppll_ss_info(rdev, &ss,
912 dig->lcd_ss_id);
913 } else {
914 if (ASIC_IS_DCE4(rdev))
915 ss_enabled =
916 radeon_atombios_get_asic_ss_info(rdev, &ss,
917 ASIC_INTERNAL_SS_ON_DP,
918 dp_clock);
919 else {
920 if (dp_clock == 16200) {
921 ss_enabled =
922 radeon_atombios_get_ppll_ss_info(rdev, &ss,
923 ATOM_DP_SS_ID2);
924 if (!ss_enabled)
925 ss_enabled =
926 radeon_atombios_get_ppll_ss_info(rdev, &ss,
927 ATOM_DP_SS_ID1);
928 } else
929 ss_enabled =
930 radeon_atombios_get_ppll_ss_info(rdev, &ss,
931 ATOM_DP_SS_ID1);
932 }
933 }
934 break;
935 case ATOM_ENCODER_MODE_LVDS:
936 if (ASIC_IS_DCE4(rdev))
937 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
938 dig->lcd_ss_id,
939 mode->clock / 10);
940 else
941 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
942 dig->lcd_ss_id);
943 break;
944 case ATOM_ENCODER_MODE_DVI:
945 if (ASIC_IS_DCE4(rdev))
946 ss_enabled =
947 radeon_atombios_get_asic_ss_info(rdev, &ss,
948 ASIC_INTERNAL_SS_ON_TMDS,
949 mode->clock / 10);
950 break;
951 case ATOM_ENCODER_MODE_HDMI:
952 if (ASIC_IS_DCE4(rdev))
953 ss_enabled =
954 radeon_atombios_get_asic_ss_info(rdev, &ss,
955 ASIC_INTERNAL_SS_ON_HDMI,
956 mode->clock / 10);
957 break;
958 default:
959 break;
960 }
961 }
962
37f9003b 963 /* adjust pixel clock as needed */
ba032a58 964 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b
AD		 965
966 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
967 &ref_div, &post_div);
968
ba032a58
AD		 969 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
970
37f9003b
AD		 971 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
972 encoder_mode, radeon_encoder->encoder_id, mode->clock,
973 ref_div, fb_div, frac_fb_div, post_div);
974
ba032a58
AD		 975 if (ss_enabled) {
976 /* calculate ss amount and step size */
977 if (ASIC_IS_DCE4(rdev)) {
978 u32 step_size;
979 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
980 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
981 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
982 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
983 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
984 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
985 (125 * 25 * pll->reference_freq / 100);
986 else
987 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
988 (125 * 25 * pll->reference_freq / 100);
989 ss.step = step_size;
990 }
991
992 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
993 }
37f9003b
AD		 994}
995
4dd19b0d
CB		 996static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
997 struct drm_framebuffer *fb,
998 int x, int y, int atomic)
bcc1c2a1
AD		 999{
1000 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1001 struct drm_device *dev = crtc->dev;
1002 struct radeon_device *rdev = dev->dev_private;
1003 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1004 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1005 struct drm_gem_object *obj;
1006 struct radeon_bo *rbo;
1007 uint64_t fb_location;
1008 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1009 int r;
1010
1011 /* no fb bound */
4dd19b0d 1012 if (!atomic && !crtc->fb) {
d9fdaafb 1013 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1014 return 0;
1015 }
1016
4dd19b0d
CB		 1017 if (atomic) {
1018 radeon_fb = to_radeon_framebuffer(fb);
1019 target_fb = fb;
1020 }
1021 else {
1022 radeon_fb = to_radeon_framebuffer(crtc->fb);
1023 target_fb = crtc->fb;
1024 }
bcc1c2a1 1025
4dd19b0d
CB		 1026 /* If atomic, assume fb object is pinned & idle & fenced and
1027 * just update base pointers
1028 */
bcc1c2a1
AD		 1029 obj = radeon_fb->obj;
1030 rbo = obj->driver_private;
1031 r = radeon_bo_reserve(rbo, false);
1032 if (unlikely(r != 0))
1033 return r;
4dd19b0d
CB		 1034
1035 if (atomic)
1036 fb_location = radeon_bo_gpu_offset(rbo);
1037 else {
1038 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1039 if (unlikely(r != 0)) {
1040 radeon_bo_unreserve(rbo);
1041 return -EINVAL;
1042 }
bcc1c2a1 1043 }
4dd19b0d 1044
bcc1c2a1
AD		 1045 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1046 radeon_bo_unreserve(rbo);
1047
4dd19b0d 1048 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1049 case 8:
1050 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1051 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1052 break;
1053 case 15:
1054 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1055 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1056 break;
1057 case 16:
1058 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1059 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1060 break;
1061 case 24:
1062 case 32:
1063 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1064 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1065 break;
1066 default:
1067 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1068 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1069 return -EINVAL;
1070 }
1071
97d66328
AD		 1072 if (tiling_flags & RADEON_TILING_MACRO)
1073 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1074 else if (tiling_flags & RADEON_TILING_MICRO)
1075 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1076
bcc1c2a1
AD		 1077 switch (radeon_crtc->crtc_id) {
1078 case 0:
1079 WREG32(AVIVO_D1VGA_CONTROL, 0);
1080 break;
1081 case 1:
1082 WREG32(AVIVO_D2VGA_CONTROL, 0);
1083 break;
1084 case 2:
1085 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1086 break;
1087 case 3:
1088 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1089 break;
1090 case 4:
1091 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1092 break;
1093 case 5:
1094 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1095 break;
1096 default:
1097 break;
1098 }
1099
1100 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1101 upper_32_bits(fb_location));
1102 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1103 upper_32_bits(fb_location));
1104 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1105 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1106 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1107 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1108 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1109
1110 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1111 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1112 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1113 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1114 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1115 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1116
4dd19b0d 1117 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1118 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1119 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1120
1121 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1122 crtc->mode.vdisplay);
1123 x &= ~3;
1124 y &= ~1;
1125 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1126 (x << 16) | y);
1127 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1128 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1129
1130 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1131 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1132 EVERGREEN_INTERLEAVE_EN);
1133 else
1134 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1135
4dd19b0d
CB		 1136 if (!atomic && fb && fb != crtc->fb) {
1137 radeon_fb = to_radeon_framebuffer(fb);
bcc1c2a1
AD		 1138 rbo = radeon_fb->obj->driver_private;
1139 r = radeon_bo_reserve(rbo, false);
1140 if (unlikely(r != 0))
1141 return r;
1142 radeon_bo_unpin(rbo);
1143 radeon_bo_unreserve(rbo);
1144 }
1145
1146 /* Bytes per pixel may have changed */
1147 radeon_bandwidth_update(rdev);
1148
1149 return 0;
1150}
1151
4dd19b0d
CB		 1152static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1153 struct drm_framebuffer *fb,
1154 int x, int y, int atomic)
771fe6b9
JG		 1155{
1156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1157 struct drm_device *dev = crtc->dev;
1158 struct radeon_device *rdev = dev->dev_private;
1159 struct radeon_framebuffer *radeon_fb;
1160 struct drm_gem_object *obj;
4c788679 1161 struct radeon_bo *rbo;
4dd19b0d 1162 struct drm_framebuffer *target_fb;
771fe6b9 1163 uint64_t fb_location;
e024e110 1164 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 1165 int r;
771fe6b9 1166
2de3b484 1167 /* no fb bound */
4dd19b0d 1168 if (!atomic && !crtc->fb) {
d9fdaafb 1169 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1170 return 0;
1171 }
771fe6b9 1172
4dd19b0d
CB		 1173 if (atomic) {
1174 radeon_fb = to_radeon_framebuffer(fb);
1175 target_fb = fb;
1176 }
1177 else {
1178 radeon_fb = to_radeon_framebuffer(crtc->fb);
1179 target_fb = crtc->fb;
1180 }
771fe6b9
JG		 1181
1182 obj = radeon_fb->obj;
4c788679
JG		 1183 rbo = obj->driver_private;
1184 r = radeon_bo_reserve(rbo, false);
1185 if (unlikely(r != 0))
1186 return r;
4dd19b0d
CB		 1187
1188 /* If atomic, assume fb object is pinned & idle & fenced and
1189 * just update base pointers
1190 */
1191 if (atomic)
1192 fb_location = radeon_bo_gpu_offset(rbo);
1193 else {
1194 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1195 if (unlikely(r != 0)) {
1196 radeon_bo_unreserve(rbo);
1197 return -EINVAL;
1198 }
771fe6b9 1199 }
4c788679
JG		 1200 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1201 radeon_bo_unreserve(rbo);
771fe6b9 1202
4dd19b0d 1203 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1204 case 8:
1205 fb_format =
1206 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1207 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1208 break;
771fe6b9
JG		 1209 case 15:
1210 fb_format =
1211 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1212 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1213 break;
1214 case 16:
1215 fb_format =
1216 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1217 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1218 break;
1219 case 24:
1220 case 32:
1221 fb_format =
1222 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1223 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1224 break;
1225 default:
1226 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1227 target_fb->bits_per_pixel);
771fe6b9
JG		 1228 return -EINVAL;
1229 }
1230
40c4ac1c
AD		 1231 if (rdev->family >= CHIP_R600) {
1232 if (tiling_flags & RADEON_TILING_MACRO)
1233 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1234 else if (tiling_flags & RADEON_TILING_MICRO)
1235 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1236 } else {
1237 if (tiling_flags & RADEON_TILING_MACRO)
1238 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1239
40c4ac1c
AD		 1240 if (tiling_flags & RADEON_TILING_MICRO)
1241 fb_format |= AVIVO_D1GRPH_TILED;
1242 }
e024e110 1243
771fe6b9
JG		 1244 if (radeon_crtc->crtc_id == 0)
1245 WREG32(AVIVO_D1VGA_CONTROL, 0);
1246 else
1247 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1248
1249 if (rdev->family >= CHIP_RV770) {
1250 if (radeon_crtc->crtc_id) {
95347871
AD		 1251 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1252 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1253 } else {
95347871
AD		 1254 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1255 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1256 }
1257 }
771fe6b9
JG		 1258 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1259 (u32) fb_location);
1260 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1261 radeon_crtc->crtc_offset, (u32) fb_location);
1262 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1263
1264 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1265 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1266 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1267 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1268 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1269 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1270
4dd19b0d 1271 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1272 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1273 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1274
1275 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1276 crtc->mode.vdisplay);
1277 x &= ~3;
1278 y &= ~1;
1279 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1280 (x << 16) | y);
1281 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1282 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1283
1284 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1285 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1286 AVIVO_D1MODE_INTERLEAVE_EN);
1287 else
1288 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1289
4dd19b0d
CB		 1290 if (!atomic && fb && fb != crtc->fb) {
1291 radeon_fb = to_radeon_framebuffer(fb);
4c788679
JG		 1292 rbo = radeon_fb->obj->driver_private;
1293 r = radeon_bo_reserve(rbo, false);
1294 if (unlikely(r != 0))
1295 return r;
1296 radeon_bo_unpin(rbo);
1297 radeon_bo_unreserve(rbo);
771fe6b9 1298 }
f30f37de
MD		 1299
1300 /* Bytes per pixel may have changed */
1301 radeon_bandwidth_update(rdev);
1302
771fe6b9
JG		 1303 return 0;
1304}
1305
54f088a9
AD		 1306int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1307 struct drm_framebuffer *old_fb)
1308{
1309 struct drm_device *dev = crtc->dev;
1310 struct radeon_device *rdev = dev->dev_private;
1311
bcc1c2a1 1312 if (ASIC_IS_DCE4(rdev))
4dd19b0d
CB		 1313 return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
1314 else if (ASIC_IS_AVIVO(rdev))
1315 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1316 else
1317 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1318}
1319
1320int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1321 struct drm_framebuffer *fb,
21c74a8e 1322 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1323{
1324 struct drm_device *dev = crtc->dev;
1325 struct radeon_device *rdev = dev->dev_private;
1326
1327 if (ASIC_IS_DCE4(rdev))
1328 return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1329 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1330 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1331 else
4dd19b0d 1332 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1333}
1334
615e0cb6
AD		 1335/* properly set additional regs when using atombios */
1336static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1337{
1338 struct drm_device *dev = crtc->dev;
1339 struct radeon_device *rdev = dev->dev_private;
1340 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1341 u32 disp_merge_cntl;
1342
1343 switch (radeon_crtc->crtc_id) {
1344 case 0:
1345 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1346 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1347 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1348 break;
1349 case 1:
1350 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1351 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1352 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1353 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1354 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1355 break;
1356 }
1357}
1358
bcc1c2a1
AD		 1359static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1360{
1361 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1362 struct drm_device *dev = crtc->dev;
1363 struct radeon_device *rdev = dev->dev_private;
1364 struct drm_encoder *test_encoder;
1365 struct drm_crtc *test_crtc;
1366 uint32_t pll_in_use = 0;
1367
1368 if (ASIC_IS_DCE4(rdev)) {
1369 /* if crtc is driving DP and we have an ext clock, use that */
1370 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1371 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1372 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1373 if (rdev->clock.dp_extclk)
1374 return ATOM_PPLL_INVALID;
1375 }
1376 }
1377 }
1378
1379 /* otherwise, pick one of the plls */
1380 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1381 struct radeon_crtc *radeon_test_crtc;
1382
1383 if (crtc == test_crtc)
1384 continue;
1385
1386 radeon_test_crtc = to_radeon_crtc(test_crtc);
1387 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1388 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1389 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1390 }
1391 if (!(pll_in_use & 1))
1392 return ATOM_PPLL1;
1393 return ATOM_PPLL2;
1394 } else
1395 return radeon_crtc->crtc_id;
1396
1397}
1398
771fe6b9
JG		 1399int atombios_crtc_mode_set(struct drm_crtc *crtc,
1400 struct drm_display_mode *mode,
1401 struct drm_display_mode *adjusted_mode,
1402 int x, int y, struct drm_framebuffer *old_fb)
1403{
1404 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1405 struct drm_device *dev = crtc->dev;
1406 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1407 struct drm_encoder *encoder;
1408 bool is_tvcv = false;
771fe6b9 1409
54bfe496
AD		 1410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1411 /* find tv std */
1412 if (encoder->crtc == crtc) {
1413 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1414 if (radeon_encoder->active_device &
1415 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1416 is_tvcv = true;
1417 }
1418 }
771fe6b9 1419
bcc1c2a1 1420 /* always set DCPLL */
ba032a58
AD		 1421 if (ASIC_IS_DCE4(rdev)) {
1422 struct radeon_atom_ss ss;
1423 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1424 ASIC_INTERNAL_SS_ON_DCPLL,
1425 rdev->clock.default_dispclk);
1426 if (ss_enabled)
1427 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
f82b3ddc
AD		 1428 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1429 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
ba032a58
AD		 1430 if (ss_enabled)
1431 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1432 }
771fe6b9 1433 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1434
54bfe496 1435 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1436 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1437 else if (ASIC_IS_AVIVO(rdev)) {
1438 if (is_tvcv)
1439 atombios_crtc_set_timing(crtc, adjusted_mode);
1440 else
1441 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1442 } else {
bcc1c2a1 1443 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1444 if (radeon_crtc->crtc_id == 0)
1445 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1446 radeon_legacy_atom_fixup(crtc);
771fe6b9 1447 }
bcc1c2a1 1448 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1449 atombios_overscan_setup(crtc, mode, adjusted_mode);
1450 atombios_scaler_setup(crtc);
771fe6b9
JG		 1451 return 0;
1452}
1453
1454static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1455 struct drm_display_mode *mode,
1456 struct drm_display_mode *adjusted_mode)
1457{
03214bd5
AD		 1458 struct drm_device *dev = crtc->dev;
1459 struct radeon_device *rdev = dev->dev_private;
1460
1461 /* adjust pm to upcoming mode change */
1462 radeon_pm_compute_clocks(rdev);
1463
c93bb85b
JG		 1464 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1465 return false;
771fe6b9
JG		 1466 return true;
1467}
1468
1469static void atombios_crtc_prepare(struct drm_crtc *crtc)
1470{
267364ac
AD		 1471 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1472
1473 /* pick pll */
1474 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1475
37b4390e 1476 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1477 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1478}
1479
1480static void atombios_crtc_commit(struct drm_crtc *crtc)
1481{
1482 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1483 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1484}
1485
37f9003b
AD		 1486static void atombios_crtc_disable(struct drm_crtc *crtc)
1487{
1488 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1489 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1490
1491 switch (radeon_crtc->pll_id) {
1492 case ATOM_PPLL1:
1493 case ATOM_PPLL2:
1494 /* disable the ppll */
1495 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1496 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1497 break;
1498 default:
1499 break;
1500 }
1501 radeon_crtc->pll_id = -1;
1502}
1503
771fe6b9
JG		 1504static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1505 .dpms = atombios_crtc_dpms,
1506 .mode_fixup = atombios_crtc_mode_fixup,
1507 .mode_set = atombios_crtc_mode_set,
1508 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1509 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1510 .prepare = atombios_crtc_prepare,
1511 .commit = atombios_crtc_commit,
068143d3 1512 .load_lut = radeon_crtc_load_lut,
37f9003b 1513 .disable = atombios_crtc_disable,
771fe6b9
JG		 1514};
1515
1516void radeon_atombios_init_crtc(struct drm_device *dev,
1517 struct radeon_crtc *radeon_crtc)
1518{
bcc1c2a1
AD		 1519 struct radeon_device *rdev = dev->dev_private;
1520
1521 if (ASIC_IS_DCE4(rdev)) {
1522 switch (radeon_crtc->crtc_id) {
1523 case 0:
1524 default:
12d7798f 1525 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1526 break;
1527 case 1:
12d7798f 1528 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1529 break;
1530 case 2:
12d7798f 1531 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1532 break;
1533 case 3:
12d7798f 1534 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1535 break;
1536 case 4:
12d7798f 1537 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1538 break;
1539 case 5:
12d7798f 1540 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1541 break;
1542 }
1543 } else {
1544 if (radeon_crtc->crtc_id == 1)
1545 radeon_crtc->crtc_offset =
1546 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1547 else
1548 radeon_crtc->crtc_offset = 0;
1549 }
1550 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1551 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1552}
Linux 6.x block layer and io_uring tree(s)